drivers/serial/sh-sci.h

   1 #include <linux/serial_core.h>
   2 #include <asm/io.h>
   3 #include <asm/gpio.h>
   4
   5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
   6 #include <asm/regs306x.h>
   7 #endif
   8 #if defined(CONFIG_H8S2678)
   9 #include <asm/regs267x.h>
  10 #endif
  11
  12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  13     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  14     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
  15     defined(CONFIG_CPU_SUBTYPE_SH7709)
  16 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  17 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  18 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  19 # define SCI_AND_SCIF
  20 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  21 # define SCIF0          0xA4400000
  22 # define SCIF2          0xA4410000
  23 # define SCSMR_Ir       0xA44A0000
  24 # define IRDA_SCIF      SCIF0
  25 # define SCPCR 0xA4000116
  26 # define SCPDR 0xA4000136
  27
  28 /* Set the clock source,
  29  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  30  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  31  */
  32 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  33 # define SCIF_ONLY
  34 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  35       defined(CONFIG_CPU_SUBTYPE_SH7721)
  36 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  37 # define SCIF_ONLY
  38 #define SCIF_ORER    0x0200   /* overrun error bit */
  39 #elif defined(CONFIG_SH_RTS7751R2D)
  40 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  41 # define SCIF_ORER 0x0001   /* overrun error bit */
  42 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  43 # define SCIF_ONLY
  44 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
  45       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  46       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  47       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
  48       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
  49       defined(CONFIG_CPU_SUBTYPE_SH7751R)
  50 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  51 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  52 # define SCIF_ORER 0x0001   /* overrun error bit */
  53 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  54         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  55         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
  56 # define SCI_AND_SCIF
  57 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  58 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  59 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  60 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  61 # define SCIF_ORER 0x0001  /* overrun error bit */
  62 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  63 # define SCIF_ONLY
  64 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  65 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  66 # define SCIF_ORER 0x0001   /* overrun error bit */
  67 # define PACR 0xa4050100
  68 # define PBCR 0xa4050102
  69 # define SCSCR_INIT(port)          0x3B
  70 # define SCIF_ONLY
  71 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
  72 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  73 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  74 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  75 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
  76 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
  77 # define SCIF_ONLY
  78 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
  79 # define PADR                   0xA4050120
  80 # define PSDR                   0xA405013e
  81 # define PWDR                   0xA4050166
  82 # define PSCR                   0xA405011E
  83 # define SCIF_ORER              0x0001  /* overrun error bit */
  84 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  85 # define SCIF_ONLY
  86 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
  87 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
  88 # define SCSPTR0                SCPDR0
  89 # define SCIF_ORER              0x0001  /* overrun error bit */
  90 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  91 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  92 # define SCSPTR0                0xa4050160
  93 # define SCSPTR1                0xa405013e
  94 # define SCSPTR2                0xa4050160
  95 # define SCSPTR3                0xa405013e
  96 # define SCSPTR4                0xa4050128
  97 # define SCSPTR5                0xa4050128
  98 # define SCIF_ORER              0x0001  /* overrun error bit */
  99 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 100 # define SCIF_ONLY
 101 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 102 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 103 # define SCIF_ORER 0x0001   /* overrun error bit */
 104 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 105 # define SCIF_ONLY
 106 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 107 # define SCIF_BASE_ADDR    0x01030000
 108 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 109 # define SCIF_PTR2_OFFS    0x0000020
 110 # define SCIF_LSR2_OFFS    0x0000024
 111 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 112 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 113 # define SCSCR_INIT(port)  0x38         /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
 114 # define SCIF_ONLY
 115 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 116 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 117 # define SCI_ONLY
 118 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 119 #elif defined(CONFIG_H8S2678)
 120 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 121 # define SCI_ONLY
 122 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 123 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 124 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
 125 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
 126 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
 127 # define SCIF_ORER 0x0001  /* overrun error bit */
 128 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 129 # define SCIF_ONLY
 130 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 131 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 132 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 133 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 134 # define SCIF_ORER 0x0001  /* overrun error bit */
 135 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 136 # define SCIF_ONLY
 137 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 138 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 139 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 140 # define SCIF_ORER      0x0001          /* Overrun error bit */
 141 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 142 # define SCIF_ONLY
 143 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 144 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
 145 # define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
 146 # define SCSPTR2        0xffec0024      /* 16 bit SCIF */
 147 # define SCSPTR3        0xffed0024      /* 16 bit SCIF */
 148 # define SCSPTR4        0xffee0024      /* 16 bit SCIF */
 149 # define SCSPTR5        0xffef0024      /* 16 bit SCIF */
 150 # define SCIF_OPER      0x0001          /* Overrun error bit */
 151 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 152 # define SCIF_ONLY
 153 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
 154       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
 155       defined(CONFIG_CPU_SUBTYPE_SH7263)
 156 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 157 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 158 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
 159 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
 160 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 161 # define SCIF_ONLY
 162 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 163 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 164 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 165 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 166 # define SCIF_ORER 0x0001  /* overrun error bit */
 167 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 168 # define SCIF_ONLY
 169 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 170 # define SCSPTR0 0xffc30020             /* 16 bit SCIF */
 171 # define SCSPTR1 0xffc40020             /* 16 bit SCIF */
 172 # define SCSPTR2 0xffc50020             /* 16 bit SCIF */
 173 # define SCSPTR3 0xffc60020             /* 16 bit SCIF */
 174 # define SCIF_ORER 0x0001               /* Overrun error bit */
 175 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 176 # define SCIF_ONLY
 177 #else
 178 # error CPU subtype not defined
 179 #endif
 180
 181 /* SCSCR */
 182 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 183 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 184 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 185 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 186 #if defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 187     defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 188     defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 189     defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 190     defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 191     defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 192     defined(CONFIG_CPU_SUBTYPE_SH7763)  || \
 193     defined(CONFIG_CPU_SUBTYPE_SH7780)  || \
 194     defined(CONFIG_CPU_SUBTYPE_SH7785)  || \
 195     defined(CONFIG_CPU_SUBTYPE_SHX3)
 196 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 197 #else
 198 #define SCI_CTRL_FLAGS_REIE 0
 199 #endif
 200 /*      SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 201 /*      SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 202 /*      SCI_CTRL_FLAGS_CKE1 0x02  * all */
 203 /*      SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 204
 205 /* SCxSR SCI */
 206 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 207 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 208 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 209 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 210 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 211 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 212 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 213 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 214
 215 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 216
 217 /* SCxSR SCIF */
 218 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 219 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 220 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 221 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 222 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 223 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 224 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 225 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 226
 227 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 228     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 229     defined(CONFIG_CPU_SUBTYPE_SH7721)
 230 # define SCIF_ORER    0x0200
 231 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 232 # define SCIF_RFDC_MASK 0x007f
 233 # define SCIF_TXROOM_MAX 64
 234 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 235 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
 236 # define SCIF_RFDC_MASK 0x007f
 237 # define SCIF_TXROOM_MAX 64
 238 /* SH7763 SCIF2 support */
 239 # define SCIF2_RFDC_MASK 0x001f
 240 # define SCIF2_TXROOM_MAX 16
 241 #else
 242 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 243 # define SCIF_RFDC_MASK 0x001f
 244 # define SCIF_TXROOM_MAX 16
 245 #endif
 246
 247 #if defined(SCI_ONLY)
 248 # define SCxSR_TEND(port)               SCI_TEND
 249 # define SCxSR_ERRORS(port)             SCI_ERRORS
 250 # define SCxSR_RDxF(port)               SCI_RDRF
 251 # define SCxSR_TDxE(port)               SCI_TDRE
 252 # define SCxSR_ORER(port)               SCI_ORER
 253 # define SCxSR_FER(port)                SCI_FER
 254 # define SCxSR_PER(port)                SCI_PER
 255 # define SCxSR_BRK(port)                0x00
 256 # define SCxSR_RDxF_CLEAR(port)         0xbc
 257 # define SCxSR_ERROR_CLEAR(port)        0xc4
 258 # define SCxSR_TDxE_CLEAR(port)         0x78
 259 # define SCxSR_BREAK_CLEAR(port)        0xc4
 260 #elif defined(SCIF_ONLY)
 261 # define SCxSR_TEND(port)               SCIF_TEND
 262 # define SCxSR_ERRORS(port)             SCIF_ERRORS
 263 # define SCxSR_RDxF(port)               SCIF_RDF
 264 # define SCxSR_TDxE(port)               SCIF_TDFE
 265 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
 266 # define SCxSR_ORER(port)               SCIF_ORER
 267 #else
 268 # define SCxSR_ORER(port)               0x0000
 269 #endif
 270 # define SCxSR_FER(port)                SCIF_FER
 271 # define SCxSR_PER(port)                SCIF_PER
 272 # define SCxSR_BRK(port)                SCIF_BRK
 273 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 274     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 275     defined(CONFIG_CPU_SUBTYPE_SH7721)
 276 # define SCxSR_RDxF_CLEAR(port)         (sci_in(port,SCxSR)&0xfffc)
 277 # define SCxSR_ERROR_CLEAR(port)        (sci_in(port,SCxSR)&0xfd73)
 278 # define SCxSR_TDxE_CLEAR(port)         (sci_in(port,SCxSR)&0xffdf)
 279 # define SCxSR_BREAK_CLEAR(port)        (sci_in(port,SCxSR)&0xffe3)
 280 #else
 281 /* SH7705 can also use this, clearing is same between 7705 and 7709 */
 282 # define SCxSR_RDxF_CLEAR(port)         0x00fc
 283 # define SCxSR_ERROR_CLEAR(port)        0x0073
 284 # define SCxSR_TDxE_CLEAR(port)         0x00df
 285 # define SCxSR_BREAK_CLEAR(port)        0x00e3
 286 #endif
 287 #else
 288 # define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 289 # define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 290 # define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 291 # define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 292 # define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : 0x0000)
 293 # define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 294 # define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 295 # define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 296 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 297 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 298 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 299 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 300 #endif
 301
 302 /* SCFCR */
 303 #define SCFCR_RFRST 0x0002
 304 #define SCFCR_TFRST 0x0004
 305 #define SCFCR_TCRST 0x4000
 306 #define SCFCR_MCE   0x0008
 307
 308 #define SCI_MAJOR               204
 309 #define SCI_MINOR_START         8
 310
 311 /* Generic serial flags */
 312 #define SCI_RX_THROTTLE         0x0000001
 313
 314 #define SCI_MAGIC 0xbabeface
 315
 316 /*
 317  * Events are used to schedule things to happen at timer-interrupt
 318  * time, instead of at rs interrupt time.
 319  */
 320 #define SCI_EVENT_WRITE_WAKEUP  0
 321
 322 #define SCI_IN(size, offset)                                    \
 323   if ((size) == 8) {                                            \
 324     return ioread8(port->membase + (offset));                   \
 325   } else {                                                      \
 326     return ioread16(port->membase + (offset));                  \
 327   }
 328 #define SCI_OUT(size, offset, value)                            \
 329   if ((size) == 8) {                                            \
 330     iowrite8(value, port->membase + (offset));                  \
 331   } else if ((size) == 16) {                                    \
 332     iowrite16(value, port->membase + (offset));                 \
 333   }
 334
 335 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 336   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 337   {                                                                     \
 338     if (port->type == PORT_SCI) {                                       \
 339       SCI_IN(sci_size, sci_offset)                                      \
 340     } else {                                                            \
 341       SCI_IN(scif_size, scif_offset);                                   \
 342     }                                                                   \
 343   }                                                                     \
 344   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 345   {                                                                     \
 346     if (port->type == PORT_SCI) {                                       \
 347       SCI_OUT(sci_size, sci_offset, value)                              \
 348     } else {                                                            \
 349       SCI_OUT(scif_size, scif_offset, value);                           \
 350     }                                                                   \
 351   }
 352
 353 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                              \
 354   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 355   {                                                                     \
 356     SCI_IN(scif_size, scif_offset);                                     \
 357   }                                                                     \
 358   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 359   {                                                                     \
 360     SCI_OUT(scif_size, scif_offset, value);                             \
 361   }
 362
 363 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 364   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 365   {                                                                     \
 366     SCI_IN(sci_size, sci_offset);                                       \
 367   }                                                                     \
 368   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 369   {                                                                     \
 370     SCI_OUT(sci_size, sci_offset, value);                               \
 371   }
 372
 373 #ifdef CONFIG_CPU_SH3
 374 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 375 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 376                                 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 377                                  h8_sci_offset, h8_sci_size) \
 378   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 379 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 380           CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 381 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 382       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 383       defined(CONFIG_CPU_SUBTYPE_SH7721)
 384 #define SCIF_FNS(name, scif_offset, scif_size) \
 385   CPU_SCIF_FNS(name, scif_offset, scif_size)
 386 #else
 387 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 388                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 389                  h8_sci_offset, h8_sci_size) \
 390   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 391 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 392   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 393 #endif
 394 #elif defined(__H8300H__) || defined(__H8300S__)
 395 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 396                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 397                  h8_sci_offset, h8_sci_size) \
 398   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 399 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
 400 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 401         #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
 402                 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
 403         #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
 404                 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 405 #else
 406 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 407                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 408                  h8_sci_offset, h8_sci_size) \
 409   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 410 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 411   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 412 #endif
 413
 414 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 415     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 416     defined(CONFIG_CPU_SUBTYPE_SH7721)
 417
 418 SCIF_FNS(SCSMR,  0x00, 16)
 419 SCIF_FNS(SCBRR,  0x04,  8)
 420 SCIF_FNS(SCSCR,  0x08, 16)
 421 SCIF_FNS(SCTDSR, 0x0c,  8)
 422 SCIF_FNS(SCFER,  0x10, 16)
 423 SCIF_FNS(SCxSR,  0x14, 16)
 424 SCIF_FNS(SCFCR,  0x18, 16)
 425 SCIF_FNS(SCFDR,  0x1c, 16)
 426 SCIF_FNS(SCxTDR, 0x20,  8)
 427 SCIF_FNS(SCxRDR, 0x24,  8)
 428 SCIF_FNS(SCLSR,  0x24, 16)
 429 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 430 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
 431 SCIx_FNS(SCBRR,  0x04,  8, 0x04,  8)
 432 SCIx_FNS(SCSCR,  0x08, 16, 0x08, 16)
 433 SCIx_FNS(SCxTDR, 0x20,  8, 0x0c,  8)
 434 SCIx_FNS(SCxSR,  0x14, 16, 0x10, 16)
 435 SCIx_FNS(SCxRDR, 0x24,  8, 0x14,  8)
 436 SCIF_FNS(SCTDSR, 0x0c,  8)
 437 SCIF_FNS(SCFER,  0x10, 16)
 438 SCIF_FNS(SCFCR,  0x18, 16)
 439 SCIF_FNS(SCFDR,  0x1c, 16)
 440 SCIF_FNS(SCLSR,  0x24, 16)
 441 #else
 442 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 443 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 444 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 445 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 446 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 447 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 448 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 449 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 450 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 451 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
 452     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 453     defined(CONFIG_CPU_SUBTYPE_SH7785)
 454 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 455 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 456 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 457 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 458 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 459 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 460 SCIF_FNS(SCFDR,                         0,  0, 0x1C, 16)
 461 SCIF_FNS(SCSPTR2,                       0,  0, 0x20, 16)
 462 SCIF_FNS(SCLSR2,                        0,  0, 0x24, 16)
 463 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 464 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 465 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 466 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 467 #else
 468 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 469 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
 470 SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 471 #else
 472 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 473 #endif
 474 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 475 #endif
 476 #endif
 477 #define sci_in(port, reg) sci_##reg##_in(port)
 478 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 479
 480 /* H8/300 series SCI pins assignment */
 481 #if defined(__H8300H__) || defined(__H8300S__)
 482 static const struct __attribute__((packed)) {
 483         int port;             /* GPIO port no */
 484         unsigned short rx,tx; /* GPIO bit no */
 485 } h8300_sci_pins[] = {
 486 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 487         {    /* SCI0 */
 488                 .port = H8300_GPIO_P9,
 489                 .rx   = H8300_GPIO_B2,
 490                 .tx   = H8300_GPIO_B0,
 491         },
 492         {    /* SCI1 */
 493                 .port = H8300_GPIO_P9,
 494                 .rx   = H8300_GPIO_B3,
 495                 .tx   = H8300_GPIO_B1,
 496         },
 497         {    /* SCI2 */
 498                 .port = H8300_GPIO_PB,
 499                 .rx   = H8300_GPIO_B7,
 500                 .tx   = H8300_GPIO_B6,
 501         }
 502 #elif defined(CONFIG_H8S2678)
 503         {    /* SCI0 */
 504                 .port = H8300_GPIO_P3,
 505                 .rx   = H8300_GPIO_B2,
 506                 .tx   = H8300_GPIO_B0,
 507         },
 508         {    /* SCI1 */
 509                 .port = H8300_GPIO_P3,
 510                 .rx   = H8300_GPIO_B3,
 511                 .tx   = H8300_GPIO_B1,
 512         },
 513         {    /* SCI2 */
 514                 .port = H8300_GPIO_P5,
 515                 .rx   = H8300_GPIO_B1,
 516                 .tx   = H8300_GPIO_B0,
 517         }
 518 #endif
 519 };
 520 #endif
 521
 522 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 523     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 524     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
 525     defined(CONFIG_CPU_SUBTYPE_SH7709)
 526 static inline int sci_rxd_in(struct uart_port *port)
 527 {
 528         if (port->mapbase == 0xfffffe80)
 529                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 530         if (port->mapbase == 0xa4000150)
 531                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 532         if (port->mapbase == 0xa4000140)
 533                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 534         return 1;
 535 }
 536 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 537 static inline int sci_rxd_in(struct uart_port *port)
 538 {
 539         if (port->mapbase == SCIF0)
 540                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 541         if (port->mapbase == SCIF2)
 542                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 543         return 1;
 544 }
 545 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 546 static inline int sci_rxd_in(struct uart_port *port)
 547 {
 548           return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
 549 }
 550 static inline void set_sh771x_scif_pfc(struct uart_port *port)
 551 {
 552         if (port->mapbase == 0xA4400000){
 553                 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
 554                 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
 555                 return;
 556         }
 557         if (port->mapbase == 0xA4410000){
 558                 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
 559                 return;
 560         }
 561 }
 562 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 563       defined(CONFIG_CPU_SUBTYPE_SH7721)
 564 static inline int sci_rxd_in(struct uart_port *port)
 565 {
 566         if (port->mapbase == 0xa4430000)
 567                 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
 568         else if (port->mapbase == 0xa4438000)
 569                 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
 570         return 1;
 571 }
 572 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 573       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 574       defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 575       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 576       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 577       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 578       defined(CONFIG_CPU_SUBTYPE_SH4_202)
 579 static inline int sci_rxd_in(struct uart_port *port)
 580 {
 581 #ifndef SCIF_ONLY
 582         if (port->mapbase == 0xffe00000)
 583                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 584 #endif
 585 #ifndef SCI_ONLY
 586         if (port->mapbase == 0xffe80000)
 587                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 588 #endif
 589         return 1;
 590 }
 591 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 592 static inline int sci_rxd_in(struct uart_port *port)
 593 {
 594         if (port->mapbase == 0xfe600000)
 595                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 596         if (port->mapbase == 0xfe610000)
 597                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 598         if (port->mapbase == 0xfe620000)
 599                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 600         return 1;
 601 }
 602 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 603 static inline int sci_rxd_in(struct uart_port *port)
 604 {
 605         if (port->mapbase == 0xffe00000)
 606                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 607         if (port->mapbase == 0xffe10000)
 608                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 609         if (port->mapbase == 0xffe20000)
 610                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 611         if (port->mapbase == 0xffe30000)
 612                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 613         return 1;
 614 }
 615 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
 616 static inline int sci_rxd_in(struct uart_port *port)
 617 {
 618         if (port->mapbase == 0xffe00000)
 619                 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
 620         return 1;
 621 }
 622 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 623 static inline int sci_rxd_in(struct uart_port *port)
 624 {
 625         if (port->mapbase == 0xffe00000)
 626                 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
 627         if (port->mapbase == 0xffe10000)
 628                 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
 629         if (port->mapbase == 0xffe20000)
 630                 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
 631
 632         return 1;
 633 }
 634 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 635 static inline int sci_rxd_in(struct uart_port *port)
 636 {
 637         if (port->mapbase == 0xffe00000)
 638                 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
 639         if (port->mapbase == 0xffe10000)
 640                 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
 641         if (port->mapbase == 0xffe20000)
 642                 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
 643         if (port->mapbase == 0xa4e30000)
 644                 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
 645         if (port->mapbase == 0xa4e40000)
 646                 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
 647         if (port->mapbase == 0xa4e50000)
 648                 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
 649         return 1;
 650 }
 651 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 652 static inline int sci_rxd_in(struct uart_port *port)
 653 {
 654          return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
 655 }
 656 #elif defined(__H8300H__) || defined(__H8300S__)
 657 static inline int sci_rxd_in(struct uart_port *port)
 658 {
 659         int ch = (port->mapbase - SMR0) >> 3;
 660         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 661 }
 662 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 663 static inline int sci_rxd_in(struct uart_port *port)
 664 {
 665         if (port->mapbase == 0xffe00000)
 666                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 667         if (port->mapbase == 0xffe08000)
 668                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 669         if (port->mapbase == 0xffe10000)
 670                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
 671
 672         return 1;
 673 }
 674 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 675 static inline int sci_rxd_in(struct uart_port *port)
 676 {
 677         if (port->mapbase == 0xff923000)
 678                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 679         if (port->mapbase == 0xff924000)
 680                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 681         if (port->mapbase == 0xff925000)
 682                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 683         return 1;
 684 }
 685 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 686 static inline int sci_rxd_in(struct uart_port *port)
 687 {
 688         if (port->mapbase == 0xffe00000)
 689                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 690         if (port->mapbase == 0xffe10000)
 691                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 692         return 1;
 693 }
 694 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 695 static inline int sci_rxd_in(struct uart_port *port)
 696 {
 697         if (port->mapbase == 0xffea0000)
 698                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 699         if (port->mapbase == 0xffeb0000)
 700                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 701         if (port->mapbase == 0xffec0000)
 702                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 703         if (port->mapbase == 0xffed0000)
 704                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 705         if (port->mapbase == 0xffee0000)
 706                 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
 707         if (port->mapbase == 0xffef0000)
 708                 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
 709         return 1;
 710 }
 711 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
 712       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
 713       defined(CONFIG_CPU_SUBTYPE_SH7263)
 714 static inline int sci_rxd_in(struct uart_port *port)
 715 {
 716         if (port->mapbase == 0xfffe8000)
 717                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 718         if (port->mapbase == 0xfffe8800)
 719                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 720         if (port->mapbase == 0xfffe9000)
 721                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 722         if (port->mapbase == 0xfffe9800)
 723                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 724         return 1;
 725 }
 726 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 727 static inline int sci_rxd_in(struct uart_port *port)
 728 {
 729         if (port->mapbase == 0xf8400000)
 730                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 731         if (port->mapbase == 0xf8410000)
 732                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 733         if (port->mapbase == 0xf8420000)
 734                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 735         return 1;
 736 }
 737 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 738 static inline int sci_rxd_in(struct uart_port *port)
 739 {
 740         if (port->mapbase == 0xffc30000)
 741                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 742         if (port->mapbase == 0xffc40000)
 743                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 744         if (port->mapbase == 0xffc50000)
 745                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 746         if (port->mapbase == 0xffc60000)
 747                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 748         return 1;
 749 }
 750 #endif
 751
 752 /*
 753  * Values for the BitRate Register (SCBRR)
 754  *
 755  * The values are actually divisors for a frequency which can
 756  * be internal to the SH3 (14.7456MHz) or derived from an external
 757  * clock source.  This driver assumes the internal clock is used;
 758  * to support using an external clock source, config options or
 759  * possibly command-line options would need to be added.
 760  *
 761  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 762  * the SCSMR register would also need to be set to non-zero values.
 763  *
 764  * -- Greg Banks 27Feb2000
 765  *
 766  * Answer: The SCBRR register is only eight bits, and the value in
 767  * it gets larger with lower baud rates. At around 2400 (depending on
 768  * the peripherial module clock) you run out of bits. However the
 769  * lower two bits of SCSMR allow the module clock to be divided down,
 770  * scaling the value which is needed in SCBRR.
 771  *
 772  * -- Stuart Menefy - 23 May 2000
 773  *
 774  * I meant, why would anyone bother with bitrates below 2400.
 775  *
 776  * -- Greg Banks - 7Jul2000
 777  *
 778  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 779  * tape reader as a console!
 780  *
 781  * -- Mitch Davis - 15 Jul 2000
 782  */
 783
 784 #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 785     defined(CONFIG_CPU_SUBTYPE_SH7785)
 786 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 787 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 788       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 789       defined(CONFIG_CPU_SUBTYPE_SH7721)
 790 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 791 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 792 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 793 {
 794         if (port->type == PORT_SCIF)
 795                 return (clk+16*bps)/(32*bps)-1;
 796         else
 797                 return ((clk*2)+16*bps)/(16*bps)-1;
 798 }
 799 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 800 #elif defined(__H8300H__) || defined(__H8300S__)
 801 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
 802 #else /* Generic SH */
 803 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 804 #endif