3 bool "Hardware crypto devices"
6 Say Y here to get to see options for hardware crypto devices and
7 processors. This option alone does not add any kernel code.
9 If you say N, all options in this submenu will be skipped and disabled.
13 config CRYPTO_DEV_PADLOCK
14 tristate "Support for VIA PadLock ACE"
15 depends on X86 && !UML
17 Some VIA processors come with an integrated crypto engine
18 (so called VIA PadLock ACE, Advanced Cryptography Engine)
19 that provides instructions for very fast cryptographic
20 operations with supported algorithms.
22 The instructions are used only when the CPU supports them.
23 Otherwise software encryption is used.
25 config CRYPTO_DEV_PADLOCK_AES
26 tristate "PadLock driver for AES algorithm"
27 depends on CRYPTO_DEV_PADLOCK
28 select CRYPTO_BLKCIPHER
31 Use VIA PadLock for AES algorithm.
33 Available in VIA C3 and newer CPUs.
35 If unsure say M. The compiled module will be
38 config CRYPTO_DEV_PADLOCK_SHA
39 tristate "PadLock driver for SHA1 and SHA256 algorithms"
40 depends on CRYPTO_DEV_PADLOCK
45 Use VIA PadLock for SHA1/SHA256 algorithms.
47 Available in VIA C7 and newer processors.
49 If unsure say M. The compiled module will be
52 config CRYPTO_DEV_GEODE
53 tristate "Support for the Geode LX AES engine"
54 depends on X86_32 && PCI
56 select CRYPTO_BLKCIPHER
58 Say 'Y' here to use the AMD Geode LX processor on-board AES
59 engine for the CryptoAPI AES algorithm.
61 To compile this driver as a module, choose M here: the module
62 will be called geode-aes.
65 tristate "Support for PCI-attached cryptographic adapters"
67 select ZCRYPT_MONOLITHIC if ZCRYPT="y"
70 Select this option if you want to use a PCI-attached cryptographic
72 + PCI Cryptographic Accelerator (PCICA)
73 + PCI Cryptographic Coprocessor (PCICC)
74 + PCI-X Cryptographic Coprocessor (PCIXCC)
75 + Crypto Express2 Coprocessor (CEX2C)
76 + Crypto Express2 Accelerator (CEX2A)
77 + Crypto Express3 Coprocessor (CEX3C)
78 + Crypto Express3 Accelerator (CEX3A)
80 config ZCRYPT_MONOLITHIC
81 bool "Monolithic zcrypt module"
84 Select this option if you want to have a single module z90crypt,
85 that contains all parts of the crypto device driver (ap bus,
86 request router and all the card drivers).
88 config CRYPTO_SHA1_S390
89 tristate "SHA1 digest algorithm"
93 This is the s390 hardware accelerated implementation of the
94 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
96 It is available as of z990.
98 config CRYPTO_SHA256_S390
99 tristate "SHA256 digest algorithm"
103 This is the s390 hardware accelerated implementation of the
104 SHA256 secure hash standard (DFIPS 180-2).
106 It is available as of z9.
108 config CRYPTO_SHA512_S390
109 tristate "SHA384 and SHA512 digest algorithm"
113 This is the s390 hardware accelerated implementation of the
114 SHA512 secure hash standard.
116 It is available as of z10.
118 config CRYPTO_DES_S390
119 tristate "DES and Triple DES cipher algorithms"
122 select CRYPTO_BLKCIPHER
124 This is the s390 hardware accelerated implementation of the
125 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
127 As of z990 the ECB and CBC mode are hardware accelerated.
128 As of z196 the CTR mode is hardware accelerated.
130 config CRYPTO_AES_S390
131 tristate "AES cipher algorithms"
134 select CRYPTO_BLKCIPHER
136 This is the s390 hardware accelerated implementation of the
137 AES cipher algorithms (FIPS-197).
139 As of z9 the ECB and CBC modes are hardware accelerated
141 As of z10 the ECB and CBC modes are hardware accelerated
142 for all AES key sizes.
143 As of z196 the CTR mode is hardware accelerated for all AES
144 key sizes and XTS mode is hardware accelerated for 256 and
148 tristate "Pseudo random number generator device driver"
152 Select this option if you want to use the s390 pseudo random number
153 generator. The PRNG is part of the cryptographic processor functions
154 and uses triple-DES to generate secure random numbers like the
155 ANSI X9.17 standard. User-space programs access the
156 pseudo-random-number device through the char device /dev/prandom.
158 It is available as of z9.
160 config CRYPTO_GHASH_S390
161 tristate "GHASH digest algorithm"
165 This is the s390 hardware accelerated implementation of the
166 GHASH message digest algorithm for GCM (Galois/Counter Mode).
168 It is available as of z196.
170 config CRYPTO_DEV_MV_CESA
171 tristate "Marvell's Cryptographic Engine"
172 depends on PLAT_ORION
175 select CRYPTO_BLKCIPHER2
177 This driver allows you to utilize the Cryptographic Engines and
178 Security Accelerator (CESA) which can be found on the Marvell Orion
179 and Kirkwood SoCs, such as QNAP's TS-209.
181 Currently the driver supports AES in ECB and CBC mode without DMA.
183 config CRYPTO_DEV_NIAGARA2
184 tristate "Niagara2 Stream Processing Unit driver"
189 Each core of a Niagara2 processor contains a Stream
190 Processing Unit, which itself contains several cryptographic
191 sub-units. One set provides the Modular Arithmetic Unit,
192 used for SSL offload. The other set provides the Cipher
193 Group, which can perform encryption, decryption, hashing,
194 checksumming, and raw copies.
196 config CRYPTO_DEV_HIFN_795X
197 tristate "Driver HIFN 795x crypto accelerator chips"
200 select CRYPTO_BLKCIPHER
201 select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG
203 depends on !ARCH_DMA_ADDR_T_64BIT
205 This option allows you to have support for HIFN 795x crypto adapters.
207 config CRYPTO_DEV_HIFN_795X_RNG
208 bool "HIFN 795x random number generator"
209 depends on CRYPTO_DEV_HIFN_795X
211 Select this option if you want to enable the random number generator
212 on the HIFN 795x crypto adapters.
214 source drivers/crypto/caam/Kconfig
216 config CRYPTO_DEV_TALITOS
217 tristate "Talitos Freescale Security Engine (SEC)"
219 select CRYPTO_AUTHENC
223 Say 'Y' here to use the Freescale Security Engine (SEC)
224 to offload cryptographic algorithm computation.
226 The Freescale SEC is present on PowerQUICC 'E' processors, such
227 as the MPC8349E and MPC8548E.
229 To compile this driver as a module, choose M here: the module
230 will be called talitos.
232 config CRYPTO_DEV_IXP4XX
233 tristate "Driver for IXP4xx crypto hardware acceleration"
234 depends on ARCH_IXP4XX
237 select CRYPTO_AUTHENC
238 select CRYPTO_BLKCIPHER
240 Driver for the IXP4xx NPE crypto engine.
242 config CRYPTO_DEV_PPC4XX
243 tristate "Driver AMCC PPC4xx crypto accelerator"
244 depends on PPC && 4xx
247 select CRYPTO_BLKCIPHER
249 This option allows you to have support for AMCC crypto acceleration.
251 config CRYPTO_DEV_OMAP_SHAM
252 tristate "Support for OMAP SHA1/MD5 hw accelerator"
253 depends on ARCH_OMAP2 || ARCH_OMAP3
257 OMAP processors have SHA1/MD5 hw accelerator. Select this if you
258 want to use the OMAP module for SHA1/MD5 algorithms.
260 config CRYPTO_DEV_OMAP_AES
261 tristate "Support for OMAP AES hw engine"
262 depends on ARCH_OMAP2 || ARCH_OMAP3
265 OMAP processors have AES module accelerator. Select this if you
266 want to use the OMAP module for AES algorithms.
268 config CRYPTO_DEV_PICOXCELL
269 tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
270 depends on ARCH_PICOXCELL && HAVE_CLK
272 select CRYPTO_AUTHENC
279 This option enables support for the hardware offload engines in the
280 Picochip picoXcell SoC devices. Select this for IPSEC ESP offload
281 and for 3gpp Layer 2 ciphering support.
283 Saying m here will build a module named pipcoxcell_crypto.
285 config CRYPTO_DEV_S5P
286 tristate "Support for Samsung S5PV210 crypto accelerator"
287 depends on ARCH_S5PV210
290 select CRYPTO_BLKCIPHER
292 This option allows you to have support for S5P crypto acceleration.
293 Select this to offload Samsung S5PV210 or S5PC110 from AES
294 algorithms execution.