arch/arm/plat-mxc/include/mach/mx25.h

   1 #ifndef __MACH_MX25_H__
   2 #define __MACH_MX25_H__
   3
   4 #define MX25_AIPS1_BASE_ADDR            0x43F00000
   5 #define MX25_AIPS1_BASE_ADDR_VIRT       0xFC000000
   6 #define MX25_AIPS1_SIZE                 SZ_1M
   7 #define MX25_AIPS2_BASE_ADDR            0x53F00000
   8 #define MX25_AIPS2_BASE_ADDR_VIRT       0xFC200000
   9 #define MX25_AIPS2_SIZE                 SZ_1M
  10 #define MX25_AVIC_BASE_ADDR             0x68000000
  11 #define MX25_AVIC_BASE_ADDR_VIRT        0xFC400000
  12 #define MX25_AVIC_SIZE                  SZ_1M
  13
  14 #define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
  15
  16 #define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
  17 #define MX25_GPT1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x90000)
  18 #define MX25_WDOG_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xdc000)
  19
  20 #define MX25_GPIO1_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
  21 #define MX25_GPIO2_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
  22 #define MX25_GPIO3_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
  23 #define MX25_GPIO4_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
  24
  25 #define MX25_AIPS1_IO_ADDRESS(x)  \
  26         (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
  27 #define MX25_AIPS2_IO_ADDRESS(x)  \
  28         (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT)
  29 #define MX25_AVIC_IO_ADDRESS(x)  \
  30         (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
  31
  32 #define __in_range(addr, name)  ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE)
  33
  34 #define MX25_IO_ADDRESS(x)                                      \
  35         (void __force __iomem *)                                \
  36         (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \
  37         __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) :  \
  38         __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) :    \
  39         0xDEADBEEF)
  40
  41 #define UART1_BASE_ADDR                 0x43f90000
  42 #define UART2_BASE_ADDR                 0x43f94000
  43
  44 #endif /* __MACH_MX25_H__ */