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[PATCH] b44: miscellaneous cleanup
[wandboard.git] / drivers / net / b44.c
blob3b6428f004f610adc375d7830c7e25f71201a3a0
1 /* b44.c: Broadcom 4400 device driver.
2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
5 *
6 * Distribute under GPL.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/types.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/mii.h>
16 #include <linux/if_ether.h>
17 #include <linux/etherdevice.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/version.h>
22 #include <linux/dma-mapping.h>
23
24 #include <asm/uaccess.h>
25 #include <asm/io.h>
26 #include <asm/irq.h>
27
28 #include "b44.h"
29
30 #define DRV_MODULE_NAME "b44"
31 #define PFX DRV_MODULE_NAME ": "
32 #define DRV_MODULE_VERSION "0.95"
33 #define DRV_MODULE_RELDATE "Aug 3, 2004"
34
35 #define B44_DEF_MSG_ENABLE \
36 (NETIF_MSG_DRV | \
37 NETIF_MSG_PROBE | \
38 NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_IFDOWN | \
41 NETIF_MSG_IFUP | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR)
44
45 /* length of time before we decide the hardware is borked,
46 * and dev->tx_timeout() should be called to fix the problem
47 */
48 #define B44_TX_TIMEOUT (5 * HZ)
49
50 /* hardware minimum and maximum for a single frame's data payload */
51 #define B44_MIN_MTU 60
52 #define B44_MAX_MTU 1500
53
54 #define B44_RX_RING_SIZE 512
55 #define B44_DEF_RX_RING_PENDING 200
56 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
57 B44_RX_RING_SIZE)
58 #define B44_TX_RING_SIZE 512
59 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
60 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
61 B44_TX_RING_SIZE)
62 #define B44_DMA_MASK 0x3fffffff
63
64 #define TX_RING_GAP(BP) \
65 (B44_TX_RING_SIZE - (BP)->tx_pending)
66 #define TX_BUFFS_AVAIL(BP) \
67 (((BP)->tx_cons <= (BP)->tx_prod) ? \
68 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
69 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
70 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
71
72 #define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
73 #define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
74
75 /* minimum number of free TX descriptors required to wake up TX process */
76 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
77
78 static char version[] __devinitdata =
79 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80
81 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
82 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
83 MODULE_LICENSE("GPL");
84 MODULE_VERSION(DRV_MODULE_VERSION);
85
86 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
87 module_param(b44_debug, int, 0);
88 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
89
90 static struct pci_device_id b44_pci_tbl[] = {
91 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
93 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
95 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
97 { } /* terminate list with empty entry */
98 };
99
100 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
101
102 static void b44_halt(struct b44 *);
103 static void b44_init_rings(struct b44 *);
104 static void b44_init_hw(struct b44 *);
105
106 static int dma_desc_align_mask;
107 static int dma_desc_sync_size;
108
109 static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
110 dma_addr_t dma_base,
111 unsigned long offset,
112 enum dma_data_direction dir)
113 {
114 dma_sync_single_range_for_device(&pdev->dev, dma_base,
115 offset & dma_desc_align_mask,
116 dma_desc_sync_size, dir);
117 }
118
119 static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
120 dma_addr_t dma_base,
121 unsigned long offset,
122 enum dma_data_direction dir)
123 {
124 dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
125 offset & dma_desc_align_mask,
126 dma_desc_sync_size, dir);
127 }
128
129 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
130 {
131 return readl(bp->regs + reg);
132 }
133
134 static inline void bw32(const struct b44 *bp,
135 unsigned long reg, unsigned long val)
136 {
137 writel(val, bp->regs + reg);
138 }
139
140 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
141 u32 bit, unsigned long timeout, const int clear)
142 {
143 unsigned long i;
144
145 for (i = 0; i < timeout; i++) {
146 u32 val = br32(bp, reg);
147
148 if (clear && !(val & bit))
149 break;
150 if (!clear && (val & bit))
151 break;
152 udelay(10);
153 }
154 if (i == timeout) {
155 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
156 "%lx to %s.\n",
157 bp->dev->name,
158 bit, reg,
159 (clear ? "clear" : "set"));
160 return -ENODEV;
161 }
162 return 0;
163 }
164
165 /* Sonics SiliconBackplane support routines. ROFL, you should see all the
166 * buzz words used on this company's website :-)
167 *
168 * All of these routines must be invoked with bp->lock held and
169 * interrupts disabled.
170 */
171
172 #define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
173 #define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
174
175 static u32 ssb_get_core_rev(struct b44 *bp)
176 {
177 return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
178 }
179
180 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
181 {
182 u32 bar_orig, pci_rev, val;
183
184 pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
185 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
186 pci_rev = ssb_get_core_rev(bp);
187
188 val = br32(bp, B44_SBINTVEC);
189 val |= cores;
190 bw32(bp, B44_SBINTVEC, val);
191
192 val = br32(bp, SSB_PCI_TRANS_2);
193 val |= SSB_PCI_PREF | SSB_PCI_BURST;
194 bw32(bp, SSB_PCI_TRANS_2, val);
195
196 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
197
198 return pci_rev;
199 }
200
201 static void ssb_core_disable(struct b44 *bp)
202 {
203 if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
204 return;
205
206 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
207 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
208 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
209 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
210 SBTMSLOW_REJECT | SBTMSLOW_RESET));
211 br32(bp, B44_SBTMSLOW);
212 udelay(1);
213 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
214 br32(bp, B44_SBTMSLOW);
215 udelay(1);
216 }
217
218 static void ssb_core_reset(struct b44 *bp)
219 {
220 u32 val;
221
222 ssb_core_disable(bp);
223 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
224 br32(bp, B44_SBTMSLOW);
225 udelay(1);
226
227 /* Clear SERR if set, this is a hw bug workaround. */
228 if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
229 bw32(bp, B44_SBTMSHIGH, 0);
230
231 val = br32(bp, B44_SBIMSTATE);
232 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
233 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
234
235 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
236 br32(bp, B44_SBTMSLOW);
237 udelay(1);
238
239 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
240 br32(bp, B44_SBTMSLOW);
241 udelay(1);
242 }
243
244 static int ssb_core_unit(struct b44 *bp)
245 {
246 #if 0
247 u32 val = br32(bp, B44_SBADMATCH0);
248 u32 base;
249
250 type = val & SBADMATCH0_TYPE_MASK;
251 switch (type) {
252 case 0:
253 base = val & SBADMATCH0_BS0_MASK;
254 break;
255
256 case 1:
257 base = val & SBADMATCH0_BS1_MASK;
258 break;
259
260 case 2:
261 default:
262 base = val & SBADMATCH0_BS2_MASK;
263 break;
264 };
265 #endif
266 return 0;
267 }
268
269 static int ssb_is_core_up(struct b44 *bp)
270 {
271 return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
272 == SBTMSLOW_CLOCK);
273 }
274
275 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
276 {
277 u32 val;
278
279 val = ((u32) data[2]) << 24;
280 val |= ((u32) data[3]) << 16;
281 val |= ((u32) data[4]) << 8;
282 val |= ((u32) data[5]) << 0;
283 bw32(bp, B44_CAM_DATA_LO, val);
284 val = (CAM_DATA_HI_VALID |
285 (((u32) data[0]) << 8) |
286 (((u32) data[1]) << 0));
287 bw32(bp, B44_CAM_DATA_HI, val);
288 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
289 (index << CAM_CTRL_INDEX_SHIFT)));
290 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
291 }
292
293 static inline void __b44_disable_ints(struct b44 *bp)
294 {
295 bw32(bp, B44_IMASK, 0);
296 }
297
298 static void b44_disable_ints(struct b44 *bp)
299 {
300 __b44_disable_ints(bp);
301
302 /* Flush posted writes. */
303 br32(bp, B44_IMASK);
304 }
305
306 static void b44_enable_ints(struct b44 *bp)
307 {
308 bw32(bp, B44_IMASK, bp->imask);
309 }
310
311 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
312 {
313 int err;
314
315 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
316 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
317 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
318 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
319 (reg << MDIO_DATA_RA_SHIFT) |
320 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
321 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
322 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
323
324 return err;
325 }
326
327 static int b44_writephy(struct b44 *bp, int reg, u32 val)
328 {
329 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
330 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
331 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
332 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
333 (reg << MDIO_DATA_RA_SHIFT) |
334 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
335 (val & MDIO_DATA_DATA)));
336 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
337 }
338
339 /* miilib interface */
340 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
341 * due to code existing before miilib use was added to this driver.
342 * Someone should remove this artificial driver limitation in
343 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
344 */
345 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
346 {
347 u32 val;
348 struct b44 *bp = netdev_priv(dev);
349 int rc = b44_readphy(bp, location, &val);
350 if (rc)
351 return 0xffffffff;
352 return val;
353 }
354
355 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
356 int val)
357 {
358 struct b44 *bp = netdev_priv(dev);
359 b44_writephy(bp, location, val);
360 }
361
362 static int b44_phy_reset(struct b44 *bp)
363 {
364 u32 val;
365 int err;
366
367 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
368 if (err)
369 return err;
370 udelay(100);
371 err = b44_readphy(bp, MII_BMCR, &val);
372 if (!err) {
373 if (val & BMCR_RESET) {
374 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
375 bp->dev->name);
376 err = -ENODEV;
377 }
378 }
379
380 return 0;
381 }
382
383 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
384 {
385 u32 val;
386
387 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
388 bp->flags |= pause_flags;
389
390 val = br32(bp, B44_RXCONFIG);
391 if (pause_flags & B44_FLAG_RX_PAUSE)
392 val |= RXCONFIG_FLOW;
393 else
394 val &= ~RXCONFIG_FLOW;
395 bw32(bp, B44_RXCONFIG, val);
396
397 val = br32(bp, B44_MAC_FLOW);
398 if (pause_flags & B44_FLAG_TX_PAUSE)
399 val |= (MAC_FLOW_PAUSE_ENAB |
400 (0xc0 & MAC_FLOW_RX_HI_WATER));
401 else
402 val &= ~MAC_FLOW_PAUSE_ENAB;
403 bw32(bp, B44_MAC_FLOW, val);
404 }
405
406 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
407 {
408 u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
409 B44_FLAG_RX_PAUSE);
410
411 if (local & ADVERTISE_PAUSE_CAP) {
412 if (local & ADVERTISE_PAUSE_ASYM) {
413 if (remote & LPA_PAUSE_CAP)
414 pause_enab |= (B44_FLAG_TX_PAUSE |
415 B44_FLAG_RX_PAUSE);
416 else if (remote & LPA_PAUSE_ASYM)
417 pause_enab |= B44_FLAG_RX_PAUSE;
418 } else {
419 if (remote & LPA_PAUSE_CAP)
420 pause_enab |= (B44_FLAG_TX_PAUSE |
421 B44_FLAG_RX_PAUSE);
422 }
423 } else if (local & ADVERTISE_PAUSE_ASYM) {
424 if ((remote & LPA_PAUSE_CAP) &&
425 (remote & LPA_PAUSE_ASYM))
426 pause_enab |= B44_FLAG_TX_PAUSE;
427 }
428
429 __b44_set_flow_ctrl(bp, pause_enab);
430 }
431
432 static int b44_setup_phy(struct b44 *bp)
433 {
434 u32 val;
435 int err;
436
437 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
438 goto out;
439 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
440 val & MII_ALEDCTRL_ALLMSK)) != 0)
441 goto out;
442 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
443 goto out;
444 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
445 val | MII_TLEDCTRL_ENABLE)) != 0)
446 goto out;
447
448 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
449 u32 adv = ADVERTISE_CSMA;
450
451 if (bp->flags & B44_FLAG_ADV_10HALF)
452 adv |= ADVERTISE_10HALF;
453 if (bp->flags & B44_FLAG_ADV_10FULL)
454 adv |= ADVERTISE_10FULL;
455 if (bp->flags & B44_FLAG_ADV_100HALF)
456 adv |= ADVERTISE_100HALF;
457 if (bp->flags & B44_FLAG_ADV_100FULL)
458 adv |= ADVERTISE_100FULL;
459
460 if (bp->flags & B44_FLAG_PAUSE_AUTO)
461 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
462
463 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
464 goto out;
465 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
466 BMCR_ANRESTART))) != 0)
467 goto out;
468 } else {
469 u32 bmcr;
470
471 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
472 goto out;
473 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
474 if (bp->flags & B44_FLAG_100_BASE_T)
475 bmcr |= BMCR_SPEED100;
476 if (bp->flags & B44_FLAG_FULL_DUPLEX)
477 bmcr |= BMCR_FULLDPLX;
478 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
479 goto out;
480
481 /* Since we will not be negotiating there is no safe way
482 * to determine if the link partner supports flow control
483 * or not. So just disable it completely in this case.
484 */
485 b44_set_flow_ctrl(bp, 0, 0);
486 }
487
488 out:
489 return err;
490 }
491
492 static void b44_stats_update(struct b44 *bp)
493 {
494 unsigned long reg;
495 u32 *val;
496
497 val = &bp->hw_stats.tx_good_octets;
498 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
499 *val++ += br32(bp, reg);
500 }
501 val = &bp->hw_stats.rx_good_octets;
502 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
503 *val++ += br32(bp, reg);
504 }
505 }
506
507 static void b44_link_report(struct b44 *bp)
508 {
509 if (!netif_carrier_ok(bp->dev)) {
510 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
511 } else {
512 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
513 bp->dev->name,
514 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
515 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
516
517 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
518 "%s for RX.\n",
519 bp->dev->name,
520 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
521 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
522 }
523 }
524
525 static void b44_check_phy(struct b44 *bp)
526 {
527 u32 bmsr, aux;
528
529 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
530 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
531 (bmsr != 0xffff)) {
532 if (aux & MII_AUXCTRL_SPEED)
533 bp->flags |= B44_FLAG_100_BASE_T;
534 else
535 bp->flags &= ~B44_FLAG_100_BASE_T;
536 if (aux & MII_AUXCTRL_DUPLEX)
537 bp->flags |= B44_FLAG_FULL_DUPLEX;
538 else
539 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
540
541 if (!netif_carrier_ok(bp->dev) &&
542 (bmsr & BMSR_LSTATUS)) {
543 u32 val = br32(bp, B44_TX_CTRL);
544 u32 local_adv, remote_adv;
545
546 if (bp->flags & B44_FLAG_FULL_DUPLEX)
547 val |= TX_CTRL_DUPLEX;
548 else
549 val &= ~TX_CTRL_DUPLEX;
550 bw32(bp, B44_TX_CTRL, val);
551
552 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
553 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
554 !b44_readphy(bp, MII_LPA, &remote_adv))
555 b44_set_flow_ctrl(bp, local_adv, remote_adv);
556
557 /* Link now up */
558 netif_carrier_on(bp->dev);
559 b44_link_report(bp);
560 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
561 /* Link now down */
562 netif_carrier_off(bp->dev);
563 b44_link_report(bp);
564 }
565
566 if (bmsr & BMSR_RFAULT)
567 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
568 bp->dev->name);
569 if (bmsr & BMSR_JCD)
570 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
571 bp->dev->name);
572 }
573 }
574
575 static void b44_timer(unsigned long __opaque)
576 {
577 struct b44 *bp = (struct b44 *) __opaque;
578
579 spin_lock_irq(&bp->lock);
580
581 b44_check_phy(bp);
582
583 b44_stats_update(bp);
584
585 spin_unlock_irq(&bp->lock);
586
587 bp->timer.expires = jiffies + HZ;
588 add_timer(&bp->timer);
589 }
590
591 static void b44_tx(struct b44 *bp)
592 {
593 u32 cur, cons;
594
595 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
596 cur /= sizeof(struct dma_desc);
597
598 /* XXX needs updating when NETIF_F_SG is supported */
599 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
600 struct ring_info *rp = &bp->tx_buffers[cons];
601 struct sk_buff *skb = rp->skb;
602
603 if (unlikely(skb == NULL))
604 BUG();
605
606 pci_unmap_single(bp->pdev,
607 pci_unmap_addr(rp, mapping),
608 skb->len,
609 PCI_DMA_TODEVICE);
610 rp->skb = NULL;
611 dev_kfree_skb_irq(skb);
612 }
613
614 bp->tx_cons = cons;
615 if (netif_queue_stopped(bp->dev) &&
616 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
617 netif_wake_queue(bp->dev);
618
619 bw32(bp, B44_GPTIMER, 0);
620 }
621
622 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
623 * before the DMA address you give it. So we allocate 30 more bytes
624 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
625 * point the chip at 30 bytes past where the rx_header will go.
626 */
627 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
628 {
629 struct dma_desc *dp;
630 struct ring_info *src_map, *map;
631 struct rx_header *rh;
632 struct sk_buff *skb;
633 dma_addr_t mapping;
634 int dest_idx;
635 u32 ctrl;
636
637 src_map = NULL;
638 if (src_idx >= 0)
639 src_map = &bp->rx_buffers[src_idx];
640 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
641 map = &bp->rx_buffers[dest_idx];
642 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
643 if (skb == NULL)
644 return -ENOMEM;
645
646 mapping = pci_map_single(bp->pdev, skb->data,
647 RX_PKT_BUF_SZ,
648 PCI_DMA_FROMDEVICE);
649
650 /* Hardware bug work-around, the chip is unable to do PCI DMA
651 to/from anything above 1GB :-( */
652 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
653 /* Sigh... */
654 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
655 dev_kfree_skb_any(skb);
656 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
657 if (skb == NULL)
658 return -ENOMEM;
659 mapping = pci_map_single(bp->pdev, skb->data,
660 RX_PKT_BUF_SZ,
661 PCI_DMA_FROMDEVICE);
662 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
663 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
664 dev_kfree_skb_any(skb);
665 return -ENOMEM;
666 }
667 }
668
669 skb->dev = bp->dev;
670 skb_reserve(skb, bp->rx_offset);
671
672 rh = (struct rx_header *)
673 (skb->data - bp->rx_offset);
674 rh->len = 0;
675 rh->flags = 0;
676
677 map->skb = skb;
678 pci_unmap_addr_set(map, mapping, mapping);
679
680 if (src_map != NULL)
681 src_map->skb = NULL;
682
683 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
684 if (dest_idx == (B44_RX_RING_SIZE - 1))
685 ctrl |= DESC_CTRL_EOT;
686
687 dp = &bp->rx_ring[dest_idx];
688 dp->ctrl = cpu_to_le32(ctrl);
689 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
690
691 if (bp->flags & B44_FLAG_RX_RING_HACK)
692 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
693 dest_idx * sizeof(dp),
694 DMA_BIDIRECTIONAL);
695
696 return RX_PKT_BUF_SZ;
697 }
698
699 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
700 {
701 struct dma_desc *src_desc, *dest_desc;
702 struct ring_info *src_map, *dest_map;
703 struct rx_header *rh;
704 int dest_idx;
705 u32 ctrl;
706
707 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
708 dest_desc = &bp->rx_ring[dest_idx];
709 dest_map = &bp->rx_buffers[dest_idx];
710 src_desc = &bp->rx_ring[src_idx];
711 src_map = &bp->rx_buffers[src_idx];
712
713 dest_map->skb = src_map->skb;
714 rh = (struct rx_header *) src_map->skb->data;
715 rh->len = 0;
716 rh->flags = 0;
717 pci_unmap_addr_set(dest_map, mapping,
718 pci_unmap_addr(src_map, mapping));
719
720 if (bp->flags & B44_FLAG_RX_RING_HACK)
721 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
722 src_idx * sizeof(src_desc),
723 DMA_BIDIRECTIONAL);
724
725 ctrl = src_desc->ctrl;
726 if (dest_idx == (B44_RX_RING_SIZE - 1))
727 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
728 else
729 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
730
731 dest_desc->ctrl = ctrl;
732 dest_desc->addr = src_desc->addr;
733
734 src_map->skb = NULL;
735
736 if (bp->flags & B44_FLAG_RX_RING_HACK)
737 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
738 dest_idx * sizeof(dest_desc),
739 DMA_BIDIRECTIONAL);
740
741 pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
742 RX_PKT_BUF_SZ,
743 PCI_DMA_FROMDEVICE);
744 }
745
746 static int b44_rx(struct b44 *bp, int budget)
747 {
748 int received;
749 u32 cons, prod;
750
751 received = 0;
752 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
753 prod /= sizeof(struct dma_desc);
754 cons = bp->rx_cons;
755
756 while (cons != prod && budget > 0) {
757 struct ring_info *rp = &bp->rx_buffers[cons];
758 struct sk_buff *skb = rp->skb;
759 dma_addr_t map = pci_unmap_addr(rp, mapping);
760 struct rx_header *rh;
761 u16 len;
762
763 pci_dma_sync_single_for_cpu(bp->pdev, map,
764 RX_PKT_BUF_SZ,
765 PCI_DMA_FROMDEVICE);
766 rh = (struct rx_header *) skb->data;
767 len = cpu_to_le16(rh->len);
768 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
769 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
770 drop_it:
771 b44_recycle_rx(bp, cons, bp->rx_prod);
772 drop_it_no_recycle:
773 bp->stats.rx_dropped++;
774 goto next_pkt;
775 }
776
777 if (len == 0) {
778 int i = 0;
779
780 do {
781 udelay(2);
782 barrier();
783 len = cpu_to_le16(rh->len);
784 } while (len == 0 && i++ < 5);
785 if (len == 0)
786 goto drop_it;
787 }
788
789 /* Omit CRC. */
790 len -= 4;
791
792 if (len > RX_COPY_THRESHOLD) {
793 int skb_size;
794 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
795 if (skb_size < 0)
796 goto drop_it;
797 pci_unmap_single(bp->pdev, map,
798 skb_size, PCI_DMA_FROMDEVICE);
799 /* Leave out rx_header */
800 skb_put(skb, len+bp->rx_offset);
801 skb_pull(skb,bp->rx_offset);
802 } else {
803 struct sk_buff *copy_skb;
804
805 b44_recycle_rx(bp, cons, bp->rx_prod);
806 copy_skb = dev_alloc_skb(len + 2);
807 if (copy_skb == NULL)
808 goto drop_it_no_recycle;
809
810 copy_skb->dev = bp->dev;
811 skb_reserve(copy_skb, 2);
812 skb_put(copy_skb, len);
813 /* DMA sync done above, copy just the actual packet */
814 memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
815
816 skb = copy_skb;
817 }
818 skb->ip_summed = CHECKSUM_NONE;
819 skb->protocol = eth_type_trans(skb, bp->dev);
820 netif_receive_skb(skb);
821 bp->dev->last_rx = jiffies;
822 received++;
823 budget--;
824 next_pkt:
825 bp->rx_prod = (bp->rx_prod + 1) &
826 (B44_RX_RING_SIZE - 1);
827 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
828 }
829
830 bp->rx_cons = cons;
831 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
832
833 return received;
834 }
835
836 static int b44_poll(struct net_device *netdev, int *budget)
837 {
838 struct b44 *bp = netdev_priv(netdev);
839 int done;
840
841 spin_lock_irq(&bp->lock);
842
843 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
844 /* spin_lock(&bp->tx_lock); */
845 b44_tx(bp);
846 /* spin_unlock(&bp->tx_lock); */
847 }
848 spin_unlock_irq(&bp->lock);
849
850 done = 1;
851 if (bp->istat & ISTAT_RX) {
852 int orig_budget = *budget;
853 int work_done;
854
855 if (orig_budget > netdev->quota)
856 orig_budget = netdev->quota;
857
858 work_done = b44_rx(bp, orig_budget);
859
860 *budget -= work_done;
861 netdev->quota -= work_done;
862
863 if (work_done >= orig_budget)
864 done = 0;
865 }
866
867 if (bp->istat & ISTAT_ERRORS) {
868 spin_lock_irq(&bp->lock);
869 b44_halt(bp);
870 b44_init_rings(bp);
871 b44_init_hw(bp);
872 netif_wake_queue(bp->dev);
873 spin_unlock_irq(&bp->lock);
874 done = 1;
875 }
876
877 if (done) {
878 netif_rx_complete(netdev);
879 b44_enable_ints(bp);
880 }
881
882 return (done ? 0 : 1);
883 }
884
885 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
886 {
887 struct net_device *dev = dev_id;
888 struct b44 *bp = netdev_priv(dev);
889 unsigned long flags;
890 u32 istat, imask;
891 int handled = 0;
892
893 spin_lock_irqsave(&bp->lock, flags);
894
895 istat = br32(bp, B44_ISTAT);
896 imask = br32(bp, B44_IMASK);
897
898 /* ??? What the fuck is the purpose of the interrupt mask
899 * ??? register if we have to mask it out by hand anyways?
900 */
901 istat &= imask;
902 if (istat) {
903 handled = 1;
904 if (netif_rx_schedule_prep(dev)) {
905 /* NOTE: These writes are posted by the readback of
906 * the ISTAT register below.
907 */
908 bp->istat = istat;
909 __b44_disable_ints(bp);
910 __netif_rx_schedule(dev);
911 } else {
912 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
913 dev->name);
914 }
915
916 bw32(bp, B44_ISTAT, istat);
917 br32(bp, B44_ISTAT);
918 }
919 spin_unlock_irqrestore(&bp->lock, flags);
920 return IRQ_RETVAL(handled);
921 }
922
923 static void b44_tx_timeout(struct net_device *dev)
924 {
925 struct b44 *bp = netdev_priv(dev);
926
927 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
928 dev->name);
929
930 spin_lock_irq(&bp->lock);
931
932 b44_halt(bp);
933 b44_init_rings(bp);
934 b44_init_hw(bp);
935
936 spin_unlock_irq(&bp->lock);
937
938 b44_enable_ints(bp);
939
940 netif_wake_queue(dev);
941 }
942
943 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
944 {
945 struct b44 *bp = netdev_priv(dev);
946 struct sk_buff *bounce_skb;
947 int rc = NETDEV_TX_OK;
948 dma_addr_t mapping;
949 u32 len, entry, ctrl;
950
951 len = skb->len;
952 spin_lock_irq(&bp->lock);
953
954 /* This is a hard error, log it. */
955 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
956 netif_stop_queue(dev);
957 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
958 dev->name);
959 goto err_out;
960 }
961
962 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
963 if (mapping + len > B44_DMA_MASK) {
964 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
965 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
966
967 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
968 GFP_ATOMIC|GFP_DMA);
969 if (!bounce_skb)
970 goto err_out;
971
972 mapping = pci_map_single(bp->pdev, bounce_skb->data,
973 len, PCI_DMA_TODEVICE);
974 if (mapping + len > B44_DMA_MASK) {
975 pci_unmap_single(bp->pdev, mapping,
976 len, PCI_DMA_TODEVICE);
977 dev_kfree_skb_any(bounce_skb);
978 goto err_out;
979 }
980
981 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
982 dev_kfree_skb_any(skb);
983 skb = bounce_skb;
984 }
985
986 entry = bp->tx_prod;
987 bp->tx_buffers[entry].skb = skb;
988 pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
989
990 ctrl = (len & DESC_CTRL_LEN);
991 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
992 if (entry == (B44_TX_RING_SIZE - 1))
993 ctrl |= DESC_CTRL_EOT;
994
995 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
996 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
997
998 if (bp->flags & B44_FLAG_TX_RING_HACK)
999 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1000 entry * sizeof(bp->tx_ring[0]),
1001 DMA_TO_DEVICE);
1002
1003 entry = NEXT_TX(entry);
1004
1005 bp->tx_prod = entry;
1006
1007 wmb();
1008
1009 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1010 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1011 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1012 if (bp->flags & B44_FLAG_REORDER_BUG)
1013 br32(bp, B44_DMATX_PTR);
1014
1015 if (TX_BUFFS_AVAIL(bp) < 1)
1016 netif_stop_queue(dev);
1017
1018 dev->trans_start = jiffies;
1019
1020 out_unlock:
1021 spin_unlock_irq(&bp->lock);
1022
1023 return rc;
1024
1025 err_out:
1026 rc = NETDEV_TX_BUSY;
1027 goto out_unlock;
1028 }
1029
1030 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1031 {
1032 struct b44 *bp = netdev_priv(dev);
1033
1034 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1035 return -EINVAL;
1036
1037 if (!netif_running(dev)) {
1038 /* We'll just catch it later when the
1039 * device is up'd.
1040 */
1041 dev->mtu = new_mtu;
1042 return 0;
1043 }
1044
1045 spin_lock_irq(&bp->lock);
1046 b44_halt(bp);
1047 dev->mtu = new_mtu;
1048 b44_init_rings(bp);
1049 b44_init_hw(bp);
1050 spin_unlock_irq(&bp->lock);
1051
1052 b44_enable_ints(bp);
1053
1054 return 0;
1055 }
1056
1057 /* Free up pending packets in all rx/tx rings.
1058 *
1059 * The chip has been shut down and the driver detached from
1060 * the networking, so no interrupts or new tx packets will
1061 * end up in the driver. bp->lock is not held and we are not
1062 * in an interrupt context and thus may sleep.
1063 */
1064 static void b44_free_rings(struct b44 *bp)
1065 {
1066 struct ring_info *rp;
1067 int i;
1068
1069 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1070 rp = &bp->rx_buffers[i];
1071
1072 if (rp->skb == NULL)
1073 continue;
1074 pci_unmap_single(bp->pdev,
1075 pci_unmap_addr(rp, mapping),
1076 RX_PKT_BUF_SZ,
1077 PCI_DMA_FROMDEVICE);
1078 dev_kfree_skb_any(rp->skb);
1079 rp->skb = NULL;
1080 }
1081
1082 /* XXX needs changes once NETIF_F_SG is set... */
1083 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1084 rp = &bp->tx_buffers[i];
1085
1086 if (rp->skb == NULL)
1087 continue;
1088 pci_unmap_single(bp->pdev,
1089 pci_unmap_addr(rp, mapping),
1090 rp->skb->len,
1091 PCI_DMA_TODEVICE);
1092 dev_kfree_skb_any(rp->skb);
1093 rp->skb = NULL;
1094 }
1095 }
1096
1097 /* Initialize tx/rx rings for packet processing.
1098 *
1099 * The chip has been shut down and the driver detached from
1100 * the networking, so no interrupts or new tx packets will
1101 * end up in the driver.
1102 */
1103 static void b44_init_rings(struct b44 *bp)
1104 {
1105 int i;
1106
1107 b44_free_rings(bp);
1108
1109 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1110 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1111
1112 if (bp->flags & B44_FLAG_RX_RING_HACK)
1113 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1114 DMA_TABLE_BYTES,
1115 PCI_DMA_BIDIRECTIONAL);
1116
1117 if (bp->flags & B44_FLAG_TX_RING_HACK)
1118 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1119 DMA_TABLE_BYTES,
1120 PCI_DMA_TODEVICE);
1121
1122 for (i = 0; i < bp->rx_pending; i++) {
1123 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1124 break;
1125 }
1126 }
1127
1128 /*
1129 * Must not be invoked with interrupt sources disabled and
1130 * the hardware shutdown down.
1131 */
1132 static void b44_free_consistent(struct b44 *bp)
1133 {
1134 kfree(bp->rx_buffers);
1135 bp->rx_buffers = NULL;
1136 kfree(bp->tx_buffers);
1137 bp->tx_buffers = NULL;
1138 if (bp->rx_ring) {
1139 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1140 dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1141 DMA_TABLE_BYTES,
1142 DMA_BIDIRECTIONAL);
1143 kfree(bp->rx_ring);
1144 } else
1145 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1146 bp->rx_ring, bp->rx_ring_dma);
1147 bp->rx_ring = NULL;
1148 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1149 }
1150 if (bp->tx_ring) {
1151 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1152 dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1153 DMA_TABLE_BYTES,
1154 DMA_TO_DEVICE);
1155 kfree(bp->tx_ring);
1156 } else
1157 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1158 bp->tx_ring, bp->tx_ring_dma);
1159 bp->tx_ring = NULL;
1160 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1161 }
1162 }
1163
1164 /*
1165 * Must not be invoked with interrupt sources disabled and
1166 * the hardware shutdown down. Can sleep.
1167 */
1168 static int b44_alloc_consistent(struct b44 *bp)
1169 {
1170 int size;
1171
1172 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1173 bp->rx_buffers = kzalloc(size, GFP_KERNEL);
1174 if (!bp->rx_buffers)
1175 goto out_err;
1176
1177 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1178 bp->tx_buffers = kzalloc(size, GFP_KERNEL);
1179 if (!bp->tx_buffers)
1180 goto out_err;
1181
1182 size = DMA_TABLE_BYTES;
1183 bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1184 if (!bp->rx_ring) {
1185 /* Allocation may have failed due to pci_alloc_consistent
1186 insisting on use of GFP_DMA, which is more restrictive
1187 than necessary... */
1188 struct dma_desc *rx_ring;
1189 dma_addr_t rx_ring_dma;
1190
1191 rx_ring = kzalloc(size, GFP_KERNEL);
1192 if (!rx_ring)
1193 goto out_err;
1194
1195 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1196 DMA_TABLE_BYTES,
1197 DMA_BIDIRECTIONAL);
1198
1199 if (rx_ring_dma + size > B44_DMA_MASK) {
1200 kfree(rx_ring);
1201 goto out_err;
1202 }
1203
1204 bp->rx_ring = rx_ring;
1205 bp->rx_ring_dma = rx_ring_dma;
1206 bp->flags |= B44_FLAG_RX_RING_HACK;
1207 }
1208
1209 bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1210 if (!bp->tx_ring) {
1211 /* Allocation may have failed due to pci_alloc_consistent
1212 insisting on use of GFP_DMA, which is more restrictive
1213 than necessary... */
1214 struct dma_desc *tx_ring;
1215 dma_addr_t tx_ring_dma;
1216
1217 tx_ring = kzalloc(size, GFP_KERNEL);
1218 if (!tx_ring)
1219 goto out_err;
1220
1221 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1222 DMA_TABLE_BYTES,
1223 DMA_TO_DEVICE);
1224
1225 if (tx_ring_dma + size > B44_DMA_MASK) {
1226 kfree(tx_ring);
1227 goto out_err;
1228 }
1229
1230 bp->tx_ring = tx_ring;
1231 bp->tx_ring_dma = tx_ring_dma;
1232 bp->flags |= B44_FLAG_TX_RING_HACK;
1233 }
1234
1235 return 0;
1236
1237 out_err:
1238 b44_free_consistent(bp);
1239 return -ENOMEM;
1240 }
1241
1242 /* bp->lock is held. */
1243 static void b44_clear_stats(struct b44 *bp)
1244 {
1245 unsigned long reg;
1246
1247 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1248 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1249 br32(bp, reg);
1250 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1251 br32(bp, reg);
1252 }
1253
1254 /* bp->lock is held. */
1255 static void b44_chip_reset(struct b44 *bp)
1256 {
1257 if (ssb_is_core_up(bp)) {
1258 bw32(bp, B44_RCV_LAZY, 0);
1259 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1260 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1261 bw32(bp, B44_DMATX_CTRL, 0);
1262 bp->tx_prod = bp->tx_cons = 0;
1263 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1264 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1265 100, 0);
1266 }
1267 bw32(bp, B44_DMARX_CTRL, 0);
1268 bp->rx_prod = bp->rx_cons = 0;
1269 } else {
1270 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1271 SBINTVEC_ENET0 :
1272 SBINTVEC_ENET1));
1273 }
1274
1275 ssb_core_reset(bp);
1276
1277 b44_clear_stats(bp);
1278
1279 /* Make PHY accessible. */
1280 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1281 (0x0d & MDIO_CTRL_MAXF_MASK)));
1282 br32(bp, B44_MDIO_CTRL);
1283
1284 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1285 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1286 br32(bp, B44_ENET_CTRL);
1287 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1288 } else {
1289 u32 val = br32(bp, B44_DEVCTRL);
1290
1291 if (val & DEVCTRL_EPR) {
1292 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1293 br32(bp, B44_DEVCTRL);
1294 udelay(100);
1295 }
1296 bp->flags |= B44_FLAG_INTERNAL_PHY;
1297 }
1298 }
1299
1300 /* bp->lock is held. */
1301 static void b44_halt(struct b44 *bp)
1302 {
1303 b44_disable_ints(bp);
1304 b44_chip_reset(bp);
1305 }
1306
1307 /* bp->lock is held. */
1308 static void __b44_set_mac_addr(struct b44 *bp)
1309 {
1310 bw32(bp, B44_CAM_CTRL, 0);
1311 if (!(bp->dev->flags & IFF_PROMISC)) {
1312 u32 val;
1313
1314 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1315 val = br32(bp, B44_CAM_CTRL);
1316 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1317 }
1318 }
1319
1320 static int b44_set_mac_addr(struct net_device *dev, void *p)
1321 {
1322 struct b44 *bp = netdev_priv(dev);
1323 struct sockaddr *addr = p;
1324
1325 if (netif_running(dev))
1326 return -EBUSY;
1327
1328 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1329
1330 spin_lock_irq(&bp->lock);
1331 __b44_set_mac_addr(bp);
1332 spin_unlock_irq(&bp->lock);
1333
1334 return 0;
1335 }
1336
1337 /* Called at device open time to get the chip ready for
1338 * packet processing. Invoked with bp->lock held.
1339 */
1340 static void __b44_set_rx_mode(struct net_device *);
1341 static void b44_init_hw(struct b44 *bp)
1342 {
1343 u32 val;
1344
1345 b44_chip_reset(bp);
1346 b44_phy_reset(bp);
1347 b44_setup_phy(bp);
1348
1349 /* Enable CRC32, set proper LED modes and power on PHY */
1350 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1351 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1352
1353 /* This sets the MAC address too. */
1354 __b44_set_rx_mode(bp->dev);
1355
1356 /* MTU + eth header + possible VLAN tag + struct rx_header */
1357 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1358 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1359
1360 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1361 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1362 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1363 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1364 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1365 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1366
1367 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1368 bp->rx_prod = bp->rx_pending;
1369
1370 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1371
1372 val = br32(bp, B44_ENET_CTRL);
1373 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1374 }
1375
1376 static int b44_open(struct net_device *dev)
1377 {
1378 struct b44 *bp = netdev_priv(dev);
1379 int err;
1380
1381 err = b44_alloc_consistent(bp);
1382 if (err)
1383 return err;
1384
1385 err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1386 if (err)
1387 goto err_out_free;
1388
1389 spin_lock_irq(&bp->lock);
1390
1391 b44_init_rings(bp);
1392 b44_init_hw(bp);
1393 bp->flags |= B44_FLAG_INIT_COMPLETE;
1394
1395 netif_carrier_off(dev);
1396 b44_check_phy(bp);
1397
1398 spin_unlock_irq(&bp->lock);
1399
1400 init_timer(&bp->timer);
1401 bp->timer.expires = jiffies + HZ;
1402 bp->timer.data = (unsigned long) bp;
1403 bp->timer.function = b44_timer;
1404 add_timer(&bp->timer);
1405
1406 b44_enable_ints(bp);
1407
1408 return 0;
1409
1410 err_out_free:
1411 b44_free_consistent(bp);
1412 return err;
1413 }
1414
1415 #if 0
1416 /*static*/ void b44_dump_state(struct b44 *bp)
1417 {
1418 u32 val32, val32_2, val32_3, val32_4, val32_5;
1419 u16 val16;
1420
1421 pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1422 printk("DEBUG: PCI status [%04x] \n", val16);
1423
1424 }
1425 #endif
1426
1427 #ifdef CONFIG_NET_POLL_CONTROLLER
1428 /*
1429 * Polling receive - used by netconsole and other diagnostic tools
1430 * to allow network i/o with interrupts disabled.
1431 */
1432 static void b44_poll_controller(struct net_device *dev)
1433 {
1434 disable_irq(dev->irq);
1435 b44_interrupt(dev->irq, dev, NULL);
1436 enable_irq(dev->irq);
1437 }
1438 #endif
1439
1440 static int b44_close(struct net_device *dev)
1441 {
1442 struct b44 *bp = netdev_priv(dev);
1443
1444 netif_stop_queue(dev);
1445
1446 del_timer_sync(&bp->timer);
1447
1448 spin_lock_irq(&bp->lock);
1449
1450 #if 0
1451 b44_dump_state(bp);
1452 #endif
1453 b44_halt(bp);
1454 b44_free_rings(bp);
1455 bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1456 netif_carrier_off(bp->dev);
1457
1458 spin_unlock_irq(&bp->lock);
1459
1460 free_irq(dev->irq, dev);
1461
1462 b44_free_consistent(bp);
1463
1464 return 0;
1465 }
1466
1467 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1468 {
1469 struct b44 *bp = netdev_priv(dev);
1470 struct net_device_stats *nstat = &bp->stats;
1471 struct b44_hw_stats *hwstat = &bp->hw_stats;
1472
1473 /* Convert HW stats into netdevice stats. */
1474 nstat->rx_packets = hwstat->rx_pkts;
1475 nstat->tx_packets = hwstat->tx_pkts;
1476 nstat->rx_bytes = hwstat->rx_octets;
1477 nstat->tx_bytes = hwstat->tx_octets;
1478 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1479 hwstat->tx_oversize_pkts +
1480 hwstat->tx_underruns +
1481 hwstat->tx_excessive_cols +
1482 hwstat->tx_late_cols);
1483 nstat->multicast = hwstat->tx_multicast_pkts;
1484 nstat->collisions = hwstat->tx_total_cols;
1485
1486 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1487 hwstat->rx_undersize);
1488 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1489 nstat->rx_frame_errors = hwstat->rx_align_errs;
1490 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1491 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1492 hwstat->rx_oversize_pkts +
1493 hwstat->rx_missed_pkts +
1494 hwstat->rx_crc_align_errs +
1495 hwstat->rx_undersize +
1496 hwstat->rx_crc_errs +
1497 hwstat->rx_align_errs +
1498 hwstat->rx_symbol_errs);
1499
1500 nstat->tx_aborted_errors = hwstat->tx_underruns;
1501 #if 0
1502 /* Carrier lost counter seems to be broken for some devices */
1503 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1504 #endif
1505
1506 return nstat;
1507 }
1508
1509 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1510 {
1511 struct dev_mc_list *mclist;
1512 int i, num_ents;
1513
1514 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1515 mclist = dev->mc_list;
1516 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1517 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1518 }
1519 return i+1;
1520 }
1521
1522 static void __b44_set_rx_mode(struct net_device *dev)
1523 {
1524 struct b44 *bp = netdev_priv(dev);
1525 u32 val;
1526
1527 val = br32(bp, B44_RXCONFIG);
1528 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1529 if (dev->flags & IFF_PROMISC) {
1530 val |= RXCONFIG_PROMISC;
1531 bw32(bp, B44_RXCONFIG, val);
1532 } else {
1533 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1534 int i = 0;
1535
1536 __b44_set_mac_addr(bp);
1537
1538 if (dev->flags & IFF_ALLMULTI)
1539 val |= RXCONFIG_ALLMULTI;
1540 else
1541 i = __b44_load_mcast(bp, dev);
1542
1543 for (; i < 64; i++) {
1544 __b44_cam_write(bp, zero, i);
1545 }
1546 bw32(bp, B44_RXCONFIG, val);
1547 val = br32(bp, B44_CAM_CTRL);
1548 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1549 }
1550 }
1551
1552 static void b44_set_rx_mode(struct net_device *dev)
1553 {
1554 struct b44 *bp = netdev_priv(dev);
1555
1556 spin_lock_irq(&bp->lock);
1557 __b44_set_rx_mode(dev);
1558 spin_unlock_irq(&bp->lock);
1559 }
1560
1561 static u32 b44_get_msglevel(struct net_device *dev)
1562 {
1563 struct b44 *bp = netdev_priv(dev);
1564 return bp->msg_enable;
1565 }
1566
1567 static void b44_set_msglevel(struct net_device *dev, u32 value)
1568 {
1569 struct b44 *bp = netdev_priv(dev);
1570 bp->msg_enable = value;
1571 }
1572
1573 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1574 {
1575 struct b44 *bp = netdev_priv(dev);
1576 struct pci_dev *pci_dev = bp->pdev;
1577
1578 strcpy (info->driver, DRV_MODULE_NAME);
1579 strcpy (info->version, DRV_MODULE_VERSION);
1580 strcpy (info->bus_info, pci_name(pci_dev));
1581 }
1582
1583 static int b44_nway_reset(struct net_device *dev)
1584 {
1585 struct b44 *bp = netdev_priv(dev);
1586 u32 bmcr;
1587 int r;
1588
1589 spin_lock_irq(&bp->lock);
1590 b44_readphy(bp, MII_BMCR, &bmcr);
1591 b44_readphy(bp, MII_BMCR, &bmcr);
1592 r = -EINVAL;
1593 if (bmcr & BMCR_ANENABLE) {
1594 b44_writephy(bp, MII_BMCR,
1595 bmcr | BMCR_ANRESTART);
1596 r = 0;
1597 }
1598 spin_unlock_irq(&bp->lock);
1599
1600 return r;
1601 }
1602
1603 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1604 {
1605 struct b44 *bp = netdev_priv(dev);
1606
1607 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1608 return -EAGAIN;
1609 cmd->supported = (SUPPORTED_Autoneg);
1610 cmd->supported |= (SUPPORTED_100baseT_Half |
1611 SUPPORTED_100baseT_Full |
1612 SUPPORTED_10baseT_Half |
1613 SUPPORTED_10baseT_Full |
1614 SUPPORTED_MII);
1615
1616 cmd->advertising = 0;
1617 if (bp->flags & B44_FLAG_ADV_10HALF)
1618 cmd->advertising |= ADVERTISED_10baseT_Half;
1619 if (bp->flags & B44_FLAG_ADV_10FULL)
1620 cmd->advertising |= ADVERTISED_10baseT_Full;
1621 if (bp->flags & B44_FLAG_ADV_100HALF)
1622 cmd->advertising |= ADVERTISED_100baseT_Half;
1623 if (bp->flags & B44_FLAG_ADV_100FULL)
1624 cmd->advertising |= ADVERTISED_100baseT_Full;
1625 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1626 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1627 SPEED_100 : SPEED_10;
1628 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1629 DUPLEX_FULL : DUPLEX_HALF;
1630 cmd->port = 0;
1631 cmd->phy_address = bp->phy_addr;
1632 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1633 XCVR_INTERNAL : XCVR_EXTERNAL;
1634 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1635 AUTONEG_DISABLE : AUTONEG_ENABLE;
1636 cmd->maxtxpkt = 0;
1637 cmd->maxrxpkt = 0;
1638 return 0;
1639 }
1640
1641 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1642 {
1643 struct b44 *bp = netdev_priv(dev);
1644
1645 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1646 return -EAGAIN;
1647
1648 /* We do not support gigabit. */
1649 if (cmd->autoneg == AUTONEG_ENABLE) {
1650 if (cmd->advertising &
1651 (ADVERTISED_1000baseT_Half |
1652 ADVERTISED_1000baseT_Full))
1653 return -EINVAL;
1654 } else if ((cmd->speed != SPEED_100 &&
1655 cmd->speed != SPEED_10) ||
1656 (cmd->duplex != DUPLEX_HALF &&
1657 cmd->duplex != DUPLEX_FULL)) {
1658 return -EINVAL;
1659 }
1660
1661 spin_lock_irq(&bp->lock);
1662
1663 if (cmd->autoneg == AUTONEG_ENABLE) {
1664 bp->flags &= ~B44_FLAG_FORCE_LINK;
1665 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1666 B44_FLAG_ADV_10FULL |
1667 B44_FLAG_ADV_100HALF |
1668 B44_FLAG_ADV_100FULL);
1669 if (cmd->advertising & ADVERTISE_10HALF)
1670 bp->flags |= B44_FLAG_ADV_10HALF;
1671 if (cmd->advertising & ADVERTISE_10FULL)
1672 bp->flags |= B44_FLAG_ADV_10FULL;
1673 if (cmd->advertising & ADVERTISE_100HALF)
1674 bp->flags |= B44_FLAG_ADV_100HALF;
1675 if (cmd->advertising & ADVERTISE_100FULL)
1676 bp->flags |= B44_FLAG_ADV_100FULL;
1677 } else {
1678 bp->flags |= B44_FLAG_FORCE_LINK;
1679 if (cmd->speed == SPEED_100)
1680 bp->flags |= B44_FLAG_100_BASE_T;
1681 if (cmd->duplex == DUPLEX_FULL)
1682 bp->flags |= B44_FLAG_FULL_DUPLEX;
1683 }
1684
1685 b44_setup_phy(bp);
1686
1687 spin_unlock_irq(&bp->lock);
1688
1689 return 0;
1690 }
1691
1692 static void b44_get_ringparam(struct net_device *dev,
1693 struct ethtool_ringparam *ering)
1694 {
1695 struct b44 *bp = netdev_priv(dev);
1696
1697 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1698 ering->rx_pending = bp->rx_pending;
1699
1700 /* XXX ethtool lacks a tx_max_pending, oops... */
1701 }
1702
1703 static int b44_set_ringparam(struct net_device *dev,
1704 struct ethtool_ringparam *ering)
1705 {
1706 struct b44 *bp = netdev_priv(dev);
1707
1708 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1709 (ering->rx_mini_pending != 0) ||
1710 (ering->rx_jumbo_pending != 0) ||
1711 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1712 return -EINVAL;
1713
1714 spin_lock_irq(&bp->lock);
1715
1716 bp->rx_pending = ering->rx_pending;
1717 bp->tx_pending = ering->tx_pending;
1718
1719 b44_halt(bp);
1720 b44_init_rings(bp);
1721 b44_init_hw(bp);
1722 netif_wake_queue(bp->dev);
1723 spin_unlock_irq(&bp->lock);
1724
1725 b44_enable_ints(bp);
1726
1727 return 0;
1728 }
1729
1730 static void b44_get_pauseparam(struct net_device *dev,
1731 struct ethtool_pauseparam *epause)
1732 {
1733 struct b44 *bp = netdev_priv(dev);
1734
1735 epause->autoneg =
1736 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1737 epause->rx_pause =
1738 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1739 epause->tx_pause =
1740 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1741 }
1742
1743 static int b44_set_pauseparam(struct net_device *dev,
1744 struct ethtool_pauseparam *epause)
1745 {
1746 struct b44 *bp = netdev_priv(dev);
1747
1748 spin_lock_irq(&bp->lock);
1749 if (epause->autoneg)
1750 bp->flags |= B44_FLAG_PAUSE_AUTO;
1751 else
1752 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1753 if (epause->rx_pause)
1754 bp->flags |= B44_FLAG_RX_PAUSE;
1755 else
1756 bp->flags &= ~B44_FLAG_RX_PAUSE;
1757 if (epause->tx_pause)
1758 bp->flags |= B44_FLAG_TX_PAUSE;
1759 else
1760 bp->flags &= ~B44_FLAG_TX_PAUSE;
1761 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1762 b44_halt(bp);
1763 b44_init_rings(bp);
1764 b44_init_hw(bp);
1765 } else {
1766 __b44_set_flow_ctrl(bp, bp->flags);
1767 }
1768 spin_unlock_irq(&bp->lock);
1769
1770 b44_enable_ints(bp);
1771
1772 return 0;
1773 }
1774
1775 static struct ethtool_ops b44_ethtool_ops = {
1776 .get_drvinfo = b44_get_drvinfo,
1777 .get_settings = b44_get_settings,
1778 .set_settings = b44_set_settings,
1779 .nway_reset = b44_nway_reset,
1780 .get_link = ethtool_op_get_link,
1781 .get_ringparam = b44_get_ringparam,
1782 .set_ringparam = b44_set_ringparam,
1783 .get_pauseparam = b44_get_pauseparam,
1784 .set_pauseparam = b44_set_pauseparam,
1785 .get_msglevel = b44_get_msglevel,
1786 .set_msglevel = b44_set_msglevel,
1787 .get_perm_addr = ethtool_op_get_perm_addr,
1788 };
1789
1790 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1791 {
1792 struct mii_ioctl_data *data = if_mii(ifr);
1793 struct b44 *bp = netdev_priv(dev);
1794 int err;
1795
1796 spin_lock_irq(&bp->lock);
1797 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1798 spin_unlock_irq(&bp->lock);
1799
1800 return err;
1801 }
1802
1803 /* Read 128-bytes of EEPROM. */
1804 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1805 {
1806 long i;
1807 u16 *ptr = (u16 *) data;
1808
1809 for (i = 0; i < 128; i += 2)
1810 ptr[i / 2] = readw(bp->regs + 4096 + i);
1811
1812 return 0;
1813 }
1814
1815 static int __devinit b44_get_invariants(struct b44 *bp)
1816 {
1817 u8 eeprom[128];
1818 int err;
1819
1820 err = b44_read_eeprom(bp, &eeprom[0]);
1821 if (err)
1822 goto out;
1823
1824 bp->dev->dev_addr[0] = eeprom[79];
1825 bp->dev->dev_addr[1] = eeprom[78];
1826 bp->dev->dev_addr[2] = eeprom[81];
1827 bp->dev->dev_addr[3] = eeprom[80];
1828 bp->dev->dev_addr[4] = eeprom[83];
1829 bp->dev->dev_addr[5] = eeprom[82];
1830 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1831
1832 bp->phy_addr = eeprom[90] & 0x1f;
1833
1834 /* With this, plus the rx_header prepended to the data by the
1835 * hardware, we'll land the ethernet header on a 2-byte boundary.
1836 */
1837 bp->rx_offset = 30;
1838
1839 bp->imask = IMASK_DEF;
1840
1841 bp->core_unit = ssb_core_unit(bp);
1842 bp->dma_offset = SB_PCI_DMA;
1843
1844 /* XXX - really required?
1845 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1846 */
1847 out:
1848 return err;
1849 }
1850
1851 static int __devinit b44_init_one(struct pci_dev *pdev,
1852 const struct pci_device_id *ent)
1853 {
1854 static int b44_version_printed = 0;
1855 unsigned long b44reg_base, b44reg_len;
1856 struct net_device *dev;
1857 struct b44 *bp;
1858 int err, i;
1859
1860 if (b44_version_printed++ == 0)
1861 printk(KERN_INFO "%s", version);
1862
1863 err = pci_enable_device(pdev);
1864 if (err) {
1865 printk(KERN_ERR PFX "Cannot enable PCI device, "
1866 "aborting.\n");
1867 return err;
1868 }
1869
1870 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1871 printk(KERN_ERR PFX "Cannot find proper PCI device "
1872 "base address, aborting.\n");
1873 err = -ENODEV;
1874 goto err_out_disable_pdev;
1875 }
1876
1877 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1878 if (err) {
1879 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1880 "aborting.\n");
1881 goto err_out_disable_pdev;
1882 }
1883
1884 pci_set_master(pdev);
1885
1886 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1887 if (err) {
1888 printk(KERN_ERR PFX "No usable DMA configuration, "
1889 "aborting.\n");
1890 goto err_out_free_res;
1891 }
1892
1893 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1894 if (err) {
1895 printk(KERN_ERR PFX "No usable DMA configuration, "
1896 "aborting.\n");
1897 goto err_out_free_res;
1898 }
1899
1900 b44reg_base = pci_resource_start(pdev, 0);
1901 b44reg_len = pci_resource_len(pdev, 0);
1902
1903 dev = alloc_etherdev(sizeof(*bp));
1904 if (!dev) {
1905 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1906 err = -ENOMEM;
1907 goto err_out_free_res;
1908 }
1909
1910 SET_MODULE_OWNER(dev);
1911 SET_NETDEV_DEV(dev,&pdev->dev);
1912
1913 /* No interesting netdevice features in this card... */
1914 dev->features |= 0;
1915
1916 bp = netdev_priv(dev);
1917 bp->pdev = pdev;
1918 bp->dev = dev;
1919
1920 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1921
1922 spin_lock_init(&bp->lock);
1923
1924 bp->regs = ioremap(b44reg_base, b44reg_len);
1925 if (bp->regs == 0UL) {
1926 printk(KERN_ERR PFX "Cannot map device registers, "
1927 "aborting.\n");
1928 err = -ENOMEM;
1929 goto err_out_free_dev;
1930 }
1931
1932 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1933 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1934
1935 dev->open = b44_open;
1936 dev->stop = b44_close;
1937 dev->hard_start_xmit = b44_start_xmit;
1938 dev->get_stats = b44_get_stats;
1939 dev->set_multicast_list = b44_set_rx_mode;
1940 dev->set_mac_address = b44_set_mac_addr;
1941 dev->do_ioctl = b44_ioctl;
1942 dev->tx_timeout = b44_tx_timeout;
1943 dev->poll = b44_poll;
1944 dev->weight = 64;
1945 dev->watchdog_timeo = B44_TX_TIMEOUT;
1946 #ifdef CONFIG_NET_POLL_CONTROLLER
1947 dev->poll_controller = b44_poll_controller;
1948 #endif
1949 dev->change_mtu = b44_change_mtu;
1950 dev->irq = pdev->irq;
1951 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1952
1953 err = b44_get_invariants(bp);
1954 if (err) {
1955 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1956 "aborting.\n");
1957 goto err_out_iounmap;
1958 }
1959
1960 bp->mii_if.dev = dev;
1961 bp->mii_if.mdio_read = b44_mii_read;
1962 bp->mii_if.mdio_write = b44_mii_write;
1963 bp->mii_if.phy_id = bp->phy_addr;
1964 bp->mii_if.phy_id_mask = 0x1f;
1965 bp->mii_if.reg_num_mask = 0x1f;
1966
1967 /* By default, advertise all speed/duplex settings. */
1968 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
1969 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
1970
1971 /* By default, auto-negotiate PAUSE. */
1972 bp->flags |= B44_FLAG_PAUSE_AUTO;
1973
1974 err = register_netdev(dev);
1975 if (err) {
1976 printk(KERN_ERR PFX "Cannot register net device, "
1977 "aborting.\n");
1978 goto err_out_iounmap;
1979 }
1980
1981 pci_set_drvdata(pdev, dev);
1982
1983 pci_save_state(bp->pdev);
1984
1985 printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1986 for (i = 0; i < 6; i++)
1987 printk("%2.2x%c", dev->dev_addr[i],
1988 i == 5 ? '\n' : ':');
1989
1990 return 0;
1991
1992 err_out_iounmap:
1993 iounmap(bp->regs);
1994
1995 err_out_free_dev:
1996 free_netdev(dev);
1997
1998 err_out_free_res:
1999 pci_release_regions(pdev);
2000
2001 err_out_disable_pdev:
2002 pci_disable_device(pdev);
2003 pci_set_drvdata(pdev, NULL);
2004 return err;
2005 }
2006
2007 static void __devexit b44_remove_one(struct pci_dev *pdev)
2008 {
2009 struct net_device *dev = pci_get_drvdata(pdev);
2010 struct b44 *bp = netdev_priv(dev);
2011
2012 unregister_netdev(dev);
2013 iounmap(bp->regs);
2014 free_netdev(dev);
2015 pci_release_regions(pdev);
2016 pci_disable_device(pdev);
2017 pci_set_drvdata(pdev, NULL);
2018 }
2019
2020 static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2021 {
2022 struct net_device *dev = pci_get_drvdata(pdev);
2023 struct b44 *bp = netdev_priv(dev);
2024
2025 if (!netif_running(dev))
2026 return 0;
2027
2028 del_timer_sync(&bp->timer);
2029
2030 spin_lock_irq(&bp->lock);
2031
2032 b44_halt(bp);
2033 netif_carrier_off(bp->dev);
2034 netif_device_detach(bp->dev);
2035 b44_free_rings(bp);
2036
2037 spin_unlock_irq(&bp->lock);
2038
2039 free_irq(dev->irq, dev);
2040 pci_disable_device(pdev);
2041 return 0;
2042 }
2043
2044 static int b44_resume(struct pci_dev *pdev)
2045 {
2046 struct net_device *dev = pci_get_drvdata(pdev);
2047 struct b44 *bp = netdev_priv(dev);
2048
2049 pci_restore_state(pdev);
2050 pci_enable_device(pdev);
2051 pci_set_master(pdev);
2052
2053 if (!netif_running(dev))
2054 return 0;
2055
2056 if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
2057 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2058
2059 spin_lock_irq(&bp->lock);
2060
2061 b44_init_rings(bp);
2062 b44_init_hw(bp);
2063 netif_device_attach(bp->dev);
2064 spin_unlock_irq(&bp->lock);
2065
2066 bp->timer.expires = jiffies + HZ;
2067 add_timer(&bp->timer);
2068
2069 b44_enable_ints(bp);
2070 return 0;
2071 }
2072
2073 static struct pci_driver b44_driver = {
2074 .name = DRV_MODULE_NAME,
2075 .id_table = b44_pci_tbl,
2076 .probe = b44_init_one,
2077 .remove = __devexit_p(b44_remove_one),
2078 .suspend = b44_suspend,
2079 .resume = b44_resume,
2080 };
2081
2082 static int __init b44_init(void)
2083 {
2084 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2085
2086 /* Setup paramaters for syncing RX/TX DMA descriptors */
2087 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2088 dma_desc_sync_size = max(dma_desc_align_size, sizeof(struct dma_desc));
2089
2090 return pci_module_init(&b44_driver);
2091 }
2092
2093 static void __exit b44_cleanup(void)
2094 {
2095 pci_unregister_driver(&b44_driver);
2096 }
2097
2098 module_init(b44_init);
2099 module_exit(b44_cleanup);
2100
WandBoard kernel