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[SPARC64]: Add boot option to force UltraSPARC-III P-Cache on.
[wandboard.git] / arch / sparc64 / kernel / traps.c
bloba9f4596d7c2bcd82419386d808b5f35d69d2a46a
1 /* $Id: traps.c,v 1.85 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/kernel/traps.c
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 /*
9 * I like traps on v9, :))))
10 */
11
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/sched.h> /* for jiffies */
15 #include <linux/kernel.h>
16 #include <linux/kallsyms.h>
17 #include <linux/signal.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/mm.h>
21 #include <linux/init.h>
22
23 #include <asm/delay.h>
24 #include <asm/system.h>
25 #include <asm/ptrace.h>
26 #include <asm/oplib.h>
27 #include <asm/page.h>
28 #include <asm/pgtable.h>
29 #include <asm/unistd.h>
30 #include <asm/uaccess.h>
31 #include <asm/fpumacro.h>
32 #include <asm/lsu.h>
33 #include <asm/dcu.h>
34 #include <asm/estate.h>
35 #include <asm/chafsr.h>
36 #include <asm/psrcompat.h>
37 #include <asm/processor.h>
38 #include <asm/timer.h>
39 #include <asm/kdebug.h>
40 #ifdef CONFIG_KMOD
41 #include <linux/kmod.h>
42 #endif
43
44 struct notifier_block *sparc64die_chain;
45 static DEFINE_SPINLOCK(die_notifier_lock);
46
47 int register_die_notifier(struct notifier_block *nb)
48 {
49 int err = 0;
50 unsigned long flags;
51 spin_lock_irqsave(&die_notifier_lock, flags);
52 err = notifier_chain_register(&sparc64die_chain, nb);
53 spin_unlock_irqrestore(&die_notifier_lock, flags);
54 return err;
55 }
56
57 /* When an irrecoverable trap occurs at tl > 0, the trap entry
58 * code logs the trap state registers at every level in the trap
59 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
60 * is as follows:
61 */
62 struct tl1_traplog {
63 struct {
64 unsigned long tstate;
65 unsigned long tpc;
66 unsigned long tnpc;
67 unsigned long tt;
68 } trapstack[4];
69 unsigned long tl;
70 };
71
72 static void dump_tl1_traplog(struct tl1_traplog *p)
73 {
74 int i;
75
76 printk("TRAPLOG: Error at trap level 0x%lx, dumping track stack.\n",
77 p->tl);
78 for (i = 0; i < 4; i++) {
79 printk(KERN_CRIT
80 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
81 "TNPC[%016lx] TT[%lx]\n",
82 i + 1,
83 p->trapstack[i].tstate, p->trapstack[i].tpc,
84 p->trapstack[i].tnpc, p->trapstack[i].tt);
85 }
86 }
87
88 void do_call_debug(struct pt_regs *regs)
89 {
90 notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
91 }
92
93 void bad_trap(struct pt_regs *regs, long lvl)
94 {
95 char buffer[32];
96 siginfo_t info;
97
98 if (notify_die(DIE_TRAP, "bad trap", regs,
99 0, lvl, SIGTRAP) == NOTIFY_STOP)
100 return;
101
102 if (lvl < 0x100) {
103 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
104 die_if_kernel(buffer, regs);
105 }
106
107 lvl -= 0x100;
108 if (regs->tstate & TSTATE_PRIV) {
109 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
110 die_if_kernel(buffer, regs);
111 }
112 if (test_thread_flag(TIF_32BIT)) {
113 regs->tpc &= 0xffffffff;
114 regs->tnpc &= 0xffffffff;
115 }
116 info.si_signo = SIGILL;
117 info.si_errno = 0;
118 info.si_code = ILL_ILLTRP;
119 info.si_addr = (void __user *)regs->tpc;
120 info.si_trapno = lvl;
121 force_sig_info(SIGILL, &info, current);
122 }
123
124 void bad_trap_tl1(struct pt_regs *regs, long lvl)
125 {
126 char buffer[32];
127
128 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
129 0, lvl, SIGTRAP) == NOTIFY_STOP)
130 return;
131
132 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
133
134 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
135 die_if_kernel (buffer, regs);
136 }
137
138 #ifdef CONFIG_DEBUG_BUGVERBOSE
139 void do_BUG(const char *file, int line)
140 {
141 bust_spinlocks(1);
142 printk("kernel BUG at %s:%d!\n", file, line);
143 }
144 #endif
145
146 void instruction_access_exception(struct pt_regs *regs,
147 unsigned long sfsr, unsigned long sfar)
148 {
149 siginfo_t info;
150
151 if (notify_die(DIE_TRAP, "instruction access exception", regs,
152 0, 0x8, SIGTRAP) == NOTIFY_STOP)
153 return;
154
155 if (regs->tstate & TSTATE_PRIV) {
156 printk("instruction_access_exception: SFSR[%016lx] SFAR[%016lx], going.\n",
157 sfsr, sfar);
158 die_if_kernel("Iax", regs);
159 }
160 if (test_thread_flag(TIF_32BIT)) {
161 regs->tpc &= 0xffffffff;
162 regs->tnpc &= 0xffffffff;
163 }
164 info.si_signo = SIGSEGV;
165 info.si_errno = 0;
166 info.si_code = SEGV_MAPERR;
167 info.si_addr = (void __user *)regs->tpc;
168 info.si_trapno = 0;
169 force_sig_info(SIGSEGV, &info, current);
170 }
171
172 void instruction_access_exception_tl1(struct pt_regs *regs,
173 unsigned long sfsr, unsigned long sfar)
174 {
175 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
176 0, 0x8, SIGTRAP) == NOTIFY_STOP)
177 return;
178
179 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
180 instruction_access_exception(regs, sfsr, sfar);
181 }
182
183 void data_access_exception(struct pt_regs *regs,
184 unsigned long sfsr, unsigned long sfar)
185 {
186 siginfo_t info;
187
188 if (notify_die(DIE_TRAP, "data access exception", regs,
189 0, 0x30, SIGTRAP) == NOTIFY_STOP)
190 return;
191
192 if (regs->tstate & TSTATE_PRIV) {
193 /* Test if this comes from uaccess places. */
194 unsigned long fixup;
195 unsigned long g2 = regs->u_regs[UREG_G2];
196
197 if ((fixup = search_extables_range(regs->tpc, &g2))) {
198 /* Ouch, somebody is trying ugly VM hole tricks on us... */
199 #ifdef DEBUG_EXCEPTIONS
200 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
201 printk("EX_TABLE: insn<%016lx> fixup<%016lx> "
202 "g2<%016lx>\n", regs->tpc, fixup, g2);
203 #endif
204 regs->tpc = fixup;
205 regs->tnpc = regs->tpc + 4;
206 regs->u_regs[UREG_G2] = g2;
207 return;
208 }
209 /* Shit... */
210 printk("data_access_exception: SFSR[%016lx] SFAR[%016lx], going.\n",
211 sfsr, sfar);
212 die_if_kernel("Dax", regs);
213 }
214
215 info.si_signo = SIGSEGV;
216 info.si_errno = 0;
217 info.si_code = SEGV_MAPERR;
218 info.si_addr = (void __user *)sfar;
219 info.si_trapno = 0;
220 force_sig_info(SIGSEGV, &info, current);
221 }
222
223 #ifdef CONFIG_PCI
224 /* This is really pathetic... */
225 extern volatile int pci_poke_in_progress;
226 extern volatile int pci_poke_cpu;
227 extern volatile int pci_poke_faulted;
228 #endif
229
230 /* When access exceptions happen, we must do this. */
231 static void spitfire_clean_and_reenable_l1_caches(void)
232 {
233 unsigned long va;
234
235 if (tlb_type != spitfire)
236 BUG();
237
238 /* Clean 'em. */
239 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
240 spitfire_put_icache_tag(va, 0x0);
241 spitfire_put_dcache_tag(va, 0x0);
242 }
243
244 /* Re-enable in LSU. */
245 __asm__ __volatile__("flush %%g6\n\t"
246 "membar #Sync\n\t"
247 "stxa %0, [%%g0] %1\n\t"
248 "membar #Sync"
249 : /* no outputs */
250 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
251 LSU_CONTROL_IM | LSU_CONTROL_DM),
252 "i" (ASI_LSU_CONTROL)
253 : "memory");
254 }
255
256 void do_iae(struct pt_regs *regs)
257 {
258 siginfo_t info;
259
260 spitfire_clean_and_reenable_l1_caches();
261
262 if (notify_die(DIE_TRAP, "instruction access exception", regs,
263 0, 0x8, SIGTRAP) == NOTIFY_STOP)
264 return;
265
266 info.si_signo = SIGBUS;
267 info.si_errno = 0;
268 info.si_code = BUS_OBJERR;
269 info.si_addr = (void *)0;
270 info.si_trapno = 0;
271 force_sig_info(SIGBUS, &info, current);
272 }
273
274 void do_dae(struct pt_regs *regs)
275 {
276 siginfo_t info;
277
278 #ifdef CONFIG_PCI
279 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
280 spitfire_clean_and_reenable_l1_caches();
281
282 pci_poke_faulted = 1;
283
284 /* Why the fuck did they have to change this? */
285 if (tlb_type == cheetah || tlb_type == cheetah_plus)
286 regs->tpc += 4;
287
288 regs->tnpc = regs->tpc + 4;
289 return;
290 }
291 #endif
292 spitfire_clean_and_reenable_l1_caches();
293
294 if (notify_die(DIE_TRAP, "data access exception", regs,
295 0, 0x30, SIGTRAP) == NOTIFY_STOP)
296 return;
297
298 info.si_signo = SIGBUS;
299 info.si_errno = 0;
300 info.si_code = BUS_OBJERR;
301 info.si_addr = (void *)0;
302 info.si_trapno = 0;
303 force_sig_info(SIGBUS, &info, current);
304 }
305
306 static char ecc_syndrome_table[] = {
307 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
308 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
309 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
310 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
311 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
312 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
313 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
314 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
315 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
316 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
317 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
318 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
319 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
320 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
321 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
322 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
323 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
324 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
325 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
326 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
327 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
328 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
329 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
330 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
331 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
332 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
333 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
334 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
335 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
336 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
337 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
338 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
339 };
340
341 /* cee_trap in entry.S encodes AFSR/UDBH/UDBL error status
342 * in the following format. The AFAR is left as is, with
343 * reserved bits cleared, and is a raw 40-bit physical
344 * address.
345 */
346 #define CE_STATUS_UDBH_UE (1UL << (43 + 9))
347 #define CE_STATUS_UDBH_CE (1UL << (43 + 8))
348 #define CE_STATUS_UDBH_ESYNDR (0xffUL << 43)
349 #define CE_STATUS_UDBH_SHIFT 43
350 #define CE_STATUS_UDBL_UE (1UL << (33 + 9))
351 #define CE_STATUS_UDBL_CE (1UL << (33 + 8))
352 #define CE_STATUS_UDBL_ESYNDR (0xffUL << 33)
353 #define CE_STATUS_UDBL_SHIFT 33
354 #define CE_STATUS_AFSR_MASK (0x1ffffffffUL)
355 #define CE_STATUS_AFSR_ME (1UL << 32)
356 #define CE_STATUS_AFSR_PRIV (1UL << 31)
357 #define CE_STATUS_AFSR_ISAP (1UL << 30)
358 #define CE_STATUS_AFSR_ETP (1UL << 29)
359 #define CE_STATUS_AFSR_IVUE (1UL << 28)
360 #define CE_STATUS_AFSR_TO (1UL << 27)
361 #define CE_STATUS_AFSR_BERR (1UL << 26)
362 #define CE_STATUS_AFSR_LDP (1UL << 25)
363 #define CE_STATUS_AFSR_CP (1UL << 24)
364 #define CE_STATUS_AFSR_WP (1UL << 23)
365 #define CE_STATUS_AFSR_EDP (1UL << 22)
366 #define CE_STATUS_AFSR_UE (1UL << 21)
367 #define CE_STATUS_AFSR_CE (1UL << 20)
368 #define CE_STATUS_AFSR_ETS (0xfUL << 16)
369 #define CE_STATUS_AFSR_ETS_SHIFT 16
370 #define CE_STATUS_AFSR_PSYND (0xffffUL << 0)
371 #define CE_STATUS_AFSR_PSYND_SHIFT 0
372
373 /* Layout of Ecache TAG Parity Syndrome of AFSR */
374 #define AFSR_ETSYNDROME_7_0 0x1UL /* E$-tag bus bits <7:0> */
375 #define AFSR_ETSYNDROME_15_8 0x2UL /* E$-tag bus bits <15:8> */
376 #define AFSR_ETSYNDROME_21_16 0x4UL /* E$-tag bus bits <21:16> */
377 #define AFSR_ETSYNDROME_24_22 0x8UL /* E$-tag bus bits <24:22> */
378
379 static char *syndrome_unknown = "<Unknown>";
380
381 asmlinkage void cee_log(unsigned long ce_status,
382 unsigned long afar,
383 struct pt_regs *regs)
384 {
385 char memmod_str[64];
386 char *p;
387 unsigned short scode, udb_reg;
388
389 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
390 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx]\n",
391 smp_processor_id(),
392 (ce_status & CE_STATUS_AFSR_MASK),
393 afar,
394 ((ce_status >> CE_STATUS_UDBL_SHIFT) & 0x3ffUL),
395 ((ce_status >> CE_STATUS_UDBH_SHIFT) & 0x3ffUL));
396
397 udb_reg = ((ce_status >> CE_STATUS_UDBL_SHIFT) & 0x3ffUL);
398 if (udb_reg & (1 << 8)) {
399 scode = ecc_syndrome_table[udb_reg & 0xff];
400 if (prom_getunumber(scode, afar,
401 memmod_str, sizeof(memmod_str)) == -1)
402 p = syndrome_unknown;
403 else
404 p = memmod_str;
405 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
406 "Memory Module \"%s\"\n",
407 smp_processor_id(), scode, p);
408 }
409
410 udb_reg = ((ce_status >> CE_STATUS_UDBH_SHIFT) & 0x3ffUL);
411 if (udb_reg & (1 << 8)) {
412 scode = ecc_syndrome_table[udb_reg & 0xff];
413 if (prom_getunumber(scode, afar,
414 memmod_str, sizeof(memmod_str)) == -1)
415 p = syndrome_unknown;
416 else
417 p = memmod_str;
418 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
419 "Memory Module \"%s\"\n",
420 smp_processor_id(), scode, p);
421 }
422 }
423
424 int cheetah_pcache_forced_on;
425
426 void cheetah_enable_pcache(void)
427 {
428 unsigned long dcr;
429
430 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
431 smp_processor_id());
432
433 __asm__ __volatile__("ldxa [%%g0] %1, %0"
434 : "=r" (dcr)
435 : "i" (ASI_DCU_CONTROL_REG));
436 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
437 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
438 "membar #Sync"
439 : /* no outputs */
440 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
441 }
442
443 /* Cheetah error trap handling. */
444 static unsigned long ecache_flush_physbase;
445 static unsigned long ecache_flush_linesize;
446 static unsigned long ecache_flush_size;
447
448 /* WARNING: The error trap handlers in assembly know the precise
449 * layout of the following structure.
450 *
451 * C-level handlers below use this information to log the error
452 * and then determine how to recover (if possible).
453 */
454 struct cheetah_err_info {
455 /*0x00*/u64 afsr;
456 /*0x08*/u64 afar;
457
458 /* D-cache state */
459 /*0x10*/u64 dcache_data[4]; /* The actual data */
460 /*0x30*/u64 dcache_index; /* D-cache index */
461 /*0x38*/u64 dcache_tag; /* D-cache tag/valid */
462 /*0x40*/u64 dcache_utag; /* D-cache microtag */
463 /*0x48*/u64 dcache_stag; /* D-cache snooptag */
464
465 /* I-cache state */
466 /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
467 /*0x90*/u64 icache_index; /* I-cache index */
468 /*0x98*/u64 icache_tag; /* I-cache phys tag */
469 /*0xa0*/u64 icache_utag; /* I-cache microtag */
470 /*0xa8*/u64 icache_stag; /* I-cache snooptag */
471 /*0xb0*/u64 icache_upper; /* I-cache upper-tag */
472 /*0xb8*/u64 icache_lower; /* I-cache lower-tag */
473
474 /* E-cache state */
475 /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
476 /*0xe0*/u64 ecache_index; /* E-cache index */
477 /*0xe8*/u64 ecache_tag; /* E-cache tag/state */
478
479 /*0xf0*/u64 __pad[32 - 30];
480 };
481 #define CHAFSR_INVALID ((u64)-1L)
482
483 /* This table is ordered in priority of errors and matches the
484 * AFAR overwrite policy as well.
485 */
486
487 struct afsr_error_table {
488 unsigned long mask;
489 const char *name;
490 };
491
492 static const char CHAFSR_PERR_msg[] =
493 "System interface protocol error";
494 static const char CHAFSR_IERR_msg[] =
495 "Internal processor error";
496 static const char CHAFSR_ISAP_msg[] =
497 "System request parity error on incoming addresss";
498 static const char CHAFSR_UCU_msg[] =
499 "Uncorrectable E-cache ECC error for ifetch/data";
500 static const char CHAFSR_UCC_msg[] =
501 "SW Correctable E-cache ECC error for ifetch/data";
502 static const char CHAFSR_UE_msg[] =
503 "Uncorrectable system bus data ECC error for read";
504 static const char CHAFSR_EDU_msg[] =
505 "Uncorrectable E-cache ECC error for stmerge/blkld";
506 static const char CHAFSR_EMU_msg[] =
507 "Uncorrectable system bus MTAG error";
508 static const char CHAFSR_WDU_msg[] =
509 "Uncorrectable E-cache ECC error for writeback";
510 static const char CHAFSR_CPU_msg[] =
511 "Uncorrectable ECC error for copyout";
512 static const char CHAFSR_CE_msg[] =
513 "HW corrected system bus data ECC error for read";
514 static const char CHAFSR_EDC_msg[] =
515 "HW corrected E-cache ECC error for stmerge/blkld";
516 static const char CHAFSR_EMC_msg[] =
517 "HW corrected system bus MTAG ECC error";
518 static const char CHAFSR_WDC_msg[] =
519 "HW corrected E-cache ECC error for writeback";
520 static const char CHAFSR_CPC_msg[] =
521 "HW corrected ECC error for copyout";
522 static const char CHAFSR_TO_msg[] =
523 "Unmapped error from system bus";
524 static const char CHAFSR_BERR_msg[] =
525 "Bus error response from system bus";
526 static const char CHAFSR_IVC_msg[] =
527 "HW corrected system bus data ECC error for ivec read";
528 static const char CHAFSR_IVU_msg[] =
529 "Uncorrectable system bus data ECC error for ivec read";
530 static struct afsr_error_table __cheetah_error_table[] = {
531 { CHAFSR_PERR, CHAFSR_PERR_msg },
532 { CHAFSR_IERR, CHAFSR_IERR_msg },
533 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
534 { CHAFSR_UCU, CHAFSR_UCU_msg },
535 { CHAFSR_UCC, CHAFSR_UCC_msg },
536 { CHAFSR_UE, CHAFSR_UE_msg },
537 { CHAFSR_EDU, CHAFSR_EDU_msg },
538 { CHAFSR_EMU, CHAFSR_EMU_msg },
539 { CHAFSR_WDU, CHAFSR_WDU_msg },
540 { CHAFSR_CPU, CHAFSR_CPU_msg },
541 { CHAFSR_CE, CHAFSR_CE_msg },
542 { CHAFSR_EDC, CHAFSR_EDC_msg },
543 { CHAFSR_EMC, CHAFSR_EMC_msg },
544 { CHAFSR_WDC, CHAFSR_WDC_msg },
545 { CHAFSR_CPC, CHAFSR_CPC_msg },
546 { CHAFSR_TO, CHAFSR_TO_msg },
547 { CHAFSR_BERR, CHAFSR_BERR_msg },
548 /* These two do not update the AFAR. */
549 { CHAFSR_IVC, CHAFSR_IVC_msg },
550 { CHAFSR_IVU, CHAFSR_IVU_msg },
551 { 0, NULL },
552 };
553 static const char CHPAFSR_DTO_msg[] =
554 "System bus unmapped error for prefetch/storequeue-read";
555 static const char CHPAFSR_DBERR_msg[] =
556 "System bus error for prefetch/storequeue-read";
557 static const char CHPAFSR_THCE_msg[] =
558 "Hardware corrected E-cache Tag ECC error";
559 static const char CHPAFSR_TSCE_msg[] =
560 "SW handled correctable E-cache Tag ECC error";
561 static const char CHPAFSR_TUE_msg[] =
562 "Uncorrectable E-cache Tag ECC error";
563 static const char CHPAFSR_DUE_msg[] =
564 "System bus uncorrectable data ECC error due to prefetch/store-fill";
565 static struct afsr_error_table __cheetah_plus_error_table[] = {
566 { CHAFSR_PERR, CHAFSR_PERR_msg },
567 { CHAFSR_IERR, CHAFSR_IERR_msg },
568 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
569 { CHAFSR_UCU, CHAFSR_UCU_msg },
570 { CHAFSR_UCC, CHAFSR_UCC_msg },
571 { CHAFSR_UE, CHAFSR_UE_msg },
572 { CHAFSR_EDU, CHAFSR_EDU_msg },
573 { CHAFSR_EMU, CHAFSR_EMU_msg },
574 { CHAFSR_WDU, CHAFSR_WDU_msg },
575 { CHAFSR_CPU, CHAFSR_CPU_msg },
576 { CHAFSR_CE, CHAFSR_CE_msg },
577 { CHAFSR_EDC, CHAFSR_EDC_msg },
578 { CHAFSR_EMC, CHAFSR_EMC_msg },
579 { CHAFSR_WDC, CHAFSR_WDC_msg },
580 { CHAFSR_CPC, CHAFSR_CPC_msg },
581 { CHAFSR_TO, CHAFSR_TO_msg },
582 { CHAFSR_BERR, CHAFSR_BERR_msg },
583 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
584 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
585 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
586 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
587 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
588 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
589 /* These two do not update the AFAR. */
590 { CHAFSR_IVC, CHAFSR_IVC_msg },
591 { CHAFSR_IVU, CHAFSR_IVU_msg },
592 { 0, NULL },
593 };
594 static const char JPAFSR_JETO_msg[] =
595 "System interface protocol error, hw timeout caused";
596 static const char JPAFSR_SCE_msg[] =
597 "Parity error on system snoop results";
598 static const char JPAFSR_JEIC_msg[] =
599 "System interface protocol error, illegal command detected";
600 static const char JPAFSR_JEIT_msg[] =
601 "System interface protocol error, illegal ADTYPE detected";
602 static const char JPAFSR_OM_msg[] =
603 "Out of range memory error has occurred";
604 static const char JPAFSR_ETP_msg[] =
605 "Parity error on L2 cache tag SRAM";
606 static const char JPAFSR_UMS_msg[] =
607 "Error due to unsupported store";
608 static const char JPAFSR_RUE_msg[] =
609 "Uncorrectable ECC error from remote cache/memory";
610 static const char JPAFSR_RCE_msg[] =
611 "Correctable ECC error from remote cache/memory";
612 static const char JPAFSR_BP_msg[] =
613 "JBUS parity error on returned read data";
614 static const char JPAFSR_WBP_msg[] =
615 "JBUS parity error on data for writeback or block store";
616 static const char JPAFSR_FRC_msg[] =
617 "Foreign read to DRAM incurring correctable ECC error";
618 static const char JPAFSR_FRU_msg[] =
619 "Foreign read to DRAM incurring uncorrectable ECC error";
620 static struct afsr_error_table __jalapeno_error_table[] = {
621 { JPAFSR_JETO, JPAFSR_JETO_msg },
622 { JPAFSR_SCE, JPAFSR_SCE_msg },
623 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
624 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
625 { CHAFSR_PERR, CHAFSR_PERR_msg },
626 { CHAFSR_IERR, CHAFSR_IERR_msg },
627 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
628 { CHAFSR_UCU, CHAFSR_UCU_msg },
629 { CHAFSR_UCC, CHAFSR_UCC_msg },
630 { CHAFSR_UE, CHAFSR_UE_msg },
631 { CHAFSR_EDU, CHAFSR_EDU_msg },
632 { JPAFSR_OM, JPAFSR_OM_msg },
633 { CHAFSR_WDU, CHAFSR_WDU_msg },
634 { CHAFSR_CPU, CHAFSR_CPU_msg },
635 { CHAFSR_CE, CHAFSR_CE_msg },
636 { CHAFSR_EDC, CHAFSR_EDC_msg },
637 { JPAFSR_ETP, JPAFSR_ETP_msg },
638 { CHAFSR_WDC, CHAFSR_WDC_msg },
639 { CHAFSR_CPC, CHAFSR_CPC_msg },
640 { CHAFSR_TO, CHAFSR_TO_msg },
641 { CHAFSR_BERR, CHAFSR_BERR_msg },
642 { JPAFSR_UMS, JPAFSR_UMS_msg },
643 { JPAFSR_RUE, JPAFSR_RUE_msg },
644 { JPAFSR_RCE, JPAFSR_RCE_msg },
645 { JPAFSR_BP, JPAFSR_BP_msg },
646 { JPAFSR_WBP, JPAFSR_WBP_msg },
647 { JPAFSR_FRC, JPAFSR_FRC_msg },
648 { JPAFSR_FRU, JPAFSR_FRU_msg },
649 /* These two do not update the AFAR. */
650 { CHAFSR_IVU, CHAFSR_IVU_msg },
651 { 0, NULL },
652 };
653 static struct afsr_error_table *cheetah_error_table;
654 static unsigned long cheetah_afsr_errors;
655
656 /* This is allocated at boot time based upon the largest hardware
657 * cpu ID in the system. We allocate two entries per cpu, one for
658 * TL==0 logging and one for TL >= 1 logging.
659 */
660 struct cheetah_err_info *cheetah_error_log;
661
662 static __inline__ struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
663 {
664 struct cheetah_err_info *p;
665 int cpu = smp_processor_id();
666
667 if (!cheetah_error_log)
668 return NULL;
669
670 p = cheetah_error_log + (cpu * 2);
671 if ((afsr & CHAFSR_TL1) != 0UL)
672 p++;
673
674 return p;
675 }
676
677 extern unsigned int tl0_icpe[], tl1_icpe[];
678 extern unsigned int tl0_dcpe[], tl1_dcpe[];
679 extern unsigned int tl0_fecc[], tl1_fecc[];
680 extern unsigned int tl0_cee[], tl1_cee[];
681 extern unsigned int tl0_iae[], tl1_iae[];
682 extern unsigned int tl0_dae[], tl1_dae[];
683 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
684 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
685 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
686 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
687 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
688
689 void __init cheetah_ecache_flush_init(void)
690 {
691 unsigned long largest_size, smallest_linesize, order, ver;
692 int node, i, instance;
693
694 /* Scan all cpu device tree nodes, note two values:
695 * 1) largest E-cache size
696 * 2) smallest E-cache line size
697 */
698 largest_size = 0UL;
699 smallest_linesize = ~0UL;
700
701 instance = 0;
702 while (!cpu_find_by_instance(instance, &node, NULL)) {
703 unsigned long val;
704
705 val = prom_getintdefault(node, "ecache-size",
706 (2 * 1024 * 1024));
707 if (val > largest_size)
708 largest_size = val;
709 val = prom_getintdefault(node, "ecache-line-size", 64);
710 if (val < smallest_linesize)
711 smallest_linesize = val;
712 instance++;
713 }
714
715 if (largest_size == 0UL || smallest_linesize == ~0UL) {
716 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
717 "parameters.\n");
718 prom_halt();
719 }
720
721 ecache_flush_size = (2 * largest_size);
722 ecache_flush_linesize = smallest_linesize;
723
724 /* Discover a physically contiguous chunk of physical
725 * memory in 'sp_banks' of size ecache_flush_size calculated
726 * above. Store the physical base of this area at
727 * ecache_flush_physbase.
728 */
729 for (node = 0; ; node++) {
730 if (sp_banks[node].num_bytes == 0)
731 break;
732 if (sp_banks[node].num_bytes >= ecache_flush_size) {
733 ecache_flush_physbase = sp_banks[node].base_addr;
734 break;
735 }
736 }
737
738 /* Note: Zero would be a valid value of ecache_flush_physbase so
739 * don't use that as the success test. :-)
740 */
741 if (sp_banks[node].num_bytes == 0) {
742 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
743 "contiguous physical memory.\n", ecache_flush_size);
744 prom_halt();
745 }
746
747 /* Now allocate error trap reporting scoreboard. */
748 node = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
749 for (order = 0; order < MAX_ORDER; order++) {
750 if ((PAGE_SIZE << order) >= node)
751 break;
752 }
753 cheetah_error_log = (struct cheetah_err_info *)
754 __get_free_pages(GFP_KERNEL, order);
755 if (!cheetah_error_log) {
756 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
757 "error logging scoreboard (%d bytes).\n", node);
758 prom_halt();
759 }
760 memset(cheetah_error_log, 0, PAGE_SIZE << order);
761
762 /* Mark all AFSRs as invalid so that the trap handler will
763 * log new new information there.
764 */
765 for (i = 0; i < 2 * NR_CPUS; i++)
766 cheetah_error_log[i].afsr = CHAFSR_INVALID;
767
768 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
769 if ((ver >> 32) == 0x003e0016) {
770 cheetah_error_table = &__jalapeno_error_table[0];
771 cheetah_afsr_errors = JPAFSR_ERRORS;
772 } else if ((ver >> 32) == 0x003e0015) {
773 cheetah_error_table = &__cheetah_plus_error_table[0];
774 cheetah_afsr_errors = CHPAFSR_ERRORS;
775 } else {
776 cheetah_error_table = &__cheetah_error_table[0];
777 cheetah_afsr_errors = CHAFSR_ERRORS;
778 }
779
780 /* Now patch trap tables. */
781 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
782 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
783 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
784 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
785 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
786 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
787 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
788 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
789 if (tlb_type == cheetah_plus) {
790 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
791 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
792 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
793 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
794 }
795 flushi(PAGE_OFFSET);
796 }
797
798 static void cheetah_flush_ecache(void)
799 {
800 unsigned long flush_base = ecache_flush_physbase;
801 unsigned long flush_linesize = ecache_flush_linesize;
802 unsigned long flush_size = ecache_flush_size;
803
804 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
805 " bne,pt %%xcc, 1b\n\t"
806 " ldxa [%2 + %0] %3, %%g0\n\t"
807 : "=&r" (flush_size)
808 : "0" (flush_size), "r" (flush_base),
809 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
810 }
811
812 static void cheetah_flush_ecache_line(unsigned long physaddr)
813 {
814 unsigned long alias;
815
816 physaddr &= ~(8UL - 1UL);
817 physaddr = (ecache_flush_physbase +
818 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
819 alias = physaddr + (ecache_flush_size >> 1UL);
820 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
821 "ldxa [%1] %2, %%g0\n\t"
822 "membar #Sync"
823 : /* no outputs */
824 : "r" (physaddr), "r" (alias),
825 "i" (ASI_PHYS_USE_EC));
826 }
827
828 /* Unfortunately, the diagnostic access to the I-cache tags we need to
829 * use to clear the thing interferes with I-cache coherency transactions.
830 *
831 * So we must only flush the I-cache when it is disabled.
832 */
833 static void __cheetah_flush_icache(void)
834 {
835 unsigned long i;
836
837 /* Clear the valid bits in all the tags. */
838 for (i = 0; i < (1 << 15); i += (1 << 5)) {
839 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
840 "membar #Sync"
841 : /* no outputs */
842 : "r" (i | (2 << 3)), "i" (ASI_IC_TAG));
843 }
844 }
845
846 static void cheetah_flush_icache(void)
847 {
848 unsigned long dcu_save;
849
850 /* Save current DCU, disable I-cache. */
851 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
852 "or %0, %2, %%g1\n\t"
853 "stxa %%g1, [%%g0] %1\n\t"
854 "membar #Sync"
855 : "=r" (dcu_save)
856 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
857 : "g1");
858
859 __cheetah_flush_icache();
860
861 /* Restore DCU register */
862 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
863 "membar #Sync"
864 : /* no outputs */
865 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
866 }
867
868 static void cheetah_flush_dcache(void)
869 {
870 unsigned long i;
871
872 for (i = 0; i < (1 << 16); i += (1 << 5)) {
873 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
874 "membar #Sync"
875 : /* no outputs */
876 : "r" (i), "i" (ASI_DCACHE_TAG));
877 }
878 }
879
880 /* In order to make the even parity correct we must do two things.
881 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
882 * Next, we clear out all 32-bytes of data for that line. Data of
883 * all-zero + tag parity value of zero == correct parity.
884 */
885 static void cheetah_plus_zap_dcache_parity(void)
886 {
887 unsigned long i;
888
889 for (i = 0; i < (1 << 16); i += (1 << 5)) {
890 unsigned long tag = (i >> 14);
891 unsigned long j;
892
893 __asm__ __volatile__("membar #Sync\n\t"
894 "stxa %0, [%1] %2\n\t"
895 "membar #Sync"
896 : /* no outputs */
897 : "r" (tag), "r" (i),
898 "i" (ASI_DCACHE_UTAG));
899 for (j = i; j < i + (1 << 5); j += (1 << 3))
900 __asm__ __volatile__("membar #Sync\n\t"
901 "stxa %%g0, [%0] %1\n\t"
902 "membar #Sync"
903 : /* no outputs */
904 : "r" (j), "i" (ASI_DCACHE_DATA));
905 }
906 }
907
908 /* Conversion tables used to frob Cheetah AFSR syndrome values into
909 * something palatable to the memory controller driver get_unumber
910 * routine.
911 */
912 #define MT0 137
913 #define MT1 138
914 #define MT2 139
915 #define NONE 254
916 #define MTC0 140
917 #define MTC1 141
918 #define MTC2 142
919 #define MTC3 143
920 #define C0 128
921 #define C1 129
922 #define C2 130
923 #define C3 131
924 #define C4 132
925 #define C5 133
926 #define C6 134
927 #define C7 135
928 #define C8 136
929 #define M2 144
930 #define M3 145
931 #define M4 146
932 #define M 147
933 static unsigned char cheetah_ecc_syntab[] = {
934 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
935 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
936 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
937 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
938 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
939 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
940 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
941 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
942 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
943 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
944 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
945 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
946 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
947 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
948 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
949 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
950 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
951 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
952 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
953 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
954 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
955 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
956 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
957 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
958 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
959 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
960 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
961 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
962 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
963 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
964 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
965 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
966 };
967 static unsigned char cheetah_mtag_syntab[] = {
968 NONE, MTC0,
969 MTC1, NONE,
970 MTC2, NONE,
971 NONE, MT0,
972 MTC3, NONE,
973 NONE, MT1,
974 NONE, MT2,
975 NONE, NONE
976 };
977
978 /* Return the highest priority error conditon mentioned. */
979 static __inline__ unsigned long cheetah_get_hipri(unsigned long afsr)
980 {
981 unsigned long tmp = 0;
982 int i;
983
984 for (i = 0; cheetah_error_table[i].mask; i++) {
985 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
986 return tmp;
987 }
988 return tmp;
989 }
990
991 static const char *cheetah_get_string(unsigned long bit)
992 {
993 int i;
994
995 for (i = 0; cheetah_error_table[i].mask; i++) {
996 if ((bit & cheetah_error_table[i].mask) != 0UL)
997 return cheetah_error_table[i].name;
998 }
999 return "???";
1000 }
1001
1002 extern int chmc_getunumber(int, unsigned long, char *, int);
1003
1004 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1005 unsigned long afsr, unsigned long afar, int recoverable)
1006 {
1007 unsigned long hipri;
1008 char unum[256];
1009
1010 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1011 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1012 afsr, afar,
1013 (afsr & CHAFSR_TL1) ? 1 : 0);
1014 printk("%s" "ERROR(%d): TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1015 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1016 regs->tpc, regs->tnpc, regs->tstate);
1017 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1018 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1019 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1020 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1021 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1022 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1023 hipri = cheetah_get_hipri(afsr);
1024 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1025 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1026 hipri, cheetah_get_string(hipri));
1027
1028 /* Try to get unumber if relevant. */
1029 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1030 CHAFSR_CPC | CHAFSR_CPU | \
1031 CHAFSR_UE | CHAFSR_CE | \
1032 CHAFSR_EDC | CHAFSR_EDU | \
1033 CHAFSR_UCC | CHAFSR_UCU | \
1034 CHAFSR_WDU | CHAFSR_WDC)
1035 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1036 if (afsr & ESYND_ERRORS) {
1037 int syndrome;
1038 int ret;
1039
1040 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1041 syndrome = cheetah_ecc_syntab[syndrome];
1042 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1043 if (ret != -1)
1044 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1045 (recoverable ? KERN_WARNING : KERN_CRIT),
1046 smp_processor_id(), unum);
1047 } else if (afsr & MSYND_ERRORS) {
1048 int syndrome;
1049 int ret;
1050
1051 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1052 syndrome = cheetah_mtag_syntab[syndrome];
1053 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1054 if (ret != -1)
1055 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1056 (recoverable ? KERN_WARNING : KERN_CRIT),
1057 smp_processor_id(), unum);
1058 }
1059
1060 /* Now dump the cache snapshots. */
1061 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx]\n",
1062 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1063 (int) info->dcache_index,
1064 info->dcache_tag,
1065 info->dcache_utag,
1066 info->dcache_stag);
1067 printk("%s" "ERROR(%d): D-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1068 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1069 info->dcache_data[0],
1070 info->dcache_data[1],
1071 info->dcache_data[2],
1072 info->dcache_data[3]);
1073 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx] "
1074 "u[%016lx] l[%016lx]\n",
1075 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1076 (int) info->icache_index,
1077 info->icache_tag,
1078 info->icache_utag,
1079 info->icache_stag,
1080 info->icache_upper,
1081 info->icache_lower);
1082 printk("%s" "ERROR(%d): I-cache INSN0[%016lx] INSN1[%016lx] INSN2[%016lx] INSN3[%016lx]\n",
1083 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1084 info->icache_data[0],
1085 info->icache_data[1],
1086 info->icache_data[2],
1087 info->icache_data[3]);
1088 printk("%s" "ERROR(%d): I-cache INSN4[%016lx] INSN5[%016lx] INSN6[%016lx] INSN7[%016lx]\n",
1089 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1090 info->icache_data[4],
1091 info->icache_data[5],
1092 info->icache_data[6],
1093 info->icache_data[7]);
1094 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016lx]\n",
1095 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1096 (int) info->ecache_index, info->ecache_tag);
1097 printk("%s" "ERROR(%d): E-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1098 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1099 info->ecache_data[0],
1100 info->ecache_data[1],
1101 info->ecache_data[2],
1102 info->ecache_data[3]);
1103
1104 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1105 while (afsr != 0UL) {
1106 unsigned long bit = cheetah_get_hipri(afsr);
1107
1108 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1109 (recoverable ? KERN_WARNING : KERN_CRIT),
1110 bit, cheetah_get_string(bit));
1111
1112 afsr &= ~bit;
1113 }
1114
1115 if (!recoverable)
1116 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1117 }
1118
1119 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1120 {
1121 unsigned long afsr, afar;
1122 int ret = 0;
1123
1124 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1125 : "=r" (afsr)
1126 : "i" (ASI_AFSR));
1127 if ((afsr & cheetah_afsr_errors) != 0) {
1128 if (logp != NULL) {
1129 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1130 : "=r" (afar)
1131 : "i" (ASI_AFAR));
1132 logp->afsr = afsr;
1133 logp->afar = afar;
1134 }
1135 ret = 1;
1136 }
1137 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1138 "membar #Sync\n\t"
1139 : : "r" (afsr), "i" (ASI_AFSR));
1140
1141 return ret;
1142 }
1143
1144 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1145 {
1146 struct cheetah_err_info local_snapshot, *p;
1147 int recoverable;
1148
1149 /* Flush E-cache */
1150 cheetah_flush_ecache();
1151
1152 p = cheetah_get_error_log(afsr);
1153 if (!p) {
1154 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1155 afsr, afar);
1156 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1157 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1158 prom_halt();
1159 }
1160
1161 /* Grab snapshot of logged error. */
1162 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1163
1164 /* If the current trap snapshot does not match what the
1165 * trap handler passed along into our args, big trouble.
1166 * In such a case, mark the local copy as invalid.
1167 *
1168 * Else, it matches and we mark the afsr in the non-local
1169 * copy as invalid so we may log new error traps there.
1170 */
1171 if (p->afsr != afsr || p->afar != afar)
1172 local_snapshot.afsr = CHAFSR_INVALID;
1173 else
1174 p->afsr = CHAFSR_INVALID;
1175
1176 cheetah_flush_icache();
1177 cheetah_flush_dcache();
1178
1179 /* Re-enable I-cache/D-cache */
1180 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1181 "or %%g1, %1, %%g1\n\t"
1182 "stxa %%g1, [%%g0] %0\n\t"
1183 "membar #Sync"
1184 : /* no outputs */
1185 : "i" (ASI_DCU_CONTROL_REG),
1186 "i" (DCU_DC | DCU_IC)
1187 : "g1");
1188
1189 /* Re-enable error reporting */
1190 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1191 "or %%g1, %1, %%g1\n\t"
1192 "stxa %%g1, [%%g0] %0\n\t"
1193 "membar #Sync"
1194 : /* no outputs */
1195 : "i" (ASI_ESTATE_ERROR_EN),
1196 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1197 : "g1");
1198
1199 /* Decide if we can continue after handling this trap and
1200 * logging the error.
1201 */
1202 recoverable = 1;
1203 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1204 recoverable = 0;
1205
1206 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1207 * error was logged while we had error reporting traps disabled.
1208 */
1209 if (cheetah_recheck_errors(&local_snapshot)) {
1210 unsigned long new_afsr = local_snapshot.afsr;
1211
1212 /* If we got a new asynchronous error, die... */
1213 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1214 CHAFSR_WDU | CHAFSR_CPU |
1215 CHAFSR_IVU | CHAFSR_UE |
1216 CHAFSR_BERR | CHAFSR_TO))
1217 recoverable = 0;
1218 }
1219
1220 /* Log errors. */
1221 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1222
1223 if (!recoverable)
1224 panic("Irrecoverable Fast-ECC error trap.\n");
1225
1226 /* Flush E-cache to kick the error trap handlers out. */
1227 cheetah_flush_ecache();
1228 }
1229
1230 /* Try to fix a correctable error by pushing the line out from
1231 * the E-cache. Recheck error reporting registers to see if the
1232 * problem is intermittent.
1233 */
1234 static int cheetah_fix_ce(unsigned long physaddr)
1235 {
1236 unsigned long orig_estate;
1237 unsigned long alias1, alias2;
1238 int ret;
1239
1240 /* Make sure correctable error traps are disabled. */
1241 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1242 "andn %0, %1, %%g1\n\t"
1243 "stxa %%g1, [%%g0] %2\n\t"
1244 "membar #Sync"
1245 : "=&r" (orig_estate)
1246 : "i" (ESTATE_ERROR_CEEN),
1247 "i" (ASI_ESTATE_ERROR_EN)
1248 : "g1");
1249
1250 /* We calculate alias addresses that will force the
1251 * cache line in question out of the E-cache. Then
1252 * we bring it back in with an atomic instruction so
1253 * that we get it in some modified/exclusive state,
1254 * then we displace it again to try and get proper ECC
1255 * pushed back into the system.
1256 */
1257 physaddr &= ~(8UL - 1UL);
1258 alias1 = (ecache_flush_physbase +
1259 (physaddr & ((ecache_flush_size >> 1) - 1)));
1260 alias2 = alias1 + (ecache_flush_size >> 1);
1261 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1262 "ldxa [%1] %3, %%g0\n\t"
1263 "casxa [%2] %3, %%g0, %%g0\n\t"
1264 "membar #StoreLoad | #StoreStore\n\t"
1265 "ldxa [%0] %3, %%g0\n\t"
1266 "ldxa [%1] %3, %%g0\n\t"
1267 "membar #Sync"
1268 : /* no outputs */
1269 : "r" (alias1), "r" (alias2),
1270 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1271
1272 /* Did that trigger another error? */
1273 if (cheetah_recheck_errors(NULL)) {
1274 /* Try one more time. */
1275 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1276 "membar #Sync"
1277 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1278 if (cheetah_recheck_errors(NULL))
1279 ret = 2;
1280 else
1281 ret = 1;
1282 } else {
1283 /* No new error, intermittent problem. */
1284 ret = 0;
1285 }
1286
1287 /* Restore error enables. */
1288 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1289 "membar #Sync"
1290 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1291
1292 return ret;
1293 }
1294
1295 /* Return non-zero if PADDR is a valid physical memory address. */
1296 static int cheetah_check_main_memory(unsigned long paddr)
1297 {
1298 int i;
1299
1300 for (i = 0; ; i++) {
1301 if (sp_banks[i].num_bytes == 0)
1302 break;
1303 if (paddr >= sp_banks[i].base_addr &&
1304 paddr < (sp_banks[i].base_addr + sp_banks[i].num_bytes))
1305 return 1;
1306 }
1307 return 0;
1308 }
1309
1310 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1311 {
1312 struct cheetah_err_info local_snapshot, *p;
1313 int recoverable, is_memory;
1314
1315 p = cheetah_get_error_log(afsr);
1316 if (!p) {
1317 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1318 afsr, afar);
1319 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1320 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1321 prom_halt();
1322 }
1323
1324 /* Grab snapshot of logged error. */
1325 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1326
1327 /* If the current trap snapshot does not match what the
1328 * trap handler passed along into our args, big trouble.
1329 * In such a case, mark the local copy as invalid.
1330 *
1331 * Else, it matches and we mark the afsr in the non-local
1332 * copy as invalid so we may log new error traps there.
1333 */
1334 if (p->afsr != afsr || p->afar != afar)
1335 local_snapshot.afsr = CHAFSR_INVALID;
1336 else
1337 p->afsr = CHAFSR_INVALID;
1338
1339 is_memory = cheetah_check_main_memory(afar);
1340
1341 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1342 /* XXX Might want to log the results of this operation
1343 * XXX somewhere... -DaveM
1344 */
1345 cheetah_fix_ce(afar);
1346 }
1347
1348 {
1349 int flush_all, flush_line;
1350
1351 flush_all = flush_line = 0;
1352 if ((afsr & CHAFSR_EDC) != 0UL) {
1353 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1354 flush_line = 1;
1355 else
1356 flush_all = 1;
1357 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1358 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1359 flush_line = 1;
1360 else
1361 flush_all = 1;
1362 }
1363
1364 /* Trap handler only disabled I-cache, flush it. */
1365 cheetah_flush_icache();
1366
1367 /* Re-enable I-cache */
1368 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1369 "or %%g1, %1, %%g1\n\t"
1370 "stxa %%g1, [%%g0] %0\n\t"
1371 "membar #Sync"
1372 : /* no outputs */
1373 : "i" (ASI_DCU_CONTROL_REG),
1374 "i" (DCU_IC)
1375 : "g1");
1376
1377 if (flush_all)
1378 cheetah_flush_ecache();
1379 else if (flush_line)
1380 cheetah_flush_ecache_line(afar);
1381 }
1382
1383 /* Re-enable error reporting */
1384 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1385 "or %%g1, %1, %%g1\n\t"
1386 "stxa %%g1, [%%g0] %0\n\t"
1387 "membar #Sync"
1388 : /* no outputs */
1389 : "i" (ASI_ESTATE_ERROR_EN),
1390 "i" (ESTATE_ERROR_CEEN)
1391 : "g1");
1392
1393 /* Decide if we can continue after handling this trap and
1394 * logging the error.
1395 */
1396 recoverable = 1;
1397 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1398 recoverable = 0;
1399
1400 /* Re-check AFSR/AFAR */
1401 (void) cheetah_recheck_errors(&local_snapshot);
1402
1403 /* Log errors. */
1404 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1405
1406 if (!recoverable)
1407 panic("Irrecoverable Correctable-ECC error trap.\n");
1408 }
1409
1410 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1411 {
1412 struct cheetah_err_info local_snapshot, *p;
1413 int recoverable, is_memory;
1414
1415 #ifdef CONFIG_PCI
1416 /* Check for the special PCI poke sequence. */
1417 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1418 cheetah_flush_icache();
1419 cheetah_flush_dcache();
1420
1421 /* Re-enable I-cache/D-cache */
1422 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1423 "or %%g1, %1, %%g1\n\t"
1424 "stxa %%g1, [%%g0] %0\n\t"
1425 "membar #Sync"
1426 : /* no outputs */
1427 : "i" (ASI_DCU_CONTROL_REG),
1428 "i" (DCU_DC | DCU_IC)
1429 : "g1");
1430
1431 /* Re-enable error reporting */
1432 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1433 "or %%g1, %1, %%g1\n\t"
1434 "stxa %%g1, [%%g0] %0\n\t"
1435 "membar #Sync"
1436 : /* no outputs */
1437 : "i" (ASI_ESTATE_ERROR_EN),
1438 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1439 : "g1");
1440
1441 (void) cheetah_recheck_errors(NULL);
1442
1443 pci_poke_faulted = 1;
1444 regs->tpc += 4;
1445 regs->tnpc = regs->tpc + 4;
1446 return;
1447 }
1448 #endif
1449
1450 p = cheetah_get_error_log(afsr);
1451 if (!p) {
1452 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1453 afsr, afar);
1454 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1455 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1456 prom_halt();
1457 }
1458
1459 /* Grab snapshot of logged error. */
1460 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1461
1462 /* If the current trap snapshot does not match what the
1463 * trap handler passed along into our args, big trouble.
1464 * In such a case, mark the local copy as invalid.
1465 *
1466 * Else, it matches and we mark the afsr in the non-local
1467 * copy as invalid so we may log new error traps there.
1468 */
1469 if (p->afsr != afsr || p->afar != afar)
1470 local_snapshot.afsr = CHAFSR_INVALID;
1471 else
1472 p->afsr = CHAFSR_INVALID;
1473
1474 is_memory = cheetah_check_main_memory(afar);
1475
1476 {
1477 int flush_all, flush_line;
1478
1479 flush_all = flush_line = 0;
1480 if ((afsr & CHAFSR_EDU) != 0UL) {
1481 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1482 flush_line = 1;
1483 else
1484 flush_all = 1;
1485 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1486 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1487 flush_line = 1;
1488 else
1489 flush_all = 1;
1490 }
1491
1492 cheetah_flush_icache();
1493 cheetah_flush_dcache();
1494
1495 /* Re-enable I/D caches */
1496 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1497 "or %%g1, %1, %%g1\n\t"
1498 "stxa %%g1, [%%g0] %0\n\t"
1499 "membar #Sync"
1500 : /* no outputs */
1501 : "i" (ASI_DCU_CONTROL_REG),
1502 "i" (DCU_IC | DCU_DC)
1503 : "g1");
1504
1505 if (flush_all)
1506 cheetah_flush_ecache();
1507 else if (flush_line)
1508 cheetah_flush_ecache_line(afar);
1509 }
1510
1511 /* Re-enable error reporting */
1512 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1513 "or %%g1, %1, %%g1\n\t"
1514 "stxa %%g1, [%%g0] %0\n\t"
1515 "membar #Sync"
1516 : /* no outputs */
1517 : "i" (ASI_ESTATE_ERROR_EN),
1518 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1519 : "g1");
1520
1521 /* Decide if we can continue after handling this trap and
1522 * logging the error.
1523 */
1524 recoverable = 1;
1525 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1526 recoverable = 0;
1527
1528 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1529 * error was logged while we had error reporting traps disabled.
1530 */
1531 if (cheetah_recheck_errors(&local_snapshot)) {
1532 unsigned long new_afsr = local_snapshot.afsr;
1533
1534 /* If we got a new asynchronous error, die... */
1535 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1536 CHAFSR_WDU | CHAFSR_CPU |
1537 CHAFSR_IVU | CHAFSR_UE |
1538 CHAFSR_BERR | CHAFSR_TO))
1539 recoverable = 0;
1540 }
1541
1542 /* Log errors. */
1543 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1544
1545 /* "Recoverable" here means we try to yank the page from ever
1546 * being newly used again. This depends upon a few things:
1547 * 1) Must be main memory, and AFAR must be valid.
1548 * 2) If we trapped from user, OK.
1549 * 3) Else, if we trapped from kernel we must find exception
1550 * table entry (ie. we have to have been accessing user
1551 * space).
1552 *
1553 * If AFAR is not in main memory, or we trapped from kernel
1554 * and cannot find an exception table entry, it is unacceptable
1555 * to try and continue.
1556 */
1557 if (recoverable && is_memory) {
1558 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1559 /* OK, usermode access. */
1560 recoverable = 1;
1561 } else {
1562 unsigned long g2 = regs->u_regs[UREG_G2];
1563 unsigned long fixup = search_extables_range(regs->tpc, &g2);
1564
1565 if (fixup != 0UL) {
1566 /* OK, kernel access to userspace. */
1567 recoverable = 1;
1568
1569 } else {
1570 /* BAD, privileged state is corrupted. */
1571 recoverable = 0;
1572 }
1573
1574 if (recoverable) {
1575 if (pfn_valid(afar >> PAGE_SHIFT))
1576 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1577 else
1578 recoverable = 0;
1579
1580 /* Only perform fixup if we still have a
1581 * recoverable condition.
1582 */
1583 if (recoverable) {
1584 regs->tpc = fixup;
1585 regs->tnpc = regs->tpc + 4;
1586 regs->u_regs[UREG_G2] = g2;
1587 }
1588 }
1589 }
1590 } else {
1591 recoverable = 0;
1592 }
1593
1594 if (!recoverable)
1595 panic("Irrecoverable deferred error trap.\n");
1596 }
1597
1598 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1599 *
1600 * Bit0: 0=dcache,1=icache
1601 * Bit1: 0=recoverable,1=unrecoverable
1602 *
1603 * The hardware has disabled both the I-cache and D-cache in
1604 * the %dcr register.
1605 */
1606 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1607 {
1608 if (type & 0x1)
1609 __cheetah_flush_icache();
1610 else
1611 cheetah_plus_zap_dcache_parity();
1612 cheetah_flush_dcache();
1613
1614 /* Re-enable I-cache/D-cache */
1615 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1616 "or %%g1, %1, %%g1\n\t"
1617 "stxa %%g1, [%%g0] %0\n\t"
1618 "membar #Sync"
1619 : /* no outputs */
1620 : "i" (ASI_DCU_CONTROL_REG),
1621 "i" (DCU_DC | DCU_IC)
1622 : "g1");
1623
1624 if (type & 0x2) {
1625 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1626 smp_processor_id(),
1627 (type & 0x1) ? 'I' : 'D',
1628 regs->tpc);
1629 panic("Irrecoverable Cheetah+ parity error.");
1630 }
1631
1632 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1633 smp_processor_id(),
1634 (type & 0x1) ? 'I' : 'D',
1635 regs->tpc);
1636 }
1637
1638 void do_fpe_common(struct pt_regs *regs)
1639 {
1640 if (regs->tstate & TSTATE_PRIV) {
1641 regs->tpc = regs->tnpc;
1642 regs->tnpc += 4;
1643 } else {
1644 unsigned long fsr = current_thread_info()->xfsr[0];
1645 siginfo_t info;
1646
1647 if (test_thread_flag(TIF_32BIT)) {
1648 regs->tpc &= 0xffffffff;
1649 regs->tnpc &= 0xffffffff;
1650 }
1651 info.si_signo = SIGFPE;
1652 info.si_errno = 0;
1653 info.si_addr = (void __user *)regs->tpc;
1654 info.si_trapno = 0;
1655 info.si_code = __SI_FAULT;
1656 if ((fsr & 0x1c000) == (1 << 14)) {
1657 if (fsr & 0x10)
1658 info.si_code = FPE_FLTINV;
1659 else if (fsr & 0x08)
1660 info.si_code = FPE_FLTOVF;
1661 else if (fsr & 0x04)
1662 info.si_code = FPE_FLTUND;
1663 else if (fsr & 0x02)
1664 info.si_code = FPE_FLTDIV;
1665 else if (fsr & 0x01)
1666 info.si_code = FPE_FLTRES;
1667 }
1668 force_sig_info(SIGFPE, &info, current);
1669 }
1670 }
1671
1672 void do_fpieee(struct pt_regs *regs)
1673 {
1674 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
1675 0, 0x24, SIGFPE) == NOTIFY_STOP)
1676 return;
1677
1678 do_fpe_common(regs);
1679 }
1680
1681 extern int do_mathemu(struct pt_regs *, struct fpustate *);
1682
1683 void do_fpother(struct pt_regs *regs)
1684 {
1685 struct fpustate *f = FPUSTATE;
1686 int ret = 0;
1687
1688 if (notify_die(DIE_TRAP, "fpu exception other", regs,
1689 0, 0x25, SIGFPE) == NOTIFY_STOP)
1690 return;
1691
1692 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
1693 case (2 << 14): /* unfinished_FPop */
1694 case (3 << 14): /* unimplemented_FPop */
1695 ret = do_mathemu(regs, f);
1696 break;
1697 }
1698 if (ret)
1699 return;
1700 do_fpe_common(regs);
1701 }
1702
1703 void do_tof(struct pt_regs *regs)
1704 {
1705 siginfo_t info;
1706
1707 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
1708 0, 0x26, SIGEMT) == NOTIFY_STOP)
1709 return;
1710
1711 if (regs->tstate & TSTATE_PRIV)
1712 die_if_kernel("Penguin overflow trap from kernel mode", regs);
1713 if (test_thread_flag(TIF_32BIT)) {
1714 regs->tpc &= 0xffffffff;
1715 regs->tnpc &= 0xffffffff;
1716 }
1717 info.si_signo = SIGEMT;
1718 info.si_errno = 0;
1719 info.si_code = EMT_TAGOVF;
1720 info.si_addr = (void __user *)regs->tpc;
1721 info.si_trapno = 0;
1722 force_sig_info(SIGEMT, &info, current);
1723 }
1724
1725 void do_div0(struct pt_regs *regs)
1726 {
1727 siginfo_t info;
1728
1729 if (notify_die(DIE_TRAP, "integer division by zero", regs,
1730 0, 0x28, SIGFPE) == NOTIFY_STOP)
1731 return;
1732
1733 if (regs->tstate & TSTATE_PRIV)
1734 die_if_kernel("TL0: Kernel divide by zero.", regs);
1735 if (test_thread_flag(TIF_32BIT)) {
1736 regs->tpc &= 0xffffffff;
1737 regs->tnpc &= 0xffffffff;
1738 }
1739 info.si_signo = SIGFPE;
1740 info.si_errno = 0;
1741 info.si_code = FPE_INTDIV;
1742 info.si_addr = (void __user *)regs->tpc;
1743 info.si_trapno = 0;
1744 force_sig_info(SIGFPE, &info, current);
1745 }
1746
1747 void instruction_dump (unsigned int *pc)
1748 {
1749 int i;
1750
1751 if ((((unsigned long) pc) & 3))
1752 return;
1753
1754 printk("Instruction DUMP:");
1755 for (i = -3; i < 6; i++)
1756 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
1757 printk("\n");
1758 }
1759
1760 static void user_instruction_dump (unsigned int __user *pc)
1761 {
1762 int i;
1763 unsigned int buf[9];
1764
1765 if ((((unsigned long) pc) & 3))
1766 return;
1767
1768 if (copy_from_user(buf, pc - 3, sizeof(buf)))
1769 return;
1770
1771 printk("Instruction DUMP:");
1772 for (i = 0; i < 9; i++)
1773 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
1774 printk("\n");
1775 }
1776
1777 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
1778 {
1779 unsigned long pc, fp, thread_base, ksp;
1780 struct thread_info *tp = tsk->thread_info;
1781 struct reg_window *rw;
1782 int count = 0;
1783
1784 ksp = (unsigned long) _ksp;
1785
1786 if (tp == current_thread_info())
1787 flushw_all();
1788
1789 fp = ksp + STACK_BIAS;
1790 thread_base = (unsigned long) tp;
1791
1792 printk("Call Trace:");
1793 #ifdef CONFIG_KALLSYMS
1794 printk("\n");
1795 #endif
1796 do {
1797 /* Bogus frame pointer? */
1798 if (fp < (thread_base + sizeof(struct thread_info)) ||
1799 fp >= (thread_base + THREAD_SIZE))
1800 break;
1801 rw = (struct reg_window *)fp;
1802 pc = rw->ins[7];
1803 printk(" [%016lx] ", pc);
1804 print_symbol("%s\n", pc);
1805 fp = rw->ins[6] + STACK_BIAS;
1806 } while (++count < 16);
1807 #ifndef CONFIG_KALLSYMS
1808 printk("\n");
1809 #endif
1810 }
1811
1812 void dump_stack(void)
1813 {
1814 unsigned long *ksp;
1815
1816 __asm__ __volatile__("mov %%fp, %0"
1817 : "=r" (ksp));
1818 show_stack(current, ksp);
1819 }
1820
1821 EXPORT_SYMBOL(dump_stack);
1822
1823 static inline int is_kernel_stack(struct task_struct *task,
1824 struct reg_window *rw)
1825 {
1826 unsigned long rw_addr = (unsigned long) rw;
1827 unsigned long thread_base, thread_end;
1828
1829 if (rw_addr < PAGE_OFFSET) {
1830 if (task != &init_task)
1831 return 0;
1832 }
1833
1834 thread_base = (unsigned long) task->thread_info;
1835 thread_end = thread_base + sizeof(union thread_union);
1836 if (rw_addr >= thread_base &&
1837 rw_addr < thread_end &&
1838 !(rw_addr & 0x7UL))
1839 return 1;
1840
1841 return 0;
1842 }
1843
1844 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
1845 {
1846 unsigned long fp = rw->ins[6];
1847
1848 if (!fp)
1849 return NULL;
1850
1851 return (struct reg_window *) (fp + STACK_BIAS);
1852 }
1853
1854 void die_if_kernel(char *str, struct pt_regs *regs)
1855 {
1856 static int die_counter;
1857 extern void __show_regs(struct pt_regs * regs);
1858 extern void smp_report_regs(void);
1859 int count = 0;
1860
1861 /* Amuse the user. */
1862 printk(
1863 " \\|/ ____ \\|/\n"
1864 " \"@'/ .. \\`@\"\n"
1865 " /_| \\__/ |_\\\n"
1866 " \\__U_/\n");
1867
1868 printk("%s(%d): %s [#%d]\n", current->comm, current->pid, str, ++die_counter);
1869 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
1870 __asm__ __volatile__("flushw");
1871 __show_regs(regs);
1872 if (regs->tstate & TSTATE_PRIV) {
1873 struct reg_window *rw = (struct reg_window *)
1874 (regs->u_regs[UREG_FP] + STACK_BIAS);
1875
1876 /* Stop the back trace when we hit userland or we
1877 * find some badly aligned kernel stack.
1878 */
1879 while (rw &&
1880 count++ < 30&&
1881 is_kernel_stack(current, rw)) {
1882 printk("Caller[%016lx]", rw->ins[7]);
1883 print_symbol(": %s", rw->ins[7]);
1884 printk("\n");
1885
1886 rw = kernel_stack_up(rw);
1887 }
1888 instruction_dump ((unsigned int *) regs->tpc);
1889 } else {
1890 if (test_thread_flag(TIF_32BIT)) {
1891 regs->tpc &= 0xffffffff;
1892 regs->tnpc &= 0xffffffff;
1893 }
1894 user_instruction_dump ((unsigned int __user *) regs->tpc);
1895 }
1896 #ifdef CONFIG_SMP
1897 smp_report_regs();
1898 #endif
1899
1900 if (regs->tstate & TSTATE_PRIV)
1901 do_exit(SIGKILL);
1902 do_exit(SIGSEGV);
1903 }
1904
1905 extern int handle_popc(u32 insn, struct pt_regs *regs);
1906 extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
1907
1908 void do_illegal_instruction(struct pt_regs *regs)
1909 {
1910 unsigned long pc = regs->tpc;
1911 unsigned long tstate = regs->tstate;
1912 u32 insn;
1913 siginfo_t info;
1914
1915 if (notify_die(DIE_TRAP, "illegal instruction", regs,
1916 0, 0x10, SIGILL) == NOTIFY_STOP)
1917 return;
1918
1919 if (tstate & TSTATE_PRIV)
1920 die_if_kernel("Kernel illegal instruction", regs);
1921 if (test_thread_flag(TIF_32BIT))
1922 pc = (u32)pc;
1923 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
1924 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
1925 if (handle_popc(insn, regs))
1926 return;
1927 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
1928 if (handle_ldf_stq(insn, regs))
1929 return;
1930 }
1931 }
1932 info.si_signo = SIGILL;
1933 info.si_errno = 0;
1934 info.si_code = ILL_ILLOPC;
1935 info.si_addr = (void __user *)pc;
1936 info.si_trapno = 0;
1937 force_sig_info(SIGILL, &info, current);
1938 }
1939
1940 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
1941 {
1942 siginfo_t info;
1943
1944 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
1945 0, 0x34, SIGSEGV) == NOTIFY_STOP)
1946 return;
1947
1948 if (regs->tstate & TSTATE_PRIV) {
1949 extern void kernel_unaligned_trap(struct pt_regs *regs,
1950 unsigned int insn,
1951 unsigned long sfar,
1952 unsigned long sfsr);
1953
1954 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc),
1955 sfar, sfsr);
1956 return;
1957 }
1958 info.si_signo = SIGBUS;
1959 info.si_errno = 0;
1960 info.si_code = BUS_ADRALN;
1961 info.si_addr = (void __user *)sfar;
1962 info.si_trapno = 0;
1963 force_sig_info(SIGBUS, &info, current);
1964 }
1965
1966 void do_privop(struct pt_regs *regs)
1967 {
1968 siginfo_t info;
1969
1970 if (notify_die(DIE_TRAP, "privileged operation", regs,
1971 0, 0x11, SIGILL) == NOTIFY_STOP)
1972 return;
1973
1974 if (test_thread_flag(TIF_32BIT)) {
1975 regs->tpc &= 0xffffffff;
1976 regs->tnpc &= 0xffffffff;
1977 }
1978 info.si_signo = SIGILL;
1979 info.si_errno = 0;
1980 info.si_code = ILL_PRVOPC;
1981 info.si_addr = (void __user *)regs->tpc;
1982 info.si_trapno = 0;
1983 force_sig_info(SIGILL, &info, current);
1984 }
1985
1986 void do_privact(struct pt_regs *regs)
1987 {
1988 do_privop(regs);
1989 }
1990
1991 /* Trap level 1 stuff or other traps we should never see... */
1992 void do_cee(struct pt_regs *regs)
1993 {
1994 die_if_kernel("TL0: Cache Error Exception", regs);
1995 }
1996
1997 void do_cee_tl1(struct pt_regs *regs)
1998 {
1999 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2000 die_if_kernel("TL1: Cache Error Exception", regs);
2001 }
2002
2003 void do_dae_tl1(struct pt_regs *regs)
2004 {
2005 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2006 die_if_kernel("TL1: Data Access Exception", regs);
2007 }
2008
2009 void do_iae_tl1(struct pt_regs *regs)
2010 {
2011 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2012 die_if_kernel("TL1: Instruction Access Exception", regs);
2013 }
2014
2015 void do_div0_tl1(struct pt_regs *regs)
2016 {
2017 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2018 die_if_kernel("TL1: DIV0 Exception", regs);
2019 }
2020
2021 void do_fpdis_tl1(struct pt_regs *regs)
2022 {
2023 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2024 die_if_kernel("TL1: FPU Disabled", regs);
2025 }
2026
2027 void do_fpieee_tl1(struct pt_regs *regs)
2028 {
2029 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2030 die_if_kernel("TL1: FPU IEEE Exception", regs);
2031 }
2032
2033 void do_fpother_tl1(struct pt_regs *regs)
2034 {
2035 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2036 die_if_kernel("TL1: FPU Other Exception", regs);
2037 }
2038
2039 void do_ill_tl1(struct pt_regs *regs)
2040 {
2041 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2042 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2043 }
2044
2045 void do_irq_tl1(struct pt_regs *regs)
2046 {
2047 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2048 die_if_kernel("TL1: IRQ Exception", regs);
2049 }
2050
2051 void do_lddfmna_tl1(struct pt_regs *regs)
2052 {
2053 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2054 die_if_kernel("TL1: LDDF Exception", regs);
2055 }
2056
2057 void do_stdfmna_tl1(struct pt_regs *regs)
2058 {
2059 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2060 die_if_kernel("TL1: STDF Exception", regs);
2061 }
2062
2063 void do_paw(struct pt_regs *regs)
2064 {
2065 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2066 }
2067
2068 void do_paw_tl1(struct pt_regs *regs)
2069 {
2070 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2071 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2072 }
2073
2074 void do_vaw(struct pt_regs *regs)
2075 {
2076 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2077 }
2078
2079 void do_vaw_tl1(struct pt_regs *regs)
2080 {
2081 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2082 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2083 }
2084
2085 void do_tof_tl1(struct pt_regs *regs)
2086 {
2087 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2088 die_if_kernel("TL1: Tag Overflow Exception", regs);
2089 }
2090
2091 void do_getpsr(struct pt_regs *regs)
2092 {
2093 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2094 regs->tpc = regs->tnpc;
2095 regs->tnpc += 4;
2096 if (test_thread_flag(TIF_32BIT)) {
2097 regs->tpc &= 0xffffffff;
2098 regs->tnpc &= 0xffffffff;
2099 }
2100 }
2101
2102 extern void thread_info_offsets_are_bolixed_dave(void);
2103
2104 /* Only invoked on boot processor. */
2105 void __init trap_init(void)
2106 {
2107 /* Compile time sanity check. */
2108 if (TI_TASK != offsetof(struct thread_info, task) ||
2109 TI_FLAGS != offsetof(struct thread_info, flags) ||
2110 TI_CPU != offsetof(struct thread_info, cpu) ||
2111 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2112 TI_KSP != offsetof(struct thread_info, ksp) ||
2113 TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
2114 TI_KREGS != offsetof(struct thread_info, kregs) ||
2115 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2116 TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
2117 TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
2118 TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
2119 TI_GSR != offsetof(struct thread_info, gsr) ||
2120 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2121 TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
2122 TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
2123 TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
2124 TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
2125 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
2126 TI_CEE_STUFF != offsetof(struct thread_info, cee_stuff) ||
2127 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
2128 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2129 (TI_FPREGS & (64 - 1)))
2130 thread_info_offsets_are_bolixed_dave();
2131
2132 /* Attach to the address space of init_task. On SMP we
2133 * do this in smp.c:smp_callin for other cpus.
2134 */
2135 atomic_inc(&init_mm.mm_count);
2136 current->active_mm = &init_mm;
2137 }
WandBoard kernel