?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
amd-iommu: resume cleanup
[wandboard.git] / arch / x86 / kernel / amd_iommu_init.c
blob10b2accd12ea5983d917b0646cf445f9c8fe8b93
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
31 #include <asm/gart.h>
32
33 /*
34 * definitions for the ACPI scanning code
35 */
36 #define IVRS_HEADER_LENGTH 48
37
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
42
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
51
52 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
53 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
54 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
55 #define IVHD_FLAG_ISOC_EN_MASK 0x08
56
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
59
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
68
69 /*
70 * ACPI table definitions
71 *
72 * These data structures are laid over the table to parse the important values
73 * out of it.
74 */
75
76 /*
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
79 */
80 struct ivhd_header {
81 u8 type;
82 u8 flags;
83 u16 length;
84 u16 devid;
85 u16 cap_ptr;
86 u64 mmio_phys;
87 u16 pci_seg;
88 u16 info;
89 u32 reserved;
90 } __attribute__((packed));
91
92 /*
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
95 */
96 struct ivhd_entry {
97 u8 type;
98 u16 devid;
99 u8 flags;
100 u32 ext;
101 } __attribute__((packed));
102
103 /*
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
106 */
107 struct ivmd_header {
108 u8 type;
109 u8 flags;
110 u16 length;
111 u16 devid;
112 u16 aux;
113 u64 resv;
114 u64 range_start;
115 u64 range_length;
116 } __attribute__((packed));
117
118 bool amd_iommu_dump;
119
120 static int __initdata amd_iommu_detected;
121
122 u16 amd_iommu_last_bdf; /* largest PCI device id we have
123 to handle */
124 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
125 we find in ACPI */
126 #ifdef CONFIG_IOMMU_STRESS
127 bool amd_iommu_isolate = false;
128 #else
129 bool amd_iommu_isolate = true; /* if true, device isolation is
130 enabled */
131 #endif
132
133 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
134
135 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
136 system */
137
138 /*
139 * Pointer to the device table which is shared by all AMD IOMMUs
140 * it is indexed by the PCI device id or the HT unit id and contains
141 * information about the domain the device belongs to as well as the
142 * page table root pointer.
143 */
144 struct dev_table_entry *amd_iommu_dev_table;
145
146 /*
147 * The alias table is a driver specific data structure which contains the
148 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
149 * More than one device can share the same requestor id.
150 */
151 u16 *amd_iommu_alias_table;
152
153 /*
154 * The rlookup table is used to find the IOMMU which is responsible
155 * for a specific device. It is also indexed by the PCI device id.
156 */
157 struct amd_iommu **amd_iommu_rlookup_table;
158
159 /*
160 * The pd table (protection domain table) is used to find the protection domain
161 * data structure a device belongs to. Indexed with the PCI device id too.
162 */
163 struct protection_domain **amd_iommu_pd_table;
164
165 /*
166 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
167 * to know which ones are already in use.
168 */
169 unsigned long *amd_iommu_pd_alloc_bitmap;
170
171 static u32 dev_table_size; /* size of the device table */
172 static u32 alias_table_size; /* size of the alias table */
173 static u32 rlookup_table_size; /* size if the rlookup table */
174
175 static inline void update_last_devid(u16 devid)
176 {
177 if (devid > amd_iommu_last_bdf)
178 amd_iommu_last_bdf = devid;
179 }
180
181 static inline unsigned long tbl_size(int entry_size)
182 {
183 unsigned shift = PAGE_SHIFT +
184 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
185
186 return 1UL << shift;
187 }
188
189 /****************************************************************************
190 *
191 * AMD IOMMU MMIO register space handling functions
192 *
193 * These functions are used to program the IOMMU device registers in
194 * MMIO space required for that driver.
195 *
196 ****************************************************************************/
197
198 /*
199 * This function set the exclusion range in the IOMMU. DMA accesses to the
200 * exclusion range are passed through untranslated
201 */
202 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
203 {
204 u64 start = iommu->exclusion_start & PAGE_MASK;
205 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
206 u64 entry;
207
208 if (!iommu->exclusion_start)
209 return;
210
211 entry = start | MMIO_EXCL_ENABLE_MASK;
212 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
213 &entry, sizeof(entry));
214
215 entry = limit;
216 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
217 &entry, sizeof(entry));
218 }
219
220 /* Programs the physical address of the device table into the IOMMU hardware */
221 static void __init iommu_set_device_table(struct amd_iommu *iommu)
222 {
223 u64 entry;
224
225 BUG_ON(iommu->mmio_base == NULL);
226
227 entry = virt_to_phys(amd_iommu_dev_table);
228 entry |= (dev_table_size >> 12) - 1;
229 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
230 &entry, sizeof(entry));
231 }
232
233 /* Generic functions to enable/disable certain features of the IOMMU. */
234 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
235 {
236 u32 ctrl;
237
238 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
239 ctrl |= (1 << bit);
240 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
241 }
242
243 static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
244 {
245 u32 ctrl;
246
247 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
248 ctrl &= ~(1 << bit);
249 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
250 }
251
252 /* Function to enable the hardware */
253 static void iommu_enable(struct amd_iommu *iommu)
254 {
255 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n",
256 dev_name(&iommu->dev->dev), iommu->cap_ptr);
257
258 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
259 }
260
261 static void iommu_disable(struct amd_iommu *iommu)
262 {
263 /* Disable command buffer */
264 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
265
266 /* Disable event logging and event interrupts */
267 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
268 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
269
270 /* Disable IOMMU hardware itself */
271 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
272 }
273
274 /*
275 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
276 * the system has one.
277 */
278 static u8 * __init iommu_map_mmio_space(u64 address)
279 {
280 u8 *ret;
281
282 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
283 return NULL;
284
285 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
286 if (ret != NULL)
287 return ret;
288
289 release_mem_region(address, MMIO_REGION_LENGTH);
290
291 return NULL;
292 }
293
294 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
295 {
296 if (iommu->mmio_base)
297 iounmap(iommu->mmio_base);
298 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
299 }
300
301 /****************************************************************************
302 *
303 * The functions below belong to the first pass of AMD IOMMU ACPI table
304 * parsing. In this pass we try to find out the highest device id this
305 * code has to handle. Upon this information the size of the shared data
306 * structures is determined later.
307 *
308 ****************************************************************************/
309
310 /*
311 * This function calculates the length of a given IVHD entry
312 */
313 static inline int ivhd_entry_length(u8 *ivhd)
314 {
315 return 0x04 << (*ivhd >> 6);
316 }
317
318 /*
319 * This function reads the last device id the IOMMU has to handle from the PCI
320 * capability header for this IOMMU
321 */
322 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
323 {
324 u32 cap;
325
326 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
327 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
328
329 return 0;
330 }
331
332 /*
333 * After reading the highest device id from the IOMMU PCI capability header
334 * this function looks if there is a higher device id defined in the ACPI table
335 */
336 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
337 {
338 u8 *p = (void *)h, *end = (void *)h;
339 struct ivhd_entry *dev;
340
341 p += sizeof(*h);
342 end += h->length;
343
344 find_last_devid_on_pci(PCI_BUS(h->devid),
345 PCI_SLOT(h->devid),
346 PCI_FUNC(h->devid),
347 h->cap_ptr);
348
349 while (p < end) {
350 dev = (struct ivhd_entry *)p;
351 switch (dev->type) {
352 case IVHD_DEV_SELECT:
353 case IVHD_DEV_RANGE_END:
354 case IVHD_DEV_ALIAS:
355 case IVHD_DEV_EXT_SELECT:
356 /* all the above subfield types refer to device ids */
357 update_last_devid(dev->devid);
358 break;
359 default:
360 break;
361 }
362 p += ivhd_entry_length(p);
363 }
364
365 WARN_ON(p != end);
366
367 return 0;
368 }
369
370 /*
371 * Iterate over all IVHD entries in the ACPI table and find the highest device
372 * id which we need to handle. This is the first of three functions which parse
373 * the ACPI table. So we check the checksum here.
374 */
375 static int __init find_last_devid_acpi(struct acpi_table_header *table)
376 {
377 int i;
378 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
379 struct ivhd_header *h;
380
381 /*
382 * Validate checksum here so we don't need to do it when
383 * we actually parse the table
384 */
385 for (i = 0; i < table->length; ++i)
386 checksum += p[i];
387 if (checksum != 0)
388 /* ACPI table corrupt */
389 return -ENODEV;
390
391 p += IVRS_HEADER_LENGTH;
392
393 end += table->length;
394 while (p < end) {
395 h = (struct ivhd_header *)p;
396 switch (h->type) {
397 case ACPI_IVHD_TYPE:
398 find_last_devid_from_ivhd(h);
399 break;
400 default:
401 break;
402 }
403 p += h->length;
404 }
405 WARN_ON(p != end);
406
407 return 0;
408 }
409
410 /****************************************************************************
411 *
412 * The following functions belong the the code path which parses the ACPI table
413 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
414 * data structures, initialize the device/alias/rlookup table and also
415 * basically initialize the hardware.
416 *
417 ****************************************************************************/
418
419 /*
420 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
421 * write commands to that buffer later and the IOMMU will execute them
422 * asynchronously
423 */
424 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
425 {
426 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
427 get_order(CMD_BUFFER_SIZE));
428
429 if (cmd_buf == NULL)
430 return NULL;
431
432 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
433
434 return cmd_buf;
435 }
436
437 /*
438 * This function writes the command buffer address to the hardware and
439 * enables it.
440 */
441 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
442 {
443 u64 entry;
444
445 BUG_ON(iommu->cmd_buf == NULL);
446
447 entry = (u64)virt_to_phys(iommu->cmd_buf);
448 entry |= MMIO_CMD_SIZE_512;
449
450 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
451 &entry, sizeof(entry));
452
453 /* set head and tail to zero manually */
454 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
455 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
456
457 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
458 }
459
460 static void __init free_command_buffer(struct amd_iommu *iommu)
461 {
462 free_pages((unsigned long)iommu->cmd_buf,
463 get_order(iommu->cmd_buf_size));
464 }
465
466 /* allocates the memory where the IOMMU will log its events to */
467 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
468 {
469 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
470 get_order(EVT_BUFFER_SIZE));
471
472 if (iommu->evt_buf == NULL)
473 return NULL;
474
475 return iommu->evt_buf;
476 }
477
478 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
479 {
480 u64 entry;
481
482 BUG_ON(iommu->evt_buf == NULL);
483
484 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
485
486 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
487 &entry, sizeof(entry));
488
489 /* set head and tail to zero manually */
490 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
491 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
492
493 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
494 }
495
496 static void __init free_event_buffer(struct amd_iommu *iommu)
497 {
498 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
499 }
500
501 /* sets a specific bit in the device table entry. */
502 static void set_dev_entry_bit(u16 devid, u8 bit)
503 {
504 int i = (bit >> 5) & 0x07;
505 int _bit = bit & 0x1f;
506
507 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
508 }
509
510 /* Writes the specific IOMMU for a device into the rlookup table */
511 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
512 {
513 amd_iommu_rlookup_table[devid] = iommu;
514 }
515
516 /*
517 * This function takes the device specific flags read from the ACPI
518 * table and sets up the device table entry with that information
519 */
520 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
521 u16 devid, u32 flags, u32 ext_flags)
522 {
523 if (flags & ACPI_DEVFLAG_INITPASS)
524 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
525 if (flags & ACPI_DEVFLAG_EXTINT)
526 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
527 if (flags & ACPI_DEVFLAG_NMI)
528 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
529 if (flags & ACPI_DEVFLAG_SYSMGT1)
530 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
531 if (flags & ACPI_DEVFLAG_SYSMGT2)
532 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
533 if (flags & ACPI_DEVFLAG_LINT0)
534 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
535 if (flags & ACPI_DEVFLAG_LINT1)
536 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
537
538 set_iommu_for_device(iommu, devid);
539 }
540
541 /*
542 * Reads the device exclusion range from ACPI and initialize IOMMU with
543 * it
544 */
545 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
546 {
547 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
548
549 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
550 return;
551
552 if (iommu) {
553 /*
554 * We only can configure exclusion ranges per IOMMU, not
555 * per device. But we can enable the exclusion range per
556 * device. This is done here
557 */
558 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
559 iommu->exclusion_start = m->range_start;
560 iommu->exclusion_length = m->range_length;
561 }
562 }
563
564 /*
565 * This function reads some important data from the IOMMU PCI space and
566 * initializes the driver data structure with it. It reads the hardware
567 * capabilities and the first/last device entries
568 */
569 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
570 {
571 int cap_ptr = iommu->cap_ptr;
572 u32 range, misc;
573
574 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
575 &iommu->cap);
576 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
577 &range);
578 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
579 &misc);
580
581 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
582 MMIO_GET_FD(range));
583 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
584 MMIO_GET_LD(range));
585 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
586 }
587
588 /*
589 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
590 * initializes the hardware and our data structures with it.
591 */
592 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
593 struct ivhd_header *h)
594 {
595 u8 *p = (u8 *)h;
596 u8 *end = p, flags = 0;
597 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
598 u32 ext_flags = 0;
599 bool alias = false;
600 struct ivhd_entry *e;
601
602 /*
603 * First set the recommended feature enable bits from ACPI
604 * into the IOMMU control registers
605 */
606 h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
607 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
608 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
609
610 h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
611 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
612 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
613
614 h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
615 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
616 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
617
618 h->flags & IVHD_FLAG_ISOC_EN_MASK ?
619 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
620 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
621
622 /*
623 * make IOMMU memory accesses cache coherent
624 */
625 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
626
627 /*
628 * Done. Now parse the device entries
629 */
630 p += sizeof(struct ivhd_header);
631 end += h->length;
632
633
634 while (p < end) {
635 e = (struct ivhd_entry *)p;
636 switch (e->type) {
637 case IVHD_DEV_ALL:
638
639 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
640 " last device %02x:%02x.%x flags: %02x\n",
641 PCI_BUS(iommu->first_device),
642 PCI_SLOT(iommu->first_device),
643 PCI_FUNC(iommu->first_device),
644 PCI_BUS(iommu->last_device),
645 PCI_SLOT(iommu->last_device),
646 PCI_FUNC(iommu->last_device),
647 e->flags);
648
649 for (dev_i = iommu->first_device;
650 dev_i <= iommu->last_device; ++dev_i)
651 set_dev_entry_from_acpi(iommu, dev_i,
652 e->flags, 0);
653 break;
654 case IVHD_DEV_SELECT:
655
656 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
657 "flags: %02x\n",
658 PCI_BUS(e->devid),
659 PCI_SLOT(e->devid),
660 PCI_FUNC(e->devid),
661 e->flags);
662
663 devid = e->devid;
664 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
665 break;
666 case IVHD_DEV_SELECT_RANGE_START:
667
668 DUMP_printk(" DEV_SELECT_RANGE_START\t "
669 "devid: %02x:%02x.%x flags: %02x\n",
670 PCI_BUS(e->devid),
671 PCI_SLOT(e->devid),
672 PCI_FUNC(e->devid),
673 e->flags);
674
675 devid_start = e->devid;
676 flags = e->flags;
677 ext_flags = 0;
678 alias = false;
679 break;
680 case IVHD_DEV_ALIAS:
681
682 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
683 "flags: %02x devid_to: %02x:%02x.%x\n",
684 PCI_BUS(e->devid),
685 PCI_SLOT(e->devid),
686 PCI_FUNC(e->devid),
687 e->flags,
688 PCI_BUS(e->ext >> 8),
689 PCI_SLOT(e->ext >> 8),
690 PCI_FUNC(e->ext >> 8));
691
692 devid = e->devid;
693 devid_to = e->ext >> 8;
694 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
695 amd_iommu_alias_table[devid] = devid_to;
696 break;
697 case IVHD_DEV_ALIAS_RANGE:
698
699 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
700 "devid: %02x:%02x.%x flags: %02x "
701 "devid_to: %02x:%02x.%x\n",
702 PCI_BUS(e->devid),
703 PCI_SLOT(e->devid),
704 PCI_FUNC(e->devid),
705 e->flags,
706 PCI_BUS(e->ext >> 8),
707 PCI_SLOT(e->ext >> 8),
708 PCI_FUNC(e->ext >> 8));
709
710 devid_start = e->devid;
711 flags = e->flags;
712 devid_to = e->ext >> 8;
713 ext_flags = 0;
714 alias = true;
715 break;
716 case IVHD_DEV_EXT_SELECT:
717
718 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
719 "flags: %02x ext: %08x\n",
720 PCI_BUS(e->devid),
721 PCI_SLOT(e->devid),
722 PCI_FUNC(e->devid),
723 e->flags, e->ext);
724
725 devid = e->devid;
726 set_dev_entry_from_acpi(iommu, devid, e->flags,
727 e->ext);
728 break;
729 case IVHD_DEV_EXT_SELECT_RANGE:
730
731 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
732 "%02x:%02x.%x flags: %02x ext: %08x\n",
733 PCI_BUS(e->devid),
734 PCI_SLOT(e->devid),
735 PCI_FUNC(e->devid),
736 e->flags, e->ext);
737
738 devid_start = e->devid;
739 flags = e->flags;
740 ext_flags = e->ext;
741 alias = false;
742 break;
743 case IVHD_DEV_RANGE_END:
744
745 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
746 PCI_BUS(e->devid),
747 PCI_SLOT(e->devid),
748 PCI_FUNC(e->devid));
749
750 devid = e->devid;
751 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
752 if (alias)
753 amd_iommu_alias_table[dev_i] = devid_to;
754 set_dev_entry_from_acpi(iommu,
755 amd_iommu_alias_table[dev_i],
756 flags, ext_flags);
757 }
758 break;
759 default:
760 break;
761 }
762
763 p += ivhd_entry_length(p);
764 }
765 }
766
767 /* Initializes the device->iommu mapping for the driver */
768 static int __init init_iommu_devices(struct amd_iommu *iommu)
769 {
770 u16 i;
771
772 for (i = iommu->first_device; i <= iommu->last_device; ++i)
773 set_iommu_for_device(iommu, i);
774
775 return 0;
776 }
777
778 static void __init free_iommu_one(struct amd_iommu *iommu)
779 {
780 free_command_buffer(iommu);
781 free_event_buffer(iommu);
782 iommu_unmap_mmio_space(iommu);
783 }
784
785 static void __init free_iommu_all(void)
786 {
787 struct amd_iommu *iommu, *next;
788
789 for_each_iommu_safe(iommu, next) {
790 list_del(&iommu->list);
791 free_iommu_one(iommu);
792 kfree(iommu);
793 }
794 }
795
796 /*
797 * This function clues the initialization function for one IOMMU
798 * together and also allocates the command buffer and programs the
799 * hardware. It does NOT enable the IOMMU. This is done afterwards.
800 */
801 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
802 {
803 spin_lock_init(&iommu->lock);
804 list_add_tail(&iommu->list, &amd_iommu_list);
805
806 /*
807 * Copy data from ACPI table entry to the iommu struct
808 */
809 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
810 if (!iommu->dev)
811 return 1;
812
813 iommu->cap_ptr = h->cap_ptr;
814 iommu->pci_seg = h->pci_seg;
815 iommu->mmio_phys = h->mmio_phys;
816 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
817 if (!iommu->mmio_base)
818 return -ENOMEM;
819
820 iommu->cmd_buf = alloc_command_buffer(iommu);
821 if (!iommu->cmd_buf)
822 return -ENOMEM;
823
824 iommu->evt_buf = alloc_event_buffer(iommu);
825 if (!iommu->evt_buf)
826 return -ENOMEM;
827
828 iommu->int_enabled = false;
829
830 init_iommu_from_pci(iommu);
831 init_iommu_from_acpi(iommu, h);
832 init_iommu_devices(iommu);
833
834 return pci_enable_device(iommu->dev);
835 }
836
837 /*
838 * Iterates over all IOMMU entries in the ACPI table, allocates the
839 * IOMMU structure and initializes it with init_iommu_one()
840 */
841 static int __init init_iommu_all(struct acpi_table_header *table)
842 {
843 u8 *p = (u8 *)table, *end = (u8 *)table;
844 struct ivhd_header *h;
845 struct amd_iommu *iommu;
846 int ret;
847
848 end += table->length;
849 p += IVRS_HEADER_LENGTH;
850
851 while (p < end) {
852 h = (struct ivhd_header *)p;
853 switch (*p) {
854 case ACPI_IVHD_TYPE:
855
856 DUMP_printk("IOMMU: device: %02x:%02x.%01x cap: %04x "
857 "seg: %d flags: %01x info %04x\n",
858 PCI_BUS(h->devid), PCI_SLOT(h->devid),
859 PCI_FUNC(h->devid), h->cap_ptr,
860 h->pci_seg, h->flags, h->info);
861 DUMP_printk(" mmio-addr: %016llx\n",
862 h->mmio_phys);
863
864 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
865 if (iommu == NULL)
866 return -ENOMEM;
867 ret = init_iommu_one(iommu, h);
868 if (ret)
869 return ret;
870 break;
871 default:
872 break;
873 }
874 p += h->length;
875
876 }
877 WARN_ON(p != end);
878
879 return 0;
880 }
881
882 /****************************************************************************
883 *
884 * The following functions initialize the MSI interrupts for all IOMMUs
885 * in the system. Its a bit challenging because there could be multiple
886 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
887 * pci_dev.
888 *
889 ****************************************************************************/
890
891 static int __init iommu_setup_msi(struct amd_iommu *iommu)
892 {
893 int r;
894
895 if (pci_enable_msi(iommu->dev))
896 return 1;
897
898 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
899 IRQF_SAMPLE_RANDOM,
900 "AMD IOMMU",
901 NULL);
902
903 if (r) {
904 pci_disable_msi(iommu->dev);
905 return 1;
906 }
907
908 iommu->int_enabled = true;
909 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
910
911 return 0;
912 }
913
914 static int iommu_init_msi(struct amd_iommu *iommu)
915 {
916 if (iommu->int_enabled)
917 return 0;
918
919 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
920 return iommu_setup_msi(iommu);
921
922 return 1;
923 }
924
925 /****************************************************************************
926 *
927 * The next functions belong to the third pass of parsing the ACPI
928 * table. In this last pass the memory mapping requirements are
929 * gathered (like exclusion and unity mapping reanges).
930 *
931 ****************************************************************************/
932
933 static void __init free_unity_maps(void)
934 {
935 struct unity_map_entry *entry, *next;
936
937 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
938 list_del(&entry->list);
939 kfree(entry);
940 }
941 }
942
943 /* called when we find an exclusion range definition in ACPI */
944 static int __init init_exclusion_range(struct ivmd_header *m)
945 {
946 int i;
947
948 switch (m->type) {
949 case ACPI_IVMD_TYPE:
950 set_device_exclusion_range(m->devid, m);
951 break;
952 case ACPI_IVMD_TYPE_ALL:
953 for (i = 0; i <= amd_iommu_last_bdf; ++i)
954 set_device_exclusion_range(i, m);
955 break;
956 case ACPI_IVMD_TYPE_RANGE:
957 for (i = m->devid; i <= m->aux; ++i)
958 set_device_exclusion_range(i, m);
959 break;
960 default:
961 break;
962 }
963
964 return 0;
965 }
966
967 /* called for unity map ACPI definition */
968 static int __init init_unity_map_range(struct ivmd_header *m)
969 {
970 struct unity_map_entry *e = 0;
971 char *s;
972
973 e = kzalloc(sizeof(*e), GFP_KERNEL);
974 if (e == NULL)
975 return -ENOMEM;
976
977 switch (m->type) {
978 default:
979 kfree(e);
980 return 0;
981 case ACPI_IVMD_TYPE:
982 s = "IVMD_TYPEi\t\t\t";
983 e->devid_start = e->devid_end = m->devid;
984 break;
985 case ACPI_IVMD_TYPE_ALL:
986 s = "IVMD_TYPE_ALL\t\t";
987 e->devid_start = 0;
988 e->devid_end = amd_iommu_last_bdf;
989 break;
990 case ACPI_IVMD_TYPE_RANGE:
991 s = "IVMD_TYPE_RANGE\t\t";
992 e->devid_start = m->devid;
993 e->devid_end = m->aux;
994 break;
995 }
996 e->address_start = PAGE_ALIGN(m->range_start);
997 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
998 e->prot = m->flags >> 1;
999
1000 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1001 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1002 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1003 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1004 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1005 e->address_start, e->address_end, m->flags);
1006
1007 list_add_tail(&e->list, &amd_iommu_unity_map);
1008
1009 return 0;
1010 }
1011
1012 /* iterates over all memory definitions we find in the ACPI table */
1013 static int __init init_memory_definitions(struct acpi_table_header *table)
1014 {
1015 u8 *p = (u8 *)table, *end = (u8 *)table;
1016 struct ivmd_header *m;
1017
1018 end += table->length;
1019 p += IVRS_HEADER_LENGTH;
1020
1021 while (p < end) {
1022 m = (struct ivmd_header *)p;
1023 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1024 init_exclusion_range(m);
1025 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1026 init_unity_map_range(m);
1027
1028 p += m->length;
1029 }
1030
1031 return 0;
1032 }
1033
1034 /*
1035 * Init the device table to not allow DMA access for devices and
1036 * suppress all page faults
1037 */
1038 static void init_device_table(void)
1039 {
1040 u16 devid;
1041
1042 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1043 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1044 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1045 }
1046 }
1047
1048 /*
1049 * This function finally enables all IOMMUs found in the system after
1050 * they have been initialized
1051 */
1052 static void enable_iommus(void)
1053 {
1054 struct amd_iommu *iommu;
1055
1056 for_each_iommu(iommu) {
1057 iommu_disable(iommu);
1058 iommu_set_device_table(iommu);
1059 iommu_enable_command_buffer(iommu);
1060 iommu_enable_event_buffer(iommu);
1061 iommu_set_exclusion_range(iommu);
1062 iommu_init_msi(iommu);
1063 iommu_enable(iommu);
1064 }
1065 }
1066
1067 static void disable_iommus(void)
1068 {
1069 struct amd_iommu *iommu;
1070
1071 for_each_iommu(iommu)
1072 iommu_disable(iommu);
1073 }
1074
1075 /*
1076 * Suspend/Resume support
1077 * disable suspend until real resume implemented
1078 */
1079
1080 static int amd_iommu_resume(struct sys_device *dev)
1081 {
1082 /* re-load the hardware */
1083 enable_iommus();
1084
1085 /*
1086 * we have to flush after the IOMMUs are enabled because a
1087 * disabled IOMMU will never execute the commands we send
1088 */
1089 amd_iommu_flush_all_devices();
1090 amd_iommu_flush_all_domains();
1091
1092 return 0;
1093 }
1094
1095 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1096 {
1097 /* disable IOMMUs to go out of the way for BIOS */
1098 disable_iommus();
1099
1100 return 0;
1101 }
1102
1103 static struct sysdev_class amd_iommu_sysdev_class = {
1104 .name = "amd_iommu",
1105 .suspend = amd_iommu_suspend,
1106 .resume = amd_iommu_resume,
1107 };
1108
1109 static struct sys_device device_amd_iommu = {
1110 .id = 0,
1111 .cls = &amd_iommu_sysdev_class,
1112 };
1113
1114 /*
1115 * This is the core init function for AMD IOMMU hardware in the system.
1116 * This function is called from the generic x86 DMA layer initialization
1117 * code.
1118 *
1119 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1120 * three times:
1121 *
1122 * 1 pass) Find the highest PCI device id the driver has to handle.
1123 * Upon this information the size of the data structures is
1124 * determined that needs to be allocated.
1125 *
1126 * 2 pass) Initialize the data structures just allocated with the
1127 * information in the ACPI table about available AMD IOMMUs
1128 * in the system. It also maps the PCI devices in the
1129 * system to specific IOMMUs
1130 *
1131 * 3 pass) After the basic data structures are allocated and
1132 * initialized we update them with information about memory
1133 * remapping requirements parsed out of the ACPI table in
1134 * this last pass.
1135 *
1136 * After that the hardware is initialized and ready to go. In the last
1137 * step we do some Linux specific things like registering the driver in
1138 * the dma_ops interface and initializing the suspend/resume support
1139 * functions. Finally it prints some information about AMD IOMMUs and
1140 * the driver state and enables the hardware.
1141 */
1142 int __init amd_iommu_init(void)
1143 {
1144 int i, ret = 0;
1145
1146
1147 if (no_iommu) {
1148 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
1149 return 0;
1150 }
1151
1152 if (!amd_iommu_detected)
1153 return -ENODEV;
1154
1155 /*
1156 * First parse ACPI tables to find the largest Bus/Dev/Func
1157 * we need to handle. Upon this information the shared data
1158 * structures for the IOMMUs in the system will be allocated
1159 */
1160 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1161 return -ENODEV;
1162
1163 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1164 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1165 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1166
1167 ret = -ENOMEM;
1168
1169 /* Device table - directly used by all IOMMUs */
1170 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1171 get_order(dev_table_size));
1172 if (amd_iommu_dev_table == NULL)
1173 goto out;
1174
1175 /*
1176 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1177 * IOMMU see for that device
1178 */
1179 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1180 get_order(alias_table_size));
1181 if (amd_iommu_alias_table == NULL)
1182 goto free;
1183
1184 /* IOMMU rlookup table - find the IOMMU for a specific device */
1185 amd_iommu_rlookup_table = (void *)__get_free_pages(
1186 GFP_KERNEL | __GFP_ZERO,
1187 get_order(rlookup_table_size));
1188 if (amd_iommu_rlookup_table == NULL)
1189 goto free;
1190
1191 /*
1192 * Protection Domain table - maps devices to protection domains
1193 * This table has the same size as the rlookup_table
1194 */
1195 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1196 get_order(rlookup_table_size));
1197 if (amd_iommu_pd_table == NULL)
1198 goto free;
1199
1200 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1201 GFP_KERNEL | __GFP_ZERO,
1202 get_order(MAX_DOMAIN_ID/8));
1203 if (amd_iommu_pd_alloc_bitmap == NULL)
1204 goto free;
1205
1206 /* init the device table */
1207 init_device_table();
1208
1209 /*
1210 * let all alias entries point to itself
1211 */
1212 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1213 amd_iommu_alias_table[i] = i;
1214
1215 /*
1216 * never allocate domain 0 because its used as the non-allocated and
1217 * error value placeholder
1218 */
1219 amd_iommu_pd_alloc_bitmap[0] = 1;
1220
1221 /*
1222 * now the data structures are allocated and basically initialized
1223 * start the real acpi table scan
1224 */
1225 ret = -ENODEV;
1226 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1227 goto free;
1228
1229 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1230 goto free;
1231
1232 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1233 if (ret)
1234 goto free;
1235
1236 ret = sysdev_register(&device_amd_iommu);
1237 if (ret)
1238 goto free;
1239
1240 ret = amd_iommu_init_dma_ops();
1241 if (ret)
1242 goto free;
1243
1244 enable_iommus();
1245
1246 printk(KERN_INFO "AMD IOMMU: device isolation ");
1247 if (amd_iommu_isolate)
1248 printk("enabled\n");
1249 else
1250 printk("disabled\n");
1251
1252 if (amd_iommu_unmap_flush)
1253 printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
1254 else
1255 printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1256
1257 out:
1258 return ret;
1259
1260 free:
1261 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1262 get_order(MAX_DOMAIN_ID/8));
1263
1264 free_pages((unsigned long)amd_iommu_pd_table,
1265 get_order(rlookup_table_size));
1266
1267 free_pages((unsigned long)amd_iommu_rlookup_table,
1268 get_order(rlookup_table_size));
1269
1270 free_pages((unsigned long)amd_iommu_alias_table,
1271 get_order(alias_table_size));
1272
1273 free_pages((unsigned long)amd_iommu_dev_table,
1274 get_order(dev_table_size));
1275
1276 free_iommu_all();
1277
1278 free_unity_maps();
1279
1280 goto out;
1281 }
1282
1283 void amd_iommu_shutdown(void)
1284 {
1285 disable_iommus();
1286 }
1287
1288 /****************************************************************************
1289 *
1290 * Early detect code. This code runs at IOMMU detection time in the DMA
1291 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1292 * IOMMUs
1293 *
1294 ****************************************************************************/
1295 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1296 {
1297 return 0;
1298 }
1299
1300 void __init amd_iommu_detect(void)
1301 {
1302 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1303 return;
1304
1305 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1306 iommu_detected = 1;
1307 amd_iommu_detected = 1;
1308 #ifdef CONFIG_GART_IOMMU
1309 gart_iommu_aperture_disabled = 1;
1310 gart_iommu_aperture = 0;
1311 #endif
1312 }
1313 }
1314
1315 /****************************************************************************
1316 *
1317 * Parsing functions for the AMD IOMMU specific kernel command line
1318 * options.
1319 *
1320 ****************************************************************************/
1321
1322 static int __init parse_amd_iommu_dump(char *str)
1323 {
1324 amd_iommu_dump = true;
1325
1326 return 1;
1327 }
1328
1329 static int __init parse_amd_iommu_options(char *str)
1330 {
1331 for (; *str; ++str) {
1332 if (strncmp(str, "isolate", 7) == 0)
1333 amd_iommu_isolate = true;
1334 if (strncmp(str, "share", 5) == 0)
1335 amd_iommu_isolate = false;
1336 if (strncmp(str, "fullflush", 9) == 0)
1337 amd_iommu_unmap_flush = true;
1338 }
1339
1340 return 1;
1341 }
1342
1343 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1344 __setup("amd_iommu=", parse_amd_iommu_options);
WandBoard kernel