2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
4 #ifndef _ASM_POWERPC_SYSTEM_H
5 #define _ASM_POWERPC_SYSTEM_H
7 #include <linux/config.h>
8 #include <linux/kernel.h>
10 #include <asm/hw_irq.h>
11 #include <asm/ppc_asm.h>
12 #include <asm/atomic.h>
16 * The sync instruction guarantees that all memory accesses initiated
17 * by this processor have been performed (with respect to all other
18 * mechanisms that access memory). The eieio instruction is a barrier
19 * providing an ordering (separately) for (a) cacheable stores and (b)
20 * loads and stores to non-cacheable memory (e.g. I/O devices).
22 * mb() prevents loads and stores being reordered across this point.
23 * rmb() prevents loads being reordered across this point.
24 * wmb() prevents stores being reordered across this point.
25 * read_barrier_depends() prevents data-dependent loads being reordered
26 * across this point (nop on PPC).
28 * We have to use the sync instructions for mb(), since lwsync doesn't
29 * order loads with respect to previous stores. Lwsync is fine for
30 * rmb(), though. Note that lwsync is interpreted as sync by
31 * 32-bit and older 64-bit CPUs.
33 * For wmb(), we use sync since wmb is used in drivers to order
34 * stores to system memory with respect to writes to the device.
35 * However, smp_wmb() can be a lighter-weight eieio barrier on
36 * SMP since it is only used to order updates to system memory.
38 #define mb() __asm__ __volatile__ ("sync" : : : "memory")
39 #define rmb() __asm__ __volatile__ ("lwsync" : : : "memory")
40 #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
41 #define read_barrier_depends() do { } while(0)
43 #define set_mb(var, value) do { var = value; mb(); } while (0)
44 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
48 #define smp_rmb() rmb()
49 #define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
50 #define smp_read_barrier_depends() read_barrier_depends()
52 #define smp_mb() barrier()
53 #define smp_rmb() barrier()
54 #define smp_wmb() barrier()
55 #define smp_read_barrier_depends() do { } while(0)
56 #endif /* CONFIG_SMP */
62 #ifdef CONFIG_DEBUGGER
64 extern int (*__debugger
)(struct pt_regs
*regs
);
65 extern int (*__debugger_ipi
)(struct pt_regs
*regs
);
66 extern int (*__debugger_bpt
)(struct pt_regs
*regs
);
67 extern int (*__debugger_sstep
)(struct pt_regs
*regs
);
68 extern int (*__debugger_iabr_match
)(struct pt_regs
*regs
);
69 extern int (*__debugger_dabr_match
)(struct pt_regs
*regs
);
70 extern int (*__debugger_fault_handler
)(struct pt_regs
*regs
);
72 #define DEBUGGER_BOILERPLATE(__NAME) \
73 static inline int __NAME(struct pt_regs *regs) \
75 if (unlikely(__ ## __NAME)) \
76 return __ ## __NAME(regs); \
80 DEBUGGER_BOILERPLATE(debugger
)
81 DEBUGGER_BOILERPLATE(debugger_ipi
)
82 DEBUGGER_BOILERPLATE(debugger_bpt
)
83 DEBUGGER_BOILERPLATE(debugger_sstep
)
84 DEBUGGER_BOILERPLATE(debugger_iabr_match
)
85 DEBUGGER_BOILERPLATE(debugger_dabr_match
)
86 DEBUGGER_BOILERPLATE(debugger_fault_handler
)
89 extern void xmon_init(int enable
);
93 static inline int debugger(struct pt_regs
*regs
) { return 0; }
94 static inline int debugger_ipi(struct pt_regs
*regs
) { return 0; }
95 static inline int debugger_bpt(struct pt_regs
*regs
) { return 0; }
96 static inline int debugger_sstep(struct pt_regs
*regs
) { return 0; }
97 static inline int debugger_iabr_match(struct pt_regs
*regs
) { return 0; }
98 static inline int debugger_dabr_match(struct pt_regs
*regs
) { return 0; }
99 static inline int debugger_fault_handler(struct pt_regs
*regs
) { return 0; }
102 extern int set_dabr(unsigned long dabr
);
103 extern void print_backtrace(unsigned long *);
104 extern void show_regs(struct pt_regs
* regs
);
105 extern void flush_instruction_cache(void);
106 extern void hard_reset_now(void);
107 extern void poweroff_now(void);
110 extern long _get_L2CR(void);
111 extern long _get_L3CR(void);
112 extern void _set_L2CR(unsigned long);
113 extern void _set_L3CR(unsigned long);
115 #define _get_L2CR() 0L
116 #define _get_L3CR() 0L
117 #define _set_L2CR(val) do { } while(0)
118 #define _set_L3CR(val) do { } while(0)
121 extern void via_cuda_init(void);
122 extern void read_rtc_time(void);
123 extern void pmac_find_display(void);
124 extern void giveup_fpu(struct task_struct
*);
125 extern void disable_kernel_fp(void);
126 extern void enable_kernel_fp(void);
127 extern void flush_fp_to_thread(struct task_struct
*);
128 extern void enable_kernel_altivec(void);
129 extern void giveup_altivec(struct task_struct
*);
130 extern void load_up_altivec(struct task_struct
*);
131 extern int emulate_altivec(struct pt_regs
*);
132 extern void giveup_spe(struct task_struct
*);
133 extern void load_up_spe(struct task_struct
*);
134 extern int fix_alignment(struct pt_regs
*);
135 extern void cvt_fd(float *from
, double *to
, struct thread_struct
*thread
);
136 extern void cvt_df(double *from
, float *to
, struct thread_struct
*thread
);
138 #ifdef CONFIG_ALTIVEC
139 extern void flush_altivec_to_thread(struct task_struct
*);
141 static inline void flush_altivec_to_thread(struct task_struct
*t
)
147 extern void flush_spe_to_thread(struct task_struct
*);
149 static inline void flush_spe_to_thread(struct task_struct
*t
)
154 extern int call_rtas(const char *, int, int, unsigned long *, ...);
155 extern void cacheable_memzero(void *p
, unsigned int nb
);
156 extern void *cacheable_memcpy(void *, const void *, unsigned int);
157 extern int do_page_fault(struct pt_regs
*, unsigned long, unsigned long);
158 extern void bad_page_fault(struct pt_regs
*, unsigned long, int);
159 extern int die(const char *, struct pt_regs
*, long);
160 extern void _exception(int, struct pt_regs
*, int, unsigned long);
161 #ifdef CONFIG_BOOKE_WDT
162 extern u32 booke_wdt_enabled
;
163 extern u32 booke_wdt_period
;
164 #endif /* CONFIG_BOOKE_WDT */
166 /* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
167 extern unsigned char e2a(unsigned char);
170 extern void note_scsi_host(struct device_node
*, void *);
172 extern struct task_struct
*__switch_to(struct task_struct
*,
173 struct task_struct
*);
174 #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
176 struct thread_struct
;
177 extern struct task_struct
*_switch(struct thread_struct
*prev
,
178 struct thread_struct
*next
);
180 extern unsigned int rtas_data
;
181 extern int mem_init_done
; /* set on boot once kmalloc can be called */
182 extern unsigned long memory_limit
;
184 extern int powersave_nap
; /* set if nap mode can be used in idle loop */
189 * Changes the memory location '*ptr' to be val and returns
190 * the previous value stored there.
192 static __inline__
unsigned long
193 __xchg_u32(volatile void *p
, unsigned long val
)
197 __asm__
__volatile__(
199 "1: lwarx %0,0,%2 \n"
204 : "=&r" (prev
), "=m" (*(volatile unsigned int *)p
)
205 : "r" (p
), "r" (val
), "m" (*(volatile unsigned int *)p
)
212 static __inline__
unsigned long
213 __xchg_u64(volatile void *p
, unsigned long val
)
217 __asm__
__volatile__(
219 "1: ldarx %0,0,%2 \n"
224 : "=&r" (prev
), "=m" (*(volatile unsigned long *)p
)
225 : "r" (p
), "r" (val
), "m" (*(volatile unsigned long *)p
)
233 * This function doesn't exist, so you'll get a linker error
234 * if something tries to do an invalid xchg().
236 extern void __xchg_called_with_bad_pointer(void);
238 static __inline__
unsigned long
239 __xchg(volatile void *ptr
, unsigned long x
, unsigned int size
)
243 return __xchg_u32(ptr
, x
);
246 return __xchg_u64(ptr
, x
);
249 __xchg_called_with_bad_pointer();
253 #define xchg(ptr,x) \
255 __typeof__(*(ptr)) _x_ = (x); \
256 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
259 #define tas(ptr) (xchg((ptr),1))
262 * Compare and exchange - if *p == old, set it to new,
263 * and return the old value of *p.
265 #define __HAVE_ARCH_CMPXCHG 1
267 static __inline__
unsigned long
268 __cmpxchg_u32(volatile unsigned int *p
, unsigned long old
, unsigned long new)
272 __asm__
__volatile__ (
274 "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
283 : "=&r" (prev
), "=m" (*p
)
284 : "r" (p
), "r" (old
), "r" (new), "m" (*p
)
291 static __inline__
unsigned long
292 __cmpxchg_u64(volatile unsigned long *p
, unsigned long old
, unsigned long new)
296 __asm__
__volatile__ (
298 "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
306 : "=&r" (prev
), "=m" (*p
)
307 : "r" (p
), "r" (old
), "r" (new), "m" (*p
)
314 /* This function doesn't exist, so you'll get a linker error
315 if something tries to do an invalid cmpxchg(). */
316 extern void __cmpxchg_called_with_bad_pointer(void);
318 static __inline__
unsigned long
319 __cmpxchg(volatile void *ptr
, unsigned long old
, unsigned long new,
324 return __cmpxchg_u32(ptr
, old
, new);
327 return __cmpxchg_u64(ptr
, old
, new);
330 __cmpxchg_called_with_bad_pointer();
334 #define cmpxchg(ptr,o,n) \
336 __typeof__(*(ptr)) _o_ = (o); \
337 __typeof__(*(ptr)) _n_ = (n); \
338 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
339 (unsigned long)_n_, sizeof(*(ptr))); \
344 * We handle most unaligned accesses in hardware. On the other hand
345 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
346 * powers of 2 writes until it reaches sufficient alignment).
348 * Based on this we disable the IP header alignment in network drivers.
350 #define NET_IP_ALIGN 0
353 #define arch_align_stack(x) (x)
355 /* Used in very early kernel initialization. */
356 extern unsigned long reloc_offset(void);
357 extern unsigned long add_reloc_offset(unsigned long);
358 extern void reloc_got2(unsigned long);
360 #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
362 static inline void create_instruction(unsigned long addr
, unsigned int instr
)
365 p
= (unsigned int *)addr
;
367 asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p
));
370 /* Flags for create_branch:
371 * "b" == create_branch(addr, target, 0);
372 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
373 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
374 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
376 #define BRANCH_SET_LINK 0x1
377 #define BRANCH_ABSOLUTE 0x2
379 static inline void create_branch(unsigned long addr
,
380 unsigned long target
, int flags
)
382 unsigned int instruction
;
384 if (! (flags
& BRANCH_ABSOLUTE
))
385 target
= target
- addr
;
387 /* Mask out the flags and target, so they don't step on each other. */
388 instruction
= 0x48000000 | (flags
& 0x3) | (target
& 0x03FFFFFC);
390 create_instruction(addr
, instruction
);
393 static inline void create_function_call(unsigned long addr
, void * func
)
395 unsigned long func_addr
;
399 * On PPC64 the function pointer actually points to the function's
400 * descriptor. The first entry in the descriptor is the address
401 * of the function text.
403 func_addr
= *(unsigned long *)func
;
405 func_addr
= (unsigned long)func
;
407 create_branch(addr
, func_addr
, BRANCH_SET_LINK
);
410 #endif /* __KERNEL__ */
411 #endif /* _ASM_POWERPC_SYSTEM_H */