arch/x86/pci/amd_bus.c

   1 #include <linux/init.h>
   2 #include <linux/pci.h>
   3 #include <linux/topology.h>
   4 #include <linux/cpu.h>
   5 #include <asm/pci_x86.h>
   6
   7 #ifdef CONFIG_X86_64
   8 #include <asm/pci-direct.h>
   9 #include <asm/mpspec.h>
  10 #include <linux/cpumask.h>
  11 #endif
  12
  13 /*
  14  * This discovers the pcibus <-> node mapping on AMD K8.
  15  * also get peer root bus resource for io,mmio
  16  */
  17
  18 #ifdef CONFIG_NUMA
  19
  20 #define BUS_NR 256
  21
  22 #ifdef CONFIG_X86_64
  23
  24 static int mp_bus_to_node[BUS_NR];
  25
  26 void set_mp_bus_to_node(int busnum, int node)
  27 {
  28         if (busnum >= 0 &&  busnum < BUS_NR)
  29                 mp_bus_to_node[busnum] = node;
  30 }
  31
  32 int get_mp_bus_to_node(int busnum)
  33 {
  34         int node = -1;
  35
  36         if (busnum < 0 || busnum > (BUS_NR - 1))
  37                 return node;
  38
  39         node = mp_bus_to_node[busnum];
  40
  41         /*
  42          * let numa_node_id to decide it later in dma_alloc_pages
  43          * if there is no ram on that node
  44          */
  45         if (node != -1 && !node_online(node))
  46                 node = -1;
  47
  48         return node;
  49 }
  50
  51 #else /* CONFIG_X86_32 */
  52
  53 static unsigned char mp_bus_to_node[BUS_NR];
  54
  55 void set_mp_bus_to_node(int busnum, int node)
  56 {
  57         if (busnum >= 0 &&  busnum < BUS_NR)
  58         mp_bus_to_node[busnum] = (unsigned char) node;
  59 }
  60
  61 int get_mp_bus_to_node(int busnum)
  62 {
  63         int node;
  64
  65         if (busnum < 0 || busnum > (BUS_NR - 1))
  66                 return 0;
  67         node = mp_bus_to_node[busnum];
  68         return node;
  69 }
  70
  71 #endif /* CONFIG_X86_32 */
  72
  73 #endif /* CONFIG_NUMA */
  74
  75 #ifdef CONFIG_X86_64
  76
  77 /*
  78  * sub bus (transparent) will use entres from 3 to store extra from root,
  79  * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
  80  */
  81 #define RES_NUM 16
  82 struct pci_root_info {
  83         char name[12];
  84         unsigned int res_num;
  85         struct resource res[RES_NUM];
  86         int bus_min;
  87         int bus_max;
  88         int node;
  89         int link;
  90 };
  91
  92 /* 4 at this time, it may become to 32 */
  93 #define PCI_ROOT_NR 4
  94 static int pci_root_num;
  95 static struct pci_root_info pci_root_info[PCI_ROOT_NR];
  96
  97 void x86_pci_root_bus_res_quirks(struct pci_bus *b)
  98 {
  99         int i;
 100         int j;
 101         struct pci_root_info *info;
 102
 103         /* don't go for it if _CRS is used already */
 104         if (b->resource[0] != &ioport_resource ||
 105             b->resource[1] != &iomem_resource)
 106                 return;
 107
 108         /* if only one root bus, don't need to anything */
 109         if (pci_root_num < 2)
 110                 return;
 111
 112         for (i = 0; i < pci_root_num; i++) {
 113                 if (pci_root_info[i].bus_min == b->number)
 114                         break;
 115         }
 116
 117         if (i == pci_root_num)
 118                 return;
 119
 120         printk(KERN_DEBUG "PCI: peer root bus %02x res updated from pci conf\n",
 121                         b->number);
 122
 123         info = &pci_root_info[i];
 124         for (j = 0; j < info->res_num; j++) {
 125                 struct resource *res;
 126                 struct resource *root;
 127
 128                 res = &info->res[j];
 129                 b->resource[j] = res;
 130                 if (res->flags & IORESOURCE_IO)
 131                         root = &ioport_resource;
 132                 else
 133                         root = &iomem_resource;
 134                 insert_resource(root, res);
 135         }
 136 }
 137
 138 #define RANGE_NUM 16
 139
 140 struct res_range {
 141         size_t start;
 142         size_t end;
 143 };
 144
 145 static void __init update_range(struct res_range *range, size_t start,
 146                                 size_t end)
 147 {
 148         int i;
 149         int j;
 150
 151         for (j = 0; j < RANGE_NUM; j++) {
 152                 if (!range[j].end)
 153                         continue;
 154
 155                 if (start <= range[j].start && end >= range[j].end) {
 156                         range[j].start = 0;
 157                         range[j].end = 0;
 158                         continue;
 159                 }
 160
 161                 if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) {
 162                         range[j].start = end + 1;
 163                         continue;
 164                 }
 165
 166
 167                 if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) {
 168                         range[j].end = start - 1;
 169                         continue;
 170                 }
 171
 172                 if (start > range[j].start && end < range[j].end) {
 173                         /* find the new spare */
 174                         for (i = 0; i < RANGE_NUM; i++) {
 175                                 if (range[i].end == 0)
 176                                         break;
 177                         }
 178                         if (i < RANGE_NUM) {
 179                                 range[i].end = range[j].end;
 180                                 range[i].start = end + 1;
 181                         } else {
 182                                 printk(KERN_ERR "run of slot in ranges\n");
 183                         }
 184                         range[j].end = start - 1;
 185                         continue;
 186                 }
 187         }
 188 }
 189
 190 static void __init update_res(struct pci_root_info *info, size_t start,
 191                               size_t end, unsigned long flags, int merge)
 192 {
 193         int i;
 194         struct resource *res;
 195
 196         if (!merge)
 197                 goto addit;
 198
 199         /* try to merge it with old one */
 200         for (i = 0; i < info->res_num; i++) {
 201                 size_t final_start, final_end;
 202                 size_t common_start, common_end;
 203
 204                 res = &info->res[i];
 205                 if (res->flags != flags)
 206                         continue;
 207
 208                 common_start = max((size_t)res->start, start);
 209                 common_end = min((size_t)res->end, end);
 210                 if (common_start > common_end + 1)
 211                         continue;
 212
 213                 final_start = min((size_t)res->start, start);
 214                 final_end = max((size_t)res->end, end);
 215
 216                 res->start = final_start;
 217                 res->end = final_end;
 218                 return;
 219         }
 220
 221 addit:
 222
 223         /* need to add that */
 224         if (info->res_num >= RES_NUM)
 225                 return;
 226
 227         res = &info->res[info->res_num];
 228         res->name = info->name;
 229         res->flags = flags;
 230         res->start = start;
 231         res->end = end;
 232         res->child = NULL;
 233         info->res_num++;
 234 }
 235
 236 struct pci_hostbridge_probe {
 237         u32 bus;
 238         u32 slot;
 239         u32 vendor;
 240         u32 device;
 241 };
 242
 243 static struct pci_hostbridge_probe pci_probes[] __initdata = {
 244         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
 245         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
 246         { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
 247         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
 248 };
 249
 250 static u64 __initdata fam10h_mmconf_start;
 251 static u64 __initdata fam10h_mmconf_end;
 252 static void __init get_pci_mmcfg_amd_fam10h_range(void)
 253 {
 254         u32 address;
 255         u64 base, msr;
 256         unsigned segn_busn_bits;
 257
 258         /* assume all cpus from fam10h have mmconf */
 259         if (boot_cpu_data.x86 < 0x10)
 260                 return;
 261
 262         address = MSR_FAM10H_MMIO_CONF_BASE;
 263         rdmsrl(address, msr);
 264
 265         /* mmconfig is not enable */
 266         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 267                 return;
 268
 269         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 270
 271         segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 272                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 273
 274         fam10h_mmconf_start = base;
 275         fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
 276 }
 277
 278 /**
 279  * early_fill_mp_bus_to_node()
 280  * called before pcibios_scan_root and pci_scan_bus
 281  * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 282  * Registers found in the K8 northbridge
 283  */
 284 static int __init early_fill_mp_bus_info(void)
 285 {
 286         int i;
 287         int j;
 288         unsigned bus;
 289         unsigned slot;
 290         int found;
 291         int node;
 292         int link;
 293         int def_node;
 294         int def_link;
 295         struct pci_root_info *info;
 296         u32 reg;
 297         struct resource *res;
 298         size_t start;
 299         size_t end;
 300         struct res_range range[RANGE_NUM];
 301         u64 val;
 302         u32 address;
 303
 304 #ifdef CONFIG_NUMA
 305         for (i = 0; i < BUS_NR; i++)
 306                 mp_bus_to_node[i] = -1;
 307 #endif
 308
 309         if (!early_pci_allowed())
 310                 return -1;
 311
 312         found = 0;
 313         for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
 314                 u32 id;
 315                 u16 device;
 316                 u16 vendor;
 317
 318                 bus = pci_probes[i].bus;
 319                 slot = pci_probes[i].slot;
 320                 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
 321
 322                 vendor = id & 0xffff;
 323                 device = (id>>16) & 0xffff;
 324                 if (pci_probes[i].vendor == vendor &&
 325                     pci_probes[i].device == device) {
 326                         found = 1;
 327                         break;
 328                 }
 329         }
 330
 331         if (!found)
 332                 return 0;
 333
 334         pci_root_num = 0;
 335         for (i = 0; i < 4; i++) {
 336                 int min_bus;
 337                 int max_bus;
 338                 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
 339
 340                 /* Check if that register is enabled for bus range */
 341                 if ((reg & 7) != 3)
 342                         continue;
 343
 344                 min_bus = (reg >> 16) & 0xff;
 345                 max_bus = (reg >> 24) & 0xff;
 346                 node = (reg >> 4) & 0x07;
 347 #ifdef CONFIG_NUMA
 348                 for (j = min_bus; j <= max_bus; j++)
 349                         mp_bus_to_node[j] = (unsigned char) node;
 350 #endif
 351                 link = (reg >> 8) & 0x03;
 352
 353                 info = &pci_root_info[pci_root_num];
 354                 info->bus_min = min_bus;
 355                 info->bus_max = max_bus;
 356                 info->node = node;
 357                 info->link = link;
 358                 sprintf(info->name, "PCI Bus #%02x", min_bus);
 359                 pci_root_num++;
 360         }
 361
 362         /* get the default node and link for left over res */
 363         reg = read_pci_config(bus, slot, 0, 0x60);
 364         def_node = (reg >> 8) & 0x07;
 365         reg = read_pci_config(bus, slot, 0, 0x64);
 366         def_link = (reg >> 8) & 0x03;
 367
 368         memset(range, 0, sizeof(range));
 369         range[0].end = 0xffff;
 370         /* io port resource */
 371         for (i = 0; i < 4; i++) {
 372                 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
 373                 if (!(reg & 3))
 374                         continue;
 375
 376                 start = reg & 0xfff000;
 377                 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
 378                 node = reg & 0x07;
 379                 link = (reg >> 4) & 0x03;
 380                 end = (reg & 0xfff000) | 0xfff;
 381
 382                 /* find the position */
 383                 for (j = 0; j < pci_root_num; j++) {
 384                         info = &pci_root_info[j];
 385                         if (info->node == node && info->link == link)
 386                                 break;
 387                 }
 388                 if (j == pci_root_num)
 389                         continue; /* not found */
 390
 391                 info = &pci_root_info[j];
 392                 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
 393                        node, link, (u64)start, (u64)end);
 394
 395                 /* kernel only handle 16 bit only */
 396                 if (end > 0xffff)
 397                         end = 0xffff;
 398                 update_res(info, start, end, IORESOURCE_IO, 1);
 399                 update_range(range, start, end);
 400         }
 401         /* add left over io port range to def node/link, [0, 0xffff] */
 402         /* find the position */
 403         for (j = 0; j < pci_root_num; j++) {
 404                 info = &pci_root_info[j];
 405                 if (info->node == def_node && info->link == def_link)
 406                         break;
 407         }
 408         if (j < pci_root_num) {
 409                 info = &pci_root_info[j];
 410                 for (i = 0; i < RANGE_NUM; i++) {
 411                         if (!range[i].end)
 412                                 continue;
 413
 414                         update_res(info, range[i].start, range[i].end,
 415                                    IORESOURCE_IO, 1);
 416                 }
 417         }
 418
 419         memset(range, 0, sizeof(range));
 420         /* 0xfd00000000-0xffffffffff for HT */
 421         range[0].end = (0xfdULL<<32) - 1;
 422
 423         /* need to take out [0, TOM) for RAM*/
 424         address = MSR_K8_TOP_MEM1;
 425         rdmsrl(address, val);
 426         end = (val & 0xffffff800000ULL);
 427         printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
 428         if (end < (1ULL<<32))
 429                 update_range(range, 0, end - 1);
 430
 431         /* get mmconfig */
 432         get_pci_mmcfg_amd_fam10h_range();
 433         /* need to take out mmconf range */
 434         if (fam10h_mmconf_end) {
 435                 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
 436                 update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
 437         }
 438
 439         /* mmio resource */
 440         for (i = 0; i < 8; i++) {
 441                 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
 442                 if (!(reg & 3))
 443                         continue;
 444
 445                 start = reg & 0xffffff00; /* 39:16 on 31:8*/
 446                 start <<= 8;
 447                 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
 448                 node = reg & 0x07;
 449                 link = (reg >> 4) & 0x03;
 450                 end = (reg & 0xffffff00);
 451                 end <<= 8;
 452                 end |= 0xffff;
 453
 454                 /* find the position */
 455                 for (j = 0; j < pci_root_num; j++) {
 456                         info = &pci_root_info[j];
 457                         if (info->node == node && info->link == link)
 458                                 break;
 459                 }
 460                 if (j == pci_root_num)
 461                         continue; /* not found */
 462
 463                 info = &pci_root_info[j];
 464
 465                 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
 466                        node, link, (u64)start, (u64)end);
 467                 /*
 468                  * some sick allocation would have range overlap with fam10h
 469                  * mmconf range, so need to update start and end.
 470                  */
 471                 if (fam10h_mmconf_end) {
 472                         int changed = 0;
 473                         u64 endx = 0;
 474                         if (start >= fam10h_mmconf_start &&
 475                             start <= fam10h_mmconf_end) {
 476                                 start = fam10h_mmconf_end + 1;
 477                                 changed = 1;
 478                         }
 479
 480                         if (end >= fam10h_mmconf_start &&
 481                             end <= fam10h_mmconf_end) {
 482                                 end = fam10h_mmconf_start - 1;
 483                                 changed = 1;
 484                         }
 485
 486                         if (start < fam10h_mmconf_start &&
 487                             end > fam10h_mmconf_end) {
 488                                 /* we got a hole */
 489                                 endx = fam10h_mmconf_start - 1;
 490                                 update_res(info, start, endx, IORESOURCE_MEM, 0);
 491                                 update_range(range, start, endx);
 492                                 printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
 493                                 start = fam10h_mmconf_end + 1;
 494                                 changed = 1;
 495                         }
 496                         if (changed) {
 497                                 if (start <= end) {
 498                                         printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
 499                                 } else {
 500                                         printk(KERN_CONT "%s\n", endx?"":" ==> none");
 501                                         continue;
 502                                 }
 503                         }
 504                 }
 505
 506                 update_res(info, start, end, IORESOURCE_MEM, 1);
 507                 update_range(range, start, end);
 508                 printk(KERN_CONT "\n");
 509         }
 510
 511         /* need to take out [4G, TOM2) for RAM*/
 512         /* SYS_CFG */
 513         address = MSR_K8_SYSCFG;
 514         rdmsrl(address, val);
 515         /* TOP_MEM2 is enabled? */
 516         if (val & (1<<21)) {
 517                 /* TOP_MEM2 */
 518                 address = MSR_K8_TOP_MEM2;
 519                 rdmsrl(address, val);
 520                 end = (val & 0xffffff800000ULL);
 521                 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
 522                 update_range(range, 1ULL<<32, end - 1);
 523         }
 524
 525         /*
 526          * add left over mmio range to def node/link ?
 527          * that is tricky, just record range in from start_min to 4G
 528          */
 529         for (j = 0; j < pci_root_num; j++) {
 530                 info = &pci_root_info[j];
 531                 if (info->node == def_node && info->link == def_link)
 532                         break;
 533         }
 534         if (j < pci_root_num) {
 535                 info = &pci_root_info[j];
 536
 537                 for (i = 0; i < RANGE_NUM; i++) {
 538                         if (!range[i].end)
 539                                 continue;
 540
 541                         update_res(info, range[i].start, range[i].end,
 542                                    IORESOURCE_MEM, 1);
 543                 }
 544         }
 545
 546         for (i = 0; i < pci_root_num; i++) {
 547                 int res_num;
 548                 int busnum;
 549
 550                 info = &pci_root_info[i];
 551                 res_num = info->res_num;
 552                 busnum = info->bus_min;
 553                 printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
 554                        info->bus_min, info->bus_max, info->node, info->link);
 555                 for (j = 0; j < res_num; j++) {
 556                         res = &info->res[j];
 557                         printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
 558                                busnum, j,
 559                                (res->flags & IORESOURCE_IO)?"io port":"mmio",
 560                                res->start, res->end);
 561                 }
 562         }
 563
 564         return 0;
 565 }
 566
 567 #else  /* !CONFIG_X86_64 */
 568
 569 static int __init early_fill_mp_bus_info(void) { return 0; }
 570
 571 #endif /* !CONFIG_X86_64 */
 572
 573 /* common 32/64 bit code */
 574
 575 #define ENABLE_CF8_EXT_CFG      (1ULL << 46)
 576
 577 static void enable_pci_io_ecs(void *unused)
 578 {
 579         u64 reg;
 580         rdmsrl(MSR_AMD64_NB_CFG, reg);
 581         if (!(reg & ENABLE_CF8_EXT_CFG)) {
 582                 reg |= ENABLE_CF8_EXT_CFG;
 583                 wrmsrl(MSR_AMD64_NB_CFG, reg);
 584         }
 585 }
 586
 587 static int __cpuinit amd_cpu_notify(struct notifier_block *self,
 588                                     unsigned long action, void *hcpu)
 589 {
 590         int cpu = (long)hcpu;
 591         switch (action) {
 592         case CPU_ONLINE:
 593         case CPU_ONLINE_FROZEN:
 594                 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
 595                 break;
 596         default:
 597                 break;
 598         }
 599         return NOTIFY_OK;
 600 }
 601
 602 static struct notifier_block __cpuinitdata amd_cpu_notifier = {
 603         .notifier_call  = amd_cpu_notify,
 604 };
 605
 606 static int __init pci_io_ecs_init(void)
 607 {
 608         int cpu;
 609
 610         /* assume all cpus from fam10h have IO ECS */
 611         if (boot_cpu_data.x86 < 0x10)
 612                 return 0;
 613
 614         register_cpu_notifier(&amd_cpu_notifier);
 615         for_each_online_cpu(cpu)
 616                 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
 617                                (void *)(long)cpu);
 618         pci_probe |= PCI_HAS_IO_ECS;
 619
 620         return 0;
 621 }
 622
 623 static int __init amd_postcore_init(void)
 624 {
 625         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
 626                 return 0;
 627
 628         early_fill_mp_bus_info();
 629         pci_io_ecs_init();
 630
 631         return 0;
 632 }
 633
 634 postcore_initcall(amd_postcore_init);