x86: move quad_local_to_mp_bus_id to numa.c
[wandboard.git] / include / asm-x86 / mpspec.h
blobdbd63f8d4750e2ec35cb4ae2aa1341daba77e193
1 #ifndef _AM_X86_MPSPEC_H
2 #define _AM_X86_MPSPEC_H
4 #include <asm/mpspec_def.h>
6 #ifdef CONFIG_X86_32
7 #include <mach_mpspec.h>
9 extern int mp_bus_id_to_type[MAX_MP_BUSSES];
10 extern int mp_bus_id_to_node[MAX_MP_BUSSES];
11 extern int mp_bus_id_to_local[MAX_MP_BUSSES];
13 extern unsigned int def_to_bigsmp;
14 extern int apic_version[MAX_APICS];
15 extern u8 apicid_2_node[];
16 extern int pic_mode;
18 #define MAX_APICID 256
20 #else
22 #define MAX_MP_BUSSES 256
23 /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
24 #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
26 extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
28 #endif
30 extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
32 extern unsigned int boot_cpu_physical_apicid;
33 extern int smp_found_config;
34 extern int nr_ioapics;
35 extern int mp_irq_entries;
36 extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
37 extern int mpc_default_type;
38 extern unsigned long mp_lapic_addr;
40 extern void find_smp_config(void);
41 extern void get_smp_config(void);
43 #ifdef CONFIG_ACPI
44 extern void mp_register_lapic(u8 id, u8 enabled);
45 extern void mp_register_lapic_address(u64 address);
46 extern void mp_register_ioapic(u8 id, u32 address, u32 gsi_base);
47 extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
48 u32 gsi);
49 extern void mp_config_acpi_legacy_irqs(void);
50 extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
51 #endif /* CONFIG_ACPI */
53 #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
55 struct physid_mask
57 unsigned long mask[PHYSID_ARRAY_SIZE];
60 typedef struct physid_mask physid_mask_t;
62 #define physid_set(physid, map) set_bit(physid, (map).mask)
63 #define physid_clear(physid, map) clear_bit(physid, (map).mask)
64 #define physid_isset(physid, map) test_bit(physid, (map).mask)
65 #define physid_test_and_set(physid, map) \
66 test_and_set_bit(physid, (map).mask)
68 #define physids_and(dst, src1, src2) \
69 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
71 #define physids_or(dst, src1, src2) \
72 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
74 #define physids_clear(map) \
75 bitmap_zero((map).mask, MAX_APICS)
77 #define physids_complement(dst, src) \
78 bitmap_complement((dst).mask, (src).mask, MAX_APICS)
80 #define physids_empty(map) \
81 bitmap_empty((map).mask, MAX_APICS)
83 #define physids_equal(map1, map2) \
84 bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
86 #define physids_weight(map) \
87 bitmap_weight((map).mask, MAX_APICS)
89 #define physids_shift_right(d, s, n) \
90 bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
92 #define physids_shift_left(d, s, n) \
93 bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
95 #define physids_coerce(map) ((map).mask[0])
97 #define physids_promote(physids) \
98 ({ \
99 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
100 __physid_mask.mask[0] = physids; \
101 __physid_mask; \
104 #define physid_mask_of_physid(physid) \
105 ({ \
106 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
107 physid_set(physid, __physid_mask); \
108 __physid_mask; \
111 #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
112 #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
114 extern physid_mask_t phys_cpu_present_map;
116 #endif