?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
V4L/DVB: media/IR/imon: testing the wrong variable
[wandboard.git] / drivers / gpu / drm / radeon / radeon_clocks.c
blobf64936cc4dd9dfaffeee50d02ea529544b338abc
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include "drmP.h"
29 #include "radeon_drm.h"
30 #include "radeon_reg.h"
31 #include "radeon.h"
32 #include "atom.h"
33
34 /* 10 khz */
35 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
36 {
37 struct radeon_pll *spll = &rdev->clock.spll;
38 uint32_t fb_div, ref_div, post_div, sclk;
39
40 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
41 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
42 fb_div <<= 1;
43 fb_div *= spll->reference_freq;
44
45 ref_div =
46 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
47
48 if (ref_div == 0)
49 return 0;
50
51 sclk = fb_div / ref_div;
52
53 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
54 if (post_div == 2)
55 sclk >>= 1;
56 else if (post_div == 3)
57 sclk >>= 2;
58 else if (post_div == 4)
59 sclk >>= 3;
60
61 return sclk;
62 }
63
64 /* 10 khz */
65 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
66 {
67 struct radeon_pll *mpll = &rdev->clock.mpll;
68 uint32_t fb_div, ref_div, post_div, mclk;
69
70 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
71 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
72 fb_div <<= 1;
73 fb_div *= mpll->reference_freq;
74
75 ref_div =
76 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
77
78 if (ref_div == 0)
79 return 0;
80
81 mclk = fb_div / ref_div;
82
83 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
84 if (post_div == 2)
85 mclk >>= 1;
86 else if (post_div == 3)
87 mclk >>= 2;
88 else if (post_div == 4)
89 mclk >>= 3;
90
91 return mclk;
92 }
93
94 void radeon_get_clock_info(struct drm_device *dev)
95 {
96 struct radeon_device *rdev = dev->dev_private;
97 struct radeon_pll *p1pll = &rdev->clock.p1pll;
98 struct radeon_pll *p2pll = &rdev->clock.p2pll;
99 struct radeon_pll *dcpll = &rdev->clock.dcpll;
100 struct radeon_pll *spll = &rdev->clock.spll;
101 struct radeon_pll *mpll = &rdev->clock.mpll;
102 int ret;
103
104 if (rdev->is_atom_bios)
105 ret = radeon_atom_get_clock_info(dev);
106 else
107 ret = radeon_combios_get_clock_info(dev);
108
109 if (ret) {
110 if (p1pll->reference_div < 2) {
111 if (!ASIC_IS_AVIVO(rdev)) {
112 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
113 if (ASIC_IS_R300(rdev))
114 p1pll->reference_div =
115 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
116 else
117 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
118 if (p1pll->reference_div < 2)
119 p1pll->reference_div = 12;
120 } else
121 p1pll->reference_div = 12;
122 }
123 if (p2pll->reference_div < 2)
124 p2pll->reference_div = 12;
125 if (rdev->family < CHIP_RS600) {
126 if (spll->reference_div < 2)
127 spll->reference_div =
128 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
129 RADEON_M_SPLL_REF_DIV_MASK;
130 }
131 if (mpll->reference_div < 2)
132 mpll->reference_div = spll->reference_div;
133 } else {
134 if (ASIC_IS_AVIVO(rdev)) {
135 /* TODO FALLBACK */
136 } else {
137 DRM_INFO("Using generic clock info\n");
138
139 if (rdev->flags & RADEON_IS_IGP) {
140 p1pll->reference_freq = 1432;
141 p2pll->reference_freq = 1432;
142 spll->reference_freq = 1432;
143 mpll->reference_freq = 1432;
144 } else {
145 p1pll->reference_freq = 2700;
146 p2pll->reference_freq = 2700;
147 spll->reference_freq = 2700;
148 mpll->reference_freq = 2700;
149 }
150 p1pll->reference_div =
151 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
152 if (p1pll->reference_div < 2)
153 p1pll->reference_div = 12;
154 p2pll->reference_div = p1pll->reference_div;
155
156 if (rdev->family >= CHIP_R420) {
157 p1pll->pll_in_min = 100;
158 p1pll->pll_in_max = 1350;
159 p1pll->pll_out_min = 20000;
160 p1pll->pll_out_max = 50000;
161 p2pll->pll_in_min = 100;
162 p2pll->pll_in_max = 1350;
163 p2pll->pll_out_min = 20000;
164 p2pll->pll_out_max = 50000;
165 } else {
166 p1pll->pll_in_min = 40;
167 p1pll->pll_in_max = 500;
168 p1pll->pll_out_min = 12500;
169 p1pll->pll_out_max = 35000;
170 p2pll->pll_in_min = 40;
171 p2pll->pll_in_max = 500;
172 p2pll->pll_out_min = 12500;
173 p2pll->pll_out_max = 35000;
174 }
175
176 spll->reference_div =
177 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
178 RADEON_M_SPLL_REF_DIV_MASK;
179 mpll->reference_div = spll->reference_div;
180 rdev->clock.default_sclk =
181 radeon_legacy_get_engine_clock(rdev);
182 rdev->clock.default_mclk =
183 radeon_legacy_get_memory_clock(rdev);
184 }
185 }
186
187 /* pixel clocks */
188 if (ASIC_IS_AVIVO(rdev)) {
189 p1pll->min_post_div = 2;
190 p1pll->max_post_div = 0x7f;
191 p1pll->min_frac_feedback_div = 0;
192 p1pll->max_frac_feedback_div = 9;
193 p2pll->min_post_div = 2;
194 p2pll->max_post_div = 0x7f;
195 p2pll->min_frac_feedback_div = 0;
196 p2pll->max_frac_feedback_div = 9;
197 } else {
198 p1pll->min_post_div = 1;
199 p1pll->max_post_div = 16;
200 p1pll->min_frac_feedback_div = 0;
201 p1pll->max_frac_feedback_div = 0;
202 p2pll->min_post_div = 1;
203 p2pll->max_post_div = 12;
204 p2pll->min_frac_feedback_div = 0;
205 p2pll->max_frac_feedback_div = 0;
206 }
207
208 /* dcpll is DCE4 only */
209 dcpll->min_post_div = 2;
210 dcpll->max_post_div = 0x7f;
211 dcpll->min_frac_feedback_div = 0;
212 dcpll->max_frac_feedback_div = 9;
213 dcpll->min_ref_div = 2;
214 dcpll->max_ref_div = 0x3ff;
215 dcpll->min_feedback_div = 4;
216 dcpll->max_feedback_div = 0xfff;
217 dcpll->best_vco = 0;
218
219 p1pll->min_ref_div = 2;
220 p1pll->max_ref_div = 0x3ff;
221 p1pll->min_feedback_div = 4;
222 p1pll->max_feedback_div = 0x7ff;
223 p1pll->best_vco = 0;
224
225 p2pll->min_ref_div = 2;
226 p2pll->max_ref_div = 0x3ff;
227 p2pll->min_feedback_div = 4;
228 p2pll->max_feedback_div = 0x7ff;
229 p2pll->best_vco = 0;
230
231 /* system clock */
232 spll->min_post_div = 1;
233 spll->max_post_div = 1;
234 spll->min_ref_div = 2;
235 spll->max_ref_div = 0xff;
236 spll->min_feedback_div = 4;
237 spll->max_feedback_div = 0xff;
238 spll->best_vco = 0;
239
240 /* memory clock */
241 mpll->min_post_div = 1;
242 mpll->max_post_div = 1;
243 mpll->min_ref_div = 2;
244 mpll->max_ref_div = 0xff;
245 mpll->min_feedback_div = 4;
246 mpll->max_feedback_div = 0xff;
247 mpll->best_vco = 0;
248
249 }
250
251 /* 10 khz */
252 static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
253 uint32_t req_clock,
254 int *fb_div, int *post_div)
255 {
256 struct radeon_pll *spll = &rdev->clock.spll;
257 int ref_div = spll->reference_div;
258
259 if (!ref_div)
260 ref_div =
261 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
262 RADEON_M_SPLL_REF_DIV_MASK;
263
264 if (req_clock < 15000) {
265 *post_div = 8;
266 req_clock *= 8;
267 } else if (req_clock < 30000) {
268 *post_div = 4;
269 req_clock *= 4;
270 } else if (req_clock < 60000) {
271 *post_div = 2;
272 req_clock *= 2;
273 } else
274 *post_div = 1;
275
276 req_clock *= ref_div;
277 req_clock += spll->reference_freq;
278 req_clock /= (2 * spll->reference_freq);
279
280 *fb_div = req_clock & 0xff;
281
282 req_clock = (req_clock & 0xffff) << 1;
283 req_clock *= spll->reference_freq;
284 req_clock /= ref_div;
285 req_clock /= *post_div;
286
287 return req_clock;
288 }
289
290 /* 10 khz */
291 void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
292 uint32_t eng_clock)
293 {
294 uint32_t tmp;
295 int fb_div, post_div;
296
297 /* XXX: wait for idle */
298
299 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
300
301 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
302 tmp &= ~RADEON_DONT_USE_XTALIN;
303 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
304
305 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
306 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
307 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
308
309 udelay(10);
310
311 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
312 tmp |= RADEON_SPLL_SLEEP;
313 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
314
315 udelay(2);
316
317 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
318 tmp |= RADEON_SPLL_RESET;
319 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
320
321 udelay(200);
322
323 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
324 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
325 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
326 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
327
328 /* XXX: verify on different asics */
329 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
330 tmp &= ~RADEON_SPLL_PVG_MASK;
331 if ((eng_clock * post_div) >= 90000)
332 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
333 else
334 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
335 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
336
337 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
338 tmp &= ~RADEON_SPLL_SLEEP;
339 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
340
341 udelay(2);
342
343 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
344 tmp &= ~RADEON_SPLL_RESET;
345 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
346
347 udelay(200);
348
349 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
350 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
351 switch (post_div) {
352 case 1:
353 default:
354 tmp |= 1;
355 break;
356 case 2:
357 tmp |= 2;
358 break;
359 case 4:
360 tmp |= 3;
361 break;
362 case 8:
363 tmp |= 4;
364 break;
365 }
366 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
367
368 udelay(20);
369
370 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
371 tmp |= RADEON_DONT_USE_XTALIN;
372 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
373
374 udelay(10);
375 }
376
377 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
378 {
379 uint32_t tmp;
380
381 if (enable) {
382 if (rdev->flags & RADEON_SINGLE_CRTC) {
383 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
384 if ((RREG32(RADEON_CONFIG_CNTL) &
385 RADEON_CFG_ATI_REV_ID_MASK) >
386 RADEON_CFG_ATI_REV_A13) {
387 tmp &=
388 ~(RADEON_SCLK_FORCE_CP |
389 RADEON_SCLK_FORCE_RB);
390 }
391 tmp &=
392 ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
393 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
394 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
395 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
396 RADEON_SCLK_FORCE_TDM);
397 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
398 } else if (ASIC_IS_R300(rdev)) {
399 if ((rdev->family == CHIP_RS400) ||
400 (rdev->family == CHIP_RS480)) {
401 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
402 tmp &=
403 ~(RADEON_SCLK_FORCE_DISP2 |
404 RADEON_SCLK_FORCE_CP |
405 RADEON_SCLK_FORCE_HDP |
406 RADEON_SCLK_FORCE_DISP1 |
407 RADEON_SCLK_FORCE_TOP |
408 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
409 | RADEON_SCLK_FORCE_IDCT |
410 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
411 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
412 | R300_SCLK_FORCE_US |
413 RADEON_SCLK_FORCE_TV_SCLK |
414 R300_SCLK_FORCE_SU |
415 RADEON_SCLK_FORCE_OV0);
416 tmp |= RADEON_DYN_STOP_LAT_MASK;
417 tmp |=
418 RADEON_SCLK_FORCE_TOP |
419 RADEON_SCLK_FORCE_VIP;
420 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
421
422 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
423 tmp &= ~RADEON_SCLK_MORE_FORCEON;
424 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
425 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
426
427 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
428 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
429 RADEON_PIXCLK_DAC_ALWAYS_ONb);
430 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
431
432 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
433 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
434 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
435 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
436 R300_DVOCLK_ALWAYS_ONb |
437 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
438 RADEON_PIXCLK_GV_ALWAYS_ONb |
439 R300_PIXCLK_DVO_ALWAYS_ONb |
440 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
441 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
442 R300_PIXCLK_TRANS_ALWAYS_ONb |
443 R300_PIXCLK_TVO_ALWAYS_ONb |
444 R300_P2G2CLK_ALWAYS_ONb |
445 R300_P2G2CLK_DAC_ALWAYS_ONb);
446 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
447 } else if (rdev->family >= CHIP_RV350) {
448 tmp = RREG32_PLL(R300_SCLK_CNTL2);
449 tmp &= ~(R300_SCLK_FORCE_TCL |
450 R300_SCLK_FORCE_GA |
451 R300_SCLK_FORCE_CBA);
452 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
453 R300_SCLK_GA_MAX_DYN_STOP_LAT |
454 R300_SCLK_CBA_MAX_DYN_STOP_LAT);
455 WREG32_PLL(R300_SCLK_CNTL2, tmp);
456
457 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
458 tmp &=
459 ~(RADEON_SCLK_FORCE_DISP2 |
460 RADEON_SCLK_FORCE_CP |
461 RADEON_SCLK_FORCE_HDP |
462 RADEON_SCLK_FORCE_DISP1 |
463 RADEON_SCLK_FORCE_TOP |
464 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
465 | RADEON_SCLK_FORCE_IDCT |
466 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
467 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
468 | R300_SCLK_FORCE_US |
469 RADEON_SCLK_FORCE_TV_SCLK |
470 R300_SCLK_FORCE_SU |
471 RADEON_SCLK_FORCE_OV0);
472 tmp |= RADEON_DYN_STOP_LAT_MASK;
473 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
474
475 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
476 tmp &= ~RADEON_SCLK_MORE_FORCEON;
477 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
478 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
479
480 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
481 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
482 RADEON_PIXCLK_DAC_ALWAYS_ONb);
483 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
484
485 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
486 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
487 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
488 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
489 R300_DVOCLK_ALWAYS_ONb |
490 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
491 RADEON_PIXCLK_GV_ALWAYS_ONb |
492 R300_PIXCLK_DVO_ALWAYS_ONb |
493 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
494 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
495 R300_PIXCLK_TRANS_ALWAYS_ONb |
496 R300_PIXCLK_TVO_ALWAYS_ONb |
497 R300_P2G2CLK_ALWAYS_ONb |
498 R300_P2G2CLK_DAC_ALWAYS_ONb);
499 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
500
501 tmp = RREG32_PLL(RADEON_MCLK_MISC);
502 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
503 RADEON_IO_MCLK_DYN_ENABLE);
504 WREG32_PLL(RADEON_MCLK_MISC, tmp);
505
506 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
507 tmp |= (RADEON_FORCEON_MCLKA |
508 RADEON_FORCEON_MCLKB);
509
510 tmp &= ~(RADEON_FORCEON_YCLKA |
511 RADEON_FORCEON_YCLKB |
512 RADEON_FORCEON_MC);
513
514 /* Some releases of vbios have set DISABLE_MC_MCLKA
515 and DISABLE_MC_MCLKB bits in the vbios table. Setting these
516 bits will cause H/W hang when reading video memory with dynamic clocking
517 enabled. */
518 if ((tmp & R300_DISABLE_MC_MCLKA) &&
519 (tmp & R300_DISABLE_MC_MCLKB)) {
520 /* If both bits are set, then check the active channels */
521 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
522 if (rdev->mc.vram_width == 64) {
523 if (RREG32(RADEON_MEM_CNTL) &
524 R300_MEM_USE_CD_CH_ONLY)
525 tmp &=
526 ~R300_DISABLE_MC_MCLKB;
527 else
528 tmp &=
529 ~R300_DISABLE_MC_MCLKA;
530 } else {
531 tmp &= ~(R300_DISABLE_MC_MCLKA |
532 R300_DISABLE_MC_MCLKB);
533 }
534 }
535
536 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
537 } else {
538 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
539 tmp &= ~(R300_SCLK_FORCE_VAP);
540 tmp |= RADEON_SCLK_FORCE_CP;
541 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
542 udelay(15000);
543
544 tmp = RREG32_PLL(R300_SCLK_CNTL2);
545 tmp &= ~(R300_SCLK_FORCE_TCL |
546 R300_SCLK_FORCE_GA |
547 R300_SCLK_FORCE_CBA);
548 WREG32_PLL(R300_SCLK_CNTL2, tmp);
549 }
550 } else {
551 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
552
553 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
554 RADEON_DISP_DYN_STOP_LAT_MASK |
555 RADEON_DYN_STOP_MODE_MASK);
556
557 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
558 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
559 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
560 udelay(15000);
561
562 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
563 tmp |= RADEON_SCLK_DYN_START_CNTL;
564 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
565 udelay(15000);
566
567 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
568 to lockup randomly, leave them as set by BIOS.
569 */
570 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
571 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
572 tmp &= ~RADEON_SCLK_FORCEON_MASK;
573
574 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
575 if (((rdev->family == CHIP_RV250) &&
576 ((RREG32(RADEON_CONFIG_CNTL) &
577 RADEON_CFG_ATI_REV_ID_MASK) <
578 RADEON_CFG_ATI_REV_A13))
579 || ((rdev->family == CHIP_RV100)
580 &&
581 ((RREG32(RADEON_CONFIG_CNTL) &
582 RADEON_CFG_ATI_REV_ID_MASK) <=
583 RADEON_CFG_ATI_REV_A13))) {
584 tmp |= RADEON_SCLK_FORCE_CP;
585 tmp |= RADEON_SCLK_FORCE_VIP;
586 }
587
588 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
589
590 if ((rdev->family == CHIP_RV200) ||
591 (rdev->family == CHIP_RV250) ||
592 (rdev->family == CHIP_RV280)) {
593 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
594 tmp &= ~RADEON_SCLK_MORE_FORCEON;
595
596 /* RV200::A11 A12 RV250::A11 A12 */
597 if (((rdev->family == CHIP_RV200) ||
598 (rdev->family == CHIP_RV250)) &&
599 ((RREG32(RADEON_CONFIG_CNTL) &
600 RADEON_CFG_ATI_REV_ID_MASK) <
601 RADEON_CFG_ATI_REV_A13)) {
602 tmp |= RADEON_SCLK_MORE_FORCEON;
603 }
604 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
605 udelay(15000);
606 }
607
608 /* RV200::A11 A12, RV250::A11 A12 */
609 if (((rdev->family == CHIP_RV200) ||
610 (rdev->family == CHIP_RV250)) &&
611 ((RREG32(RADEON_CONFIG_CNTL) &
612 RADEON_CFG_ATI_REV_ID_MASK) <
613 RADEON_CFG_ATI_REV_A13)) {
614 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
615 tmp |= RADEON_TCL_BYPASS_DISABLE;
616 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
617 }
618 udelay(15000);
619
620 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
621 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
622 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
623 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
624 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
625 RADEON_PIXCLK_GV_ALWAYS_ONb |
626 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
627 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
628 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
629
630 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
631 udelay(15000);
632
633 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
634 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
635 RADEON_PIXCLK_DAC_ALWAYS_ONb);
636
637 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
638 udelay(15000);
639 }
640 } else {
641 /* Turn everything OFF (ForceON to everything) */
642 if (rdev->flags & RADEON_SINGLE_CRTC) {
643 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
644 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
645 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
646 | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
647 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
648 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
649 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
650 RADEON_SCLK_FORCE_RB);
651 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
652 } else if ((rdev->family == CHIP_RS400) ||
653 (rdev->family == CHIP_RS480)) {
654 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
655 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
656 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
657 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
658 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
659 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
660 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
661 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
662 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
663 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
664
665 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
666 tmp |= RADEON_SCLK_MORE_FORCEON;
667 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
668
669 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
670 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
671 RADEON_PIXCLK_DAC_ALWAYS_ONb |
672 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
673 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
674
675 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
676 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
677 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
678 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
679 R300_DVOCLK_ALWAYS_ONb |
680 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
681 RADEON_PIXCLK_GV_ALWAYS_ONb |
682 R300_PIXCLK_DVO_ALWAYS_ONb |
683 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
684 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
685 R300_PIXCLK_TRANS_ALWAYS_ONb |
686 R300_PIXCLK_TVO_ALWAYS_ONb |
687 R300_P2G2CLK_ALWAYS_ONb |
688 R300_P2G2CLK_DAC_ALWAYS_ONb |
689 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
690 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
691 } else if (rdev->family >= CHIP_RV350) {
692 /* for RV350/M10, no delays are required. */
693 tmp = RREG32_PLL(R300_SCLK_CNTL2);
694 tmp |= (R300_SCLK_FORCE_TCL |
695 R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
696 WREG32_PLL(R300_SCLK_CNTL2, tmp);
697
698 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
699 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
700 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
701 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
702 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
703 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
704 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
705 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
706 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
707 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
708
709 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
710 tmp |= RADEON_SCLK_MORE_FORCEON;
711 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
712
713 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
714 tmp |= (RADEON_FORCEON_MCLKA |
715 RADEON_FORCEON_MCLKB |
716 RADEON_FORCEON_YCLKA |
717 RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
718 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
719
720 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
721 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
722 RADEON_PIXCLK_DAC_ALWAYS_ONb |
723 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
724 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
725
726 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
727 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
728 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
729 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
730 R300_DVOCLK_ALWAYS_ONb |
731 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
732 RADEON_PIXCLK_GV_ALWAYS_ONb |
733 R300_PIXCLK_DVO_ALWAYS_ONb |
734 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
735 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
736 R300_PIXCLK_TRANS_ALWAYS_ONb |
737 R300_PIXCLK_TVO_ALWAYS_ONb |
738 R300_P2G2CLK_ALWAYS_ONb |
739 R300_P2G2CLK_DAC_ALWAYS_ONb |
740 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
741 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
742 } else {
743 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
744 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
745 tmp |= RADEON_SCLK_FORCE_SE;
746
747 if (rdev->flags & RADEON_SINGLE_CRTC) {
748 tmp |= (RADEON_SCLK_FORCE_RB |
749 RADEON_SCLK_FORCE_TDM |
750 RADEON_SCLK_FORCE_TAM |
751 RADEON_SCLK_FORCE_PB |
752 RADEON_SCLK_FORCE_RE |
753 RADEON_SCLK_FORCE_VIP |
754 RADEON_SCLK_FORCE_IDCT |
755 RADEON_SCLK_FORCE_TOP |
756 RADEON_SCLK_FORCE_DISP1 |
757 RADEON_SCLK_FORCE_DISP2 |
758 RADEON_SCLK_FORCE_HDP);
759 } else if ((rdev->family == CHIP_R300) ||
760 (rdev->family == CHIP_R350)) {
761 tmp |= (RADEON_SCLK_FORCE_HDP |
762 RADEON_SCLK_FORCE_DISP1 |
763 RADEON_SCLK_FORCE_DISP2 |
764 RADEON_SCLK_FORCE_TOP |
765 RADEON_SCLK_FORCE_IDCT |
766 RADEON_SCLK_FORCE_VIP);
767 }
768 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
769
770 udelay(16000);
771
772 if ((rdev->family == CHIP_R300) ||
773 (rdev->family == CHIP_R350)) {
774 tmp = RREG32_PLL(R300_SCLK_CNTL2);
775 tmp |= (R300_SCLK_FORCE_TCL |
776 R300_SCLK_FORCE_GA |
777 R300_SCLK_FORCE_CBA);
778 WREG32_PLL(R300_SCLK_CNTL2, tmp);
779 udelay(16000);
780 }
781
782 if (rdev->flags & RADEON_IS_IGP) {
783 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
784 tmp &= ~(RADEON_FORCEON_MCLKA |
785 RADEON_FORCEON_YCLKA);
786 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
787 udelay(16000);
788 }
789
790 if ((rdev->family == CHIP_RV200) ||
791 (rdev->family == CHIP_RV250) ||
792 (rdev->family == CHIP_RV280)) {
793 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
794 tmp |= RADEON_SCLK_MORE_FORCEON;
795 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
796 udelay(16000);
797 }
798
799 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
800 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
801 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
802 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
803 RADEON_PIXCLK_GV_ALWAYS_ONb |
804 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
805 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
806 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
807
808 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
809 udelay(16000);
810
811 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
812 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
813 RADEON_PIXCLK_DAC_ALWAYS_ONb);
814 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
815 }
816 }
817 }
818
819 static void radeon_apply_clock_quirks(struct radeon_device *rdev)
820 {
821 uint32_t tmp;
822
823 /* XXX make sure engine is idle */
824
825 if (rdev->family < CHIP_RS600) {
826 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
827 if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev))
828 tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
829 if ((rdev->family == CHIP_RV250)
830 || (rdev->family == CHIP_RV280))
831 tmp |=
832 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2;
833 if ((rdev->family == CHIP_RV350)
834 || (rdev->family == CHIP_RV380))
835 tmp |= R300_SCLK_FORCE_VAP;
836 if (rdev->family == CHIP_R420)
837 tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX;
838 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
839 } else if (rdev->family < CHIP_R600) {
840 tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL);
841 tmp |= AVIVO_CP_FORCEON;
842 WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp);
843
844 tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL);
845 tmp |= AVIVO_E2_FORCEON;
846 WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp);
847
848 tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL);
849 tmp |= AVIVO_IDCT_FORCEON;
850 WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp);
851 }
852 }
853
854 int radeon_static_clocks_init(struct drm_device *dev)
855 {
856 struct radeon_device *rdev = dev->dev_private;
857
858 /* XXX make sure engine is idle */
859
860 if (radeon_dynclks != -1) {
861 if (radeon_dynclks) {
862 if (rdev->asic->set_clock_gating)
863 radeon_set_clock_gating(rdev, 1);
864 }
865 }
866 radeon_apply_clock_quirks(rdev);
867 return 0;
868 }
WandBoard kernel