2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
31 struct nv50_fifo_priv
{
32 struct nouveau_gpuobj_ref
*thingo
[2];
36 #define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
39 nv50_fifo_init_thingo(struct drm_device
*dev
)
41 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
42 struct nv50_fifo_priv
*priv
= dev_priv
->engine
.fifo
.priv
;
43 struct nouveau_gpuobj_ref
*cur
;
48 cur
= priv
->thingo
[priv
->cur_thingo
];
49 priv
->cur_thingo
= !priv
->cur_thingo
;
51 /* We never schedule channel 0 or 127 */
52 dev_priv
->engine
.instmem
.prepare_access(dev
, true);
53 for (i
= 1, nr
= 0; i
< 127; i
++) {
54 if (dev_priv
->fifos
[i
] && dev_priv
->fifos
[i
]->ramfc
)
55 nv_wo32(dev
, cur
->gpuobj
, nr
++, i
);
57 dev_priv
->engine
.instmem
.finish_access(dev
);
59 nv_wr32(dev
, 0x32f4, cur
->instance
>> 12);
60 nv_wr32(dev
, 0x32ec, nr
);
61 nv_wr32(dev
, 0x2500, 0x101);
65 nv50_fifo_channel_enable(struct drm_device
*dev
, int channel
, bool nt
)
67 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
68 struct nouveau_channel
*chan
= dev_priv
->fifos
[channel
];
71 NV_DEBUG(dev
, "ch%d\n", channel
);
77 inst
= chan
->ramfc
->instance
>> 12;
79 inst
= chan
->ramfc
->instance
>> 8;
80 nv_wr32(dev
, NV50_PFIFO_CTX_TABLE(channel
),
81 inst
| NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED
);
84 nv50_fifo_init_thingo(dev
);
89 nv50_fifo_channel_disable(struct drm_device
*dev
, int channel
, bool nt
)
91 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
94 NV_DEBUG(dev
, "ch%d, nt=%d\n", channel
, nt
);
97 inst
= NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80
;
99 inst
= NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84
;
100 nv_wr32(dev
, NV50_PFIFO_CTX_TABLE(channel
), inst
);
103 nv50_fifo_init_thingo(dev
);
107 nv50_fifo_init_reset(struct drm_device
*dev
)
109 uint32_t pmc_e
= NV_PMC_ENABLE_PFIFO
;
113 nv_wr32(dev
, NV03_PMC_ENABLE
, nv_rd32(dev
, NV03_PMC_ENABLE
) & ~pmc_e
);
114 nv_wr32(dev
, NV03_PMC_ENABLE
, nv_rd32(dev
, NV03_PMC_ENABLE
) | pmc_e
);
118 nv50_fifo_init_intr(struct drm_device
*dev
)
122 nv_wr32(dev
, NV03_PFIFO_INTR_0
, 0xFFFFFFFF);
123 nv_wr32(dev
, NV03_PFIFO_INTR_EN_0
, 0xFFFFFFFF);
127 nv50_fifo_init_context_table(struct drm_device
*dev
)
129 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
134 for (i
= 0; i
< NV50_PFIFO_CTX_TABLE__SIZE
; i
++) {
135 if (dev_priv
->fifos
[i
])
136 nv50_fifo_channel_enable(dev
, i
, true);
138 nv50_fifo_channel_disable(dev
, i
, true);
141 nv50_fifo_init_thingo(dev
);
145 nv50_fifo_init_regs__nv(struct drm_device
*dev
)
149 nv_wr32(dev
, 0x250c, 0x6f3cfc34);
153 nv50_fifo_init_regs(struct drm_device
*dev
)
157 nv_wr32(dev
, 0x2500, 0);
158 nv_wr32(dev
, 0x3250, 0);
159 nv_wr32(dev
, 0x3220, 0);
160 nv_wr32(dev
, 0x3204, 0);
161 nv_wr32(dev
, 0x3210, 0);
162 nv_wr32(dev
, 0x3270, 0);
164 /* Enable dummy channels setup by nv50_instmem.c */
165 nv50_fifo_channel_enable(dev
, 0, true);
166 nv50_fifo_channel_enable(dev
, 127, true);
170 nv50_fifo_init(struct drm_device
*dev
)
172 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
173 struct nv50_fifo_priv
*priv
;
178 priv
= dev_priv
->engine
.fifo
.priv
;
180 priv
->cur_thingo
= !priv
->cur_thingo
;
184 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
187 dev_priv
->engine
.fifo
.priv
= priv
;
189 ret
= nouveau_gpuobj_new_ref(dev
, NULL
, NULL
, 0, 128*4, 0x1000,
190 NVOBJ_FLAG_ZERO_ALLOC
, &priv
->thingo
[0]);
192 NV_ERROR(dev
, "error creating thingo0: %d\n", ret
);
196 ret
= nouveau_gpuobj_new_ref(dev
, NULL
, NULL
, 0, 128*4, 0x1000,
197 NVOBJ_FLAG_ZERO_ALLOC
, &priv
->thingo
[1]);
199 NV_ERROR(dev
, "error creating thingo1: %d\n", ret
);
204 nv50_fifo_init_reset(dev
);
205 nv50_fifo_init_intr(dev
);
206 nv50_fifo_init_context_table(dev
);
207 nv50_fifo_init_regs__nv(dev
);
208 nv50_fifo_init_regs(dev
);
209 dev_priv
->engine
.fifo
.enable(dev
);
210 dev_priv
->engine
.fifo
.reassign(dev
, true);
216 nv50_fifo_takedown(struct drm_device
*dev
)
218 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
219 struct nv50_fifo_priv
*priv
= dev_priv
->engine
.fifo
.priv
;
226 nouveau_gpuobj_ref_del(dev
, &priv
->thingo
[0]);
227 nouveau_gpuobj_ref_del(dev
, &priv
->thingo
[1]);
229 dev_priv
->engine
.fifo
.priv
= NULL
;
234 nv50_fifo_channel_id(struct drm_device
*dev
)
236 return nv_rd32(dev
, NV03_PFIFO_CACHE1_PUSH1
) &
237 NV50_PFIFO_CACHE1_PUSH1_CHID_MASK
;
241 nv50_fifo_create_context(struct nouveau_channel
*chan
)
243 struct drm_device
*dev
= chan
->dev
;
244 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
245 struct nouveau_gpuobj
*ramfc
= NULL
;
249 NV_DEBUG(dev
, "ch%d\n", chan
->id
);
252 uint32_t ramin_poffset
= chan
->ramin
->gpuobj
->im_pramin
->start
;
253 uint32_t ramin_voffset
= chan
->ramin
->gpuobj
->im_backing_start
;
255 ret
= nouveau_gpuobj_new_fake(dev
, ramin_poffset
, ramin_voffset
,
256 0x100, NVOBJ_FLAG_ZERO_ALLOC
|
257 NVOBJ_FLAG_ZERO_FREE
, &ramfc
,
262 ret
= nouveau_gpuobj_new_fake(dev
, ramin_poffset
+ 0x0400,
263 ramin_voffset
+ 0x0400, 4096,
264 0, NULL
, &chan
->cache
);
268 ret
= nouveau_gpuobj_new_ref(dev
, chan
, NULL
, 0, 0x100, 256,
269 NVOBJ_FLAG_ZERO_ALLOC
|
270 NVOBJ_FLAG_ZERO_FREE
,
274 ramfc
= chan
->ramfc
->gpuobj
;
276 ret
= nouveau_gpuobj_new_ref(dev
, chan
, NULL
, 0, 4096, 1024,
282 spin_lock_irqsave(&dev_priv
->context_switch_lock
, flags
);
284 dev_priv
->engine
.instmem
.prepare_access(dev
, true);
286 nv_wo32(dev
, ramfc
, 0x48/4, chan
->pushbuf
->instance
>> 4);
287 nv_wo32(dev
, ramfc
, 0x80/4, (0xc << 24) | (chan
->ramht
->instance
>> 4));
288 nv_wo32(dev
, ramfc
, 0x44/4, 0x2101ffff);
289 nv_wo32(dev
, ramfc
, 0x60/4, 0x7fffffff);
290 nv_wo32(dev
, ramfc
, 0x40/4, 0x00000000);
291 nv_wo32(dev
, ramfc
, 0x7c/4, 0x30000001);
292 nv_wo32(dev
, ramfc
, 0x78/4, 0x00000000);
293 nv_wo32(dev
, ramfc
, 0x3c/4, 0x403f6078);
294 nv_wo32(dev
, ramfc
, 0x50/4, chan
->pushbuf_base
+
295 chan
->dma
.ib_base
* 4);
296 nv_wo32(dev
, ramfc
, 0x54/4, drm_order(chan
->dma
.ib_max
+ 1) << 16);
299 nv_wo32(dev
, chan
->ramin
->gpuobj
, 0, chan
->id
);
300 nv_wo32(dev
, chan
->ramin
->gpuobj
, 1,
301 chan
->ramfc
->instance
>> 8);
303 nv_wo32(dev
, ramfc
, 0x88/4, chan
->cache
->instance
>> 10);
304 nv_wo32(dev
, ramfc
, 0x98/4, chan
->ramin
->instance
>> 12);
307 dev_priv
->engine
.instmem
.finish_access(dev
);
309 ret
= nv50_fifo_channel_enable(dev
, chan
->id
, false);
311 NV_ERROR(dev
, "error enabling ch%d: %d\n", chan
->id
, ret
);
312 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);
313 nouveau_gpuobj_ref_del(dev
, &chan
->ramfc
);
317 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);
322 nv50_fifo_destroy_context(struct nouveau_channel
*chan
)
324 struct drm_device
*dev
= chan
->dev
;
325 struct nouveau_gpuobj_ref
*ramfc
= chan
->ramfc
;
327 NV_DEBUG(dev
, "ch%d\n", chan
->id
);
329 /* This will ensure the channel is seen as disabled. */
331 nv50_fifo_channel_disable(dev
, chan
->id
, false);
333 /* Dummy channel, also used on ch 127 */
335 nv50_fifo_channel_disable(dev
, 127, false);
337 nouveau_gpuobj_ref_del(dev
, &ramfc
);
338 nouveau_gpuobj_ref_del(dev
, &chan
->cache
);
342 nv50_fifo_load_context(struct nouveau_channel
*chan
)
344 struct drm_device
*dev
= chan
->dev
;
345 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
346 struct nouveau_gpuobj
*ramfc
= chan
->ramfc
->gpuobj
;
347 struct nouveau_gpuobj
*cache
= chan
->cache
->gpuobj
;
350 NV_DEBUG(dev
, "ch%d\n", chan
->id
);
352 dev_priv
->engine
.instmem
.prepare_access(dev
, false);
354 nv_wr32(dev
, 0x3330, nv_ro32(dev
, ramfc
, 0x00/4));
355 nv_wr32(dev
, 0x3334, nv_ro32(dev
, ramfc
, 0x04/4));
356 nv_wr32(dev
, 0x3240, nv_ro32(dev
, ramfc
, 0x08/4));
357 nv_wr32(dev
, 0x3320, nv_ro32(dev
, ramfc
, 0x0c/4));
358 nv_wr32(dev
, 0x3244, nv_ro32(dev
, ramfc
, 0x10/4));
359 nv_wr32(dev
, 0x3328, nv_ro32(dev
, ramfc
, 0x14/4));
360 nv_wr32(dev
, 0x3368, nv_ro32(dev
, ramfc
, 0x18/4));
361 nv_wr32(dev
, 0x336c, nv_ro32(dev
, ramfc
, 0x1c/4));
362 nv_wr32(dev
, 0x3370, nv_ro32(dev
, ramfc
, 0x20/4));
363 nv_wr32(dev
, 0x3374, nv_ro32(dev
, ramfc
, 0x24/4));
364 nv_wr32(dev
, 0x3378, nv_ro32(dev
, ramfc
, 0x28/4));
365 nv_wr32(dev
, 0x337c, nv_ro32(dev
, ramfc
, 0x2c/4));
366 nv_wr32(dev
, 0x3228, nv_ro32(dev
, ramfc
, 0x30/4));
367 nv_wr32(dev
, 0x3364, nv_ro32(dev
, ramfc
, 0x34/4));
368 nv_wr32(dev
, 0x32a0, nv_ro32(dev
, ramfc
, 0x38/4));
369 nv_wr32(dev
, 0x3224, nv_ro32(dev
, ramfc
, 0x3c/4));
370 nv_wr32(dev
, 0x324c, nv_ro32(dev
, ramfc
, 0x40/4));
371 nv_wr32(dev
, 0x2044, nv_ro32(dev
, ramfc
, 0x44/4));
372 nv_wr32(dev
, 0x322c, nv_ro32(dev
, ramfc
, 0x48/4));
373 nv_wr32(dev
, 0x3234, nv_ro32(dev
, ramfc
, 0x4c/4));
374 nv_wr32(dev
, 0x3340, nv_ro32(dev
, ramfc
, 0x50/4));
375 nv_wr32(dev
, 0x3344, nv_ro32(dev
, ramfc
, 0x54/4));
376 nv_wr32(dev
, 0x3280, nv_ro32(dev
, ramfc
, 0x58/4));
377 nv_wr32(dev
, 0x3254, nv_ro32(dev
, ramfc
, 0x5c/4));
378 nv_wr32(dev
, 0x3260, nv_ro32(dev
, ramfc
, 0x60/4));
379 nv_wr32(dev
, 0x3264, nv_ro32(dev
, ramfc
, 0x64/4));
380 nv_wr32(dev
, 0x3268, nv_ro32(dev
, ramfc
, 0x68/4));
381 nv_wr32(dev
, 0x326c, nv_ro32(dev
, ramfc
, 0x6c/4));
382 nv_wr32(dev
, 0x32e4, nv_ro32(dev
, ramfc
, 0x70/4));
383 nv_wr32(dev
, 0x3248, nv_ro32(dev
, ramfc
, 0x74/4));
384 nv_wr32(dev
, 0x2088, nv_ro32(dev
, ramfc
, 0x78/4));
385 nv_wr32(dev
, 0x2058, nv_ro32(dev
, ramfc
, 0x7c/4));
386 nv_wr32(dev
, 0x2210, nv_ro32(dev
, ramfc
, 0x80/4));
388 cnt
= nv_ro32(dev
, ramfc
, 0x84/4);
389 for (ptr
= 0; ptr
< cnt
; ptr
++) {
390 nv_wr32(dev
, NV40_PFIFO_CACHE1_METHOD(ptr
),
391 nv_ro32(dev
, cache
, (ptr
* 2) + 0));
392 nv_wr32(dev
, NV40_PFIFO_CACHE1_DATA(ptr
),
393 nv_ro32(dev
, cache
, (ptr
* 2) + 1));
395 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUT
, cnt
<< 2);
396 nv_wr32(dev
, NV03_PFIFO_CACHE1_GET
, 0);
398 /* guessing that all the 0x34xx regs aren't on NV50 */
400 nv_wr32(dev
, 0x340c, nv_ro32(dev
, ramfc
, 0x88/4));
401 nv_wr32(dev
, 0x3400, nv_ro32(dev
, ramfc
, 0x8c/4));
402 nv_wr32(dev
, 0x3404, nv_ro32(dev
, ramfc
, 0x90/4));
403 nv_wr32(dev
, 0x3408, nv_ro32(dev
, ramfc
, 0x94/4));
404 nv_wr32(dev
, 0x3410, nv_ro32(dev
, ramfc
, 0x98/4));
407 dev_priv
->engine
.instmem
.finish_access(dev
);
409 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUSH1
, chan
->id
| (1<<16));
414 nv50_fifo_unload_context(struct drm_device
*dev
)
416 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
417 struct nouveau_fifo_engine
*pfifo
= &dev_priv
->engine
.fifo
;
418 struct nouveau_gpuobj
*ramfc
, *cache
;
419 struct nouveau_channel
*chan
= NULL
;
420 int chid
, get
, put
, ptr
;
424 chid
= pfifo
->channel_id(dev
);
425 if (chid
< 1 || chid
>= dev_priv
->engine
.fifo
.channels
- 1)
428 chan
= dev_priv
->fifos
[chid
];
430 NV_ERROR(dev
, "Inactive channel on PFIFO: %d\n", chid
);
433 NV_DEBUG(dev
, "ch%d\n", chan
->id
);
434 ramfc
= chan
->ramfc
->gpuobj
;
435 cache
= chan
->cache
->gpuobj
;
437 dev_priv
->engine
.instmem
.prepare_access(dev
, true);
439 nv_wo32(dev
, ramfc
, 0x00/4, nv_rd32(dev
, 0x3330));
440 nv_wo32(dev
, ramfc
, 0x04/4, nv_rd32(dev
, 0x3334));
441 nv_wo32(dev
, ramfc
, 0x08/4, nv_rd32(dev
, 0x3240));
442 nv_wo32(dev
, ramfc
, 0x0c/4, nv_rd32(dev
, 0x3320));
443 nv_wo32(dev
, ramfc
, 0x10/4, nv_rd32(dev
, 0x3244));
444 nv_wo32(dev
, ramfc
, 0x14/4, nv_rd32(dev
, 0x3328));
445 nv_wo32(dev
, ramfc
, 0x18/4, nv_rd32(dev
, 0x3368));
446 nv_wo32(dev
, ramfc
, 0x1c/4, nv_rd32(dev
, 0x336c));
447 nv_wo32(dev
, ramfc
, 0x20/4, nv_rd32(dev
, 0x3370));
448 nv_wo32(dev
, ramfc
, 0x24/4, nv_rd32(dev
, 0x3374));
449 nv_wo32(dev
, ramfc
, 0x28/4, nv_rd32(dev
, 0x3378));
450 nv_wo32(dev
, ramfc
, 0x2c/4, nv_rd32(dev
, 0x337c));
451 nv_wo32(dev
, ramfc
, 0x30/4, nv_rd32(dev
, 0x3228));
452 nv_wo32(dev
, ramfc
, 0x34/4, nv_rd32(dev
, 0x3364));
453 nv_wo32(dev
, ramfc
, 0x38/4, nv_rd32(dev
, 0x32a0));
454 nv_wo32(dev
, ramfc
, 0x3c/4, nv_rd32(dev
, 0x3224));
455 nv_wo32(dev
, ramfc
, 0x40/4, nv_rd32(dev
, 0x324c));
456 nv_wo32(dev
, ramfc
, 0x44/4, nv_rd32(dev
, 0x2044));
457 nv_wo32(dev
, ramfc
, 0x48/4, nv_rd32(dev
, 0x322c));
458 nv_wo32(dev
, ramfc
, 0x4c/4, nv_rd32(dev
, 0x3234));
459 nv_wo32(dev
, ramfc
, 0x50/4, nv_rd32(dev
, 0x3340));
460 nv_wo32(dev
, ramfc
, 0x54/4, nv_rd32(dev
, 0x3344));
461 nv_wo32(dev
, ramfc
, 0x58/4, nv_rd32(dev
, 0x3280));
462 nv_wo32(dev
, ramfc
, 0x5c/4, nv_rd32(dev
, 0x3254));
463 nv_wo32(dev
, ramfc
, 0x60/4, nv_rd32(dev
, 0x3260));
464 nv_wo32(dev
, ramfc
, 0x64/4, nv_rd32(dev
, 0x3264));
465 nv_wo32(dev
, ramfc
, 0x68/4, nv_rd32(dev
, 0x3268));
466 nv_wo32(dev
, ramfc
, 0x6c/4, nv_rd32(dev
, 0x326c));
467 nv_wo32(dev
, ramfc
, 0x70/4, nv_rd32(dev
, 0x32e4));
468 nv_wo32(dev
, ramfc
, 0x74/4, nv_rd32(dev
, 0x3248));
469 nv_wo32(dev
, ramfc
, 0x78/4, nv_rd32(dev
, 0x2088));
470 nv_wo32(dev
, ramfc
, 0x7c/4, nv_rd32(dev
, 0x2058));
471 nv_wo32(dev
, ramfc
, 0x80/4, nv_rd32(dev
, 0x2210));
473 put
= (nv_rd32(dev
, NV03_PFIFO_CACHE1_PUT
) & 0x7ff) >> 2;
474 get
= (nv_rd32(dev
, NV03_PFIFO_CACHE1_GET
) & 0x7ff) >> 2;
477 nv_wo32(dev
, cache
, ptr
++,
478 nv_rd32(dev
, NV40_PFIFO_CACHE1_METHOD(get
)));
479 nv_wo32(dev
, cache
, ptr
++,
480 nv_rd32(dev
, NV40_PFIFO_CACHE1_DATA(get
)));
481 get
= (get
+ 1) & 0x1ff;
484 /* guessing that all the 0x34xx regs aren't on NV50 */
486 nv_wo32(dev
, ramfc
, 0x84/4, ptr
>> 1);
487 nv_wo32(dev
, ramfc
, 0x88/4, nv_rd32(dev
, 0x340c));
488 nv_wo32(dev
, ramfc
, 0x8c/4, nv_rd32(dev
, 0x3400));
489 nv_wo32(dev
, ramfc
, 0x90/4, nv_rd32(dev
, 0x3404));
490 nv_wo32(dev
, ramfc
, 0x94/4, nv_rd32(dev
, 0x3408));
491 nv_wo32(dev
, ramfc
, 0x98/4, nv_rd32(dev
, 0x3410));
494 dev_priv
->engine
.instmem
.finish_access(dev
);
496 /*XXX: probably reload ch127 (NULL) state back too */
497 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUSH1
, 127);