drivers/gpu/drm/nouveau/nv04_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30
  31 #define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))
  32 #define NV04_RAMFC__SIZE 32
  33 #define NV04_RAMFC_DMA_PUT                                       0x00
  34 #define NV04_RAMFC_DMA_GET                                       0x04
  35 #define NV04_RAMFC_DMA_INSTANCE                                  0x08
  36 #define NV04_RAMFC_DMA_STATE                                     0x0C
  37 #define NV04_RAMFC_DMA_FETCH                                     0x10
  38 #define NV04_RAMFC_ENGINE                                        0x14
  39 #define NV04_RAMFC_PULL1_ENGINE                                  0x18
  40
  41 #define RAMFC_WR(offset, val) nv_wo32(dev, chan->ramfc->gpuobj, \
  42                                          NV04_RAMFC_##offset/4, (val))
  43 #define RAMFC_RD(offset)      nv_ro32(dev, chan->ramfc->gpuobj, \
  44                                          NV04_RAMFC_##offset/4)
  45
  46 void
  47 nv04_fifo_disable(struct drm_device *dev)
  48 {
  49         uint32_t tmp;
  50
  51         tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH);
  52         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, tmp & ~1);
  53         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
  54         tmp = nv_rd32(dev, NV03_PFIFO_CACHE1_PULL1);
  55         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, tmp & ~1);
  56 }
  57
  58 void
  59 nv04_fifo_enable(struct drm_device *dev)
  60 {
  61         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
  62         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
  63 }
  64
  65 bool
  66 nv04_fifo_reassign(struct drm_device *dev, bool enable)
  67 {
  68         uint32_t reassign = nv_rd32(dev, NV03_PFIFO_CACHES);
  69
  70         nv_wr32(dev, NV03_PFIFO_CACHES, enable ? 1 : 0);
  71         return (reassign == 1);
  72 }
  73
  74 bool
  75 nv04_fifo_cache_flush(struct drm_device *dev)
  76 {
  77         struct drm_nouveau_private *dev_priv = dev->dev_private;
  78         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
  79         uint64_t start = ptimer->read(dev);
  80
  81         do {
  82                 if (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) ==
  83                     nv_rd32(dev, NV03_PFIFO_CACHE1_PUT))
  84                         return true;
  85
  86         } while (ptimer->read(dev) - start < 100000000);
  87
  88         NV_ERROR(dev, "Timeout flushing the PFIFO cache.\n");
  89
  90         return false;
  91 }
  92
  93 bool
  94 nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
  95 {
  96         uint32_t pull = nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0);
  97
  98         if (enable) {
  99                 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull | 1);
 100         } else {
 101                 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull & ~1);
 102                 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
 103         }
 104
 105         return !!(pull & 1);
 106 }
 107
 108 int
 109 nv04_fifo_channel_id(struct drm_device *dev)
 110 {
 111         return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
 112                         NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
 113 }
 114
 115 int
 116 nv04_fifo_create_context(struct nouveau_channel *chan)
 117 {
 118         struct drm_device *dev = chan->dev;
 119         struct drm_nouveau_private *dev_priv = dev->dev_private;
 120         unsigned long flags;
 121         int ret;
 122
 123         ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0,
 124                                                 NV04_RAMFC__SIZE,
 125                                                 NVOBJ_FLAG_ZERO_ALLOC |
 126                                                 NVOBJ_FLAG_ZERO_FREE,
 127                                                 NULL, &chan->ramfc);
 128         if (ret)
 129                 return ret;
 130
 131         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 132
 133         /* Setup initial state */
 134         dev_priv->engine.instmem.prepare_access(dev, true);
 135         RAMFC_WR(DMA_PUT, chan->pushbuf_base);
 136         RAMFC_WR(DMA_GET, chan->pushbuf_base);
 137         RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4);
 138         RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 139                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 140                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
 141 #ifdef __BIG_ENDIAN
 142                              NV_PFIFO_CACHE1_BIG_ENDIAN |
 143 #endif
 144                              0));
 145         dev_priv->engine.instmem.finish_access(dev);
 146
 147         /* enable the fifo dma operation */
 148         nv_wr32(dev, NV04_PFIFO_MODE,
 149                 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
 150
 151         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 152         return 0;
 153 }
 154
 155 void
 156 nv04_fifo_destroy_context(struct nouveau_channel *chan)
 157 {
 158         struct drm_device *dev = chan->dev;
 159
 160         nv_wr32(dev, NV04_PFIFO_MODE,
 161                 nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id));
 162
 163         nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 164 }
 165
 166 static void
 167 nv04_fifo_do_load_context(struct drm_device *dev, int chid)
 168 {
 169         struct drm_nouveau_private *dev_priv = dev->dev_private;
 170         uint32_t fc = NV04_RAMFC(chid), tmp;
 171
 172         dev_priv->engine.instmem.prepare_access(dev, false);
 173
 174         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
 175         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
 176         tmp = nv_ri32(dev, fc + 8);
 177         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
 178         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
 179         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 12));
 180         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 16));
 181         nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 20));
 182         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 24));
 183
 184         dev_priv->engine.instmem.finish_access(dev);
 185
 186         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 187         nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
 188 }
 189
 190 int
 191 nv04_fifo_load_context(struct nouveau_channel *chan)
 192 {
 193         uint32_t tmp;
 194
 195         nv_wr32(chan->dev, NV03_PFIFO_CACHE1_PUSH1,
 196                            NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 197         nv04_fifo_do_load_context(chan->dev, chan->id);
 198         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
 199
 200         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
 201         tmp = nv_rd32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
 202         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 203
 204         return 0;
 205 }
 206
 207 int
 208 nv04_fifo_unload_context(struct drm_device *dev)
 209 {
 210         struct drm_nouveau_private *dev_priv = dev->dev_private;
 211         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 212         struct nouveau_channel *chan = NULL;
 213         uint32_t tmp;
 214         int chid;
 215
 216         chid = pfifo->channel_id(dev);
 217         if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
 218                 return 0;
 219
 220         chan = dev_priv->fifos[chid];
 221         if (!chan) {
 222                 NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
 223                 return -EINVAL;
 224         }
 225
 226         dev_priv->engine.instmem.prepare_access(dev, true);
 227         RAMFC_WR(DMA_PUT, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
 228         RAMFC_WR(DMA_GET, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
 229         tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
 230         tmp |= nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE);
 231         RAMFC_WR(DMA_INSTANCE, tmp);
 232         RAMFC_WR(DMA_STATE, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
 233         RAMFC_WR(DMA_FETCH, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
 234         RAMFC_WR(ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
 235         RAMFC_WR(PULL1_ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
 236         dev_priv->engine.instmem.finish_access(dev);
 237
 238         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 239         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 240         return 0;
 241 }
 242
 243 static void
 244 nv04_fifo_init_reset(struct drm_device *dev)
 245 {
 246         nv_wr32(dev, NV03_PMC_ENABLE,
 247                 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
 248         nv_wr32(dev, NV03_PMC_ENABLE,
 249                 nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);
 250
 251         nv_wr32(dev, 0x003224, 0x000f0078);
 252         nv_wr32(dev, 0x002044, 0x0101ffff);
 253         nv_wr32(dev, 0x002040, 0x000000ff);
 254         nv_wr32(dev, 0x002500, 0x00000000);
 255         nv_wr32(dev, 0x003000, 0x00000000);
 256         nv_wr32(dev, 0x003050, 0x00000000);
 257         nv_wr32(dev, 0x003200, 0x00000000);
 258         nv_wr32(dev, 0x003250, 0x00000000);
 259         nv_wr32(dev, 0x003220, 0x00000000);
 260
 261         nv_wr32(dev, 0x003250, 0x00000000);
 262         nv_wr32(dev, 0x003270, 0x00000000);
 263         nv_wr32(dev, 0x003210, 0x00000000);
 264 }
 265
 266 static void
 267 nv04_fifo_init_ramxx(struct drm_device *dev)
 268 {
 269         struct drm_nouveau_private *dev_priv = dev->dev_private;
 270
 271         nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 272                                        ((dev_priv->ramht_bits - 9) << 16) |
 273                                        (dev_priv->ramht_offset >> 8));
 274         nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
 275         nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc_offset >> 8);
 276 }
 277
 278 static void
 279 nv04_fifo_init_intr(struct drm_device *dev)
 280 {
 281         nv_wr32(dev, 0x002100, 0xffffffff);
 282         nv_wr32(dev, 0x002140, 0xffffffff);
 283 }
 284
 285 int
 286 nv04_fifo_init(struct drm_device *dev)
 287 {
 288         struct drm_nouveau_private *dev_priv = dev->dev_private;
 289         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 290         int i;
 291
 292         nv04_fifo_init_reset(dev);
 293         nv04_fifo_init_ramxx(dev);
 294
 295         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 296         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 297
 298         nv04_fifo_init_intr(dev);
 299         pfifo->enable(dev);
 300
 301         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 302                 if (dev_priv->fifos[i]) {
 303                         uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
 304                         nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
 305                 }
 306         }
 307
 308         return 0;
 309 }
 310