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V4L/DVB: media/IR/imon: testing the wrong variable
[wandboard.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
blobace630aa89e1c6b9755df63a1af28a61a6db6229
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 struct nouveau_grctx;
58
59 #define MAX_NUM_DCB_ENTRIES 16
60
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
63
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73 };
74
75 struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
87 bool validate_mapped;
88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
96 struct nouveau_tile_reg *tile;
97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101 };
102
103 static inline struct nouveau_bo *
104 nouveau_bo(struct ttm_buffer_object *bo)
105 {
106 return container_of(bo, struct nouveau_bo, bo);
107 }
108
109 static inline struct nouveau_bo *
110 nouveau_gem_object(struct drm_gem_object *gem)
111 {
112 return gem ? gem->driver_private : NULL;
113 }
114
115 /* TODO: submit equivalent to TTM generic API upstream? */
116 static inline void __iomem *
117 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118 {
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124 }
125
126 struct mem_block {
127 struct mem_block *next;
128 struct mem_block *prev;
129 uint64_t start;
130 uint64_t size;
131 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
132 };
133
134 enum nouveau_flags {
135 NV_NFORCE = 0x10000000,
136 NV_NFORCE2 = 0x20000000
137 };
138
139 #define NVOBJ_ENGINE_SW 0
140 #define NVOBJ_ENGINE_GR 1
141 #define NVOBJ_ENGINE_DISPLAY 2
142 #define NVOBJ_ENGINE_INT 0xdeadbeef
143
144 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
145 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
146 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
147 #define NVOBJ_FLAG_FAKE (1 << 3)
148 struct nouveau_gpuobj {
149 struct list_head list;
150
151 struct nouveau_channel *im_channel;
152 struct mem_block *im_pramin;
153 struct nouveau_bo *im_backing;
154 uint32_t im_backing_start;
155 uint32_t *im_backing_suspend;
156 int im_bound;
157
158 uint32_t flags;
159 int refcount;
160
161 uint32_t engine;
162 uint32_t class;
163
164 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
165 void *priv;
166 };
167
168 struct nouveau_gpuobj_ref {
169 struct list_head list;
170
171 struct nouveau_gpuobj *gpuobj;
172 uint32_t instance;
173
174 struct nouveau_channel *channel;
175 int handle;
176 };
177
178 struct nouveau_channel {
179 struct drm_device *dev;
180 int id;
181
182 /* owner of this fifo */
183 struct drm_file *file_priv;
184 /* mapping of the fifo itself */
185 struct drm_local_map *map;
186
187 /* mapping of the regs controling the fifo */
188 void __iomem *user;
189 uint32_t user_get;
190 uint32_t user_put;
191
192 /* Fencing */
193 struct {
194 /* lock protects the pending list only */
195 spinlock_t lock;
196 struct list_head pending;
197 uint32_t sequence;
198 uint32_t sequence_ack;
199 uint32_t last_sequence_irq;
200 } fence;
201
202 /* DMA push buffer */
203 struct nouveau_gpuobj_ref *pushbuf;
204 struct nouveau_bo *pushbuf_bo;
205 uint32_t pushbuf_base;
206
207 /* Notifier memory */
208 struct nouveau_bo *notifier_bo;
209 struct mem_block *notifier_heap;
210
211 /* PFIFO context */
212 struct nouveau_gpuobj_ref *ramfc;
213 struct nouveau_gpuobj_ref *cache;
214
215 /* PGRAPH context */
216 /* XXX may be merge 2 pointers as private data ??? */
217 struct nouveau_gpuobj_ref *ramin_grctx;
218 void *pgraph_ctx;
219
220 /* NV50 VM */
221 struct nouveau_gpuobj *vm_pd;
222 struct nouveau_gpuobj_ref *vm_gart_pt;
223 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
224
225 /* Objects */
226 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
227 struct mem_block *ramin_heap; /* Private PRAMIN heap */
228 struct nouveau_gpuobj_ref *ramht; /* Hash table */
229 struct list_head ramht_refs; /* Objects referenced by RAMHT */
230
231 /* GPU object info for stuff used in-kernel (mm_enabled) */
232 uint32_t m2mf_ntfy;
233 uint32_t vram_handle;
234 uint32_t gart_handle;
235 bool accel_done;
236
237 /* Push buffer state (only for drm's channel on !mm_enabled) */
238 struct {
239 int max;
240 int free;
241 int cur;
242 int put;
243 /* access via pushbuf_bo */
244
245 int ib_base;
246 int ib_max;
247 int ib_free;
248 int ib_put;
249 } dma;
250
251 uint32_t sw_subchannel[8];
252
253 struct {
254 struct nouveau_gpuobj *vblsem;
255 uint32_t vblsem_offset;
256 uint32_t vblsem_rval;
257 struct list_head vbl_wait;
258 } nvsw;
259
260 struct {
261 bool active;
262 char name[32];
263 struct drm_info_list info;
264 } debugfs;
265 };
266
267 struct nouveau_instmem_engine {
268 void *priv;
269
270 int (*init)(struct drm_device *dev);
271 void (*takedown)(struct drm_device *dev);
272 int (*suspend)(struct drm_device *dev);
273 void (*resume)(struct drm_device *dev);
274
275 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
276 uint32_t *size);
277 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
278 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
279 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
280 void (*prepare_access)(struct drm_device *, bool write);
281 void (*finish_access)(struct drm_device *);
282 };
283
284 struct nouveau_mc_engine {
285 int (*init)(struct drm_device *dev);
286 void (*takedown)(struct drm_device *dev);
287 };
288
289 struct nouveau_timer_engine {
290 int (*init)(struct drm_device *dev);
291 void (*takedown)(struct drm_device *dev);
292 uint64_t (*read)(struct drm_device *dev);
293 };
294
295 struct nouveau_fb_engine {
296 int num_tiles;
297
298 int (*init)(struct drm_device *dev);
299 void (*takedown)(struct drm_device *dev);
300
301 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
302 uint32_t size, uint32_t pitch);
303 };
304
305 struct nouveau_fifo_engine {
306 void *priv;
307
308 int channels;
309
310 int (*init)(struct drm_device *);
311 void (*takedown)(struct drm_device *);
312
313 void (*disable)(struct drm_device *);
314 void (*enable)(struct drm_device *);
315 bool (*reassign)(struct drm_device *, bool enable);
316 bool (*cache_flush)(struct drm_device *dev);
317 bool (*cache_pull)(struct drm_device *dev, bool enable);
318
319 int (*channel_id)(struct drm_device *);
320
321 int (*create_context)(struct nouveau_channel *);
322 void (*destroy_context)(struct nouveau_channel *);
323 int (*load_context)(struct nouveau_channel *);
324 int (*unload_context)(struct drm_device *);
325 };
326
327 struct nouveau_pgraph_object_method {
328 int id;
329 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
330 uint32_t data);
331 };
332
333 struct nouveau_pgraph_object_class {
334 int id;
335 bool software;
336 struct nouveau_pgraph_object_method *methods;
337 };
338
339 struct nouveau_pgraph_engine {
340 struct nouveau_pgraph_object_class *grclass;
341 bool accel_blocked;
342 void *ctxprog;
343 void *ctxvals;
344 int grctx_size;
345
346 int (*init)(struct drm_device *);
347 void (*takedown)(struct drm_device *);
348
349 void (*fifo_access)(struct drm_device *, bool);
350
351 struct nouveau_channel *(*channel)(struct drm_device *);
352 int (*create_context)(struct nouveau_channel *);
353 void (*destroy_context)(struct nouveau_channel *);
354 int (*load_context)(struct nouveau_channel *);
355 int (*unload_context)(struct drm_device *);
356
357 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
358 uint32_t size, uint32_t pitch);
359 };
360
361 struct nouveau_engine {
362 struct nouveau_instmem_engine instmem;
363 struct nouveau_mc_engine mc;
364 struct nouveau_timer_engine timer;
365 struct nouveau_fb_engine fb;
366 struct nouveau_pgraph_engine graph;
367 struct nouveau_fifo_engine fifo;
368 };
369
370 struct nouveau_pll_vals {
371 union {
372 struct {
373 #ifdef __BIG_ENDIAN
374 uint8_t N1, M1, N2, M2;
375 #else
376 uint8_t M1, N1, M2, N2;
377 #endif
378 };
379 struct {
380 uint16_t NM1, NM2;
381 } __attribute__((packed));
382 };
383 int log2P;
384
385 int refclk;
386 };
387
388 enum nv04_fp_display_regs {
389 FP_DISPLAY_END,
390 FP_TOTAL,
391 FP_CRTC,
392 FP_SYNC_START,
393 FP_SYNC_END,
394 FP_VALID_START,
395 FP_VALID_END
396 };
397
398 struct nv04_crtc_reg {
399 unsigned char MiscOutReg; /* */
400 uint8_t CRTC[0x9f];
401 uint8_t CR58[0x10];
402 uint8_t Sequencer[5];
403 uint8_t Graphics[9];
404 uint8_t Attribute[21];
405 unsigned char DAC[768]; /* Internal Colorlookuptable */
406
407 /* PCRTC regs */
408 uint32_t fb_start;
409 uint32_t crtc_cfg;
410 uint32_t cursor_cfg;
411 uint32_t gpio_ext;
412 uint32_t crtc_830;
413 uint32_t crtc_834;
414 uint32_t crtc_850;
415 uint32_t crtc_eng_ctrl;
416
417 /* PRAMDAC regs */
418 uint32_t nv10_cursync;
419 struct nouveau_pll_vals pllvals;
420 uint32_t ramdac_gen_ctrl;
421 uint32_t ramdac_630;
422 uint32_t ramdac_634;
423 uint32_t tv_setup;
424 uint32_t tv_vtotal;
425 uint32_t tv_vskew;
426 uint32_t tv_vsync_delay;
427 uint32_t tv_htotal;
428 uint32_t tv_hskew;
429 uint32_t tv_hsync_delay;
430 uint32_t tv_hsync_delay2;
431 uint32_t fp_horiz_regs[7];
432 uint32_t fp_vert_regs[7];
433 uint32_t dither;
434 uint32_t fp_control;
435 uint32_t dither_regs[6];
436 uint32_t fp_debug_0;
437 uint32_t fp_debug_1;
438 uint32_t fp_debug_2;
439 uint32_t fp_margin_color;
440 uint32_t ramdac_8c0;
441 uint32_t ramdac_a20;
442 uint32_t ramdac_a24;
443 uint32_t ramdac_a34;
444 uint32_t ctv_regs[38];
445 };
446
447 struct nv04_output_reg {
448 uint32_t output;
449 int head;
450 };
451
452 struct nv04_mode_state {
453 uint32_t bpp;
454 uint32_t width;
455 uint32_t height;
456 uint32_t interlace;
457 uint32_t repaint0;
458 uint32_t repaint1;
459 uint32_t screen;
460 uint32_t scale;
461 uint32_t dither;
462 uint32_t extra;
463 uint32_t fifo;
464 uint32_t pixel;
465 uint32_t horiz;
466 int arbitration0;
467 int arbitration1;
468 uint32_t pll;
469 uint32_t pllB;
470 uint32_t vpll;
471 uint32_t vpll2;
472 uint32_t vpllB;
473 uint32_t vpll2B;
474 uint32_t pllsel;
475 uint32_t sel_clk;
476 uint32_t general;
477 uint32_t crtcOwner;
478 uint32_t head;
479 uint32_t head2;
480 uint32_t cursorConfig;
481 uint32_t cursor0;
482 uint32_t cursor1;
483 uint32_t cursor2;
484 uint32_t timingH;
485 uint32_t timingV;
486 uint32_t displayV;
487 uint32_t crtcSync;
488
489 struct nv04_crtc_reg crtc_reg[2];
490 };
491
492 enum nouveau_card_type {
493 NV_04 = 0x00,
494 NV_10 = 0x10,
495 NV_20 = 0x20,
496 NV_30 = 0x30,
497 NV_40 = 0x40,
498 NV_50 = 0x50,
499 };
500
501 struct drm_nouveau_private {
502 struct drm_device *dev;
503 enum {
504 NOUVEAU_CARD_INIT_DOWN,
505 NOUVEAU_CARD_INIT_DONE,
506 NOUVEAU_CARD_INIT_FAILED
507 } init_state;
508
509 /* the card type, takes NV_* as values */
510 enum nouveau_card_type card_type;
511 /* exact chipset, derived from NV_PMC_BOOT_0 */
512 int chipset;
513 int flags;
514
515 void __iomem *mmio;
516 void __iomem *ramin;
517 uint32_t ramin_size;
518
519 struct nouveau_bo *vga_ram;
520
521 struct workqueue_struct *wq;
522 struct work_struct irq_work;
523 struct work_struct hpd_work;
524
525 struct list_head vbl_waiting;
526
527 struct {
528 struct ttm_global_reference mem_global_ref;
529 struct ttm_bo_global_ref bo_global_ref;
530 struct ttm_bo_device bdev;
531 spinlock_t bo_list_lock;
532 struct list_head bo_list;
533 atomic_t validate_sequence;
534 } ttm;
535
536 struct fb_info *fbdev_info;
537
538 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
539
540 struct nouveau_engine engine;
541 struct nouveau_channel *channel;
542
543 /* For PFIFO and PGRAPH. */
544 spinlock_t context_switch_lock;
545
546 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
547 struct nouveau_gpuobj *ramht;
548 uint32_t ramin_rsvd_vram;
549 uint32_t ramht_offset;
550 uint32_t ramht_size;
551 uint32_t ramht_bits;
552 uint32_t ramfc_offset;
553 uint32_t ramfc_size;
554 uint32_t ramro_offset;
555 uint32_t ramro_size;
556
557 struct {
558 enum {
559 NOUVEAU_GART_NONE = 0,
560 NOUVEAU_GART_AGP,
561 NOUVEAU_GART_SGDMA
562 } type;
563 uint64_t aper_base;
564 uint64_t aper_size;
565 uint64_t aper_free;
566
567 struct nouveau_gpuobj *sg_ctxdma;
568 struct page *sg_dummy_page;
569 dma_addr_t sg_dummy_bus;
570 } gart_info;
571
572 /* nv10-nv40 tiling regions */
573 struct {
574 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
575 spinlock_t lock;
576 } tile;
577
578 /* VRAM/fb configuration */
579 uint64_t vram_size;
580 uint64_t vram_sys_base;
581
582 uint64_t fb_phys;
583 uint64_t fb_available_size;
584 uint64_t fb_mappable_pages;
585 uint64_t fb_aper_free;
586 int fb_mtrr;
587
588 /* G8x/G9x virtual address space */
589 uint64_t vm_gart_base;
590 uint64_t vm_gart_size;
591 uint64_t vm_vram_base;
592 uint64_t vm_vram_size;
593 uint64_t vm_end;
594 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
595 int vm_vram_pt_nr;
596
597 struct mem_block *ramin_heap;
598
599 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
600 uint32_t ctx_table_size;
601 struct nouveau_gpuobj_ref *ctx_table;
602
603 struct list_head gpuobj_list;
604
605 struct nvbios vbios;
606
607 struct nv04_mode_state mode_reg;
608 struct nv04_mode_state saved_reg;
609 uint32_t saved_vga_font[4][16384];
610 uint32_t crtc_owner;
611 uint32_t dac_users[4];
612
613 struct nouveau_suspend_resume {
614 uint32_t *ramin_copy;
615 } susres;
616
617 struct backlight_device *backlight;
618
619 struct nouveau_channel *evo;
620
621 struct {
622 struct dentry *channel_root;
623 } debugfs;
624 };
625
626 static inline struct drm_nouveau_private *
627 nouveau_bdev(struct ttm_bo_device *bd)
628 {
629 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
630 }
631
632 static inline int
633 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
634 {
635 struct nouveau_bo *prev;
636
637 if (!pnvbo)
638 return -EINVAL;
639 prev = *pnvbo;
640
641 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
642 if (prev) {
643 struct ttm_buffer_object *bo = &prev->bo;
644
645 ttm_bo_unref(&bo);
646 }
647
648 return 0;
649 }
650
651 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
652 struct drm_nouveau_private *nv = dev->dev_private; \
653 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
654 NV_ERROR(dev, "called without init\n"); \
655 return -EINVAL; \
656 } \
657 } while (0)
658
659 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
660 struct drm_nouveau_private *nv = dev->dev_private; \
661 if (!nouveau_channel_owner(dev, (cl), (id))) { \
662 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
663 DRM_CURRENTPID, (id)); \
664 return -EPERM; \
665 } \
666 (ch) = nv->fifos[(id)]; \
667 } while (0)
668
669 /* nouveau_drv.c */
670 extern int nouveau_noagp;
671 extern int nouveau_duallink;
672 extern int nouveau_uscript_lvds;
673 extern int nouveau_uscript_tmds;
674 extern int nouveau_vram_pushbuf;
675 extern int nouveau_vram_notify;
676 extern int nouveau_fbpercrtc;
677 extern int nouveau_tv_disable;
678 extern char *nouveau_tv_norm;
679 extern int nouveau_reg_debug;
680 extern char *nouveau_vbios;
681 extern int nouveau_ctxfw;
682 extern int nouveau_ignorelid;
683 extern int nouveau_nofbaccel;
684 extern int nouveau_noaccel;
685 extern int nouveau_override_conntype;
686
687 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
688 extern int nouveau_pci_resume(struct pci_dev *pdev);
689
690 /* nouveau_state.c */
691 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
692 extern int nouveau_load(struct drm_device *, unsigned long flags);
693 extern int nouveau_firstopen(struct drm_device *);
694 extern void nouveau_lastclose(struct drm_device *);
695 extern int nouveau_unload(struct drm_device *);
696 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
697 struct drm_file *);
698 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
699 struct drm_file *);
700 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
701 uint32_t reg, uint32_t mask, uint32_t val);
702 extern bool nouveau_wait_for_idle(struct drm_device *);
703 extern int nouveau_card_init(struct drm_device *);
704
705 /* nouveau_mem.c */
706 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
707 uint64_t size);
708 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
709 uint64_t size, int align2,
710 struct drm_file *, int tail);
711 extern void nouveau_mem_takedown(struct mem_block **heap);
712 extern void nouveau_mem_free_block(struct mem_block *);
713 extern int nouveau_mem_detect(struct drm_device *dev);
714 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
715 extern int nouveau_mem_init(struct drm_device *);
716 extern int nouveau_mem_init_agp(struct drm_device *);
717 extern void nouveau_mem_close(struct drm_device *);
718 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
719 uint32_t addr,
720 uint32_t size,
721 uint32_t pitch);
722 extern void nv10_mem_expire_tiling(struct drm_device *dev,
723 struct nouveau_tile_reg *tile,
724 struct nouveau_fence *fence);
725 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
726 uint32_t size, uint32_t flags,
727 uint64_t phys);
728 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
729 uint32_t size);
730
731 /* nouveau_notifier.c */
732 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
733 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
734 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
735 int cout, uint32_t *offset);
736 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
737 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
738 struct drm_file *);
739 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
740 struct drm_file *);
741
742 /* nouveau_channel.c */
743 extern struct drm_ioctl_desc nouveau_ioctls[];
744 extern int nouveau_max_ioctl;
745 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
746 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
747 int channel);
748 extern int nouveau_channel_alloc(struct drm_device *dev,
749 struct nouveau_channel **chan,
750 struct drm_file *file_priv,
751 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
752 extern void nouveau_channel_free(struct nouveau_channel *);
753
754 /* nouveau_object.c */
755 extern int nouveau_gpuobj_early_init(struct drm_device *);
756 extern int nouveau_gpuobj_init(struct drm_device *);
757 extern void nouveau_gpuobj_takedown(struct drm_device *);
758 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
759 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
760 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
761 extern void nouveau_gpuobj_resume(struct drm_device *dev);
762 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
763 uint32_t vram_h, uint32_t tt_h);
764 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
765 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
766 uint32_t size, int align, uint32_t flags,
767 struct nouveau_gpuobj **);
768 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
769 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
770 uint32_t handle, struct nouveau_gpuobj *,
771 struct nouveau_gpuobj_ref **);
772 extern int nouveau_gpuobj_ref_del(struct drm_device *,
773 struct nouveau_gpuobj_ref **);
774 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
775 struct nouveau_gpuobj_ref **ref_ret);
776 extern int nouveau_gpuobj_new_ref(struct drm_device *,
777 struct nouveau_channel *alloc_chan,
778 struct nouveau_channel *ref_chan,
779 uint32_t handle, uint32_t size, int align,
780 uint32_t flags, struct nouveau_gpuobj_ref **);
781 extern int nouveau_gpuobj_new_fake(struct drm_device *,
782 uint32_t p_offset, uint32_t b_offset,
783 uint32_t size, uint32_t flags,
784 struct nouveau_gpuobj **,
785 struct nouveau_gpuobj_ref**);
786 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
787 uint64_t offset, uint64_t size, int access,
788 int target, struct nouveau_gpuobj **);
789 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
790 uint64_t offset, uint64_t size,
791 int access, struct nouveau_gpuobj **,
792 uint32_t *o_ret);
793 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
794 struct nouveau_gpuobj **);
795 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
796 struct nouveau_gpuobj **);
797 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
798 struct drm_file *);
799 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
800 struct drm_file *);
801
802 /* nouveau_irq.c */
803 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
804 extern void nouveau_irq_preinstall(struct drm_device *);
805 extern int nouveau_irq_postinstall(struct drm_device *);
806 extern void nouveau_irq_uninstall(struct drm_device *);
807
808 /* nouveau_sgdma.c */
809 extern int nouveau_sgdma_init(struct drm_device *);
810 extern void nouveau_sgdma_takedown(struct drm_device *);
811 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
812 uint32_t *page);
813 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
814
815 /* nouveau_debugfs.c */
816 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
817 extern int nouveau_debugfs_init(struct drm_minor *);
818 extern void nouveau_debugfs_takedown(struct drm_minor *);
819 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
820 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
821 #else
822 static inline int
823 nouveau_debugfs_init(struct drm_minor *minor)
824 {
825 return 0;
826 }
827
828 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
829 {
830 }
831
832 static inline int
833 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
834 {
835 return 0;
836 }
837
838 static inline void
839 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
840 {
841 }
842 #endif
843
844 /* nouveau_dma.c */
845 extern void nouveau_dma_pre_init(struct nouveau_channel *);
846 extern int nouveau_dma_init(struct nouveau_channel *);
847 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
848
849 /* nouveau_acpi.c */
850 #if defined(CONFIG_ACPI)
851 void nouveau_register_dsm_handler(void);
852 void nouveau_unregister_dsm_handler(void);
853 #else
854 static inline void nouveau_register_dsm_handler(void) {}
855 static inline void nouveau_unregister_dsm_handler(void) {}
856 #endif
857
858 /* nouveau_backlight.c */
859 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
860 extern int nouveau_backlight_init(struct drm_device *);
861 extern void nouveau_backlight_exit(struct drm_device *);
862 #else
863 static inline int nouveau_backlight_init(struct drm_device *dev)
864 {
865 return 0;
866 }
867
868 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
869 #endif
870
871 /* nouveau_bios.c */
872 extern int nouveau_bios_init(struct drm_device *);
873 extern void nouveau_bios_takedown(struct drm_device *dev);
874 extern int nouveau_run_vbios_init(struct drm_device *);
875 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
876 struct dcb_entry *);
877 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
878 enum dcb_gpio_tag);
879 extern struct dcb_connector_table_entry *
880 nouveau_bios_connector_entry(struct drm_device *, int index);
881 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
882 struct pll_lims *);
883 extern int nouveau_bios_run_display_table(struct drm_device *,
884 struct dcb_entry *,
885 uint32_t script, int pxclk);
886 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
887 int *length);
888 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
889 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
890 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
891 bool *dl, bool *if_is_24bit);
892 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
893 int head, int pxclk);
894 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
895 enum LVDS_script, int pxclk);
896
897 /* nouveau_ttm.c */
898 int nouveau_ttm_global_init(struct drm_nouveau_private *);
899 void nouveau_ttm_global_release(struct drm_nouveau_private *);
900 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
901
902 /* nouveau_dp.c */
903 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
904 uint8_t *data, int data_nr);
905 bool nouveau_dp_detect(struct drm_encoder *);
906 bool nouveau_dp_link_train(struct drm_encoder *);
907
908 /* nv04_fb.c */
909 extern int nv04_fb_init(struct drm_device *);
910 extern void nv04_fb_takedown(struct drm_device *);
911
912 /* nv10_fb.c */
913 extern int nv10_fb_init(struct drm_device *);
914 extern void nv10_fb_takedown(struct drm_device *);
915 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
916 uint32_t, uint32_t);
917
918 /* nv40_fb.c */
919 extern int nv40_fb_init(struct drm_device *);
920 extern void nv40_fb_takedown(struct drm_device *);
921 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
922 uint32_t, uint32_t);
923
924 /* nv50_fb.c */
925 extern int nv50_fb_init(struct drm_device *);
926 extern void nv50_fb_takedown(struct drm_device *);
927
928 /* nv04_fifo.c */
929 extern int nv04_fifo_init(struct drm_device *);
930 extern void nv04_fifo_disable(struct drm_device *);
931 extern void nv04_fifo_enable(struct drm_device *);
932 extern bool nv04_fifo_reassign(struct drm_device *, bool);
933 extern bool nv04_fifo_cache_flush(struct drm_device *);
934 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
935 extern int nv04_fifo_channel_id(struct drm_device *);
936 extern int nv04_fifo_create_context(struct nouveau_channel *);
937 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
938 extern int nv04_fifo_load_context(struct nouveau_channel *);
939 extern int nv04_fifo_unload_context(struct drm_device *);
940
941 /* nv10_fifo.c */
942 extern int nv10_fifo_init(struct drm_device *);
943 extern int nv10_fifo_channel_id(struct drm_device *);
944 extern int nv10_fifo_create_context(struct nouveau_channel *);
945 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
946 extern int nv10_fifo_load_context(struct nouveau_channel *);
947 extern int nv10_fifo_unload_context(struct drm_device *);
948
949 /* nv40_fifo.c */
950 extern int nv40_fifo_init(struct drm_device *);
951 extern int nv40_fifo_create_context(struct nouveau_channel *);
952 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
953 extern int nv40_fifo_load_context(struct nouveau_channel *);
954 extern int nv40_fifo_unload_context(struct drm_device *);
955
956 /* nv50_fifo.c */
957 extern int nv50_fifo_init(struct drm_device *);
958 extern void nv50_fifo_takedown(struct drm_device *);
959 extern int nv50_fifo_channel_id(struct drm_device *);
960 extern int nv50_fifo_create_context(struct nouveau_channel *);
961 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
962 extern int nv50_fifo_load_context(struct nouveau_channel *);
963 extern int nv50_fifo_unload_context(struct drm_device *);
964
965 /* nv04_graph.c */
966 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
967 extern int nv04_graph_init(struct drm_device *);
968 extern void nv04_graph_takedown(struct drm_device *);
969 extern void nv04_graph_fifo_access(struct drm_device *, bool);
970 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
971 extern int nv04_graph_create_context(struct nouveau_channel *);
972 extern void nv04_graph_destroy_context(struct nouveau_channel *);
973 extern int nv04_graph_load_context(struct nouveau_channel *);
974 extern int nv04_graph_unload_context(struct drm_device *);
975 extern void nv04_graph_context_switch(struct drm_device *);
976
977 /* nv10_graph.c */
978 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
979 extern int nv10_graph_init(struct drm_device *);
980 extern void nv10_graph_takedown(struct drm_device *);
981 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
982 extern int nv10_graph_create_context(struct nouveau_channel *);
983 extern void nv10_graph_destroy_context(struct nouveau_channel *);
984 extern int nv10_graph_load_context(struct nouveau_channel *);
985 extern int nv10_graph_unload_context(struct drm_device *);
986 extern void nv10_graph_context_switch(struct drm_device *);
987 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
988 uint32_t, uint32_t);
989
990 /* nv20_graph.c */
991 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
992 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
993 extern int nv20_graph_create_context(struct nouveau_channel *);
994 extern void nv20_graph_destroy_context(struct nouveau_channel *);
995 extern int nv20_graph_load_context(struct nouveau_channel *);
996 extern int nv20_graph_unload_context(struct drm_device *);
997 extern int nv20_graph_init(struct drm_device *);
998 extern void nv20_graph_takedown(struct drm_device *);
999 extern int nv30_graph_init(struct drm_device *);
1000 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1001 uint32_t, uint32_t);
1002
1003 /* nv40_graph.c */
1004 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1005 extern int nv40_graph_init(struct drm_device *);
1006 extern void nv40_graph_takedown(struct drm_device *);
1007 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1008 extern int nv40_graph_create_context(struct nouveau_channel *);
1009 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1010 extern int nv40_graph_load_context(struct nouveau_channel *);
1011 extern int nv40_graph_unload_context(struct drm_device *);
1012 extern void nv40_grctx_init(struct nouveau_grctx *);
1013 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1014 uint32_t, uint32_t);
1015
1016 /* nv50_graph.c */
1017 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1018 extern int nv50_graph_init(struct drm_device *);
1019 extern void nv50_graph_takedown(struct drm_device *);
1020 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1021 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1022 extern int nv50_graph_create_context(struct nouveau_channel *);
1023 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1024 extern int nv50_graph_load_context(struct nouveau_channel *);
1025 extern int nv50_graph_unload_context(struct drm_device *);
1026 extern void nv50_graph_context_switch(struct drm_device *);
1027 extern int nv50_grctx_init(struct nouveau_grctx *);
1028
1029 /* nouveau_grctx.c */
1030 extern int nouveau_grctx_prog_load(struct drm_device *);
1031 extern void nouveau_grctx_vals_load(struct drm_device *,
1032 struct nouveau_gpuobj *);
1033 extern void nouveau_grctx_fini(struct drm_device *);
1034
1035 /* nv04_instmem.c */
1036 extern int nv04_instmem_init(struct drm_device *);
1037 extern void nv04_instmem_takedown(struct drm_device *);
1038 extern int nv04_instmem_suspend(struct drm_device *);
1039 extern void nv04_instmem_resume(struct drm_device *);
1040 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1041 uint32_t *size);
1042 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1043 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1044 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1045 extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1046 extern void nv04_instmem_finish_access(struct drm_device *);
1047
1048 /* nv50_instmem.c */
1049 extern int nv50_instmem_init(struct drm_device *);
1050 extern void nv50_instmem_takedown(struct drm_device *);
1051 extern int nv50_instmem_suspend(struct drm_device *);
1052 extern void nv50_instmem_resume(struct drm_device *);
1053 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1054 uint32_t *size);
1055 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1056 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1057 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1058 extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1059 extern void nv50_instmem_finish_access(struct drm_device *);
1060
1061 /* nv04_mc.c */
1062 extern int nv04_mc_init(struct drm_device *);
1063 extern void nv04_mc_takedown(struct drm_device *);
1064
1065 /* nv40_mc.c */
1066 extern int nv40_mc_init(struct drm_device *);
1067 extern void nv40_mc_takedown(struct drm_device *);
1068
1069 /* nv50_mc.c */
1070 extern int nv50_mc_init(struct drm_device *);
1071 extern void nv50_mc_takedown(struct drm_device *);
1072
1073 /* nv04_timer.c */
1074 extern int nv04_timer_init(struct drm_device *);
1075 extern uint64_t nv04_timer_read(struct drm_device *);
1076 extern void nv04_timer_takedown(struct drm_device *);
1077
1078 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1079 unsigned long arg);
1080
1081 /* nv04_dac.c */
1082 extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1083 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1084 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1085 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1086
1087 /* nv04_dfp.c */
1088 extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1089 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1090 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1091 int head, bool dl);
1092 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1093 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1094
1095 /* nv04_tv.c */
1096 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1097 extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1098
1099 /* nv17_tv.c */
1100 extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1101
1102 /* nv04_display.c */
1103 extern int nv04_display_create(struct drm_device *);
1104 extern void nv04_display_destroy(struct drm_device *);
1105 extern void nv04_display_restore(struct drm_device *);
1106
1107 /* nv04_crtc.c */
1108 extern int nv04_crtc_create(struct drm_device *, int index);
1109
1110 /* nouveau_bo.c */
1111 extern struct ttm_bo_driver nouveau_bo_driver;
1112 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1113 int size, int align, uint32_t flags,
1114 uint32_t tile_mode, uint32_t tile_flags,
1115 bool no_vm, bool mappable, struct nouveau_bo **);
1116 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1117 extern int nouveau_bo_unpin(struct nouveau_bo *);
1118 extern int nouveau_bo_map(struct nouveau_bo *);
1119 extern void nouveau_bo_unmap(struct nouveau_bo *);
1120 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1121 uint32_t busy);
1122 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1123 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1124 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1125 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1126
1127 /* nouveau_fence.c */
1128 struct nouveau_fence;
1129 extern int nouveau_fence_init(struct nouveau_channel *);
1130 extern void nouveau_fence_fini(struct nouveau_channel *);
1131 extern void nouveau_fence_update(struct nouveau_channel *);
1132 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1133 bool emit);
1134 extern int nouveau_fence_emit(struct nouveau_fence *);
1135 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1136 extern bool nouveau_fence_signalled(void *obj, void *arg);
1137 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1138 extern int nouveau_fence_flush(void *obj, void *arg);
1139 extern void nouveau_fence_unref(void **obj);
1140 extern void *nouveau_fence_ref(void *obj);
1141 extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1142
1143 /* nouveau_gem.c */
1144 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1145 int size, int align, uint32_t flags,
1146 uint32_t tile_mode, uint32_t tile_flags,
1147 bool no_vm, bool mappable, struct nouveau_bo **);
1148 extern int nouveau_gem_object_new(struct drm_gem_object *);
1149 extern void nouveau_gem_object_del(struct drm_gem_object *);
1150 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1151 struct drm_file *);
1152 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1153 struct drm_file *);
1154 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1155 struct drm_file *);
1156 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1157 struct drm_file *);
1158 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1159 struct drm_file *);
1160
1161 /* nv17_gpio.c */
1162 int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1163 int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1164
1165 /* nv50_gpio.c */
1166 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1167 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1168
1169 #ifndef ioread32_native
1170 #ifdef __BIG_ENDIAN
1171 #define ioread16_native ioread16be
1172 #define iowrite16_native iowrite16be
1173 #define ioread32_native ioread32be
1174 #define iowrite32_native iowrite32be
1175 #else /* def __BIG_ENDIAN */
1176 #define ioread16_native ioread16
1177 #define iowrite16_native iowrite16
1178 #define ioread32_native ioread32
1179 #define iowrite32_native iowrite32
1180 #endif /* def __BIG_ENDIAN else */
1181 #endif /* !ioread32_native */
1182
1183 /* channel control reg access */
1184 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1185 {
1186 return ioread32_native(chan->user + reg);
1187 }
1188
1189 static inline void nvchan_wr32(struct nouveau_channel *chan,
1190 unsigned reg, u32 val)
1191 {
1192 iowrite32_native(val, chan->user + reg);
1193 }
1194
1195 /* register access */
1196 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1197 {
1198 struct drm_nouveau_private *dev_priv = dev->dev_private;
1199 return ioread32_native(dev_priv->mmio + reg);
1200 }
1201
1202 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1203 {
1204 struct drm_nouveau_private *dev_priv = dev->dev_private;
1205 iowrite32_native(val, dev_priv->mmio + reg);
1206 }
1207
1208 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1209 {
1210 struct drm_nouveau_private *dev_priv = dev->dev_private;
1211 return ioread8(dev_priv->mmio + reg);
1212 }
1213
1214 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1215 {
1216 struct drm_nouveau_private *dev_priv = dev->dev_private;
1217 iowrite8(val, dev_priv->mmio + reg);
1218 }
1219
1220 #define nv_wait(reg, mask, val) \
1221 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1222
1223 /* PRAMIN access */
1224 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1225 {
1226 struct drm_nouveau_private *dev_priv = dev->dev_private;
1227 return ioread32_native(dev_priv->ramin + offset);
1228 }
1229
1230 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1231 {
1232 struct drm_nouveau_private *dev_priv = dev->dev_private;
1233 iowrite32_native(val, dev_priv->ramin + offset);
1234 }
1235
1236 /* object access */
1237 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1238 unsigned index)
1239 {
1240 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1241 }
1242
1243 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1244 unsigned index, u32 val)
1245 {
1246 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1247 }
1248
1249 /*
1250 * Logging
1251 * Argument d is (struct drm_device *).
1252 */
1253 #define NV_PRINTK(level, d, fmt, arg...) \
1254 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1255 pci_name(d->pdev), ##arg)
1256 #ifndef NV_DEBUG_NOTRACE
1257 #define NV_DEBUG(d, fmt, arg...) do { \
1258 if (drm_debug & DRM_UT_DRIVER) { \
1259 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1260 __LINE__, ##arg); \
1261 } \
1262 } while (0)
1263 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1264 if (drm_debug & DRM_UT_KMS) { \
1265 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1266 __LINE__, ##arg); \
1267 } \
1268 } while (0)
1269 #else
1270 #define NV_DEBUG(d, fmt, arg...) do { \
1271 if (drm_debug & DRM_UT_DRIVER) \
1272 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1273 } while (0)
1274 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1275 if (drm_debug & DRM_UT_KMS) \
1276 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1277 } while (0)
1278 #endif
1279 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1280 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1281 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1282 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1283 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1284
1285 /* nouveau_reg_debug bitmask */
1286 enum {
1287 NOUVEAU_REG_DEBUG_MC = 0x1,
1288 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1289 NOUVEAU_REG_DEBUG_FB = 0x4,
1290 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1291 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1292 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1293 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1294 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1295 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1296 NOUVEAU_REG_DEBUG_EVO = 0x200,
1297 };
1298
1299 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1300 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1301 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1302 } while (0)
1303
1304 static inline bool
1305 nv_two_heads(struct drm_device *dev)
1306 {
1307 struct drm_nouveau_private *dev_priv = dev->dev_private;
1308 const int impl = dev->pci_device & 0x0ff0;
1309
1310 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1311 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1312 return true;
1313
1314 return false;
1315 }
1316
1317 static inline bool
1318 nv_gf4_disp_arch(struct drm_device *dev)
1319 {
1320 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1321 }
1322
1323 static inline bool
1324 nv_two_reg_pll(struct drm_device *dev)
1325 {
1326 struct drm_nouveau_private *dev_priv = dev->dev_private;
1327 const int impl = dev->pci_device & 0x0ff0;
1328
1329 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1330 return true;
1331 return false;
1332 }
1333
1334 #define NV_SW 0x0000506e
1335 #define NV_SW_DMA_SEMAPHORE 0x00000060
1336 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1337 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1338 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1339 #define NV_SW_DMA_VBLSEM 0x0000018c
1340 #define NV_SW_VBLSEM_OFFSET 0x00000400
1341 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1342 #define NV_SW_VBLSEM_RELEASE 0x00000408
1343
1344 #endif /* __NOUVEAU_DRV_H__ */
WandBoard kernel