2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
30 /* these defines are made up */
31 #define NV_CIO_CRE_44_HEADA 0x0
32 #define NV_CIO_CRE_44_HEADB 0x3
33 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
34 #define LEGACY_I2C_CRT 0x80
35 #define LEGACY_I2C_PANEL 0x81
36 #define LEGACY_I2C_TV 0x82
40 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
41 #define LOG_OLD_VALUE(x)
43 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
44 #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
51 static bool nv_cksum(const uint8_t *data
, unsigned int length
)
54 * There's a few checksums in the BIOS, so here's a generic checking
60 for (i
= 0; i
< length
; i
++)
70 score_vbios(struct drm_device
*dev
, const uint8_t *data
, const bool writeable
)
72 if (!(data
[0] == 0x55 && data
[1] == 0xAA)) {
73 NV_TRACEWARN(dev
, "... BIOS signature not found\n");
77 if (nv_cksum(data
, data
[2] * 512)) {
78 NV_TRACEWARN(dev
, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable
? 2 : 1;
82 NV_TRACE(dev
, "... appears to be valid\n");
87 static void load_vbios_prom(struct drm_device
*dev
, uint8_t *data
)
89 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
90 uint32_t pci_nv_20
, save_pci_nv_20
;
94 if (dev_priv
->card_type
>= NV_50
)
97 pci_nv_20
= NV_PBUS_PCI_NV_20
;
99 /* enable ROM access */
100 save_pci_nv_20
= nvReadMC(dev
, pci_nv_20
);
101 nvWriteMC(dev
, pci_nv_20
,
102 save_pci_nv_20
& ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
);
104 /* bail if no rom signature */
105 if (nv_rd08(dev
, NV_PROM_OFFSET
) != 0x55 ||
106 nv_rd08(dev
, NV_PROM_OFFSET
+ 1) != 0xaa)
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr
= nv_rd08(dev
, NV_PROM_OFFSET
+ 0x18) |
111 nv_rd08(dev
, NV_PROM_OFFSET
+ 0x19) << 8;
112 if (nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
) != 'P' ||
113 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 1) != 'C' ||
114 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 2) != 'I' ||
115 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 3) != 'R')
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
122 for (i
= 0; i
< NV_PROM_SIZE
; i
++)
123 data
[i
] = nv_rd08(dev
, NV_PROM_OFFSET
+ i
);
126 /* disable ROM access */
127 nvWriteMC(dev
, pci_nv_20
,
128 save_pci_nv_20
| NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
);
131 static void load_vbios_pramin(struct drm_device
*dev
, uint8_t *data
)
133 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
134 uint32_t old_bar0_pramin
= 0;
137 if (dev_priv
->card_type
>= NV_50
) {
138 uint32_t vbios_vram
= (nv_rd32(dev
, 0x619f04) & ~0xff) << 8;
141 vbios_vram
= (nv_rd32(dev
, 0x1700) << 16) + 0xf0000;
143 old_bar0_pramin
= nv_rd32(dev
, 0x1700);
144 nv_wr32(dev
, 0x1700, vbios_vram
>> 16);
147 /* bail if no rom signature */
148 if (nv_rd08(dev
, NV_PRAMIN_OFFSET
) != 0x55 ||
149 nv_rd08(dev
, NV_PRAMIN_OFFSET
+ 1) != 0xaa)
152 for (i
= 0; i
< NV_PROM_SIZE
; i
++)
153 data
[i
] = nv_rd08(dev
, NV_PRAMIN_OFFSET
+ i
);
156 if (dev_priv
->card_type
>= NV_50
)
157 nv_wr32(dev
, 0x1700, old_bar0_pramin
);
160 static void load_vbios_pci(struct drm_device
*dev
, uint8_t *data
)
162 void __iomem
*rom
= NULL
;
166 ret
= pci_enable_rom(dev
->pdev
);
170 rom
= pci_map_rom(dev
->pdev
, &rom_len
);
173 memcpy_fromio(data
, rom
, rom_len
);
174 pci_unmap_rom(dev
->pdev
, rom
);
177 pci_disable_rom(dev
->pdev
);
182 void (*loadbios
)(struct drm_device
*, uint8_t *);
186 static struct methods nv04_methods
[] = {
187 { "PROM", load_vbios_prom
, false },
188 { "PRAMIN", load_vbios_pramin
, true },
189 { "PCIROM", load_vbios_pci
, true },
192 static struct methods nv50_methods
[] = {
193 { "PRAMIN", load_vbios_pramin
, true },
194 { "PROM", load_vbios_prom
, false },
195 { "PCIROM", load_vbios_pci
, true },
200 static bool NVShadowVBIOS(struct drm_device
*dev
, uint8_t *data
)
202 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
203 struct methods
*methods
;
206 int scores
[METHODCNT
];
209 methods
= nv04_methods
;
210 for (i
= 0; i
< METHODCNT
; i
++)
211 if (!strcasecmp(nouveau_vbios
, methods
[i
].desc
))
215 NV_INFO(dev
, "Attempting to use BIOS image from %s\n",
218 methods
[i
].loadbios(dev
, data
);
219 if (score_vbios(dev
, data
, methods
[i
].rw
))
223 NV_ERROR(dev
, "VBIOS source \'%s\' invalid\n", nouveau_vbios
);
226 if (dev_priv
->card_type
< NV_50
)
227 methods
= nv04_methods
;
229 methods
= nv50_methods
;
231 for (i
= 0; i
< METHODCNT
; i
++) {
232 NV_TRACE(dev
, "Attempting to load BIOS image from %s\n",
234 data
[0] = data
[1] = 0; /* avoid reuse of previous image */
235 methods
[i
].loadbios(dev
, data
);
236 scores
[i
] = score_vbios(dev
, data
, methods
[i
].rw
);
237 if (scores
[i
] == testscore
)
241 while (--testscore
> 0) {
242 for (i
= 0; i
< METHODCNT
; i
++) {
243 if (scores
[i
] == testscore
) {
244 NV_TRACE(dev
, "Using BIOS image from %s\n",
246 methods
[i
].loadbios(dev
, data
);
252 NV_ERROR(dev
, "No valid BIOS image found\n");
256 struct init_tbl_entry
{
259 int (*handler
)(struct nvbios
*, uint16_t, struct init_exec
*);
268 static int parse_init_table(struct nvbios
*, unsigned int, struct init_exec
*);
270 #define MACRO_INDEX_SIZE 2
272 #define CONDITION_SIZE 12
273 #define IO_FLAG_CONDITION_SIZE 9
274 #define IO_CONDITION_SIZE 5
275 #define MEM_INIT_SIZE 66
277 static void still_alive(void)
286 munge_reg(struct nvbios
*bios
, uint32_t reg
)
288 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
289 struct dcb_entry
*dcbent
= bios
->display
.output
;
291 if (dev_priv
->card_type
< NV_50
)
294 if (reg
& 0x40000000) {
297 reg
+= (ffs(dcbent
->or) - 1) * 0x800;
298 if ((reg
& 0x20000000) && !(dcbent
->sorconf
.link
& 1))
307 valid_reg(struct nvbios
*bios
, uint32_t reg
)
309 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
310 struct drm_device
*dev
= bios
->dev
;
312 /* C51 has misaligned regs on purpose. Marvellous */
314 (reg
& 0x1 && dev_priv
->vbios
.chip_version
!= 0x51))
315 NV_ERROR(dev
, "======= misaligned reg 0x%08X =======\n", reg
);
317 /* warn on C51 regs that haven't been verified accessible in tracing */
318 if (reg
& 0x1 && dev_priv
->vbios
.chip_version
== 0x51 &&
319 reg
!= 0x130d && reg
!= 0x1311 && reg
!= 0x60081d)
320 NV_WARN(dev
, "=== C51 misaligned reg 0x%08X not verified ===\n",
323 if (reg
>= (8*1024*1024)) {
324 NV_ERROR(dev
, "=== reg 0x%08x out of mapped bounds ===\n", reg
);
332 valid_idx_port(struct nvbios
*bios
, uint16_t port
)
334 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
335 struct drm_device
*dev
= bios
->dev
;
338 * If adding more ports here, the read/write functions below will need
339 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
340 * used for the port in question
342 if (dev_priv
->card_type
< NV_50
) {
343 if (port
== NV_CIO_CRX__COLOR
)
345 if (port
== NV_VIO_SRX
)
348 if (port
== NV_CIO_CRX__COLOR
)
352 NV_ERROR(dev
, "========== unknown indexed io port 0x%04X ==========\n",
359 valid_port(struct nvbios
*bios
, uint16_t port
)
361 struct drm_device
*dev
= bios
->dev
;
364 * If adding more ports here, the read/write functions below will need
365 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
366 * used for the port in question
368 if (port
== NV_VIO_VSE2
)
371 NV_ERROR(dev
, "========== unknown io port 0x%04X ==========\n", port
);
377 bios_rd32(struct nvbios
*bios
, uint32_t reg
)
381 reg
= munge_reg(bios
, reg
);
382 if (!valid_reg(bios
, reg
))
386 * C51 sometimes uses regs with bit0 set in the address. For these
387 * cases there should exist a translation in a BIOS table to an IO
388 * port address which the BIOS uses for accessing the reg
390 * These only seem to appear for the power control regs to a flat panel,
391 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
392 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
393 * suspend-resume mmio trace from a C51 will be required to see if this
394 * is true for the power microcode in 0x14.., or whether the direct IO
395 * port access method is needed
400 data
= nv_rd32(bios
->dev
, reg
);
402 BIOSLOG(bios
, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg
, data
);
408 bios_wr32(struct nvbios
*bios
, uint32_t reg
, uint32_t data
)
410 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
412 reg
= munge_reg(bios
, reg
);
413 if (!valid_reg(bios
, reg
))
416 /* see note in bios_rd32 */
420 LOG_OLD_VALUE(bios_rd32(bios
, reg
));
421 BIOSLOG(bios
, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg
, data
);
423 if (dev_priv
->vbios
.execute
) {
425 nv_wr32(bios
->dev
, reg
, data
);
430 bios_idxprt_rd(struct nvbios
*bios
, uint16_t port
, uint8_t index
)
432 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
433 struct drm_device
*dev
= bios
->dev
;
436 if (!valid_idx_port(bios
, port
))
439 if (dev_priv
->card_type
< NV_50
) {
440 if (port
== NV_VIO_SRX
)
441 data
= NVReadVgaSeq(dev
, bios
->state
.crtchead
, index
);
442 else /* assume NV_CIO_CRX__COLOR */
443 data
= NVReadVgaCrtc(dev
, bios
->state
.crtchead
, index
);
447 data32
= bios_rd32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3));
448 data
= (data32
>> ((index
& 3) << 3)) & 0xff;
451 BIOSLOG(bios
, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
452 "Head: 0x%02X, Data: 0x%02X\n",
453 port
, index
, bios
->state
.crtchead
, data
);
458 bios_idxprt_wr(struct nvbios
*bios
, uint16_t port
, uint8_t index
, uint8_t data
)
460 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
461 struct drm_device
*dev
= bios
->dev
;
463 if (!valid_idx_port(bios
, port
))
467 * The current head is maintained in the nvbios member state.crtchead.
468 * We trap changes to CR44 and update the head variable and hence the
469 * register set written.
470 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
471 * of the write, and to head1 after the write
473 if (port
== NV_CIO_CRX__COLOR
&& index
== NV_CIO_CRE_44
&&
474 data
!= NV_CIO_CRE_44_HEADB
)
475 bios
->state
.crtchead
= 0;
477 LOG_OLD_VALUE(bios_idxprt_rd(bios
, port
, index
));
478 BIOSLOG(bios
, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
479 "Head: 0x%02X, Data: 0x%02X\n",
480 port
, index
, bios
->state
.crtchead
, data
);
482 if (bios
->execute
&& dev_priv
->card_type
< NV_50
) {
484 if (port
== NV_VIO_SRX
)
485 NVWriteVgaSeq(dev
, bios
->state
.crtchead
, index
, data
);
486 else /* assume NV_CIO_CRX__COLOR */
487 NVWriteVgaCrtc(dev
, bios
->state
.crtchead
, index
, data
);
490 uint32_t data32
, shift
= (index
& 3) << 3;
494 data32
= bios_rd32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3));
495 data32
&= ~(0xff << shift
);
496 data32
|= (data
<< shift
);
497 bios_wr32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3), data32
);
500 if (port
== NV_CIO_CRX__COLOR
&&
501 index
== NV_CIO_CRE_44
&& data
== NV_CIO_CRE_44_HEADB
)
502 bios
->state
.crtchead
= 1;
506 bios_port_rd(struct nvbios
*bios
, uint16_t port
)
508 uint8_t data
, head
= bios
->state
.crtchead
;
510 if (!valid_port(bios
, port
))
513 data
= NVReadPRMVIO(bios
->dev
, head
, NV_PRMVIO0_OFFSET
+ port
);
515 BIOSLOG(bios
, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
522 bios_port_wr(struct nvbios
*bios
, uint16_t port
, uint8_t data
)
524 int head
= bios
->state
.crtchead
;
526 if (!valid_port(bios
, port
))
529 LOG_OLD_VALUE(bios_port_rd(bios
, port
));
530 BIOSLOG(bios
, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
537 NVWritePRMVIO(bios
->dev
, head
, NV_PRMVIO0_OFFSET
+ port
, data
);
541 io_flag_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
544 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
545 * for the CRTC index; 1 byte for the mask to apply to the value
546 * retrieved from the CRTC; 1 byte for the shift right to apply to the
547 * masked CRTC value; 2 bytes for the offset to the flag array, to
548 * which the shifted value is added; 1 byte for the mask applied to the
549 * value read from the flag array; and 1 byte for the value to compare
550 * against the masked byte from the flag table.
553 uint16_t condptr
= bios
->io_flag_condition_tbl_ptr
+ cond
* IO_FLAG_CONDITION_SIZE
;
554 uint16_t crtcport
= ROM16(bios
->data
[condptr
]);
555 uint8_t crtcindex
= bios
->data
[condptr
+ 2];
556 uint8_t mask
= bios
->data
[condptr
+ 3];
557 uint8_t shift
= bios
->data
[condptr
+ 4];
558 uint16_t flagarray
= ROM16(bios
->data
[condptr
+ 5]);
559 uint8_t flagarraymask
= bios
->data
[condptr
+ 7];
560 uint8_t cmpval
= bios
->data
[condptr
+ 8];
563 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
564 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
566 offset
, crtcport
, crtcindex
, mask
, shift
, flagarray
, flagarraymask
, cmpval
);
568 data
= bios_idxprt_rd(bios
, crtcport
, crtcindex
);
570 data
= bios
->data
[flagarray
+ ((data
& mask
) >> shift
)];
571 data
&= flagarraymask
;
573 BIOSLOG(bios
, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
574 offset
, data
, cmpval
);
576 return (data
== cmpval
);
580 bios_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
583 * The condition table entry has 4 bytes for the address of the
584 * register to check, 4 bytes for a mask to apply to the register and
585 * 4 for a test comparison value
588 uint16_t condptr
= bios
->condition_tbl_ptr
+ cond
* CONDITION_SIZE
;
589 uint32_t reg
= ROM32(bios
->data
[condptr
]);
590 uint32_t mask
= ROM32(bios
->data
[condptr
+ 4]);
591 uint32_t cmpval
= ROM32(bios
->data
[condptr
+ 8]);
594 BIOSLOG(bios
, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
595 offset
, cond
, reg
, mask
);
597 data
= bios_rd32(bios
, reg
) & mask
;
599 BIOSLOG(bios
, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
600 offset
, data
, cmpval
);
602 return (data
== cmpval
);
606 io_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
609 * The IO condition entry has 2 bytes for the IO port address; 1 byte
610 * for the index to write to io_port; 1 byte for the mask to apply to
611 * the byte read from io_port+1; and 1 byte for the value to compare
612 * against the masked byte.
615 uint16_t condptr
= bios
->io_condition_tbl_ptr
+ cond
* IO_CONDITION_SIZE
;
616 uint16_t io_port
= ROM16(bios
->data
[condptr
]);
617 uint8_t port_index
= bios
->data
[condptr
+ 2];
618 uint8_t mask
= bios
->data
[condptr
+ 3];
619 uint8_t cmpval
= bios
->data
[condptr
+ 4];
621 uint8_t data
= bios_idxprt_rd(bios
, io_port
, port_index
) & mask
;
623 BIOSLOG(bios
, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
624 offset
, data
, cmpval
);
626 return (data
== cmpval
);
630 nv50_pll_set(struct drm_device
*dev
, uint32_t reg
, uint32_t clk
)
632 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
633 uint32_t reg0
= nv_rd32(dev
, reg
+ 0);
634 uint32_t reg1
= nv_rd32(dev
, reg
+ 4);
635 struct nouveau_pll_vals pll
;
636 struct pll_lims pll_limits
;
639 ret
= get_pll_limits(dev
, reg
, &pll_limits
);
643 clk
= nouveau_calc_pll_mnp(dev
, &pll_limits
, clk
, &pll
);
647 reg0
= (reg0
& 0xfff8ffff) | (pll
.log2P
<< 16);
648 reg1
= (reg1
& 0xffff0000) | (pll
.N1
<< 8) | pll
.M1
;
650 if (dev_priv
->vbios
.execute
) {
652 nv_wr32(dev
, reg
+ 4, reg1
);
653 nv_wr32(dev
, reg
+ 0, reg0
);
660 setPLL(struct nvbios
*bios
, uint32_t reg
, uint32_t clk
)
662 struct drm_device
*dev
= bios
->dev
;
663 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
665 struct pll_lims pll_lim
;
666 struct nouveau_pll_vals pllvals
;
669 if (dev_priv
->card_type
>= NV_50
)
670 return nv50_pll_set(dev
, reg
, clk
);
672 /* high regs (such as in the mac g5 table) are not -= 4 */
673 ret
= get_pll_limits(dev
, reg
> 0x405c ? reg
: reg
- 4, &pll_lim
);
677 clk
= nouveau_calc_pll_mnp(dev
, &pll_lim
, clk
, &pllvals
);
683 nouveau_hw_setpll(dev
, reg
, &pllvals
);
689 static int dcb_entry_idx_from_crtchead(struct drm_device
*dev
)
691 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
692 struct nvbios
*bios
= &dev_priv
->vbios
;
695 * For the results of this function to be correct, CR44 must have been
696 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
697 * and the DCB table parsed, before the script calling the function is
698 * run. run_digital_op_script is example of how to do such setup
701 uint8_t dcb_entry
= NVReadVgaCrtc5758(dev
, bios
->state
.crtchead
, 0);
703 if (dcb_entry
> bios
->dcb
.entries
) {
704 NV_ERROR(dev
, "CR58 doesn't have a valid DCB entry currently "
705 "(%02X)\n", dcb_entry
);
706 dcb_entry
= 0x7f; /* unused / invalid marker */
712 static struct nouveau_i2c_chan
*
713 init_i2c_device_find(struct drm_device
*dev
, int i2c_index
)
715 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
716 struct dcb_table
*dcb
= &dev_priv
->vbios
.dcb
;
718 if (i2c_index
== 0xff) {
719 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
720 int idx
= dcb_entry_idx_from_crtchead(dev
), shift
= 0;
721 int default_indices
= dcb
->i2c_default_indices
;
723 if (idx
!= 0x7f && dcb
->entry
[idx
].i2c_upper_default
)
726 i2c_index
= (default_indices
>> shift
) & 0xf;
728 if (i2c_index
== 0x80) /* g80+ */
729 i2c_index
= dcb
->i2c_default_indices
& 0xf;
731 return nouveau_i2c_find(dev
, i2c_index
);
735 get_tmds_index_reg(struct drm_device
*dev
, uint8_t mlv
)
738 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
739 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
740 * CR58 for CR57 = 0 to index a table of offsets to the basic
742 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
743 * CR58 for CR57 = 0 to index a table of offsets to the basic
744 * 0x6808b0 address, and then flip the offset by 8.
747 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
748 struct nvbios
*bios
= &dev_priv
->vbios
;
749 const int pramdac_offset
[13] = {
750 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
751 const uint32_t pramdac_table
[4] = {
752 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
755 int dcb_entry
, dacoffset
;
757 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
758 dcb_entry
= dcb_entry_idx_from_crtchead(dev
);
759 if (dcb_entry
== 0x7f)
761 dacoffset
= pramdac_offset
[bios
->dcb
.entry
[dcb_entry
].or];
764 return 0x6808b0 + dacoffset
;
766 if (mlv
>= ARRAY_SIZE(pramdac_table
)) {
767 NV_ERROR(dev
, "Magic Lookup Value too big (%02X)\n",
771 return pramdac_table
[mlv
];
776 init_io_restrict_prog(struct nvbios
*bios
, uint16_t offset
,
777 struct init_exec
*iexec
)
780 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
782 * offset (8 bit): opcode
783 * offset + 1 (16 bit): CRTC port
784 * offset + 3 (8 bit): CRTC index
785 * offset + 4 (8 bit): mask
786 * offset + 5 (8 bit): shift
787 * offset + 6 (8 bit): count
788 * offset + 7 (32 bit): register
789 * offset + 11 (32 bit): configuration 1
792 * Starting at offset + 11 there are "count" 32 bit values.
793 * To find out which value to use read index "CRTC index" on "CRTC
794 * port", AND this value with "mask" and then bit shift right "shift"
795 * bits. Read the appropriate value using this index and write to
799 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
800 uint8_t crtcindex
= bios
->data
[offset
+ 3];
801 uint8_t mask
= bios
->data
[offset
+ 4];
802 uint8_t shift
= bios
->data
[offset
+ 5];
803 uint8_t count
= bios
->data
[offset
+ 6];
804 uint32_t reg
= ROM32(bios
->data
[offset
+ 7]);
807 int len
= 11 + count
* 4;
812 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
813 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
814 offset
, crtcport
, crtcindex
, mask
, shift
, count
, reg
);
816 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
817 if (config
> count
) {
819 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
820 offset
, config
, count
);
824 configval
= ROM32(bios
->data
[offset
+ 11 + config
* 4]);
826 BIOSLOG(bios
, "0x%04X: Writing config %02X\n", offset
, config
);
828 bios_wr32(bios
, reg
, configval
);
834 init_repeat(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
837 * INIT_REPEAT opcode: 0x33 ('3')
839 * offset (8 bit): opcode
840 * offset + 1 (8 bit): count
842 * Execute script following this opcode up to INIT_REPEAT_END
846 uint8_t count
= bios
->data
[offset
+ 1];
849 /* no iexec->execute check by design */
851 BIOSLOG(bios
, "0x%04X: Repeating following segment %d times\n",
854 iexec
->repeat
= true;
857 * count - 1, as the script block will execute once when we leave this
858 * opcode -- this is compatible with bios behaviour as:
859 * a) the block is always executed at least once, even if count == 0
860 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
863 for (i
= 0; i
< count
- 1; i
++)
864 parse_init_table(bios
, offset
+ 2, iexec
);
866 iexec
->repeat
= false;
872 init_io_restrict_pll(struct nvbios
*bios
, uint16_t offset
,
873 struct init_exec
*iexec
)
876 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
878 * offset (8 bit): opcode
879 * offset + 1 (16 bit): CRTC port
880 * offset + 3 (8 bit): CRTC index
881 * offset + 4 (8 bit): mask
882 * offset + 5 (8 bit): shift
883 * offset + 6 (8 bit): IO flag condition index
884 * offset + 7 (8 bit): count
885 * offset + 8 (32 bit): register
886 * offset + 12 (16 bit): frequency 1
889 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
890 * Set PLL register "register" to coefficients for frequency n,
891 * selected by reading index "CRTC index" of "CRTC port" ANDed with
892 * "mask" and shifted right by "shift".
894 * If "IO flag condition index" > 0, and condition met, double
895 * frequency before setting it.
898 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
899 uint8_t crtcindex
= bios
->data
[offset
+ 3];
900 uint8_t mask
= bios
->data
[offset
+ 4];
901 uint8_t shift
= bios
->data
[offset
+ 5];
902 int8_t io_flag_condition_idx
= bios
->data
[offset
+ 6];
903 uint8_t count
= bios
->data
[offset
+ 7];
904 uint32_t reg
= ROM32(bios
->data
[offset
+ 8]);
907 int len
= 12 + count
* 2;
912 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
913 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
914 "Count: 0x%02X, Reg: 0x%08X\n",
915 offset
, crtcport
, crtcindex
, mask
, shift
,
916 io_flag_condition_idx
, count
, reg
);
918 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
919 if (config
> count
) {
921 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
922 offset
, config
, count
);
926 freq
= ROM16(bios
->data
[offset
+ 12 + config
* 2]);
928 if (io_flag_condition_idx
> 0) {
929 if (io_flag_condition_met(bios
, offset
, io_flag_condition_idx
)) {
930 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- "
931 "frequency doubled\n", offset
);
934 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- "
935 "frequency unchanged\n", offset
);
938 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
939 offset
, reg
, config
, freq
);
941 setPLL(bios
, reg
, freq
* 10);
947 init_end_repeat(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
950 * INIT_END_REPEAT opcode: 0x36 ('6')
952 * offset (8 bit): opcode
954 * Marks the end of the block for INIT_REPEAT to repeat
957 /* no iexec->execute check by design */
960 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
961 * we're not in repeat mode
970 init_copy(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
973 * INIT_COPY opcode: 0x37 ('7')
975 * offset (8 bit): opcode
976 * offset + 1 (32 bit): register
977 * offset + 5 (8 bit): shift
978 * offset + 6 (8 bit): srcmask
979 * offset + 7 (16 bit): CRTC port
980 * offset + 9 (8 bit): CRTC index
981 * offset + 10 (8 bit): mask
983 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
984 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
988 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
989 uint8_t shift
= bios
->data
[offset
+ 5];
990 uint8_t srcmask
= bios
->data
[offset
+ 6];
991 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 7]);
992 uint8_t crtcindex
= bios
->data
[offset
+ 9];
993 uint8_t mask
= bios
->data
[offset
+ 10];
1000 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1001 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1002 offset
, reg
, shift
, srcmask
, crtcport
, crtcindex
, mask
);
1004 data
= bios_rd32(bios
, reg
);
1009 data
<<= (0x100 - shift
);
1013 crtcdata
= bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
;
1014 crtcdata
|= (uint8_t)data
;
1015 bios_idxprt_wr(bios
, crtcport
, crtcindex
, crtcdata
);
1021 init_not(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1024 * INIT_NOT opcode: 0x38 ('8')
1026 * offset (8 bit): opcode
1028 * Invert the current execute / no-execute condition (i.e. "else")
1031 BIOSLOG(bios
, "0x%04X: ------ Skipping following commands ------\n", offset
);
1033 BIOSLOG(bios
, "0x%04X: ------ Executing following commands ------\n", offset
);
1035 iexec
->execute
= !iexec
->execute
;
1040 init_io_flag_condition(struct nvbios
*bios
, uint16_t offset
,
1041 struct init_exec
*iexec
)
1044 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1046 * offset (8 bit): opcode
1047 * offset + 1 (8 bit): condition number
1049 * Check condition "condition number" in the IO flag condition table.
1050 * If condition not met skip subsequent opcodes until condition is
1051 * inverted (INIT_NOT), or we hit INIT_RESUME
1054 uint8_t cond
= bios
->data
[offset
+ 1];
1056 if (!iexec
->execute
)
1059 if (io_flag_condition_met(bios
, offset
, cond
))
1060 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
1062 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
1063 iexec
->execute
= false;
1070 init_idx_addr_latched(struct nvbios
*bios
, uint16_t offset
,
1071 struct init_exec
*iexec
)
1074 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1076 * offset (8 bit): opcode
1077 * offset + 1 (32 bit): control register
1078 * offset + 5 (32 bit): data register
1079 * offset + 9 (32 bit): mask
1080 * offset + 13 (32 bit): data
1081 * offset + 17 (8 bit): count
1082 * offset + 18 (8 bit): address 1
1083 * offset + 19 (8 bit): data 1
1086 * For each of "count" address and data pairs, write "data n" to
1087 * "data register", read the current value of "control register",
1088 * and write it back once ANDed with "mask", ORed with "data",
1089 * and ORed with "address n"
1092 uint32_t controlreg
= ROM32(bios
->data
[offset
+ 1]);
1093 uint32_t datareg
= ROM32(bios
->data
[offset
+ 5]);
1094 uint32_t mask
= ROM32(bios
->data
[offset
+ 9]);
1095 uint32_t data
= ROM32(bios
->data
[offset
+ 13]);
1096 uint8_t count
= bios
->data
[offset
+ 17];
1097 int len
= 18 + count
* 2;
1101 if (!iexec
->execute
)
1104 BIOSLOG(bios
, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1105 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1106 offset
, controlreg
, datareg
, mask
, data
, count
);
1108 for (i
= 0; i
< count
; i
++) {
1109 uint8_t instaddress
= bios
->data
[offset
+ 18 + i
* 2];
1110 uint8_t instdata
= bios
->data
[offset
+ 19 + i
* 2];
1112 BIOSLOG(bios
, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1113 offset
, instaddress
, instdata
);
1115 bios_wr32(bios
, datareg
, instdata
);
1116 value
= bios_rd32(bios
, controlreg
) & mask
;
1118 value
|= instaddress
;
1119 bios_wr32(bios
, controlreg
, value
);
1126 init_io_restrict_pll2(struct nvbios
*bios
, uint16_t offset
,
1127 struct init_exec
*iexec
)
1130 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1132 * offset (8 bit): opcode
1133 * offset + 1 (16 bit): CRTC port
1134 * offset + 3 (8 bit): CRTC index
1135 * offset + 4 (8 bit): mask
1136 * offset + 5 (8 bit): shift
1137 * offset + 6 (8 bit): count
1138 * offset + 7 (32 bit): register
1139 * offset + 11 (32 bit): frequency 1
1142 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1143 * Set PLL register "register" to coefficients for frequency n,
1144 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1145 * "mask" and shifted right by "shift".
1148 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
1149 uint8_t crtcindex
= bios
->data
[offset
+ 3];
1150 uint8_t mask
= bios
->data
[offset
+ 4];
1151 uint8_t shift
= bios
->data
[offset
+ 5];
1152 uint8_t count
= bios
->data
[offset
+ 6];
1153 uint32_t reg
= ROM32(bios
->data
[offset
+ 7]);
1154 int len
= 11 + count
* 4;
1158 if (!iexec
->execute
)
1161 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1162 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1163 offset
, crtcport
, crtcindex
, mask
, shift
, count
, reg
);
1168 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
1169 if (config
> count
) {
1171 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1172 offset
, config
, count
);
1176 freq
= ROM32(bios
->data
[offset
+ 11 + config
* 4]);
1178 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1179 offset
, reg
, config
, freq
);
1181 setPLL(bios
, reg
, freq
);
1187 init_pll2(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1190 * INIT_PLL2 opcode: 0x4B ('K')
1192 * offset (8 bit): opcode
1193 * offset + 1 (32 bit): register
1194 * offset + 5 (32 bit): freq
1196 * Set PLL register "register" to coefficients for frequency "freq"
1199 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
1200 uint32_t freq
= ROM32(bios
->data
[offset
+ 5]);
1202 if (!iexec
->execute
)
1205 BIOSLOG(bios
, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1208 setPLL(bios
, reg
, freq
);
1213 init_i2c_byte(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1216 * INIT_I2C_BYTE opcode: 0x4C ('L')
1218 * offset (8 bit): opcode
1219 * offset + 1 (8 bit): DCB I2C table entry index
1220 * offset + 2 (8 bit): I2C slave address
1221 * offset + 3 (8 bit): count
1222 * offset + 4 (8 bit): I2C register 1
1223 * offset + 5 (8 bit): mask 1
1224 * offset + 6 (8 bit): data 1
1227 * For each of "count" registers given by "I2C register n" on the device
1228 * addressed by "I2C slave address" on the I2C bus given by
1229 * "DCB I2C table entry index", read the register, AND the result with
1230 * "mask n" and OR it with "data n" before writing it back to the device
1233 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1234 uint8_t i2c_address
= bios
->data
[offset
+ 2];
1235 uint8_t count
= bios
->data
[offset
+ 3];
1236 int len
= 4 + count
* 3;
1237 struct nouveau_i2c_chan
*chan
;
1241 if (!iexec
->execute
)
1244 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1246 offset
, i2c_index
, i2c_address
, count
);
1248 chan
= init_i2c_device_find(bios
->dev
, i2c_index
);
1252 for (i
= 0; i
< count
; i
++) {
1253 uint8_t i2c_reg
= bios
->data
[offset
+ 4 + i
* 3];
1254 uint8_t mask
= bios
->data
[offset
+ 5 + i
* 3];
1255 uint8_t data
= bios
->data
[offset
+ 6 + i
* 3];
1258 msg
.addr
= i2c_address
;
1259 msg
.flags
= I2C_M_RD
;
1262 if (i2c_transfer(&chan
->adapter
, &msg
, 1) != 1)
1265 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1266 "Mask: 0x%02X, Data: 0x%02X\n",
1267 offset
, i2c_reg
, value
, mask
, data
);
1269 value
= (value
& mask
) | data
;
1271 if (bios
->execute
) {
1272 msg
.addr
= i2c_address
;
1276 if (i2c_transfer(&chan
->adapter
, &msg
, 1) != 1)
1285 init_zm_i2c_byte(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1288 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1290 * offset (8 bit): opcode
1291 * offset + 1 (8 bit): DCB I2C table entry index
1292 * offset + 2 (8 bit): I2C slave address
1293 * offset + 3 (8 bit): count
1294 * offset + 4 (8 bit): I2C register 1
1295 * offset + 5 (8 bit): data 1
1298 * For each of "count" registers given by "I2C register n" on the device
1299 * addressed by "I2C slave address" on the I2C bus given by
1300 * "DCB I2C table entry index", set the register to "data n"
1303 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1304 uint8_t i2c_address
= bios
->data
[offset
+ 2];
1305 uint8_t count
= bios
->data
[offset
+ 3];
1306 int len
= 4 + count
* 2;
1307 struct nouveau_i2c_chan
*chan
;
1311 if (!iexec
->execute
)
1314 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1316 offset
, i2c_index
, i2c_address
, count
);
1318 chan
= init_i2c_device_find(bios
->dev
, i2c_index
);
1322 for (i
= 0; i
< count
; i
++) {
1323 uint8_t i2c_reg
= bios
->data
[offset
+ 4 + i
* 2];
1324 uint8_t data
= bios
->data
[offset
+ 5 + i
* 2];
1326 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1327 offset
, i2c_reg
, data
);
1329 if (bios
->execute
) {
1330 msg
.addr
= i2c_address
;
1334 if (i2c_transfer(&chan
->adapter
, &msg
, 1) != 1)
1343 init_zm_i2c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1346 * INIT_ZM_I2C opcode: 0x4E ('N')
1348 * offset (8 bit): opcode
1349 * offset + 1 (8 bit): DCB I2C table entry index
1350 * offset + 2 (8 bit): I2C slave address
1351 * offset + 3 (8 bit): count
1352 * offset + 4 (8 bit): data 1
1355 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1356 * address" on the I2C bus given by "DCB I2C table entry index"
1359 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1360 uint8_t i2c_address
= bios
->data
[offset
+ 2];
1361 uint8_t count
= bios
->data
[offset
+ 3];
1362 int len
= 4 + count
;
1363 struct nouveau_i2c_chan
*chan
;
1368 if (!iexec
->execute
)
1371 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1373 offset
, i2c_index
, i2c_address
, count
);
1375 chan
= init_i2c_device_find(bios
->dev
, i2c_index
);
1379 for (i
= 0; i
< count
; i
++) {
1380 data
[i
] = bios
->data
[offset
+ 4 + i
];
1382 BIOSLOG(bios
, "0x%04X: Data: 0x%02X\n", offset
, data
[i
]);
1385 if (bios
->execute
) {
1386 msg
.addr
= i2c_address
;
1390 if (i2c_transfer(&chan
->adapter
, &msg
, 1) != 1)
1398 init_tmds(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1401 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1403 * offset (8 bit): opcode
1404 * offset + 1 (8 bit): magic lookup value
1405 * offset + 2 (8 bit): TMDS address
1406 * offset + 3 (8 bit): mask
1407 * offset + 4 (8 bit): data
1409 * Read the data reg for TMDS address "TMDS address", AND it with mask
1410 * and OR it with data, then write it back
1411 * "magic lookup value" determines which TMDS base address register is
1412 * used -- see get_tmds_index_reg()
1415 uint8_t mlv
= bios
->data
[offset
+ 1];
1416 uint32_t tmdsaddr
= bios
->data
[offset
+ 2];
1417 uint8_t mask
= bios
->data
[offset
+ 3];
1418 uint8_t data
= bios
->data
[offset
+ 4];
1419 uint32_t reg
, value
;
1421 if (!iexec
->execute
)
1424 BIOSLOG(bios
, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1425 "Mask: 0x%02X, Data: 0x%02X\n",
1426 offset
, mlv
, tmdsaddr
, mask
, data
);
1428 reg
= get_tmds_index_reg(bios
->dev
, mlv
);
1432 bios_wr32(bios
, reg
,
1433 tmdsaddr
| NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE
);
1434 value
= (bios_rd32(bios
, reg
+ 4) & mask
) | data
;
1435 bios_wr32(bios
, reg
+ 4, value
);
1436 bios_wr32(bios
, reg
, tmdsaddr
);
1442 init_zm_tmds_group(struct nvbios
*bios
, uint16_t offset
,
1443 struct init_exec
*iexec
)
1446 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1448 * offset (8 bit): opcode
1449 * offset + 1 (8 bit): magic lookup value
1450 * offset + 2 (8 bit): count
1451 * offset + 3 (8 bit): addr 1
1452 * offset + 4 (8 bit): data 1
1455 * For each of "count" TMDS address and data pairs write "data n" to
1456 * "addr n". "magic lookup value" determines which TMDS base address
1457 * register is used -- see get_tmds_index_reg()
1460 uint8_t mlv
= bios
->data
[offset
+ 1];
1461 uint8_t count
= bios
->data
[offset
+ 2];
1462 int len
= 3 + count
* 2;
1466 if (!iexec
->execute
)
1469 BIOSLOG(bios
, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1470 offset
, mlv
, count
);
1472 reg
= get_tmds_index_reg(bios
->dev
, mlv
);
1476 for (i
= 0; i
< count
; i
++) {
1477 uint8_t tmdsaddr
= bios
->data
[offset
+ 3 + i
* 2];
1478 uint8_t tmdsdata
= bios
->data
[offset
+ 4 + i
* 2];
1480 bios_wr32(bios
, reg
+ 4, tmdsdata
);
1481 bios_wr32(bios
, reg
, tmdsaddr
);
1488 init_cr_idx_adr_latch(struct nvbios
*bios
, uint16_t offset
,
1489 struct init_exec
*iexec
)
1492 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1494 * offset (8 bit): opcode
1495 * offset + 1 (8 bit): CRTC index1
1496 * offset + 2 (8 bit): CRTC index2
1497 * offset + 3 (8 bit): baseaddr
1498 * offset + 4 (8 bit): count
1499 * offset + 5 (8 bit): data 1
1502 * For each of "count" address and data pairs, write "baseaddr + n" to
1503 * "CRTC index1" and "data n" to "CRTC index2"
1504 * Once complete, restore initial value read from "CRTC index1"
1506 uint8_t crtcindex1
= bios
->data
[offset
+ 1];
1507 uint8_t crtcindex2
= bios
->data
[offset
+ 2];
1508 uint8_t baseaddr
= bios
->data
[offset
+ 3];
1509 uint8_t count
= bios
->data
[offset
+ 4];
1510 int len
= 5 + count
;
1511 uint8_t oldaddr
, data
;
1514 if (!iexec
->execute
)
1517 BIOSLOG(bios
, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1518 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1519 offset
, crtcindex1
, crtcindex2
, baseaddr
, count
);
1521 oldaddr
= bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, crtcindex1
);
1523 for (i
= 0; i
< count
; i
++) {
1524 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex1
,
1526 data
= bios
->data
[offset
+ 5 + i
];
1527 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex2
, data
);
1530 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex1
, oldaddr
);
1536 init_cr(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1539 * INIT_CR opcode: 0x52 ('R')
1541 * offset (8 bit): opcode
1542 * offset + 1 (8 bit): CRTC index
1543 * offset + 2 (8 bit): mask
1544 * offset + 3 (8 bit): data
1546 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1547 * data back to "CRTC index"
1550 uint8_t crtcindex
= bios
->data
[offset
+ 1];
1551 uint8_t mask
= bios
->data
[offset
+ 2];
1552 uint8_t data
= bios
->data
[offset
+ 3];
1555 if (!iexec
->execute
)
1558 BIOSLOG(bios
, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1559 offset
, crtcindex
, mask
, data
);
1561 value
= bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, crtcindex
) & mask
;
1563 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex
, value
);
1569 init_zm_cr(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1572 * INIT_ZM_CR opcode: 0x53 ('S')
1574 * offset (8 bit): opcode
1575 * offset + 1 (8 bit): CRTC index
1576 * offset + 2 (8 bit): value
1578 * Assign "value" to CRTC register with index "CRTC index".
1581 uint8_t crtcindex
= ROM32(bios
->data
[offset
+ 1]);
1582 uint8_t data
= bios
->data
[offset
+ 2];
1584 if (!iexec
->execute
)
1587 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex
, data
);
1593 init_zm_cr_group(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1596 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1598 * offset (8 bit): opcode
1599 * offset + 1 (8 bit): count
1600 * offset + 2 (8 bit): CRTC index 1
1601 * offset + 3 (8 bit): value 1
1604 * For "count", assign "value n" to CRTC register with index
1608 uint8_t count
= bios
->data
[offset
+ 1];
1609 int len
= 2 + count
* 2;
1612 if (!iexec
->execute
)
1615 for (i
= 0; i
< count
; i
++)
1616 init_zm_cr(bios
, offset
+ 2 + 2 * i
- 1, iexec
);
1622 init_condition_time(struct nvbios
*bios
, uint16_t offset
,
1623 struct init_exec
*iexec
)
1626 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1628 * offset (8 bit): opcode
1629 * offset + 1 (8 bit): condition number
1630 * offset + 2 (8 bit): retries / 50
1632 * Check condition "condition number" in the condition table.
1633 * Bios code then sleeps for 2ms if the condition is not met, and
1634 * repeats up to "retries" times, but on one C51 this has proved
1635 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1636 * this, and bail after "retries" times, or 2s, whichever is less.
1637 * If still not met after retries, clear execution flag for this table.
1640 uint8_t cond
= bios
->data
[offset
+ 1];
1641 uint16_t retries
= bios
->data
[offset
+ 2] * 50;
1644 if (!iexec
->execute
)
1650 BIOSLOG(bios
, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1651 offset
, cond
, retries
);
1653 if (!bios
->execute
) /* avoid 2s delays when "faking" execution */
1656 for (cnt
= 0; cnt
< retries
; cnt
++) {
1657 if (bios_condition_met(bios
, offset
, cond
)) {
1658 BIOSLOG(bios
, "0x%04X: Condition met, continuing\n",
1662 BIOSLOG(bios
, "0x%04X: "
1663 "Condition not met, sleeping for 20ms\n",
1669 if (!bios_condition_met(bios
, offset
, cond
)) {
1671 "0x%04X: Condition still not met after %dms, "
1672 "skipping following opcodes\n", offset
, 20 * retries
);
1673 iexec
->execute
= false;
1680 init_zm_reg_sequence(struct nvbios
*bios
, uint16_t offset
,
1681 struct init_exec
*iexec
)
1684 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1686 * offset (8 bit): opcode
1687 * offset + 1 (32 bit): base register
1688 * offset + 5 (8 bit): count
1689 * offset + 6 (32 bit): value 1
1692 * Starting at offset + 6 there are "count" 32 bit values.
1693 * For "count" iterations set "base register" + 4 * current_iteration
1694 * to "value current_iteration"
1697 uint32_t basereg
= ROM32(bios
->data
[offset
+ 1]);
1698 uint32_t count
= bios
->data
[offset
+ 5];
1699 int len
= 6 + count
* 4;
1702 if (!iexec
->execute
)
1705 BIOSLOG(bios
, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1706 offset
, basereg
, count
);
1708 for (i
= 0; i
< count
; i
++) {
1709 uint32_t reg
= basereg
+ i
* 4;
1710 uint32_t data
= ROM32(bios
->data
[offset
+ 6 + i
* 4]);
1712 bios_wr32(bios
, reg
, data
);
1719 init_sub_direct(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1722 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1724 * offset (8 bit): opcode
1725 * offset + 1 (16 bit): subroutine offset (in bios)
1727 * Calls a subroutine that will execute commands until INIT_DONE
1731 uint16_t sub_offset
= ROM16(bios
->data
[offset
+ 1]);
1733 if (!iexec
->execute
)
1736 BIOSLOG(bios
, "0x%04X: Executing subroutine at 0x%04X\n",
1737 offset
, sub_offset
);
1739 parse_init_table(bios
, sub_offset
, iexec
);
1741 BIOSLOG(bios
, "0x%04X: End of 0x%04X subroutine\n", offset
, sub_offset
);
1747 init_copy_nv_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1750 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1752 * offset (8 bit): opcode
1753 * offset + 1 (32 bit): src reg
1754 * offset + 5 (8 bit): shift
1755 * offset + 6 (32 bit): src mask
1756 * offset + 10 (32 bit): xor
1757 * offset + 14 (32 bit): dst reg
1758 * offset + 18 (32 bit): dst mask
1760 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1761 * "src mask", then XOR with "xor". Write this OR'd with
1762 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1765 uint32_t srcreg
= *((uint32_t *)(&bios
->data
[offset
+ 1]));
1766 uint8_t shift
= bios
->data
[offset
+ 5];
1767 uint32_t srcmask
= *((uint32_t *)(&bios
->data
[offset
+ 6]));
1768 uint32_t xor = *((uint32_t *)(&bios
->data
[offset
+ 10]));
1769 uint32_t dstreg
= *((uint32_t *)(&bios
->data
[offset
+ 14]));
1770 uint32_t dstmask
= *((uint32_t *)(&bios
->data
[offset
+ 18]));
1771 uint32_t srcvalue
, dstvalue
;
1773 if (!iexec
->execute
)
1776 BIOSLOG(bios
, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1777 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1778 offset
, srcreg
, shift
, srcmask
, xor, dstreg
, dstmask
);
1780 srcvalue
= bios_rd32(bios
, srcreg
);
1785 srcvalue
<<= (0x100 - shift
);
1787 srcvalue
= (srcvalue
& srcmask
) ^ xor;
1789 dstvalue
= bios_rd32(bios
, dstreg
) & dstmask
;
1791 bios_wr32(bios
, dstreg
, dstvalue
| srcvalue
);
1797 init_zm_index_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1800 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1802 * offset (8 bit): opcode
1803 * offset + 1 (16 bit): CRTC port
1804 * offset + 3 (8 bit): CRTC index
1805 * offset + 4 (8 bit): data
1807 * Write "data" to index "CRTC index" of "CRTC port"
1809 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
1810 uint8_t crtcindex
= bios
->data
[offset
+ 3];
1811 uint8_t data
= bios
->data
[offset
+ 4];
1813 if (!iexec
->execute
)
1816 bios_idxprt_wr(bios
, crtcport
, crtcindex
, data
);
1822 init_compute_mem(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1825 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
1827 * offset (8 bit): opcode
1829 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1830 * that the hardware can correctly calculate how much VRAM it has
1831 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
1833 * The implementation of this opcode in general consists of two parts:
1834 * 1) determination of the memory bus width
1835 * 2) determination of how many of the card's RAM pads have ICs attached
1837 * 1) is done by a cunning combination of writes to offsets 0x1c and
1838 * 0x3c in the framebuffer, and seeing whether the written values are
1839 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1841 * 2) is done by a cunning combination of writes to an offset slightly
1842 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
1843 * if the test pattern can be read back. This then affects bits 12-15 of
1846 * In this context a "cunning combination" may include multiple reads
1847 * and writes to varying locations, often alternating the test pattern
1848 * and 0, doubtless to make sure buffers are filled, residual charges
1849 * on tracks are removed etc.
1851 * Unfortunately, the "cunning combination"s mentioned above, and the
1852 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1855 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1856 * we started was correct, and use that instead
1859 /* no iexec->execute check by design */
1862 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
1863 * and kmmio traces of the binary driver POSTing the card show nothing
1864 * being done for this opcode. why is it still listed in the table?!
1867 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
1869 if (dev_priv
->card_type
>= NV_40
)
1873 * On every card I've seen, this step gets done for us earlier in
1875 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
1876 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
1880 * This also has probably been done in the scripts, but an mmio trace of
1881 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
1883 bios_wr32(bios
, NV_PFB_REFCTRL
, NV_PFB_REFCTRL_VALID_1
);
1885 /* write back the saved configuration value */
1886 bios_wr32(bios
, NV_PFB_CFG0
, bios
->state
.saved_nv_pfb_cfg0
);
1892 init_reset(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1895 * INIT_RESET opcode: 0x65 ('e')
1897 * offset (8 bit): opcode
1898 * offset + 1 (32 bit): register
1899 * offset + 5 (32 bit): value1
1900 * offset + 9 (32 bit): value2
1902 * Assign "value1" to "register", then assign "value2" to "register"
1905 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
1906 uint32_t value1
= ROM32(bios
->data
[offset
+ 5]);
1907 uint32_t value2
= ROM32(bios
->data
[offset
+ 9]);
1908 uint32_t pci_nv_19
, pci_nv_20
;
1910 /* no iexec->execute check by design */
1912 pci_nv_19
= bios_rd32(bios
, NV_PBUS_PCI_NV_19
);
1913 bios_wr32(bios
, NV_PBUS_PCI_NV_19
, 0);
1914 bios_wr32(bios
, reg
, value1
);
1918 bios_wr32(bios
, reg
, value2
);
1919 bios_wr32(bios
, NV_PBUS_PCI_NV_19
, pci_nv_19
);
1921 pci_nv_20
= bios_rd32(bios
, NV_PBUS_PCI_NV_20
);
1922 pci_nv_20
&= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
; /* 0xfffffffe */
1923 bios_wr32(bios
, NV_PBUS_PCI_NV_20
, pci_nv_20
);
1929 init_configure_mem(struct nvbios
*bios
, uint16_t offset
,
1930 struct init_exec
*iexec
)
1933 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1935 * offset (8 bit): opcode
1937 * Equivalent to INIT_DONE on bios version 3 or greater.
1938 * For early bios versions, sets up the memory registers, using values
1939 * taken from the memory init table
1942 /* no iexec->execute check by design */
1944 uint16_t meminitoffs
= bios
->legacy
.mem_init_tbl_ptr
+ MEM_INIT_SIZE
* (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_SCRATCH4__INDEX
) >> 4);
1945 uint16_t seqtbloffs
= bios
->legacy
.sdr_seq_tbl_ptr
, meminitdata
= meminitoffs
+ 6;
1948 if (bios
->major_version
> 2)
1951 bios_idxprt_wr(bios
, NV_VIO_SRX
, NV_VIO_SR_CLOCK_INDEX
, bios_idxprt_rd(
1952 bios
, NV_VIO_SRX
, NV_VIO_SR_CLOCK_INDEX
) | 0x20);
1954 if (bios
->data
[meminitoffs
] & 1)
1955 seqtbloffs
= bios
->legacy
.ddr_seq_tbl_ptr
;
1957 for (reg
= ROM32(bios
->data
[seqtbloffs
]);
1959 reg
= ROM32(bios
->data
[seqtbloffs
+= 4])) {
1963 data
= NV_PFB_PRE_CMD_PRECHARGE
;
1966 data
= NV_PFB_PAD_CKE_NORMAL
;
1969 data
= NV_PFB_REF_CMD_REFRESH
;
1972 data
= ROM32(bios
->data
[meminitdata
]);
1974 if (data
== 0xffffffff)
1978 bios_wr32(bios
, reg
, data
);
1985 init_configure_clk(struct nvbios
*bios
, uint16_t offset
,
1986 struct init_exec
*iexec
)
1989 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
1991 * offset (8 bit): opcode
1993 * Equivalent to INIT_DONE on bios version 3 or greater.
1994 * For early bios versions, sets up the NVClk and MClk PLLs, using
1995 * values taken from the memory init table
1998 /* no iexec->execute check by design */
2000 uint16_t meminitoffs
= bios
->legacy
.mem_init_tbl_ptr
+ MEM_INIT_SIZE
* (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_SCRATCH4__INDEX
) >> 4);
2003 if (bios
->major_version
> 2)
2006 clock
= ROM16(bios
->data
[meminitoffs
+ 4]) * 10;
2007 setPLL(bios
, NV_PRAMDAC_NVPLL_COEFF
, clock
);
2009 clock
= ROM16(bios
->data
[meminitoffs
+ 2]) * 10;
2010 if (bios
->data
[meminitoffs
] & 1) /* DDR */
2012 setPLL(bios
, NV_PRAMDAC_MPLL_COEFF
, clock
);
2018 init_configure_preinit(struct nvbios
*bios
, uint16_t offset
,
2019 struct init_exec
*iexec
)
2022 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2024 * offset (8 bit): opcode
2026 * Equivalent to INIT_DONE on bios version 3 or greater.
2027 * For early bios versions, does early init, loading ram and crystal
2028 * configuration from straps into CR3C
2031 /* no iexec->execute check by design */
2033 uint32_t straps
= bios_rd32(bios
, NV_PEXTDEV_BOOT_0
);
2034 uint8_t cr3c
= ((straps
<< 2) & 0xf0) | (straps
& (1 << 6));
2036 if (bios
->major_version
> 2)
2039 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
,
2040 NV_CIO_CRE_SCRATCH4__INDEX
, cr3c
);
2046 init_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2049 * INIT_IO opcode: 0x69 ('i')
2051 * offset (8 bit): opcode
2052 * offset + 1 (16 bit): CRTC port
2053 * offset + 3 (8 bit): mask
2054 * offset + 4 (8 bit): data
2056 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2059 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2060 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
2061 uint8_t mask
= bios
->data
[offset
+ 3];
2062 uint8_t data
= bios
->data
[offset
+ 4];
2064 if (!iexec
->execute
)
2067 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2068 offset
, crtcport
, mask
, data
);
2071 * I have no idea what this does, but NVIDIA do this magic sequence
2072 * in the places where this INIT_IO happens..
2074 if (dev_priv
->card_type
>= NV_50
&& crtcport
== 0x3c3 && data
== 1) {
2077 bios_wr32(bios
, 0x614100, (bios_rd32(
2078 bios
, 0x614100) & 0x0fffffff) | 0x00800000);
2080 bios_wr32(bios
, 0x00e18c, bios_rd32(
2081 bios
, 0x00e18c) | 0x00020000);
2083 bios_wr32(bios
, 0x614900, (bios_rd32(
2084 bios
, 0x614900) & 0x0fffffff) | 0x00800000);
2086 bios_wr32(bios
, 0x000200, bios_rd32(
2087 bios
, 0x000200) & ~0x40000000);
2091 bios_wr32(bios
, 0x00e18c, bios_rd32(
2092 bios
, 0x00e18c) & ~0x00020000);
2094 bios_wr32(bios
, 0x000200, bios_rd32(
2095 bios
, 0x000200) | 0x40000000);
2097 bios_wr32(bios
, 0x614100, 0x00800018);
2098 bios_wr32(bios
, 0x614900, 0x00800018);
2102 bios_wr32(bios
, 0x614100, 0x10000018);
2103 bios_wr32(bios
, 0x614900, 0x10000018);
2105 for (i
= 0; i
< 3; i
++)
2106 bios_wr32(bios
, 0x614280 + (i
*0x800), bios_rd32(
2107 bios
, 0x614280 + (i
*0x800)) & 0xf0f0f0f0);
2109 for (i
= 0; i
< 2; i
++)
2110 bios_wr32(bios
, 0x614300 + (i
*0x800), bios_rd32(
2111 bios
, 0x614300 + (i
*0x800)) & 0xfffff0f0);
2113 for (i
= 0; i
< 3; i
++)
2114 bios_wr32(bios
, 0x614380 + (i
*0x800), bios_rd32(
2115 bios
, 0x614380 + (i
*0x800)) & 0xfffff0f0);
2117 for (i
= 0; i
< 2; i
++)
2118 bios_wr32(bios
, 0x614200 + (i
*0x800), bios_rd32(
2119 bios
, 0x614200 + (i
*0x800)) & 0xfffffff0);
2121 for (i
= 0; i
< 2; i
++)
2122 bios_wr32(bios
, 0x614108 + (i
*0x800), bios_rd32(
2123 bios
, 0x614108 + (i
*0x800)) & 0x0fffffff);
2127 bios_port_wr(bios
, crtcport
, (bios_port_rd(bios
, crtcport
) & mask
) |
2133 init_sub(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2136 * INIT_SUB opcode: 0x6B ('k')
2138 * offset (8 bit): opcode
2139 * offset + 1 (8 bit): script number
2141 * Execute script number "script number", as a subroutine
2144 uint8_t sub
= bios
->data
[offset
+ 1];
2146 if (!iexec
->execute
)
2149 BIOSLOG(bios
, "0x%04X: Calling script %d\n", offset
, sub
);
2151 parse_init_table(bios
,
2152 ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ sub
* 2]),
2155 BIOSLOG(bios
, "0x%04X: End of script %d\n", offset
, sub
);
2161 init_ram_condition(struct nvbios
*bios
, uint16_t offset
,
2162 struct init_exec
*iexec
)
2165 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2167 * offset (8 bit): opcode
2168 * offset + 1 (8 bit): mask
2169 * offset + 2 (8 bit): cmpval
2171 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2172 * If condition not met skip subsequent opcodes until condition is
2173 * inverted (INIT_NOT), or we hit INIT_RESUME
2176 uint8_t mask
= bios
->data
[offset
+ 1];
2177 uint8_t cmpval
= bios
->data
[offset
+ 2];
2180 if (!iexec
->execute
)
2183 data
= bios_rd32(bios
, NV_PFB_BOOT_0
) & mask
;
2185 BIOSLOG(bios
, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2186 offset
, data
, cmpval
);
2189 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2191 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2192 iexec
->execute
= false;
2199 init_nv_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2202 * INIT_NV_REG opcode: 0x6E ('n')
2204 * offset (8 bit): opcode
2205 * offset + 1 (32 bit): register
2206 * offset + 5 (32 bit): mask
2207 * offset + 9 (32 bit): data
2209 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2212 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2213 uint32_t mask
= ROM32(bios
->data
[offset
+ 5]);
2214 uint32_t data
= ROM32(bios
->data
[offset
+ 9]);
2216 if (!iexec
->execute
)
2219 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2220 offset
, reg
, mask
, data
);
2222 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & mask
) | data
);
2228 init_macro(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2231 * INIT_MACRO opcode: 0x6F ('o')
2233 * offset (8 bit): opcode
2234 * offset + 1 (8 bit): macro number
2236 * Look up macro index "macro number" in the macro index table.
2237 * The macro index table entry has 1 byte for the index in the macro
2238 * table, and 1 byte for the number of times to repeat the macro.
2239 * The macro table entry has 4 bytes for the register address and
2240 * 4 bytes for the value to write to that register
2243 uint8_t macro_index_tbl_idx
= bios
->data
[offset
+ 1];
2244 uint16_t tmp
= bios
->macro_index_tbl_ptr
+ (macro_index_tbl_idx
* MACRO_INDEX_SIZE
);
2245 uint8_t macro_tbl_idx
= bios
->data
[tmp
];
2246 uint8_t count
= bios
->data
[tmp
+ 1];
2250 if (!iexec
->execute
)
2253 BIOSLOG(bios
, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2255 offset
, macro_index_tbl_idx
, macro_tbl_idx
, count
);
2257 for (i
= 0; i
< count
; i
++) {
2258 uint16_t macroentryptr
= bios
->macro_tbl_ptr
+ (macro_tbl_idx
+ i
) * MACRO_SIZE
;
2260 reg
= ROM32(bios
->data
[macroentryptr
]);
2261 data
= ROM32(bios
->data
[macroentryptr
+ 4]);
2263 bios_wr32(bios
, reg
, data
);
2270 init_done(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2273 * INIT_DONE opcode: 0x71 ('q')
2275 * offset (8 bit): opcode
2277 * End the current script
2280 /* mild retval abuse to stop parsing this table */
2285 init_resume(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2288 * INIT_RESUME opcode: 0x72 ('r')
2290 * offset (8 bit): opcode
2292 * End the current execute / no-execute condition
2298 iexec
->execute
= true;
2299 BIOSLOG(bios
, "0x%04X: ---- Executing following commands ----\n", offset
);
2305 init_time(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2308 * INIT_TIME opcode: 0x74 ('t')
2310 * offset (8 bit): opcode
2311 * offset + 1 (16 bit): time
2313 * Sleep for "time" microseconds.
2316 unsigned time
= ROM16(bios
->data
[offset
+ 1]);
2318 if (!iexec
->execute
)
2321 BIOSLOG(bios
, "0x%04X: Sleeping for 0x%04X microseconds\n",
2327 msleep((time
+ 900) / 1000);
2333 init_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2336 * INIT_CONDITION opcode: 0x75 ('u')
2338 * offset (8 bit): opcode
2339 * offset + 1 (8 bit): condition number
2341 * Check condition "condition number" in the condition table.
2342 * If condition not met skip subsequent opcodes until condition is
2343 * inverted (INIT_NOT), or we hit INIT_RESUME
2346 uint8_t cond
= bios
->data
[offset
+ 1];
2348 if (!iexec
->execute
)
2351 BIOSLOG(bios
, "0x%04X: Condition: 0x%02X\n", offset
, cond
);
2353 if (bios_condition_met(bios
, offset
, cond
))
2354 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2356 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2357 iexec
->execute
= false;
2364 init_io_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2367 * INIT_IO_CONDITION opcode: 0x76
2369 * offset (8 bit): opcode
2370 * offset + 1 (8 bit): condition number
2372 * Check condition "condition number" in the io condition table.
2373 * If condition not met skip subsequent opcodes until condition is
2374 * inverted (INIT_NOT), or we hit INIT_RESUME
2377 uint8_t cond
= bios
->data
[offset
+ 1];
2379 if (!iexec
->execute
)
2382 BIOSLOG(bios
, "0x%04X: IO condition: 0x%02X\n", offset
, cond
);
2384 if (io_condition_met(bios
, offset
, cond
))
2385 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2387 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2388 iexec
->execute
= false;
2395 init_index_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2398 * INIT_INDEX_IO opcode: 0x78 ('x')
2400 * offset (8 bit): opcode
2401 * offset + 1 (16 bit): CRTC port
2402 * offset + 3 (8 bit): CRTC index
2403 * offset + 4 (8 bit): mask
2404 * offset + 5 (8 bit): data
2406 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2407 * OR with "data", write-back
2410 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
2411 uint8_t crtcindex
= bios
->data
[offset
+ 3];
2412 uint8_t mask
= bios
->data
[offset
+ 4];
2413 uint8_t data
= bios
->data
[offset
+ 5];
2416 if (!iexec
->execute
)
2419 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2421 offset
, crtcport
, crtcindex
, mask
, data
);
2423 value
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) | data
;
2424 bios_idxprt_wr(bios
, crtcport
, crtcindex
, value
);
2430 init_pll(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2433 * INIT_PLL opcode: 0x79 ('y')
2435 * offset (8 bit): opcode
2436 * offset + 1 (32 bit): register
2437 * offset + 5 (16 bit): freq
2439 * Set PLL register "register" to coefficients for frequency (10kHz)
2443 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2444 uint16_t freq
= ROM16(bios
->data
[offset
+ 5]);
2446 if (!iexec
->execute
)
2449 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset
, reg
, freq
);
2451 setPLL(bios
, reg
, freq
* 10);
2457 init_zm_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2460 * INIT_ZM_REG opcode: 0x7A ('z')
2462 * offset (8 bit): opcode
2463 * offset + 1 (32 bit): register
2464 * offset + 5 (32 bit): value
2466 * Assign "value" to "register"
2469 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2470 uint32_t value
= ROM32(bios
->data
[offset
+ 5]);
2472 if (!iexec
->execute
)
2475 if (reg
== 0x000200)
2478 bios_wr32(bios
, reg
, value
);
2484 init_ram_restrict_pll(struct nvbios
*bios
, uint16_t offset
,
2485 struct init_exec
*iexec
)
2488 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2490 * offset (8 bit): opcode
2491 * offset + 1 (8 bit): PLL type
2492 * offset + 2 (32 bit): frequency 0
2494 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2495 * ram_restrict_table_ptr. The value read from there is used to select
2496 * a frequency from the table starting at 'frequency 0' to be
2497 * programmed into the PLL corresponding to 'type'.
2499 * The PLL limits table on cards using this opcode has a mapping of
2500 * 'type' to the relevant registers.
2503 struct drm_device
*dev
= bios
->dev
;
2504 uint32_t strap
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) & 0x0000003c) >> 2;
2505 uint8_t index
= bios
->data
[bios
->ram_restrict_tbl_ptr
+ strap
];
2506 uint8_t type
= bios
->data
[offset
+ 1];
2507 uint32_t freq
= ROM32(bios
->data
[offset
+ 2 + (index
* 4)]);
2508 uint8_t *pll_limits
= &bios
->data
[bios
->pll_limit_tbl_ptr
], *entry
;
2509 int len
= 2 + bios
->ram_restrict_group_count
* 4;
2512 if (!iexec
->execute
)
2515 if (!bios
->pll_limit_tbl_ptr
|| (pll_limits
[0] & 0xf0) != 0x30) {
2516 NV_ERROR(dev
, "PLL limits table not version 3.x\n");
2517 return len
; /* deliberate, allow default clocks to remain */
2520 entry
= pll_limits
+ pll_limits
[1];
2521 for (i
= 0; i
< pll_limits
[3]; i
++, entry
+= pll_limits
[2]) {
2522 if (entry
[0] == type
) {
2523 uint32_t reg
= ROM32(entry
[3]);
2525 BIOSLOG(bios
, "0x%04X: "
2526 "Type %02x Reg 0x%08x Freq %dKHz\n",
2527 offset
, type
, reg
, freq
);
2529 setPLL(bios
, reg
, freq
);
2534 NV_ERROR(dev
, "PLL type 0x%02x not found in PLL limits table", type
);
2539 init_8c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2542 * INIT_8C opcode: 0x8C ('')
2552 init_8d(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2555 * INIT_8D opcode: 0x8D ('')
2565 init_gpio(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2568 * INIT_GPIO opcode: 0x8E ('')
2570 * offset (8 bit): opcode
2572 * Loop over all entries in the DCB GPIO table, and initialise
2573 * each GPIO according to various values listed in each entry
2576 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2577 const uint32_t nv50_gpio_ctl
[2] = { 0xe100, 0xe28c };
2580 if (dev_priv
->card_type
!= NV_50
) {
2581 NV_ERROR(bios
->dev
, "INIT_GPIO on unsupported chipset\n");
2585 if (!iexec
->execute
)
2588 for (i
= 0; i
< bios
->dcb
.gpio
.entries
; i
++) {
2589 struct dcb_gpio_entry
*gpio
= &bios
->dcb
.gpio
.entry
[i
];
2592 BIOSLOG(bios
, "0x%04X: Entry: 0x%08X\n", offset
, gpio
->entry
);
2594 nv50_gpio_set(bios
->dev
, gpio
->tag
, gpio
->state_default
);
2596 /* The NVIDIA binary driver doesn't appear to actually do
2597 * any of this, my VBIOS does however.
2599 /* Not a clue, needs de-magicing */
2600 r
= nv50_gpio_ctl
[gpio
->line
>> 4];
2601 s
= (gpio
->line
& 0x0f);
2602 v
= bios_rd32(bios
, r
) & ~(0x00010001 << s
);
2603 switch ((gpio
->entry
& 0x06000000) >> 25) {
2605 v
|= (0x00000001 << s
);
2608 v
|= (0x00010000 << s
);
2613 bios_wr32(bios
, r
, v
);
2620 init_ram_restrict_zm_reg_group(struct nvbios
*bios
, uint16_t offset
,
2621 struct init_exec
*iexec
)
2624 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2626 * offset (8 bit): opcode
2627 * offset + 1 (32 bit): reg
2628 * offset + 5 (8 bit): regincrement
2629 * offset + 6 (8 bit): count
2630 * offset + 7 (32 bit): value 1,1
2633 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2634 * ram_restrict_table_ptr. The value read from here is 'n', and
2635 * "value 1,n" gets written to "reg". This repeats "count" times and on
2636 * each iteration 'm', "reg" increases by "regincrement" and
2637 * "value m,n" is used. The extent of n is limited by a number read
2638 * from the 'M' BIT table, herein called "blocklen"
2641 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2642 uint8_t regincrement
= bios
->data
[offset
+ 5];
2643 uint8_t count
= bios
->data
[offset
+ 6];
2644 uint32_t strap_ramcfg
, data
;
2645 /* previously set by 'M' BIT table */
2646 uint16_t blocklen
= bios
->ram_restrict_group_count
* 4;
2647 int len
= 7 + count
* blocklen
;
2652 if (!iexec
->execute
)
2657 "0x%04X: Zero block length - has the M table "
2658 "been parsed?\n", offset
);
2662 strap_ramcfg
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 2) & 0xf;
2663 index
= bios
->data
[bios
->ram_restrict_tbl_ptr
+ strap_ramcfg
];
2665 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2666 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2667 offset
, reg
, regincrement
, count
, strap_ramcfg
, index
);
2669 for (i
= 0; i
< count
; i
++) {
2670 data
= ROM32(bios
->data
[offset
+ 7 + index
* 4 + blocklen
* i
]);
2672 bios_wr32(bios
, reg
, data
);
2674 reg
+= regincrement
;
2681 init_copy_zm_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2684 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2686 * offset (8 bit): opcode
2687 * offset + 1 (32 bit): src reg
2688 * offset + 5 (32 bit): dst reg
2690 * Put contents of "src reg" into "dst reg"
2693 uint32_t srcreg
= ROM32(bios
->data
[offset
+ 1]);
2694 uint32_t dstreg
= ROM32(bios
->data
[offset
+ 5]);
2696 if (!iexec
->execute
)
2699 bios_wr32(bios
, dstreg
, bios_rd32(bios
, srcreg
));
2705 init_zm_reg_group_addr_latched(struct nvbios
*bios
, uint16_t offset
,
2706 struct init_exec
*iexec
)
2709 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2711 * offset (8 bit): opcode
2712 * offset + 1 (32 bit): dst reg
2713 * offset + 5 (8 bit): count
2714 * offset + 6 (32 bit): data 1
2717 * For each of "count" values write "data n" to "dst reg"
2720 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2721 uint8_t count
= bios
->data
[offset
+ 5];
2722 int len
= 6 + count
* 4;
2725 if (!iexec
->execute
)
2728 for (i
= 0; i
< count
; i
++) {
2729 uint32_t data
= ROM32(bios
->data
[offset
+ 6 + 4 * i
]);
2730 bios_wr32(bios
, reg
, data
);
2737 init_reserved(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2740 * INIT_RESERVED opcode: 0x92 ('')
2742 * offset (8 bit): opcode
2744 * Seemingly does nothing
2751 init_96(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2754 * INIT_96 opcode: 0x96 ('')
2756 * offset (8 bit): opcode
2757 * offset + 1 (32 bit): sreg
2758 * offset + 5 (8 bit): sshift
2759 * offset + 6 (8 bit): smask
2760 * offset + 7 (8 bit): index
2761 * offset + 8 (32 bit): reg
2762 * offset + 12 (32 bit): mask
2763 * offset + 16 (8 bit): shift
2767 uint16_t xlatptr
= bios
->init96_tbl_ptr
+ (bios
->data
[offset
+ 7] * 2);
2768 uint32_t reg
= ROM32(bios
->data
[offset
+ 8]);
2769 uint32_t mask
= ROM32(bios
->data
[offset
+ 12]);
2772 val
= bios_rd32(bios
, ROM32(bios
->data
[offset
+ 1]));
2773 if (bios
->data
[offset
+ 5] < 0x80)
2774 val
>>= bios
->data
[offset
+ 5];
2776 val
<<= (0x100 - bios
->data
[offset
+ 5]);
2777 val
&= bios
->data
[offset
+ 6];
2779 val
= bios
->data
[ROM16(bios
->data
[xlatptr
]) + val
];
2780 val
<<= bios
->data
[offset
+ 16];
2782 if (!iexec
->execute
)
2785 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & mask
) | val
);
2790 init_97(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2793 * INIT_97 opcode: 0x97 ('')
2795 * offset (8 bit): opcode
2796 * offset + 1 (32 bit): register
2797 * offset + 5 (32 bit): mask
2798 * offset + 9 (32 bit): value
2800 * Adds "value" to "register" preserving the fields specified
2804 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2805 uint32_t mask
= ROM32(bios
->data
[offset
+ 5]);
2806 uint32_t add
= ROM32(bios
->data
[offset
+ 9]);
2809 val
= bios_rd32(bios
, reg
);
2810 val
= (val
& mask
) | ((val
+ add
) & ~mask
);
2812 if (!iexec
->execute
)
2815 bios_wr32(bios
, reg
, val
);
2820 init_auxch(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2823 * INIT_AUXCH opcode: 0x98 ('')
2825 * offset (8 bit): opcode
2826 * offset + 1 (32 bit): address
2827 * offset + 5 (8 bit): count
2828 * offset + 6 (8 bit): mask 0
2829 * offset + 7 (8 bit): data 0
2834 struct drm_device
*dev
= bios
->dev
;
2835 struct nouveau_i2c_chan
*auxch
;
2836 uint32_t addr
= ROM32(bios
->data
[offset
+ 1]);
2837 uint8_t count
= bios
->data
[offset
+ 5];
2838 int len
= 6 + count
* 2;
2841 if (!bios
->display
.output
) {
2842 NV_ERROR(dev
, "INIT_AUXCH: no active output\n");
2846 auxch
= init_i2c_device_find(dev
, bios
->display
.output
->i2c_index
);
2848 NV_ERROR(dev
, "INIT_AUXCH: couldn't get auxch %d\n",
2849 bios
->display
.output
->i2c_index
);
2853 if (!iexec
->execute
)
2857 for (i
= 0; i
< count
; i
++, offset
+= 2) {
2860 ret
= nouveau_dp_auxch(auxch
, 9, addr
, &data
, 1);
2862 NV_ERROR(dev
, "INIT_AUXCH: rd auxch fail %d\n", ret
);
2866 data
&= bios
->data
[offset
+ 0];
2867 data
|= bios
->data
[offset
+ 1];
2869 ret
= nouveau_dp_auxch(auxch
, 8, addr
, &data
, 1);
2871 NV_ERROR(dev
, "INIT_AUXCH: wr auxch fail %d\n", ret
);
2880 init_zm_auxch(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2883 * INIT_ZM_AUXCH opcode: 0x99 ('')
2885 * offset (8 bit): opcode
2886 * offset + 1 (32 bit): address
2887 * offset + 5 (8 bit): count
2888 * offset + 6 (8 bit): data 0
2893 struct drm_device
*dev
= bios
->dev
;
2894 struct nouveau_i2c_chan
*auxch
;
2895 uint32_t addr
= ROM32(bios
->data
[offset
+ 1]);
2896 uint8_t count
= bios
->data
[offset
+ 5];
2897 int len
= 6 + count
;
2900 if (!bios
->display
.output
) {
2901 NV_ERROR(dev
, "INIT_ZM_AUXCH: no active output\n");
2905 auxch
= init_i2c_device_find(dev
, bios
->display
.output
->i2c_index
);
2907 NV_ERROR(dev
, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
2908 bios
->display
.output
->i2c_index
);
2912 if (!iexec
->execute
)
2916 for (i
= 0; i
< count
; i
++, offset
++) {
2917 ret
= nouveau_dp_auxch(auxch
, 8, addr
, &bios
->data
[offset
], 1);
2919 NV_ERROR(dev
, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret
);
2927 static struct init_tbl_entry itbl_entry
[] = {
2928 /* command name , id , length , offset , mult , command handler */
2929 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
2930 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog
},
2931 { "INIT_REPEAT" , 0x33, init_repeat
},
2932 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll
},
2933 { "INIT_END_REPEAT" , 0x36, init_end_repeat
},
2934 { "INIT_COPY" , 0x37, init_copy
},
2935 { "INIT_NOT" , 0x38, init_not
},
2936 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition
},
2937 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched
},
2938 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2
},
2939 { "INIT_PLL2" , 0x4B, init_pll2
},
2940 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte
},
2941 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte
},
2942 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c
},
2943 { "INIT_TMDS" , 0x4F, init_tmds
},
2944 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group
},
2945 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch
},
2946 { "INIT_CR" , 0x52, init_cr
},
2947 { "INIT_ZM_CR" , 0x53, init_zm_cr
},
2948 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group
},
2949 { "INIT_CONDITION_TIME" , 0x56, init_condition_time
},
2950 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence
},
2951 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
2952 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct
},
2953 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg
},
2954 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io
},
2955 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem
},
2956 { "INIT_RESET" , 0x65, init_reset
},
2957 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem
},
2958 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk
},
2959 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit
},
2960 { "INIT_IO" , 0x69, init_io
},
2961 { "INIT_SUB" , 0x6B, init_sub
},
2962 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition
},
2963 { "INIT_NV_REG" , 0x6E, init_nv_reg
},
2964 { "INIT_MACRO" , 0x6F, init_macro
},
2965 { "INIT_DONE" , 0x71, init_done
},
2966 { "INIT_RESUME" , 0x72, init_resume
},
2967 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
2968 { "INIT_TIME" , 0x74, init_time
},
2969 { "INIT_CONDITION" , 0x75, init_condition
},
2970 { "INIT_IO_CONDITION" , 0x76, init_io_condition
},
2971 { "INIT_INDEX_IO" , 0x78, init_index_io
},
2972 { "INIT_PLL" , 0x79, init_pll
},
2973 { "INIT_ZM_REG" , 0x7A, init_zm_reg
},
2974 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll
},
2975 { "INIT_8C" , 0x8C, init_8c
},
2976 { "INIT_8D" , 0x8D, init_8d
},
2977 { "INIT_GPIO" , 0x8E, init_gpio
},
2978 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group
},
2979 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg
},
2980 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched
},
2981 { "INIT_RESERVED" , 0x92, init_reserved
},
2982 { "INIT_96" , 0x96, init_96
},
2983 { "INIT_97" , 0x97, init_97
},
2984 { "INIT_AUXCH" , 0x98, init_auxch
},
2985 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch
},
2989 #define MAX_TABLE_OPS 1000
2992 parse_init_table(struct nvbios
*bios
, unsigned int offset
,
2993 struct init_exec
*iexec
)
2996 * Parses all commands in an init table.
2998 * We start out executing all commands found in the init table. Some
2999 * opcodes may change the status of iexec->execute to SKIP, which will
3000 * cause the following opcodes to perform no operation until the value
3001 * is changed back to EXECUTE.
3004 int count
= 0, i
, res
;
3008 * Loop until INIT_DONE causes us to break out of the loop
3009 * (or until offset > bios length just in case... )
3010 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3012 while ((offset
< bios
->length
) && (count
++ < MAX_TABLE_OPS
)) {
3013 id
= bios
->data
[offset
];
3015 /* Find matching id in itbl_entry */
3016 for (i
= 0; itbl_entry
[i
].name
&& (itbl_entry
[i
].id
!= id
); i
++)
3019 if (itbl_entry
[i
].name
) {
3020 BIOSLOG(bios
, "0x%04X: [ (0x%02X) - %s ]\n",
3021 offset
, itbl_entry
[i
].id
, itbl_entry
[i
].name
);
3023 /* execute eventual command handler */
3024 res
= (*itbl_entry
[i
].handler
)(bios
, offset
, iexec
);
3028 * Add the offset of the current command including all data
3029 * of that command. The offset will then be pointing on the
3035 "0x%04X: Init table command not found: "
3036 "0x%02X\n", offset
, id
);
3041 if (offset
>= bios
->length
)
3043 "Offset 0x%04X greater than known bios image length. "
3044 "Corrupt image?\n", offset
);
3045 if (count
>= MAX_TABLE_OPS
)
3047 "More than %d opcodes to a table is unlikely, "
3048 "is the bios image corrupt?\n", MAX_TABLE_OPS
);
3054 parse_init_tables(struct nvbios
*bios
)
3056 /* Loops and calls parse_init_table() for each present table. */
3060 struct init_exec iexec
= {true, false};
3062 if (bios
->old_style_init
) {
3063 if (bios
->init_script_tbls_ptr
)
3064 parse_init_table(bios
, bios
->init_script_tbls_ptr
, &iexec
);
3065 if (bios
->extra_init_script_tbl_ptr
)
3066 parse_init_table(bios
, bios
->extra_init_script_tbl_ptr
, &iexec
);
3071 while ((table
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ i
]))) {
3073 "Parsing VBIOS init table %d at offset 0x%04X\n",
3075 BIOSLOG(bios
, "0x%04X: ------ Executing following commands ------\n", table
);
3077 parse_init_table(bios
, table
, &iexec
);
3082 static uint16_t clkcmptable(struct nvbios
*bios
, uint16_t clktable
, int pxclk
)
3084 int compare_record_len
, i
= 0;
3085 uint16_t compareclk
, scriptptr
= 0;
3087 if (bios
->major_version
< 5) /* pre BIT */
3088 compare_record_len
= 3;
3090 compare_record_len
= 4;
3093 compareclk
= ROM16(bios
->data
[clktable
+ compare_record_len
* i
]);
3094 if (pxclk
>= compareclk
* 10) {
3095 if (bios
->major_version
< 5) {
3096 uint8_t tmdssub
= bios
->data
[clktable
+ 2 + compare_record_len
* i
];
3097 scriptptr
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ tmdssub
* 2]);
3099 scriptptr
= ROM16(bios
->data
[clktable
+ 2 + compare_record_len
* i
]);
3103 } while (compareclk
);
3109 run_digital_op_script(struct drm_device
*dev
, uint16_t scriptptr
,
3110 struct dcb_entry
*dcbent
, int head
, bool dl
)
3112 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3113 struct nvbios
*bios
= &dev_priv
->vbios
;
3114 struct init_exec iexec
= {true, false};
3116 NV_TRACE(dev
, "0x%04X: Parsing digital output script table\n",
3118 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_44
,
3119 head
? NV_CIO_CRE_44_HEADB
: NV_CIO_CRE_44_HEADA
);
3120 /* note: if dcb entries have been merged, index may be misleading */
3121 NVWriteVgaCrtc5758(dev
, head
, 0, dcbent
->index
);
3122 parse_init_table(bios
, scriptptr
, &iexec
);
3124 nv04_dfp_bind_head(dev
, dcbent
, head
, dl
);
3127 static int call_lvds_manufacturer_script(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
)
3129 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3130 struct nvbios
*bios
= &dev_priv
->vbios
;
3131 uint8_t sub
= bios
->data
[bios
->fp
.xlated_entry
+ script
] + (bios
->fp
.link_c_increment
&& dcbent
->or & OUTPUT_C
? 1 : 0);
3132 uint16_t scriptofs
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ sub
* 2]);
3134 if (!bios
->fp
.xlated_entry
|| !sub
|| !scriptofs
)
3137 run_digital_op_script(dev
, scriptofs
, dcbent
, head
, bios
->fp
.dual_link
);
3139 if (script
== LVDS_PANEL_OFF
) {
3140 /* off-on delay in ms */
3141 msleep(ROM16(bios
->data
[bios
->fp
.xlated_entry
+ 7]));
3144 /* Powerbook specific quirks */
3145 if ((dev
->pci_device
& 0xffff) == 0x0179 ||
3146 (dev
->pci_device
& 0xffff) == 0x0189 ||
3147 (dev
->pci_device
& 0xffff) == 0x0329) {
3148 if (script
== LVDS_RESET
) {
3149 nv_write_tmds(dev
, dcbent
->or, 0, 0x02, 0x72);
3151 } else if (script
== LVDS_PANEL_ON
) {
3152 bios_wr32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
,
3153 bios_rd32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
)
3155 bios_wr32(bios
, NV_PCRTC_GPIO_EXT
,
3156 bios_rd32(bios
, NV_PCRTC_GPIO_EXT
) | 1);
3158 } else if (script
== LVDS_PANEL_OFF
) {
3159 bios_wr32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
,
3160 bios_rd32(bios
, NV_PBUS_DEBUG_DUALHEAD_CTL
)
3162 bios_wr32(bios
, NV_PCRTC_GPIO_EXT
,
3163 bios_rd32(bios
, NV_PCRTC_GPIO_EXT
) & ~3);
3171 static int run_lvds_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
, int pxclk
)
3174 * The BIT LVDS table's header has the information to setup the
3175 * necessary registers. Following the standard 4 byte header are:
3176 * A bitmask byte and a dual-link transition pxclk value for use in
3177 * selecting the init script when not using straps; 4 script pointers
3178 * for panel power, selected by output and on/off; and 8 table pointers
3179 * for panel init, the needed one determined by output, and bits in the
3180 * conf byte. These tables are similar to the TMDS tables, consisting
3181 * of a list of pxclks and script pointers.
3183 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3184 struct nvbios
*bios
= &dev_priv
->vbios
;
3185 unsigned int outputset
= (dcbent
->or == 4) ? 1 : 0;
3186 uint16_t scriptptr
= 0, clktable
;
3189 * For now we assume version 3.0 table - g80 support will need some
3196 case LVDS_BACKLIGHT_ON
:
3198 scriptptr
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 7 + outputset
* 2]);
3200 case LVDS_BACKLIGHT_OFF
:
3201 case LVDS_PANEL_OFF
:
3202 scriptptr
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 11 + outputset
* 2]);
3205 clktable
= bios
->fp
.lvdsmanufacturerpointer
+ 15;
3206 if (dcbent
->or == 4)
3209 if (dcbent
->lvdsconf
.use_straps_for_mode
) {
3210 if (bios
->fp
.dual_link
)
3212 if (bios
->fp
.if_is_24bit
)
3216 int cmpval_24bit
= (dcbent
->or == 4) ? 4 : 1;
3218 if (bios
->fp
.dual_link
) {
3223 if (bios
->fp
.strapless_is_24bit
& cmpval_24bit
)
3227 clktable
= ROM16(bios
->data
[clktable
]);
3229 NV_ERROR(dev
, "Pixel clock comparison table not found\n");
3232 scriptptr
= clkcmptable(bios
, clktable
, pxclk
);
3236 NV_ERROR(dev
, "LVDS output init script not found\n");
3239 run_digital_op_script(dev
, scriptptr
, dcbent
, head
, bios
->fp
.dual_link
);
3244 int call_lvds_script(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
, int pxclk
)
3247 * LVDS operations are multiplexed in an effort to present a single API
3248 * which works with two vastly differing underlying structures.
3249 * This acts as the demux
3252 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3253 struct nvbios
*bios
= &dev_priv
->vbios
;
3254 uint8_t lvds_ver
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
];
3255 uint32_t sel_clk_binding
, sel_clk
;
3258 if (bios
->fp
.last_script_invoc
== (script
<< 1 | head
) || !lvds_ver
||
3259 (lvds_ver
>= 0x30 && script
== LVDS_INIT
))
3262 if (!bios
->fp
.lvds_init_run
) {
3263 bios
->fp
.lvds_init_run
= true;
3264 call_lvds_script(dev
, dcbent
, head
, LVDS_INIT
, pxclk
);
3267 if (script
== LVDS_PANEL_ON
&& bios
->fp
.reset_after_pclk_change
)
3268 call_lvds_script(dev
, dcbent
, head
, LVDS_RESET
, pxclk
);
3269 if (script
== LVDS_RESET
&& bios
->fp
.power_off_for_reset
)
3270 call_lvds_script(dev
, dcbent
, head
, LVDS_PANEL_OFF
, pxclk
);
3272 NV_TRACE(dev
, "Calling LVDS script %d:\n", script
);
3274 /* don't let script change pll->head binding */
3275 sel_clk_binding
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
) & 0x50000;
3277 if (lvds_ver
< 0x30)
3278 ret
= call_lvds_manufacturer_script(dev
, dcbent
, head
, script
);
3280 ret
= run_lvds_table(dev
, dcbent
, head
, script
, pxclk
);
3282 bios
->fp
.last_script_invoc
= (script
<< 1 | head
);
3284 sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
) & ~0x50000;
3285 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, sel_clk
| sel_clk_binding
);
3286 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3287 nvWriteMC(dev
, NV_PBUS_POWERCTRL_2
, 0);
3292 struct lvdstableheader
{
3293 uint8_t lvds_ver
, headerlen
, recordlen
;
3296 static int parse_lvds_manufacturer_table_header(struct drm_device
*dev
, struct nvbios
*bios
, struct lvdstableheader
*lth
)
3299 * BMP version (0xa) LVDS table has a simple header of version and
3300 * record length. The BIT LVDS table has the typical BIT table header:
3301 * version byte, header length byte, record length byte, and a byte for
3302 * the maximum number of records that can be held in the table.
3305 uint8_t lvds_ver
, headerlen
, recordlen
;
3307 memset(lth
, 0, sizeof(struct lvdstableheader
));
3309 if (bios
->fp
.lvdsmanufacturerpointer
== 0x0) {
3310 NV_ERROR(dev
, "Pointer to LVDS manufacturer table invalid\n");
3314 lvds_ver
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
];
3317 case 0x0a: /* pre NV40 */
3319 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
3321 case 0x30: /* NV4x */
3322 headerlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
3323 if (headerlen
< 0x1f) {
3324 NV_ERROR(dev
, "LVDS table header not understood\n");
3327 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 2];
3329 case 0x40: /* G80/G90 */
3330 headerlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
3331 if (headerlen
< 0x7) {
3332 NV_ERROR(dev
, "LVDS table header not understood\n");
3335 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 2];
3339 "LVDS table revision %d.%d not currently supported\n",
3340 lvds_ver
>> 4, lvds_ver
& 0xf);
3344 lth
->lvds_ver
= lvds_ver
;
3345 lth
->headerlen
= headerlen
;
3346 lth
->recordlen
= recordlen
;
3352 get_fp_strap(struct drm_device
*dev
, struct nvbios
*bios
)
3354 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3357 * The fp strap is normally dictated by the "User Strap" in
3358 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3359 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3360 * by the PCI subsystem ID during POST, but not before the previous user
3361 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3362 * read and used instead
3365 if (bios
->major_version
< 5 && bios
->data
[0x48] & 0x4)
3366 return NVReadVgaCrtc5758(dev
, 0, 0xf) & 0xf;
3368 if (dev_priv
->card_type
>= NV_50
)
3369 return (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 24) & 0xf;
3371 return (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 16) & 0xf;
3374 static int parse_fp_mode_table(struct drm_device
*dev
, struct nvbios
*bios
)
3377 uint8_t fptable_ver
, headerlen
= 0, recordlen
, fpentries
= 0xf, fpindex
;
3378 int ret
, ofs
, fpstrapping
;
3379 struct lvdstableheader lth
;
3381 if (bios
->fp
.fptablepointer
== 0x0) {
3382 /* Apple cards don't have the fp table; the laptops use DDC */
3383 /* The table is also missing on some x86 IGPs */
3385 NV_ERROR(dev
, "Pointer to flat panel table invalid\n");
3387 bios
->digital_min_front_porch
= 0x4b;
3391 fptable
= &bios
->data
[bios
->fp
.fptablepointer
];
3392 fptable_ver
= fptable
[0];
3394 switch (fptable_ver
) {
3396 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3397 * version field, and miss one of the spread spectrum/PWM bytes.
3398 * This could affect early GF2Go parts (not seen any appropriate ROMs
3399 * though). Here we assume that a version of 0x05 matches this case
3400 * (combining with a BMP version check would be better), as the
3401 * common case for the panel type field is 0x0005, and that is in
3402 * fact what we are reading the first byte of.
3404 case 0x05: /* some NV10, 11, 15, 16 */
3408 case 0x10: /* some NV15/16, and NV11+ */
3412 case 0x20: /* NV40+ */
3413 headerlen
= fptable
[1];
3414 recordlen
= fptable
[2];
3415 fpentries
= fptable
[3];
3417 * fptable[4] is the minimum
3418 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3420 bios
->digital_min_front_porch
= fptable
[4];
3425 "FP table revision %d.%d not currently supported\n",
3426 fptable_ver
>> 4, fptable_ver
& 0xf);
3430 if (!bios
->is_mobile
) /* !mobile only needs digital_min_front_porch */
3433 ret
= parse_lvds_manufacturer_table_header(dev
, bios
, <h
);
3437 if (lth
.lvds_ver
== 0x30 || lth
.lvds_ver
== 0x40) {
3438 bios
->fp
.fpxlatetableptr
= bios
->fp
.lvdsmanufacturerpointer
+
3440 bios
->fp
.xlatwidth
= lth
.recordlen
;
3442 if (bios
->fp
.fpxlatetableptr
== 0x0) {
3443 NV_ERROR(dev
, "Pointer to flat panel xlat table invalid\n");
3447 fpstrapping
= get_fp_strap(dev
, bios
);
3449 fpindex
= bios
->data
[bios
->fp
.fpxlatetableptr
+
3450 fpstrapping
* bios
->fp
.xlatwidth
];
3452 if (fpindex
> fpentries
) {
3453 NV_ERROR(dev
, "Bad flat panel table index\n");
3457 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3458 if (lth
.lvds_ver
> 0x10)
3459 bios
->fp_no_ddc
= fpstrapping
!= 0xf || fpindex
!= 0xf;
3462 * If either the strap or xlated fpindex value are 0xf there is no
3463 * panel using a strap-derived bios mode present. this condition
3464 * includes, but is different from, the DDC panel indicator above
3466 if (fpstrapping
== 0xf || fpindex
== 0xf)
3469 bios
->fp
.mode_ptr
= bios
->fp
.fptablepointer
+ headerlen
+
3470 recordlen
* fpindex
+ ofs
;
3472 NV_TRACE(dev
, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3473 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 11]) + 1,
3474 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 25]) + 1,
3475 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 7]) * 10);
3480 bool nouveau_bios_fp_mode(struct drm_device
*dev
, struct drm_display_mode
*mode
)
3482 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3483 struct nvbios
*bios
= &dev_priv
->vbios
;
3484 uint8_t *mode_entry
= &bios
->data
[bios
->fp
.mode_ptr
];
3486 if (!mode
) /* just checking whether we can produce a mode */
3487 return bios
->fp
.mode_ptr
;
3489 memset(mode
, 0, sizeof(struct drm_display_mode
));
3491 * For version 1.0 (version in byte 0):
3492 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3493 * single/dual link, and type (TFT etc.)
3494 * bytes 3-6 are bits per colour in RGBX
3496 mode
->clock
= ROM16(mode_entry
[7]) * 10;
3497 /* bytes 9-10 is HActive */
3498 mode
->hdisplay
= ROM16(mode_entry
[11]) + 1;
3500 * bytes 13-14 is HValid Start
3501 * bytes 15-16 is HValid End
3503 mode
->hsync_start
= ROM16(mode_entry
[17]) + 1;
3504 mode
->hsync_end
= ROM16(mode_entry
[19]) + 1;
3505 mode
->htotal
= ROM16(mode_entry
[21]) + 1;
3506 /* bytes 23-24, 27-30 similarly, but vertical */
3507 mode
->vdisplay
= ROM16(mode_entry
[25]) + 1;
3508 mode
->vsync_start
= ROM16(mode_entry
[31]) + 1;
3509 mode
->vsync_end
= ROM16(mode_entry
[33]) + 1;
3510 mode
->vtotal
= ROM16(mode_entry
[35]) + 1;
3511 mode
->flags
|= (mode_entry
[37] & 0x10) ?
3512 DRM_MODE_FLAG_PHSYNC
: DRM_MODE_FLAG_NHSYNC
;
3513 mode
->flags
|= (mode_entry
[37] & 0x1) ?
3514 DRM_MODE_FLAG_PVSYNC
: DRM_MODE_FLAG_NVSYNC
;
3516 * bytes 38-39 relate to spread spectrum settings
3517 * bytes 40-43 are something to do with PWM
3520 mode
->status
= MODE_OK
;
3521 mode
->type
= DRM_MODE_TYPE_DRIVER
| DRM_MODE_TYPE_PREFERRED
;
3522 drm_mode_set_name(mode
);
3523 return bios
->fp
.mode_ptr
;
3526 int nouveau_bios_parse_lvds_table(struct drm_device
*dev
, int pxclk
, bool *dl
, bool *if_is_24bit
)
3529 * The LVDS table header is (mostly) described in
3530 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3531 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3532 * straps are not being used for the panel, this specifies the frequency
3533 * at which modes should be set up in the dual link style.
3535 * Following the header, the BMP (ver 0xa) table has several records,
3536 * indexed by a separate xlat table, indexed in turn by the fp strap in
3537 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3538 * numbers for use by INIT_SUB which controlled panel init and power,
3539 * and finally a dword of ms to sleep between power off and on
3542 * In the BIT versions, the table following the header serves as an
3543 * integrated config and xlat table: the records in the table are
3544 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3545 * two bytes - the first as a config byte, the second for indexing the
3546 * fp mode table pointed to by the BIT 'D' table
3548 * DDC is not used until after card init, so selecting the correct table
3549 * entry and setting the dual link flag for EDID equipped panels,
3550 * requiring tests against the native-mode pixel clock, cannot be done
3551 * until later, when this function should be called with non-zero pxclk
3553 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3554 struct nvbios
*bios
= &dev_priv
->vbios
;
3555 int fpstrapping
= get_fp_strap(dev
, bios
), lvdsmanufacturerindex
= 0;
3556 struct lvdstableheader lth
;
3558 int ret
, chip_version
= bios
->chip_version
;
3560 ret
= parse_lvds_manufacturer_table_header(dev
, bios
, <h
);
3564 switch (lth
.lvds_ver
) {
3565 case 0x0a: /* pre NV40 */
3566 lvdsmanufacturerindex
= bios
->data
[
3567 bios
->fp
.fpxlatemanufacturertableptr
+
3570 /* we're done if this isn't the EDID panel case */
3574 if (chip_version
< 0x25) {
3577 * It seems the old style lvds script pointer is reused
3578 * to select 18/24 bit colour depth for EDID panels.
3580 lvdsmanufacturerindex
=
3581 (bios
->legacy
.lvds_single_a_script_ptr
& 1) ?
3583 if (pxclk
>= bios
->fp
.duallink_transition_clk
)
3584 lvdsmanufacturerindex
++;
3585 } else if (chip_version
< 0x30) {
3586 /* nv28 behaviour (off-chip encoder)
3588 * nv28 does a complex dance of first using byte 121 of
3589 * the EDID to choose the lvdsmanufacturerindex, then
3590 * later attempting to match the EDID manufacturer and
3591 * product IDs in a table (signature 'pidt' (panel id
3592 * table?)), setting an lvdsmanufacturerindex of 0 and
3593 * an fp strap of the match index (or 0xf if none)
3595 lvdsmanufacturerindex
= 0;
3597 /* nv31, nv34 behaviour */
3598 lvdsmanufacturerindex
= 0;
3599 if (pxclk
>= bios
->fp
.duallink_transition_clk
)
3600 lvdsmanufacturerindex
= 2;
3601 if (pxclk
>= 140000)
3602 lvdsmanufacturerindex
= 3;
3606 * nvidia set the high nibble of (cr57=f, cr58) to
3607 * lvdsmanufacturerindex in this case; we don't
3610 case 0x30: /* NV4x */
3611 case 0x40: /* G80/G90 */
3612 lvdsmanufacturerindex
= fpstrapping
;
3615 NV_ERROR(dev
, "LVDS table revision not currently supported\n");
3619 lvdsofs
= bios
->fp
.xlated_entry
= bios
->fp
.lvdsmanufacturerpointer
+ lth
.headerlen
+ lth
.recordlen
* lvdsmanufacturerindex
;
3620 switch (lth
.lvds_ver
) {
3622 bios
->fp
.power_off_for_reset
= bios
->data
[lvdsofs
] & 1;
3623 bios
->fp
.reset_after_pclk_change
= bios
->data
[lvdsofs
] & 2;
3624 bios
->fp
.dual_link
= bios
->data
[lvdsofs
] & 4;
3625 bios
->fp
.link_c_increment
= bios
->data
[lvdsofs
] & 8;
3626 *if_is_24bit
= bios
->data
[lvdsofs
] & 16;
3631 * No sign of the "power off for reset" or "reset for panel
3632 * on" bits, but it's safer to assume we should
3634 bios
->fp
.power_off_for_reset
= true;
3635 bios
->fp
.reset_after_pclk_change
= true;
3638 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
3639 * over-written, and if_is_24bit isn't used
3641 bios
->fp
.dual_link
= bios
->data
[lvdsofs
] & 1;
3642 bios
->fp
.if_is_24bit
= bios
->data
[lvdsofs
] & 2;
3643 bios
->fp
.strapless_is_24bit
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 4];
3644 bios
->fp
.duallink_transition_clk
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 5]) * 10;
3648 /* Dell Latitude D620 reports a too-high value for the dual-link
3649 * transition freq, causing us to program the panel incorrectly.
3651 * It doesn't appear the VBIOS actually uses its transition freq
3652 * (90000kHz), instead it uses the "Number of LVDS channels" field
3653 * out of the panel ID structure (http://www.spwg.org/).
3655 * For the moment, a quirk will do :)
3657 if ((dev
->pdev
->device
== 0x01d7) &&
3658 (dev
->pdev
->subsystem_vendor
== 0x1028) &&
3659 (dev
->pdev
->subsystem_device
== 0x01c2)) {
3660 bios
->fp
.duallink_transition_clk
= 80000;
3663 /* set dual_link flag for EDID case */
3664 if (pxclk
&& (chip_version
< 0x25 || chip_version
> 0x28))
3665 bios
->fp
.dual_link
= (pxclk
>= bios
->fp
.duallink_transition_clk
);
3667 *dl
= bios
->fp
.dual_link
;
3673 bios_output_config_match(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
3674 uint16_t record
, int record_len
, int record_nr
)
3676 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3677 struct nvbios
*bios
= &dev_priv
->vbios
;
3682 for (i
= 0; i
< record_nr
; i
++, record
+= record_len
) {
3683 table
= ROM16(bios
->data
[record
]);
3686 entry
= ROM32(bios
->data
[table
]);
3688 v
= (entry
& 0x000f0000) >> 16;
3689 if (!(v
& dcbent
->or))
3692 v
= (entry
& 0x000000f0) >> 4;
3693 if (v
!= dcbent
->location
)
3696 v
= (entry
& 0x0000000f);
3697 if (v
!= dcbent
->type
)
3700 return &bios
->data
[table
];
3707 nouveau_bios_dp_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
3710 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3711 struct nvbios
*bios
= &dev_priv
->vbios
;
3714 if (!bios
->display
.dp_table_ptr
) {
3715 NV_ERROR(dev
, "No pointer to DisplayPort table\n");
3718 table
= &bios
->data
[bios
->display
.dp_table_ptr
];
3720 if (table
[0] != 0x20 && table
[0] != 0x21) {
3721 NV_ERROR(dev
, "DisplayPort table version 0x%02x unknown\n",
3727 return bios_output_config_match(dev
, dcbent
,
3728 bios
->display
.dp_table_ptr
+ table
[1],
3729 table
[2], table
[3]);
3733 nouveau_bios_run_display_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
3734 uint32_t sub
, int pxclk
)
3737 * The display script table is located by the BIT 'U' table.
3739 * It contains an array of pointers to various tables describing
3740 * a particular output type. The first 32-bits of the output
3741 * tables contains similar information to a DCB entry, and is
3742 * used to decide whether that particular table is suitable for
3743 * the output you want to access.
3745 * The "record header length" field here seems to indicate the
3746 * offset of the first configuration entry in the output tables.
3747 * This is 10 on most cards I've seen, but 12 has been witnessed
3748 * on DP cards, and there's another script pointer within the
3751 * offset + 0 ( 8 bits): version
3752 * offset + 1 ( 8 bits): header length
3753 * offset + 2 ( 8 bits): record length
3754 * offset + 3 ( 8 bits): number of records
3755 * offset + 4 ( 8 bits): record header length
3756 * offset + 5 (16 bits): pointer to first output script table
3759 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3760 struct nvbios
*bios
= &dev_priv
->vbios
;
3761 uint8_t *table
= &bios
->data
[bios
->display
.script_table_ptr
];
3762 uint8_t *otable
= NULL
;
3766 if (!bios
->display
.script_table_ptr
) {
3767 NV_ERROR(dev
, "No pointer to output script table\n");
3772 * Nothing useful has been in any of the pre-2.0 tables I've seen,
3773 * so until they are, we really don't need to care.
3775 if (table
[0] < 0x20)
3778 if (table
[0] != 0x20 && table
[0] != 0x21) {
3779 NV_ERROR(dev
, "Output script table version 0x%02x unknown\n",
3785 * The output script tables describing a particular output type
3788 * offset + 0 (32 bits): output this table matches (hash of DCB)
3789 * offset + 4 ( 8 bits): unknown
3790 * offset + 5 ( 8 bits): number of configurations
3791 * offset + 6 (16 bits): pointer to some script
3792 * offset + 8 (16 bits): pointer to some script
3795 * offset + 10 : configuration 0
3798 * offset + 10 : pointer to some script
3799 * offset + 12 : configuration 0
3801 * Each config entry is as follows:
3803 * offset + 0 (16 bits): unknown, assumed to be a match value
3804 * offset + 2 (16 bits): pointer to script table (clock set?)
3805 * offset + 4 (16 bits): pointer to script table (reset?)
3807 * There doesn't appear to be a count value to say how many
3808 * entries exist in each script table, instead, a 0 value in
3809 * the first 16-bit word seems to indicate both the end of the
3810 * list and the default entry. The second 16-bit word in the
3811 * script tables is a pointer to the script to execute.
3814 NV_DEBUG_KMS(dev
, "Searching for output entry for %d %d %d\n",
3815 dcbent
->type
, dcbent
->location
, dcbent
->or);
3816 otable
= bios_output_config_match(dev
, dcbent
, table
[1] +
3817 bios
->display
.script_table_ptr
,
3818 table
[2], table
[3]);
3820 NV_ERROR(dev
, "Couldn't find matching output script table\n");
3824 if (pxclk
< -2 || pxclk
> 0) {
3825 /* Try to find matching script table entry */
3826 for (i
= 0; i
< otable
[5]; i
++) {
3827 if (ROM16(otable
[table
[4] + i
*6]) == sub
)
3831 if (i
== otable
[5]) {
3832 NV_ERROR(dev
, "Table 0x%04x not found for %d/%d, "
3834 sub
, dcbent
->type
, dcbent
->or);
3840 script
= ROM16(otable
[6]);
3842 NV_DEBUG_KMS(dev
, "output script 0 not found\n");
3846 NV_TRACE(dev
, "0x%04X: parsing output script 0\n", script
);
3847 nouveau_bios_run_init_table(dev
, script
, dcbent
);
3850 script
= ROM16(otable
[8]);
3852 NV_DEBUG_KMS(dev
, "output script 1 not found\n");
3856 NV_TRACE(dev
, "0x%04X: parsing output script 1\n", script
);
3857 nouveau_bios_run_init_table(dev
, script
, dcbent
);
3861 script
= ROM16(otable
[10]);
3865 NV_DEBUG_KMS(dev
, "output script 2 not found\n");
3869 NV_TRACE(dev
, "0x%04X: parsing output script 2\n", script
);
3870 nouveau_bios_run_init_table(dev
, script
, dcbent
);
3873 script
= ROM16(otable
[table
[4] + i
*6 + 2]);
3875 script
= clkcmptable(bios
, script
, pxclk
);
3877 NV_ERROR(dev
, "clock script 0 not found\n");
3881 NV_TRACE(dev
, "0x%04X: parsing clock script 0\n", script
);
3882 nouveau_bios_run_init_table(dev
, script
, dcbent
);
3885 script
= ROM16(otable
[table
[4] + i
*6 + 4]);
3887 script
= clkcmptable(bios
, script
, -pxclk
);
3889 NV_DEBUG_KMS(dev
, "clock script 1 not found\n");
3893 NV_TRACE(dev
, "0x%04X: parsing clock script 1\n", script
);
3894 nouveau_bios_run_init_table(dev
, script
, dcbent
);
3901 int run_tmds_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, int pxclk
)
3904 * the pxclk parameter is in kHz
3906 * This runs the TMDS regs setting code found on BIT bios cards
3908 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3909 * ffs(or) == 3, use the second.
3912 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3913 struct nvbios
*bios
= &dev_priv
->vbios
;
3914 int cv
= bios
->chip_version
;
3915 uint16_t clktable
= 0, scriptptr
;
3916 uint32_t sel_clk_binding
, sel_clk
;
3918 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
3919 if (cv
>= 0x17 && cv
!= 0x1a && cv
!= 0x20 &&
3920 dcbent
->location
!= DCB_LOC_ON_CHIP
)
3923 switch (ffs(dcbent
->or)) {
3925 clktable
= bios
->tmds
.output0_script_ptr
;
3929 clktable
= bios
->tmds
.output1_script_ptr
;
3934 NV_ERROR(dev
, "Pixel clock comparison table not found\n");
3938 scriptptr
= clkcmptable(bios
, clktable
, pxclk
);
3941 NV_ERROR(dev
, "TMDS output init script not found\n");
3945 /* don't let script change pll->head binding */
3946 sel_clk_binding
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
) & 0x50000;
3947 run_digital_op_script(dev
, scriptptr
, dcbent
, head
, pxclk
>= 165000);
3948 sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
) & ~0x50000;
3949 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, sel_clk
| sel_clk_binding
);
3954 int get_pll_limits(struct drm_device
*dev
, uint32_t limit_match
, struct pll_lims
*pll_lim
)
3959 * Version 0x10: NV30, NV31
3960 * One byte header (version), one record of 24 bytes
3961 * Version 0x11: NV36 - Not implemented
3962 * Seems to have same record style as 0x10, but 3 records rather than 1
3963 * Version 0x20: Found on Geforce 6 cards
3964 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3965 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3966 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
3967 * length in general, some (integrated) have an extra configuration byte
3968 * Version 0x30: Found on Geforce 8, separates the register mapping
3969 * from the limits tables.
3972 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3973 struct nvbios
*bios
= &dev_priv
->vbios
;
3974 int cv
= bios
->chip_version
, pllindex
= 0;
3975 uint8_t pll_lim_ver
= 0, headerlen
= 0, recordlen
= 0, entries
= 0;
3976 uint32_t crystal_strap_mask
, crystal_straps
;
3978 if (!bios
->pll_limit_tbl_ptr
) {
3979 if (cv
== 0x30 || cv
== 0x31 || cv
== 0x35 || cv
== 0x36 ||
3981 NV_ERROR(dev
, "Pointer to PLL limits table invalid\n");
3985 pll_lim_ver
= bios
->data
[bios
->pll_limit_tbl_ptr
];
3987 crystal_strap_mask
= 1 << 6;
3988 /* open coded dev->twoHeads test */
3989 if (cv
> 0x10 && cv
!= 0x15 && cv
!= 0x1a && cv
!= 0x20)
3990 crystal_strap_mask
|= 1 << 22;
3991 crystal_straps
= nvReadEXTDEV(dev
, NV_PEXTDEV_BOOT_0
) &
3994 switch (pll_lim_ver
) {
3996 * We use version 0 to indicate a pre limit table bios (single stage
3997 * pll) and load the hard coded limits instead.
4004 * Strictly v0x11 has 3 entries, but the last two don't seem
4016 headerlen
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 1];
4017 recordlen
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 2];
4018 entries
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 3];
4021 NV_ERROR(dev
, "PLL limits table revision 0x%X not currently "
4022 "supported\n", pll_lim_ver
);
4026 /* initialize all members to zero */
4027 memset(pll_lim
, 0, sizeof(struct pll_lims
));
4029 if (pll_lim_ver
== 0x10 || pll_lim_ver
== 0x11) {
4030 uint8_t *pll_rec
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
+ recordlen
* pllindex
];
4032 pll_lim
->vco1
.minfreq
= ROM32(pll_rec
[0]);
4033 pll_lim
->vco1
.maxfreq
= ROM32(pll_rec
[4]);
4034 pll_lim
->vco2
.minfreq
= ROM32(pll_rec
[8]);
4035 pll_lim
->vco2
.maxfreq
= ROM32(pll_rec
[12]);
4036 pll_lim
->vco1
.min_inputfreq
= ROM32(pll_rec
[16]);
4037 pll_lim
->vco2
.min_inputfreq
= ROM32(pll_rec
[20]);
4038 pll_lim
->vco1
.max_inputfreq
= pll_lim
->vco2
.max_inputfreq
= INT_MAX
;
4040 /* these values taken from nv30/31/36 */
4041 pll_lim
->vco1
.min_n
= 0x1;
4043 pll_lim
->vco1
.min_n
= 0x5;
4044 pll_lim
->vco1
.max_n
= 0xff;
4045 pll_lim
->vco1
.min_m
= 0x1;
4046 pll_lim
->vco1
.max_m
= 0xd;
4047 pll_lim
->vco2
.min_n
= 0x4;
4049 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4050 * table version (apart from nv35)), N2 is compared to
4051 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4054 pll_lim
->vco2
.max_n
= 0x28;
4055 if (cv
== 0x30 || cv
== 0x35)
4056 /* only 5 bits available for N2 on nv30/35 */
4057 pll_lim
->vco2
.max_n
= 0x1f;
4058 pll_lim
->vco2
.min_m
= 0x1;
4059 pll_lim
->vco2
.max_m
= 0x4;
4060 pll_lim
->max_log2p
= 0x7;
4061 pll_lim
->max_usable_log2p
= 0x6;
4062 } else if (pll_lim_ver
== 0x20 || pll_lim_ver
== 0x21) {
4063 uint16_t plloffs
= bios
->pll_limit_tbl_ptr
+ headerlen
;
4064 uint32_t reg
= 0; /* default match */
4069 * First entry is default match, if nothing better. warn if
4072 if (ROM32(bios
->data
[plloffs
]))
4073 NV_WARN(dev
, "Default PLL limit entry has non-zero "
4074 "register field\n");
4076 if (limit_match
> MAX_PLL_TYPES
)
4077 /* we've been passed a reg as the match */
4079 else /* limit match is a pll type */
4080 for (i
= 1; i
< entries
&& !reg
; i
++) {
4081 uint32_t cmpreg
= ROM32(bios
->data
[plloffs
+ recordlen
* i
]);
4083 if (limit_match
== NVPLL
&&
4084 (cmpreg
== NV_PRAMDAC_NVPLL_COEFF
|| cmpreg
== 0x4000))
4086 if (limit_match
== MPLL
&&
4087 (cmpreg
== NV_PRAMDAC_MPLL_COEFF
|| cmpreg
== 0x4020))
4089 if (limit_match
== VPLL1
&&
4090 (cmpreg
== NV_PRAMDAC_VPLL_COEFF
|| cmpreg
== 0x4010))
4092 if (limit_match
== VPLL2
&&
4093 (cmpreg
== NV_RAMDAC_VPLL2
|| cmpreg
== 0x4018))
4097 for (i
= 1; i
< entries
; i
++)
4098 if (ROM32(bios
->data
[plloffs
+ recordlen
* i
]) == reg
) {
4103 pll_rec
= &bios
->data
[plloffs
+ recordlen
* pllindex
];
4105 BIOSLOG(bios
, "Loading PLL limits for reg 0x%08x\n",
4106 pllindex
? reg
: 0);
4109 * Frequencies are stored in tables in MHz, kHz are more
4110 * useful, so we convert.
4113 /* What output frequencies can each VCO generate? */
4114 pll_lim
->vco1
.minfreq
= ROM16(pll_rec
[4]) * 1000;
4115 pll_lim
->vco1
.maxfreq
= ROM16(pll_rec
[6]) * 1000;
4116 pll_lim
->vco2
.minfreq
= ROM16(pll_rec
[8]) * 1000;
4117 pll_lim
->vco2
.maxfreq
= ROM16(pll_rec
[10]) * 1000;
4119 /* What input frequencies they accept (past the m-divider)? */
4120 pll_lim
->vco1
.min_inputfreq
= ROM16(pll_rec
[12]) * 1000;
4121 pll_lim
->vco2
.min_inputfreq
= ROM16(pll_rec
[14]) * 1000;
4122 pll_lim
->vco1
.max_inputfreq
= ROM16(pll_rec
[16]) * 1000;
4123 pll_lim
->vco2
.max_inputfreq
= ROM16(pll_rec
[18]) * 1000;
4125 /* What values are accepted as multiplier and divider? */
4126 pll_lim
->vco1
.min_n
= pll_rec
[20];
4127 pll_lim
->vco1
.max_n
= pll_rec
[21];
4128 pll_lim
->vco1
.min_m
= pll_rec
[22];
4129 pll_lim
->vco1
.max_m
= pll_rec
[23];
4130 pll_lim
->vco2
.min_n
= pll_rec
[24];
4131 pll_lim
->vco2
.max_n
= pll_rec
[25];
4132 pll_lim
->vco2
.min_m
= pll_rec
[26];
4133 pll_lim
->vco2
.max_m
= pll_rec
[27];
4135 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
= pll_rec
[29];
4136 if (pll_lim
->max_log2p
> 0x7)
4137 /* pll decoding in nv_hw.c assumes never > 7 */
4138 NV_WARN(dev
, "Max log2 P value greater than 7 (%d)\n",
4139 pll_lim
->max_log2p
);
4141 pll_lim
->max_usable_log2p
= 0x6;
4142 pll_lim
->log2p_bias
= pll_rec
[30];
4144 if (recordlen
> 0x22)
4145 pll_lim
->refclk
= ROM32(pll_rec
[31]);
4147 if (recordlen
> 0x23 && pll_rec
[35])
4149 "Bits set in PLL configuration byte (%x)\n",
4152 /* C51 special not seen elsewhere */
4153 if (cv
== 0x51 && !pll_lim
->refclk
) {
4154 uint32_t sel_clk
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
);
4156 if (((limit_match
== NV_PRAMDAC_VPLL_COEFF
|| limit_match
== VPLL1
) && sel_clk
& 0x20) ||
4157 ((limit_match
== NV_RAMDAC_VPLL2
|| limit_match
== VPLL2
) && sel_clk
& 0x80)) {
4158 if (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_CHIP_ID_INDEX
) < 0xa3)
4159 pll_lim
->refclk
= 200000;
4161 pll_lim
->refclk
= 25000;
4164 } else if (pll_lim_ver
== 0x30) { /* ver 0x30 */
4165 uint8_t *entry
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
];
4166 uint8_t *record
= NULL
;
4169 BIOSLOG(bios
, "Loading PLL limits for register 0x%08x\n",
4172 for (i
= 0; i
< entries
; i
++, entry
+= recordlen
) {
4173 if (ROM32(entry
[3]) == limit_match
) {
4174 record
= &bios
->data
[ROM16(entry
[1])];
4180 NV_ERROR(dev
, "Register 0x%08x not found in PLL "
4181 "limits table", limit_match
);
4185 pll_lim
->vco1
.minfreq
= ROM16(record
[0]) * 1000;
4186 pll_lim
->vco1
.maxfreq
= ROM16(record
[2]) * 1000;
4187 pll_lim
->vco2
.minfreq
= ROM16(record
[4]) * 1000;
4188 pll_lim
->vco2
.maxfreq
= ROM16(record
[6]) * 1000;
4189 pll_lim
->vco1
.min_inputfreq
= ROM16(record
[8]) * 1000;
4190 pll_lim
->vco2
.min_inputfreq
= ROM16(record
[10]) * 1000;
4191 pll_lim
->vco1
.max_inputfreq
= ROM16(record
[12]) * 1000;
4192 pll_lim
->vco2
.max_inputfreq
= ROM16(record
[14]) * 1000;
4193 pll_lim
->vco1
.min_n
= record
[16];
4194 pll_lim
->vco1
.max_n
= record
[17];
4195 pll_lim
->vco1
.min_m
= record
[18];
4196 pll_lim
->vco1
.max_m
= record
[19];
4197 pll_lim
->vco2
.min_n
= record
[20];
4198 pll_lim
->vco2
.max_n
= record
[21];
4199 pll_lim
->vco2
.min_m
= record
[22];
4200 pll_lim
->vco2
.max_m
= record
[23];
4201 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
= record
[25];
4202 pll_lim
->log2p_bias
= record
[27];
4203 pll_lim
->refclk
= ROM32(record
[28]);
4204 } else if (pll_lim_ver
) { /* ver 0x40 */
4205 uint8_t *entry
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
];
4206 uint8_t *record
= NULL
;
4209 BIOSLOG(bios
, "Loading PLL limits for register 0x%08x\n",
4212 for (i
= 0; i
< entries
; i
++, entry
+= recordlen
) {
4213 if (ROM32(entry
[3]) == limit_match
) {
4214 record
= &bios
->data
[ROM16(entry
[1])];
4220 NV_ERROR(dev
, "Register 0x%08x not found in PLL "
4221 "limits table", limit_match
);
4225 pll_lim
->vco1
.minfreq
= ROM16(record
[0]) * 1000;
4226 pll_lim
->vco1
.maxfreq
= ROM16(record
[2]) * 1000;
4227 pll_lim
->vco1
.min_inputfreq
= ROM16(record
[4]) * 1000;
4228 pll_lim
->vco1
.max_inputfreq
= ROM16(record
[6]) * 1000;
4229 pll_lim
->vco1
.min_m
= record
[8];
4230 pll_lim
->vco1
.max_m
= record
[9];
4231 pll_lim
->vco1
.min_n
= record
[10];
4232 pll_lim
->vco1
.max_n
= record
[11];
4233 pll_lim
->min_p
= record
[12];
4234 pll_lim
->max_p
= record
[13];
4235 /* where did this go to?? */
4236 if (limit_match
== 0x00614100 || limit_match
== 0x00614900)
4237 pll_lim
->refclk
= 27000;
4239 pll_lim
->refclk
= 100000;
4243 * By now any valid limit table ought to have set a max frequency for
4244 * vco1, so if it's zero it's either a pre limit table bios, or one
4245 * with an empty limit table (seen on nv18)
4247 if (!pll_lim
->vco1
.maxfreq
) {
4248 pll_lim
->vco1
.minfreq
= bios
->fminvco
;
4249 pll_lim
->vco1
.maxfreq
= bios
->fmaxvco
;
4250 pll_lim
->vco1
.min_inputfreq
= 0;
4251 pll_lim
->vco1
.max_inputfreq
= INT_MAX
;
4252 pll_lim
->vco1
.min_n
= 0x1;
4253 pll_lim
->vco1
.max_n
= 0xff;
4254 pll_lim
->vco1
.min_m
= 0x1;
4255 if (crystal_straps
== 0) {
4256 /* nv05 does this, nv11 doesn't, nv10 unknown */
4258 pll_lim
->vco1
.min_m
= 0x7;
4259 pll_lim
->vco1
.max_m
= 0xd;
4262 pll_lim
->vco1
.min_m
= 0x8;
4263 pll_lim
->vco1
.max_m
= 0xe;
4265 if (cv
< 0x17 || cv
== 0x1a || cv
== 0x20)
4266 pll_lim
->max_log2p
= 4;
4268 pll_lim
->max_log2p
= 5;
4269 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
;
4272 if (!pll_lim
->refclk
)
4273 switch (crystal_straps
) {
4275 pll_lim
->refclk
= 13500;
4278 pll_lim
->refclk
= 14318;
4281 pll_lim
->refclk
= 27000;
4283 case (1 << 22 | 1 << 6):
4284 pll_lim
->refclk
= 25000;
4288 #if 0 /* for easy debugging */
4289 ErrorF("pll.vco1.minfreq: %d\n", pll_lim
->vco1
.minfreq
);
4290 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim
->vco1
.maxfreq
);
4291 ErrorF("pll.vco2.minfreq: %d\n", pll_lim
->vco2
.minfreq
);
4292 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim
->vco2
.maxfreq
);
4294 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim
->vco1
.min_inputfreq
);
4295 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim
->vco1
.max_inputfreq
);
4296 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim
->vco2
.min_inputfreq
);
4297 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim
->vco2
.max_inputfreq
);
4299 ErrorF("pll.vco1.min_n: %d\n", pll_lim
->vco1
.min_n
);
4300 ErrorF("pll.vco1.max_n: %d\n", pll_lim
->vco1
.max_n
);
4301 ErrorF("pll.vco1.min_m: %d\n", pll_lim
->vco1
.min_m
);
4302 ErrorF("pll.vco1.max_m: %d\n", pll_lim
->vco1
.max_m
);
4303 ErrorF("pll.vco2.min_n: %d\n", pll_lim
->vco2
.min_n
);
4304 ErrorF("pll.vco2.max_n: %d\n", pll_lim
->vco2
.max_n
);
4305 ErrorF("pll.vco2.min_m: %d\n", pll_lim
->vco2
.min_m
);
4306 ErrorF("pll.vco2.max_m: %d\n", pll_lim
->vco2
.max_m
);
4308 ErrorF("pll.max_log2p: %d\n", pll_lim
->max_log2p
);
4309 ErrorF("pll.log2p_bias: %d\n", pll_lim
->log2p_bias
);
4311 ErrorF("pll.refclk: %d\n", pll_lim
->refclk
);
4317 static void parse_bios_version(struct drm_device
*dev
, struct nvbios
*bios
, uint16_t offset
)
4320 * offset + 0 (8 bits): Micro version
4321 * offset + 1 (8 bits): Minor version
4322 * offset + 2 (8 bits): Chip version
4323 * offset + 3 (8 bits): Major version
4326 bios
->major_version
= bios
->data
[offset
+ 3];
4327 bios
->chip_version
= bios
->data
[offset
+ 2];
4328 NV_TRACE(dev
, "Bios version %02x.%02x.%02x.%02x\n",
4329 bios
->data
[offset
+ 3], bios
->data
[offset
+ 2],
4330 bios
->data
[offset
+ 1], bios
->data
[offset
]);
4333 static void parse_script_table_pointers(struct nvbios
*bios
, uint16_t offset
)
4336 * Parses the init table segment for pointers used in script execution.
4338 * offset + 0 (16 bits): init script tables pointer
4339 * offset + 2 (16 bits): macro index table pointer
4340 * offset + 4 (16 bits): macro table pointer
4341 * offset + 6 (16 bits): condition table pointer
4342 * offset + 8 (16 bits): io condition table pointer
4343 * offset + 10 (16 bits): io flag condition table pointer
4344 * offset + 12 (16 bits): init function table pointer
4347 bios
->init_script_tbls_ptr
= ROM16(bios
->data
[offset
]);
4348 bios
->macro_index_tbl_ptr
= ROM16(bios
->data
[offset
+ 2]);
4349 bios
->macro_tbl_ptr
= ROM16(bios
->data
[offset
+ 4]);
4350 bios
->condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 6]);
4351 bios
->io_condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 8]);
4352 bios
->io_flag_condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 10]);
4353 bios
->init_function_tbl_ptr
= ROM16(bios
->data
[offset
+ 12]);
4356 static int parse_bit_A_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4359 * Parses the load detect values for g80 cards.
4361 * offset + 0 (16 bits): loadval table pointer
4364 uint16_t load_table_ptr
;
4365 uint8_t version
, headerlen
, entrylen
, num_entries
;
4367 if (bitentry
->length
!= 3) {
4368 NV_ERROR(dev
, "Do not understand BIT A table\n");
4372 load_table_ptr
= ROM16(bios
->data
[bitentry
->offset
]);
4374 if (load_table_ptr
== 0x0) {
4375 NV_ERROR(dev
, "Pointer to BIT loadval table invalid\n");
4379 version
= bios
->data
[load_table_ptr
];
4381 if (version
!= 0x10) {
4382 NV_ERROR(dev
, "BIT loadval table version %d.%d not supported\n",
4383 version
>> 4, version
& 0xF);
4387 headerlen
= bios
->data
[load_table_ptr
+ 1];
4388 entrylen
= bios
->data
[load_table_ptr
+ 2];
4389 num_entries
= bios
->data
[load_table_ptr
+ 3];
4391 if (headerlen
!= 4 || entrylen
!= 4 || num_entries
!= 2) {
4392 NV_ERROR(dev
, "Do not understand BIT loadval table\n");
4396 /* First entry is normal dac, 2nd tv-out perhaps? */
4397 bios
->dactestval
= ROM32(bios
->data
[load_table_ptr
+ headerlen
]) & 0x3ff;
4402 static int parse_bit_C_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4405 * offset + 8 (16 bits): PLL limits table pointer
4407 * There's more in here, but that's unknown.
4410 if (bitentry
->length
< 10) {
4411 NV_ERROR(dev
, "Do not understand BIT C table\n");
4415 bios
->pll_limit_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 8]);
4420 static int parse_bit_display_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4423 * Parses the flat panel table segment that the bit entry points to.
4424 * Starting at bitentry->offset:
4426 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4427 * records beginning with a freq.
4428 * offset + 2 (16 bits): mode table pointer
4431 if (bitentry
->length
!= 4) {
4432 NV_ERROR(dev
, "Do not understand BIT display table\n");
4436 bios
->fp
.fptablepointer
= ROM16(bios
->data
[bitentry
->offset
+ 2]);
4441 static int parse_bit_init_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4444 * Parses the init table segment that the bit entry points to.
4446 * See parse_script_table_pointers for layout
4449 if (bitentry
->length
< 14) {
4450 NV_ERROR(dev
, "Do not understand init table\n");
4454 parse_script_table_pointers(bios
, bitentry
->offset
);
4456 if (bitentry
->length
>= 16)
4457 bios
->some_script_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 14]);
4458 if (bitentry
->length
>= 18)
4459 bios
->init96_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 16]);
4464 static int parse_bit_i_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4467 * BIT 'i' (info?) table
4469 * offset + 0 (32 bits): BIOS version dword (as in B table)
4470 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4471 * offset + 13 (16 bits): pointer to table containing DAC load
4472 * detection comparison values
4474 * There's other things in the table, purpose unknown
4477 uint16_t daccmpoffset
;
4478 uint8_t dacver
, dacheaderlen
;
4480 if (bitentry
->length
< 6) {
4481 NV_ERROR(dev
, "BIT i table too short for needed information\n");
4485 parse_bios_version(dev
, bios
, bitentry
->offset
);
4488 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4489 * Quadro identity crisis), other bits possibly as for BMP feature byte
4491 bios
->feature_byte
= bios
->data
[bitentry
->offset
+ 5];
4492 bios
->is_mobile
= bios
->feature_byte
& FEATURE_MOBILE
;
4494 if (bitentry
->length
< 15) {
4495 NV_WARN(dev
, "BIT i table not long enough for DAC load "
4496 "detection comparison table\n");
4500 daccmpoffset
= ROM16(bios
->data
[bitentry
->offset
+ 13]);
4502 /* doesn't exist on g80 */
4507 * The first value in the table, following the header, is the
4508 * comparison value, the second entry is a comparison value for
4509 * TV load detection.
4512 dacver
= bios
->data
[daccmpoffset
];
4513 dacheaderlen
= bios
->data
[daccmpoffset
+ 1];
4515 if (dacver
!= 0x00 && dacver
!= 0x10) {
4516 NV_WARN(dev
, "DAC load detection comparison table version "
4517 "%d.%d not known\n", dacver
>> 4, dacver
& 0xf);
4521 bios
->dactestval
= ROM32(bios
->data
[daccmpoffset
+ dacheaderlen
]);
4522 bios
->tvdactestval
= ROM32(bios
->data
[daccmpoffset
+ dacheaderlen
+ 4]);
4527 static int parse_bit_lvds_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4530 * Parses the LVDS table segment that the bit entry points to.
4531 * Starting at bitentry->offset:
4533 * offset + 0 (16 bits): LVDS strap xlate table pointer
4536 if (bitentry
->length
!= 2) {
4537 NV_ERROR(dev
, "Do not understand BIT LVDS table\n");
4542 * No idea if it's still called the LVDS manufacturer table, but
4543 * the concept's close enough.
4545 bios
->fp
.lvdsmanufacturerpointer
= ROM16(bios
->data
[bitentry
->offset
]);
4551 parse_bit_M_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
4552 struct bit_entry
*bitentry
)
4555 * offset + 2 (8 bits): number of options in an
4556 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4557 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4558 * restrict option selection
4560 * There's a bunch of bits in this table other than the RAM restrict
4561 * stuff that we don't use - their use currently unknown
4565 * Older bios versions don't have a sufficiently long table for
4568 if (bitentry
->length
< 0x5)
4571 if (bitentry
->id
[1] < 2) {
4572 bios
->ram_restrict_group_count
= bios
->data
[bitentry
->offset
+ 2];
4573 bios
->ram_restrict_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 3]);
4575 bios
->ram_restrict_group_count
= bios
->data
[bitentry
->offset
+ 0];
4576 bios
->ram_restrict_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 1]);
4582 static int parse_bit_tmds_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
4585 * Parses the pointer to the TMDS table
4587 * Starting at bitentry->offset:
4589 * offset + 0 (16 bits): TMDS table pointer
4591 * The TMDS table is typically found just before the DCB table, with a
4592 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4595 * At offset +7 is a pointer to a script, which I don't know how to
4597 * At offset +9 is a pointer to another script, likewise
4598 * Offset +11 has a pointer to a table where the first word is a pxclk
4599 * frequency and the second word a pointer to a script, which should be
4600 * run if the comparison pxclk frequency is less than the pxclk desired.
4601 * This repeats for decreasing comparison frequencies
4602 * Offset +13 has a pointer to a similar table
4603 * The selection of table (and possibly +7/+9 script) is dictated by
4604 * "or" from the DCB.
4607 uint16_t tmdstableptr
, script1
, script2
;
4609 if (bitentry
->length
!= 2) {
4610 NV_ERROR(dev
, "Do not understand BIT TMDS table\n");
4614 tmdstableptr
= ROM16(bios
->data
[bitentry
->offset
]);
4616 if (tmdstableptr
== 0x0) {
4617 NV_ERROR(dev
, "Pointer to TMDS table invalid\n");
4621 /* nv50+ has v2.0, but we don't parse it atm */
4622 if (bios
->data
[tmdstableptr
] != 0x11) {
4624 "TMDS table revision %d.%d not currently supported\n",
4625 bios
->data
[tmdstableptr
] >> 4, bios
->data
[tmdstableptr
] & 0xf);
4630 * These two scripts are odd: they don't seem to get run even when
4631 * they are not stubbed.
4633 script1
= ROM16(bios
->data
[tmdstableptr
+ 7]);
4634 script2
= ROM16(bios
->data
[tmdstableptr
+ 9]);
4635 if (bios
->data
[script1
] != 'q' || bios
->data
[script2
] != 'q')
4636 NV_WARN(dev
, "TMDS table script pointers not stubbed\n");
4638 bios
->tmds
.output0_script_ptr
= ROM16(bios
->data
[tmdstableptr
+ 11]);
4639 bios
->tmds
.output1_script_ptr
= ROM16(bios
->data
[tmdstableptr
+ 13]);
4645 parse_bit_U_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
4646 struct bit_entry
*bitentry
)
4649 * Parses the pointer to the G80 output script tables
4651 * Starting at bitentry->offset:
4653 * offset + 0 (16 bits): output script table pointer
4656 uint16_t outputscripttableptr
;
4658 if (bitentry
->length
!= 3) {
4659 NV_ERROR(dev
, "Do not understand BIT U table\n");
4663 outputscripttableptr
= ROM16(bios
->data
[bitentry
->offset
]);
4664 bios
->display
.script_table_ptr
= outputscripttableptr
;
4669 parse_bit_displayport_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
4670 struct bit_entry
*bitentry
)
4672 bios
->display
.dp_table_ptr
= ROM16(bios
->data
[bitentry
->offset
]);
4678 int (* const parse_fn
)(struct drm_device
*, struct nvbios
*, struct bit_entry
*);
4681 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4684 parse_bit_table(struct nvbios
*bios
, const uint16_t bitoffset
,
4685 struct bit_table
*table
)
4687 struct drm_device
*dev
= bios
->dev
;
4688 uint8_t maxentries
= bios
->data
[bitoffset
+ 4];
4690 struct bit_entry bitentry
;
4692 for (i
= 0, offset
= bitoffset
+ 6; i
< maxentries
; i
++, offset
+= 6) {
4693 bitentry
.id
[0] = bios
->data
[offset
];
4695 if (bitentry
.id
[0] != table
->id
)
4698 bitentry
.id
[1] = bios
->data
[offset
+ 1];
4699 bitentry
.length
= ROM16(bios
->data
[offset
+ 2]);
4700 bitentry
.offset
= ROM16(bios
->data
[offset
+ 4]);
4702 return table
->parse_fn(dev
, bios
, &bitentry
);
4705 NV_INFO(dev
, "BIT table '%c' not found\n", table
->id
);
4710 parse_bit_structure(struct nvbios
*bios
, const uint16_t bitoffset
)
4715 * The only restriction on parsing order currently is having 'i' first
4716 * for use of bios->*_version or bios->feature_byte while parsing;
4717 * functions shouldn't be actually *doing* anything apart from pulling
4718 * data from the image into the bios struct, thus no interdependencies
4720 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('i', i
));
4721 if (ret
) /* info? */
4723 if (bios
->major_version
>= 0x60) /* g80+ */
4724 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('A', A
));
4725 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('C', C
));
4728 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('D', display
));
4729 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('I', init
));
4732 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('M', M
)); /* memory? */
4733 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('L', lvds
));
4734 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('T', tmds
));
4735 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('U', U
));
4736 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('d', displayport
));
4741 static int parse_bmp_structure(struct drm_device
*dev
, struct nvbios
*bios
, unsigned int offset
)
4744 * Parses the BMP structure for useful things, but does not act on them
4746 * offset + 5: BMP major version
4747 * offset + 6: BMP minor version
4748 * offset + 9: BMP feature byte
4749 * offset + 10: BCD encoded BIOS version
4751 * offset + 18: init script table pointer (for bios versions < 5.10h)
4752 * offset + 20: extra init script table pointer (for bios
4755 * offset + 24: memory init table pointer (used on early bios versions)
4756 * offset + 26: SDR memory sequencing setup data table
4757 * offset + 28: DDR memory sequencing setup data table
4759 * offset + 54: index of I2C CRTC pair to use for CRT output
4760 * offset + 55: index of I2C CRTC pair to use for TV output
4761 * offset + 56: index of I2C CRTC pair to use for flat panel output
4762 * offset + 58: write CRTC index for I2C pair 0
4763 * offset + 59: read CRTC index for I2C pair 0
4764 * offset + 60: write CRTC index for I2C pair 1
4765 * offset + 61: read CRTC index for I2C pair 1
4767 * offset + 67: maximum internal PLL frequency (single stage PLL)
4768 * offset + 71: minimum internal PLL frequency (single stage PLL)
4770 * offset + 75: script table pointers, as described in
4771 * parse_script_table_pointers
4773 * offset + 89: TMDS single link output A table pointer
4774 * offset + 91: TMDS single link output B table pointer
4775 * offset + 95: LVDS single link output A table pointer
4776 * offset + 105: flat panel timings table pointer
4777 * offset + 107: flat panel strapping translation table pointer
4778 * offset + 117: LVDS manufacturer panel config table pointer
4779 * offset + 119: LVDS manufacturer strapping translation table pointer
4781 * offset + 142: PLL limits table pointer
4783 * offset + 156: minimum pixel clock for LVDS dual link
4786 uint8_t *bmp
= &bios
->data
[offset
], bmp_version_major
, bmp_version_minor
;
4788 uint16_t legacy_scripts_offset
, legacy_i2c_offset
;
4790 /* load needed defaults in case we can't parse this info */
4791 bios
->dcb
.i2c
[0].write
= NV_CIO_CRE_DDC_WR__INDEX
;
4792 bios
->dcb
.i2c
[0].read
= NV_CIO_CRE_DDC_STATUS__INDEX
;
4793 bios
->dcb
.i2c
[1].write
= NV_CIO_CRE_DDC0_WR__INDEX
;
4794 bios
->dcb
.i2c
[1].read
= NV_CIO_CRE_DDC0_STATUS__INDEX
;
4795 bios
->digital_min_front_porch
= 0x4b;
4796 bios
->fmaxvco
= 256000;
4797 bios
->fminvco
= 128000;
4798 bios
->fp
.duallink_transition_clk
= 90000;
4800 bmp_version_major
= bmp
[5];
4801 bmp_version_minor
= bmp
[6];
4803 NV_TRACE(dev
, "BMP version %d.%d\n",
4804 bmp_version_major
, bmp_version_minor
);
4807 * Make sure that 0x36 is blank and can't be mistaken for a DCB
4808 * pointer on early versions
4810 if (bmp_version_major
< 5)
4811 *(uint16_t *)&bios
->data
[0x36] = 0;
4814 * Seems that the minor version was 1 for all major versions prior
4815 * to 5. Version 6 could theoretically exist, but I suspect BIT
4818 if ((bmp_version_major
< 5 && bmp_version_minor
!= 1) || bmp_version_major
> 5) {
4819 NV_ERROR(dev
, "You have an unsupported BMP version. "
4820 "Please send in your bios\n");
4824 if (bmp_version_major
== 0)
4825 /* nothing that's currently useful in this version */
4827 else if (bmp_version_major
== 1)
4828 bmplength
= 44; /* exact for 1.01 */
4829 else if (bmp_version_major
== 2)
4830 bmplength
= 48; /* exact for 2.01 */
4831 else if (bmp_version_major
== 3)
4833 /* guessed - mem init tables added in this version */
4834 else if (bmp_version_major
== 4 || bmp_version_minor
< 0x1)
4835 /* don't know if 5.0 exists... */
4837 /* guessed - BMP I2C indices added in version 4*/
4838 else if (bmp_version_minor
< 0x6)
4839 bmplength
= 67; /* exact for 5.01 */
4840 else if (bmp_version_minor
< 0x10)
4841 bmplength
= 75; /* exact for 5.06 */
4842 else if (bmp_version_minor
== 0x10)
4843 bmplength
= 89; /* exact for 5.10h */
4844 else if (bmp_version_minor
< 0x14)
4845 bmplength
= 118; /* exact for 5.11h */
4846 else if (bmp_version_minor
< 0x24)
4848 * Not sure of version where pll limits came in;
4849 * certainly exist by 0x24 though.
4851 /* length not exact: this is long enough to get lvds members */
4853 else if (bmp_version_minor
< 0x27)
4855 * Length not exact: this is long enough to get pll limit
4861 * Length not exact: this is long enough to get dual link
4867 if (nv_cksum(bmp
, 8)) {
4868 NV_ERROR(dev
, "Bad BMP checksum\n");
4873 * Bit 4 seems to indicate either a mobile bios or a quadro card --
4874 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
4875 * (not nv10gl), bit 5 that the flat panel tables are present, and
4878 bios
->feature_byte
= bmp
[9];
4880 parse_bios_version(dev
, bios
, offset
+ 10);
4882 if (bmp_version_major
< 5 || bmp_version_minor
< 0x10)
4883 bios
->old_style_init
= true;
4884 legacy_scripts_offset
= 18;
4885 if (bmp_version_major
< 2)
4886 legacy_scripts_offset
-= 4;
4887 bios
->init_script_tbls_ptr
= ROM16(bmp
[legacy_scripts_offset
]);
4888 bios
->extra_init_script_tbl_ptr
= ROM16(bmp
[legacy_scripts_offset
+ 2]);
4890 if (bmp_version_major
> 2) { /* appears in BMP 3 */
4891 bios
->legacy
.mem_init_tbl_ptr
= ROM16(bmp
[24]);
4892 bios
->legacy
.sdr_seq_tbl_ptr
= ROM16(bmp
[26]);
4893 bios
->legacy
.ddr_seq_tbl_ptr
= ROM16(bmp
[28]);
4896 legacy_i2c_offset
= 0x48; /* BMP version 2 & 3 */
4898 legacy_i2c_offset
= offset
+ 54;
4899 bios
->legacy
.i2c_indices
.crt
= bios
->data
[legacy_i2c_offset
];
4900 bios
->legacy
.i2c_indices
.tv
= bios
->data
[legacy_i2c_offset
+ 1];
4901 bios
->legacy
.i2c_indices
.panel
= bios
->data
[legacy_i2c_offset
+ 2];
4902 bios
->dcb
.i2c
[0].write
= bios
->data
[legacy_i2c_offset
+ 4];
4903 bios
->dcb
.i2c
[0].read
= bios
->data
[legacy_i2c_offset
+ 5];
4904 bios
->dcb
.i2c
[1].write
= bios
->data
[legacy_i2c_offset
+ 6];
4905 bios
->dcb
.i2c
[1].read
= bios
->data
[legacy_i2c_offset
+ 7];
4907 if (bmplength
> 74) {
4908 bios
->fmaxvco
= ROM32(bmp
[67]);
4909 bios
->fminvco
= ROM32(bmp
[71]);
4912 parse_script_table_pointers(bios
, offset
+ 75);
4913 if (bmplength
> 94) {
4914 bios
->tmds
.output0_script_ptr
= ROM16(bmp
[89]);
4915 bios
->tmds
.output1_script_ptr
= ROM16(bmp
[91]);
4917 * Never observed in use with lvds scripts, but is reused for
4918 * 18/24 bit panel interface default for EDID equipped panels
4919 * (if_is_24bit not set directly to avoid any oscillation).
4921 bios
->legacy
.lvds_single_a_script_ptr
= ROM16(bmp
[95]);
4923 if (bmplength
> 108) {
4924 bios
->fp
.fptablepointer
= ROM16(bmp
[105]);
4925 bios
->fp
.fpxlatetableptr
= ROM16(bmp
[107]);
4926 bios
->fp
.xlatwidth
= 1;
4928 if (bmplength
> 120) {
4929 bios
->fp
.lvdsmanufacturerpointer
= ROM16(bmp
[117]);
4930 bios
->fp
.fpxlatemanufacturertableptr
= ROM16(bmp
[119]);
4932 if (bmplength
> 143)
4933 bios
->pll_limit_tbl_ptr
= ROM16(bmp
[142]);
4935 if (bmplength
> 157)
4936 bios
->fp
.duallink_transition_clk
= ROM16(bmp
[156]) * 10;
4941 static uint16_t findstr(uint8_t *data
, int n
, const uint8_t *str
, int len
)
4945 for (i
= 0; i
<= (n
- len
); i
++) {
4946 for (j
= 0; j
< len
; j
++)
4947 if (data
[i
+ j
] != str
[j
])
4957 read_dcb_i2c_entry(struct drm_device
*dev
, int dcb_version
, uint8_t *i2ctable
, int index
, struct dcb_i2c_entry
*i2c
)
4959 uint8_t dcb_i2c_ver
= dcb_version
, headerlen
= 0, entry_len
= 4;
4960 int i2c_entries
= DCB_MAX_NUM_I2C_ENTRIES
;
4961 int recordoffset
= 0, rdofs
= 1, wrofs
= 0;
4962 uint8_t port_type
= 0;
4967 if (dcb_version
>= 0x30) {
4968 if (i2ctable
[0] != dcb_version
) /* necessary? */
4970 "DCB I2C table version mismatch (%02X vs %02X)\n",
4971 i2ctable
[0], dcb_version
);
4972 dcb_i2c_ver
= i2ctable
[0];
4973 headerlen
= i2ctable
[1];
4974 if (i2ctable
[2] <= DCB_MAX_NUM_I2C_ENTRIES
)
4975 i2c_entries
= i2ctable
[2];
4978 "DCB I2C table has more entries than indexable "
4979 "(%d entries, max %d)\n", i2ctable
[2],
4980 DCB_MAX_NUM_I2C_ENTRIES
);
4981 entry_len
= i2ctable
[3];
4982 /* [4] is i2c_default_indices, read in parse_dcb_table() */
4985 * It's your own fault if you call this function on a DCB 1.1 BIOS --
4986 * the test below is for DCB 1.2
4988 if (dcb_version
< 0x14) {
4996 if (index
>= i2c_entries
) {
4997 NV_ERROR(dev
, "DCB I2C index too big (%d >= %d)\n",
4998 index
, i2ctable
[2]);
5001 if (i2ctable
[headerlen
+ entry_len
* index
+ 3] == 0xff) {
5002 NV_ERROR(dev
, "DCB I2C entry invalid\n");
5006 if (dcb_i2c_ver
>= 0x30) {
5007 port_type
= i2ctable
[headerlen
+ recordoffset
+ 3 + entry_len
* index
];
5010 * Fixup for chips using same address offset for read and
5013 if (port_type
== 4) /* seen on C51 */
5015 if (port_type
>= 5) /* G80+ */
5019 if (dcb_i2c_ver
>= 0x40 && port_type
!= 5 && port_type
!= 6)
5020 NV_WARN(dev
, "DCB I2C table has port type %d\n", port_type
);
5022 i2c
->port_type
= port_type
;
5023 i2c
->read
= i2ctable
[headerlen
+ recordoffset
+ rdofs
+ entry_len
* index
];
5024 i2c
->write
= i2ctable
[headerlen
+ recordoffset
+ wrofs
+ entry_len
* index
];
5029 static struct dcb_gpio_entry
*
5030 new_gpio_entry(struct nvbios
*bios
)
5032 struct dcb_gpio_table
*gpio
= &bios
->dcb
.gpio
;
5034 return &gpio
->entry
[gpio
->entries
++];
5037 struct dcb_gpio_entry
*
5038 nouveau_bios_gpio_entry(struct drm_device
*dev
, enum dcb_gpio_tag tag
)
5040 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5041 struct nvbios
*bios
= &dev_priv
->vbios
;
5044 for (i
= 0; i
< bios
->dcb
.gpio
.entries
; i
++) {
5045 if (bios
->dcb
.gpio
.entry
[i
].tag
!= tag
)
5048 return &bios
->dcb
.gpio
.entry
[i
];
5055 parse_dcb30_gpio_entry(struct nvbios
*bios
, uint16_t offset
)
5057 struct dcb_gpio_entry
*gpio
;
5058 uint16_t ent
= ROM16(bios
->data
[offset
]);
5059 uint8_t line
= ent
& 0x1f,
5060 tag
= ent
>> 5 & 0x3f,
5061 flags
= ent
>> 11 & 0x1f;
5066 gpio
= new_gpio_entry(bios
);
5070 gpio
->invert
= flags
!= 4;
5075 parse_dcb40_gpio_entry(struct nvbios
*bios
, uint16_t offset
)
5077 uint32_t entry
= ROM32(bios
->data
[offset
]);
5078 struct dcb_gpio_entry
*gpio
;
5080 if ((entry
& 0x0000ff00) == 0x0000ff00)
5083 gpio
= new_gpio_entry(bios
);
5084 gpio
->tag
= (entry
& 0x0000ff00) >> 8;
5085 gpio
->line
= (entry
& 0x0000001f) >> 0;
5086 gpio
->state_default
= (entry
& 0x01000000) >> 24;
5087 gpio
->state
[0] = (entry
& 0x18000000) >> 27;
5088 gpio
->state
[1] = (entry
& 0x60000000) >> 29;
5089 gpio
->entry
= entry
;
5093 parse_dcb_gpio_table(struct nvbios
*bios
)
5095 struct drm_device
*dev
= bios
->dev
;
5096 uint16_t gpio_table_ptr
= bios
->dcb
.gpio_table_ptr
;
5097 uint8_t *gpio_table
= &bios
->data
[gpio_table_ptr
];
5098 int header_len
= gpio_table
[1],
5099 entries
= gpio_table
[2],
5100 entry_len
= gpio_table
[3];
5101 void (*parse_entry
)(struct nvbios
*, uint16_t) = NULL
;
5104 if (bios
->dcb
.version
>= 0x40) {
5105 if (gpio_table_ptr
&& entry_len
!= 4) {
5106 NV_WARN(dev
, "Invalid DCB GPIO table entry length.\n");
5110 parse_entry
= parse_dcb40_gpio_entry
;
5112 } else if (bios
->dcb
.version
>= 0x30) {
5113 if (gpio_table_ptr
&& entry_len
!= 2) {
5114 NV_WARN(dev
, "Invalid DCB GPIO table entry length.\n");
5118 parse_entry
= parse_dcb30_gpio_entry
;
5120 } else if (bios
->dcb
.version
>= 0x22) {
5122 * DCBs older than v3.0 don't really have a GPIO
5123 * table, instead they keep some GPIO info at fixed
5126 uint16_t dcbptr
= ROM16(bios
->data
[0x36]);
5127 uint8_t *tvdac_gpio
= &bios
->data
[dcbptr
- 5];
5129 if (tvdac_gpio
[0] & 1) {
5130 struct dcb_gpio_entry
*gpio
= new_gpio_entry(bios
);
5132 gpio
->tag
= DCB_GPIO_TVDAC0
;
5133 gpio
->line
= tvdac_gpio
[1] >> 4;
5134 gpio
->invert
= tvdac_gpio
[0] & 2;
5138 if (!gpio_table_ptr
)
5141 if (entries
> DCB_MAX_NUM_GPIO_ENTRIES
) {
5142 NV_WARN(dev
, "Too many entries in the DCB GPIO table.\n");
5143 entries
= DCB_MAX_NUM_GPIO_ENTRIES
;
5146 for (i
= 0; i
< entries
; i
++)
5147 parse_entry(bios
, gpio_table_ptr
+ header_len
+ entry_len
* i
);
5150 struct dcb_connector_table_entry
*
5151 nouveau_bios_connector_entry(struct drm_device
*dev
, int index
)
5153 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5154 struct nvbios
*bios
= &dev_priv
->vbios
;
5155 struct dcb_connector_table_entry
*cte
;
5157 if (index
>= bios
->dcb
.connector
.entries
)
5160 cte
= &bios
->dcb
.connector
.entry
[index
];
5161 if (cte
->type
== 0xff)
5167 static enum dcb_connector_type
5168 divine_connector_type(struct nvbios
*bios
, int index
)
5170 struct dcb_table
*dcb
= &bios
->dcb
;
5171 unsigned encoders
= 0, type
= DCB_CONNECTOR_NONE
;
5174 for (i
= 0; i
< dcb
->entries
; i
++) {
5175 if (dcb
->entry
[i
].connector
== index
)
5176 encoders
|= (1 << dcb
->entry
[i
].type
);
5179 if (encoders
& (1 << OUTPUT_DP
)) {
5180 if (encoders
& (1 << OUTPUT_TMDS
))
5181 type
= DCB_CONNECTOR_DP
;
5183 type
= DCB_CONNECTOR_eDP
;
5185 if (encoders
& (1 << OUTPUT_TMDS
)) {
5186 if (encoders
& (1 << OUTPUT_ANALOG
))
5187 type
= DCB_CONNECTOR_DVI_I
;
5189 type
= DCB_CONNECTOR_DVI_D
;
5191 if (encoders
& (1 << OUTPUT_ANALOG
)) {
5192 type
= DCB_CONNECTOR_VGA
;
5194 if (encoders
& (1 << OUTPUT_LVDS
)) {
5195 type
= DCB_CONNECTOR_LVDS
;
5197 if (encoders
& (1 << OUTPUT_TV
)) {
5198 type
= DCB_CONNECTOR_TV_0
;
5205 apply_dcb_connector_quirks(struct nvbios
*bios
, int idx
)
5207 struct dcb_connector_table_entry
*cte
= &bios
->dcb
.connector
.entry
[idx
];
5208 struct drm_device
*dev
= bios
->dev
;
5210 /* Gigabyte NX85T */
5211 if ((dev
->pdev
->device
== 0x0421) &&
5212 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
5213 (dev
->pdev
->subsystem_device
== 0x344c)) {
5214 if (cte
->type
== DCB_CONNECTOR_HDMI_1
)
5215 cte
->type
= DCB_CONNECTOR_DVI_I
;
5220 parse_dcb_connector_table(struct nvbios
*bios
)
5222 struct drm_device
*dev
= bios
->dev
;
5223 struct dcb_connector_table
*ct
= &bios
->dcb
.connector
;
5224 struct dcb_connector_table_entry
*cte
;
5225 uint8_t *conntab
= &bios
->data
[bios
->dcb
.connector_table_ptr
];
5229 if (!bios
->dcb
.connector_table_ptr
) {
5230 NV_DEBUG_KMS(dev
, "No DCB connector table present\n");
5234 NV_INFO(dev
, "DCB connector table: VHER 0x%02x %d %d %d\n",
5235 conntab
[0], conntab
[1], conntab
[2], conntab
[3]);
5236 if ((conntab
[0] != 0x30 && conntab
[0] != 0x40) ||
5237 (conntab
[3] != 2 && conntab
[3] != 4)) {
5238 NV_ERROR(dev
, " Unknown! Please report.\n");
5242 ct
->entries
= conntab
[2];
5244 entry
= conntab
+ conntab
[1];
5245 cte
= &ct
->entry
[0];
5246 for (i
= 0; i
< conntab
[2]; i
++, entry
+= conntab
[3], cte
++) {
5248 if (conntab
[3] == 2)
5249 cte
->entry
= ROM16(entry
[0]);
5251 cte
->entry
= ROM32(entry
[0]);
5253 cte
->type
= (cte
->entry
& 0x000000ff) >> 0;
5254 cte
->index2
= (cte
->entry
& 0x00000f00) >> 8;
5255 switch (cte
->entry
& 0x00033000) {
5257 cte
->gpio_tag
= 0x07;
5260 cte
->gpio_tag
= 0x08;
5263 cte
->gpio_tag
= 0x51;
5266 cte
->gpio_tag
= 0x52;
5269 cte
->gpio_tag
= 0xff;
5273 if (cte
->type
== 0xff)
5276 apply_dcb_connector_quirks(bios
, i
);
5278 NV_INFO(dev
, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5279 i
, cte
->entry
, cte
->type
, cte
->index
, cte
->gpio_tag
);
5281 /* check for known types, fallback to guessing the type
5282 * from attached encoders if we hit an unknown.
5284 switch (cte
->type
) {
5285 case DCB_CONNECTOR_VGA
:
5286 case DCB_CONNECTOR_TV_0
:
5287 case DCB_CONNECTOR_TV_1
:
5288 case DCB_CONNECTOR_TV_3
:
5289 case DCB_CONNECTOR_DVI_I
:
5290 case DCB_CONNECTOR_DVI_D
:
5291 case DCB_CONNECTOR_LVDS
:
5292 case DCB_CONNECTOR_DP
:
5293 case DCB_CONNECTOR_eDP
:
5294 case DCB_CONNECTOR_HDMI_0
:
5295 case DCB_CONNECTOR_HDMI_1
:
5298 cte
->type
= divine_connector_type(bios
, cte
->index
);
5299 NV_WARN(dev
, "unknown type, using 0x%02x\n", cte
->type
);
5303 if (nouveau_override_conntype
) {
5304 int type
= divine_connector_type(bios
, cte
->index
);
5305 if (type
!= cte
->type
)
5306 NV_WARN(dev
, " -> type 0x%02x\n", cte
->type
);
5312 static struct dcb_entry
*new_dcb_entry(struct dcb_table
*dcb
)
5314 struct dcb_entry
*entry
= &dcb
->entry
[dcb
->entries
];
5316 memset(entry
, 0, sizeof(struct dcb_entry
));
5317 entry
->index
= dcb
->entries
++;
5322 static void fabricate_vga_output(struct dcb_table
*dcb
, int i2c
, int heads
)
5324 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5327 entry
->i2c_index
= i2c
;
5328 entry
->heads
= heads
;
5329 entry
->location
= DCB_LOC_ON_CHIP
;
5330 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5333 static void fabricate_dvi_i_output(struct dcb_table
*dcb
, bool twoHeads
)
5335 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5338 entry
->i2c_index
= LEGACY_I2C_PANEL
;
5339 entry
->heads
= twoHeads
? 3 : 1;
5340 entry
->location
= !DCB_LOC_ON_CHIP
; /* ie OFF CHIP */
5341 entry
->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5342 entry
->duallink_possible
= false; /* SiI164 and co. are single link */
5346 * For dvi-a either crtc probably works, but my card appears to only
5347 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5348 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5349 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5350 * the monitor picks up the mode res ok and lights up, but no pixel
5351 * data appears, so the board manufacturer probably connected up the
5352 * sync lines, but missed the video traces / components
5354 * with this introduction, dvi-a left as an exercise for the reader.
5356 fabricate_vga_output(dcb
, LEGACY_I2C_PANEL
, entry
->heads
);
5360 static void fabricate_tv_output(struct dcb_table
*dcb
, bool twoHeads
)
5362 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5365 entry
->i2c_index
= LEGACY_I2C_TV
;
5366 entry
->heads
= twoHeads
? 3 : 1;
5367 entry
->location
= !DCB_LOC_ON_CHIP
; /* ie OFF CHIP */
5371 parse_dcb20_entry(struct drm_device
*dev
, struct dcb_table
*dcb
,
5372 uint32_t conn
, uint32_t conf
, struct dcb_entry
*entry
)
5374 entry
->type
= conn
& 0xf;
5375 entry
->i2c_index
= (conn
>> 4) & 0xf;
5376 entry
->heads
= (conn
>> 8) & 0xf;
5377 if (dcb
->version
>= 0x40)
5378 entry
->connector
= (conn
>> 12) & 0xf;
5379 entry
->bus
= (conn
>> 16) & 0xf;
5380 entry
->location
= (conn
>> 20) & 0x3;
5381 entry
->or = (conn
>> 24) & 0xf;
5383 * Normal entries consist of a single bit, but dual link has the
5384 * next most significant bit set too
5386 entry
->duallink_possible
=
5387 ((1 << (ffs(entry
->or) - 1)) * 3 == entry
->or);
5389 switch (entry
->type
) {
5392 * Although the rest of a CRT conf dword is usually
5393 * zeros, mac biosen have stuff there so we must mask
5395 entry
->crtconf
.maxfreq
= (dcb
->version
< 0x30) ?
5396 (conf
& 0xffff) * 10 :
5397 (conf
& 0xff) * 10000;
5403 entry
->lvdsconf
.use_straps_for_mode
= true;
5404 if (dcb
->version
< 0x22) {
5407 * The laptop in bug 14567 lies and claims to not use
5408 * straps when it does, so assume all DCB 2.0 laptops
5409 * use straps, until a broken EDID using one is produced
5411 entry
->lvdsconf
.use_straps_for_mode
= true;
5413 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5414 * mean the same thing (probably wrong, but might work)
5416 if (conf
& 0x4 || conf
& 0x8)
5417 entry
->lvdsconf
.use_power_scripts
= true;
5421 entry
->lvdsconf
.use_power_scripts
= true;
5425 * Until we even try to use these on G8x, it's
5426 * useless reporting unknown bits. They all are.
5428 if (dcb
->version
>= 0x40)
5431 NV_ERROR(dev
, "Unknown LVDS configuration bits, "
5438 if (dcb
->version
>= 0x30)
5439 entry
->tvconf
.has_component_output
= conf
& (0x8 << 4);
5441 entry
->tvconf
.has_component_output
= false;
5446 entry
->dpconf
.sor
.link
= (conf
& 0x00000030) >> 4;
5447 entry
->dpconf
.link_bw
= (conf
& 0x00e00000) >> 21;
5448 switch ((conf
& 0x0f000000) >> 24) {
5450 entry
->dpconf
.link_nr
= 4;
5453 entry
->dpconf
.link_nr
= 2;
5456 entry
->dpconf
.link_nr
= 1;
5461 entry
->tmdsconf
.sor
.link
= (conf
& 0x00000030) >> 4;
5464 /* weird g80 mobile type that "nv" treats as a terminator */
5471 /* unsure what DCB version introduces this, 3.0? */
5472 if (conf
& 0x100000)
5473 entry
->i2c_upper_default
= true;
5479 parse_dcb15_entry(struct drm_device
*dev
, struct dcb_table
*dcb
,
5480 uint32_t conn
, uint32_t conf
, struct dcb_entry
*entry
)
5482 switch (conn
& 0x0000000f) {
5484 entry
->type
= OUTPUT_ANALOG
;
5487 entry
->type
= OUTPUT_TV
;
5491 entry
->type
= OUTPUT_LVDS
;
5494 switch ((conn
& 0x000000f0) >> 4) {
5496 entry
->type
= OUTPUT_TMDS
;
5499 entry
->type
= OUTPUT_LVDS
;
5502 NV_ERROR(dev
, "Unknown DCB subtype 4/%d\n",
5503 (conn
& 0x000000f0) >> 4);
5508 NV_ERROR(dev
, "Unknown DCB type %d\n", conn
& 0x0000000f);
5512 entry
->i2c_index
= (conn
& 0x0003c000) >> 14;
5513 entry
->heads
= ((conn
& 0x001c0000) >> 18) + 1;
5514 entry
->or = entry
->heads
; /* same as heads, hopefully safe enough */
5515 entry
->location
= (conn
& 0x01e00000) >> 21;
5516 entry
->bus
= (conn
& 0x0e000000) >> 25;
5517 entry
->duallink_possible
= false;
5519 switch (entry
->type
) {
5521 entry
->crtconf
.maxfreq
= (conf
& 0xffff) * 10;
5524 entry
->tvconf
.has_component_output
= false;
5528 * Invent a DVI-A output, by copying the fields of the DVI-D
5529 * output; reported to work by math_b on an NV20(!).
5531 fabricate_vga_output(dcb
, entry
->i2c_index
, entry
->heads
);
5534 if ((conn
& 0x00003f00) != 0x10)
5535 entry
->lvdsconf
.use_straps_for_mode
= true;
5536 entry
->lvdsconf
.use_power_scripts
= true;
5545 static bool parse_dcb_entry(struct drm_device
*dev
, struct dcb_table
*dcb
,
5546 uint32_t conn
, uint32_t conf
)
5548 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5551 if (dcb
->version
>= 0x20)
5552 ret
= parse_dcb20_entry(dev
, dcb
, conn
, conf
, entry
);
5554 ret
= parse_dcb15_entry(dev
, dcb
, conn
, conf
, entry
);
5558 read_dcb_i2c_entry(dev
, dcb
->version
, dcb
->i2c_table
,
5559 entry
->i2c_index
, &dcb
->i2c
[entry
->i2c_index
]);
5565 void merge_like_dcb_entries(struct drm_device
*dev
, struct dcb_table
*dcb
)
5568 * DCB v2.0 lists each output combination separately.
5569 * Here we merge compatible entries to have fewer outputs, with
5573 int i
, newentries
= 0;
5575 for (i
= 0; i
< dcb
->entries
; i
++) {
5576 struct dcb_entry
*ient
= &dcb
->entry
[i
];
5579 for (j
= i
+ 1; j
< dcb
->entries
; j
++) {
5580 struct dcb_entry
*jent
= &dcb
->entry
[j
];
5582 if (jent
->type
== 100) /* already merged entry */
5585 /* merge heads field when all other fields the same */
5586 if (jent
->i2c_index
== ient
->i2c_index
&&
5587 jent
->type
== ient
->type
&&
5588 jent
->location
== ient
->location
&&
5589 jent
->or == ient
->or) {
5590 NV_TRACE(dev
, "Merging DCB entries %d and %d\n",
5592 ient
->heads
|= jent
->heads
;
5593 jent
->type
= 100; /* dummy value */
5598 /* Compact entries merged into others out of dcb */
5599 for (i
= 0; i
< dcb
->entries
; i
++) {
5600 if (dcb
->entry
[i
].type
== 100)
5603 if (newentries
!= i
) {
5604 dcb
->entry
[newentries
] = dcb
->entry
[i
];
5605 dcb
->entry
[newentries
].index
= newentries
;
5610 dcb
->entries
= newentries
;
5614 parse_dcb_table(struct drm_device
*dev
, struct nvbios
*bios
, bool twoHeads
)
5616 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5617 struct dcb_table
*dcb
= &bios
->dcb
;
5618 uint16_t dcbptr
= 0, i2ctabptr
= 0;
5620 uint8_t headerlen
= 0x4, entries
= DCB_MAX_NUM_ENTRIES
;
5621 bool configblock
= true;
5622 int recordlength
= 8, confofs
= 4;
5625 /* get the offset from 0x36 */
5626 if (dev_priv
->card_type
> NV_04
) {
5627 dcbptr
= ROM16(bios
->data
[0x36]);
5628 if (dcbptr
== 0x0000)
5629 NV_WARN(dev
, "No output data (DCB) found in BIOS\n");
5632 /* this situation likely means a really old card, pre DCB */
5633 if (dcbptr
== 0x0) {
5634 NV_INFO(dev
, "Assuming a CRT output exists\n");
5635 fabricate_vga_output(dcb
, LEGACY_I2C_CRT
, 1);
5637 if (nv04_tv_identify(dev
, bios
->legacy
.i2c_indices
.tv
) >= 0)
5638 fabricate_tv_output(dcb
, twoHeads
);
5643 dcbtable
= &bios
->data
[dcbptr
];
5645 /* get DCB version */
5646 dcb
->version
= dcbtable
[0];
5647 NV_TRACE(dev
, "Found Display Configuration Block version %d.%d\n",
5648 dcb
->version
>> 4, dcb
->version
& 0xf);
5650 if (dcb
->version
>= 0x20) { /* NV17+ */
5653 if (dcb
->version
>= 0x30) { /* NV40+ */
5654 headerlen
= dcbtable
[1];
5655 entries
= dcbtable
[2];
5656 recordlength
= dcbtable
[3];
5657 i2ctabptr
= ROM16(dcbtable
[4]);
5658 sig
= ROM32(dcbtable
[6]);
5659 dcb
->gpio_table_ptr
= ROM16(dcbtable
[10]);
5660 dcb
->connector_table_ptr
= ROM16(dcbtable
[20]);
5662 i2ctabptr
= ROM16(dcbtable
[2]);
5663 sig
= ROM32(dcbtable
[4]);
5667 if (sig
!= 0x4edcbdcb) {
5668 NV_ERROR(dev
, "Bad Display Configuration Block "
5669 "signature (%08X)\n", sig
);
5672 } else if (dcb
->version
>= 0x15) { /* some NV11 and NV20 */
5673 char sig
[8] = { 0 };
5675 strncpy(sig
, (char *)&dcbtable
[-7], 7);
5676 i2ctabptr
= ROM16(dcbtable
[2]);
5680 if (strcmp(sig
, "DEV_REC")) {
5681 NV_ERROR(dev
, "Bad Display Configuration Block "
5682 "signature (%s)\n", sig
);
5687 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5688 * has the same single (crt) entry, even when tv-out present, so
5689 * the conclusion is this version cannot really be used.
5690 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5691 * 5 entries, which are not specific to the card and so no use.
5692 * v1.2 does have an I2C table that read_dcb_i2c_table can
5693 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5694 * pointer, so use the indices parsed in parse_bmp_structure.
5695 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5697 NV_TRACEWARN(dev
, "No useful information in BIOS output table; "
5698 "adding all possible outputs\n");
5699 fabricate_vga_output(dcb
, LEGACY_I2C_CRT
, 1);
5702 * Attempt to detect TV before DVI because the test
5703 * for the former is more accurate and it rules the
5706 if (nv04_tv_identify(dev
,
5707 bios
->legacy
.i2c_indices
.tv
) >= 0)
5708 fabricate_tv_output(dcb
, twoHeads
);
5710 else if (bios
->tmds
.output0_script_ptr
||
5711 bios
->tmds
.output1_script_ptr
)
5712 fabricate_dvi_i_output(dcb
, twoHeads
);
5718 NV_WARN(dev
, "No pointer to DCB I2C port table\n");
5720 dcb
->i2c_table
= &bios
->data
[i2ctabptr
];
5721 if (dcb
->version
>= 0x30)
5722 dcb
->i2c_default_indices
= dcb
->i2c_table
[4];
5725 if (entries
> DCB_MAX_NUM_ENTRIES
)
5726 entries
= DCB_MAX_NUM_ENTRIES
;
5728 for (i
= 0; i
< entries
; i
++) {
5729 uint32_t connection
, config
= 0;
5731 connection
= ROM32(dcbtable
[headerlen
+ recordlength
* i
]);
5733 config
= ROM32(dcbtable
[headerlen
+ confofs
+ recordlength
* i
]);
5735 /* seen on an NV11 with DCB v1.5 */
5736 if (connection
== 0x00000000)
5739 /* seen on an NV17 with DCB v2.0 */
5740 if (connection
== 0xffffffff)
5743 if ((connection
& 0x0000000f) == 0x0000000f)
5746 NV_TRACEWARN(dev
, "Raw DCB entry %d: %08x %08x\n",
5747 dcb
->entries
, connection
, config
);
5749 if (!parse_dcb_entry(dev
, dcb
, connection
, config
))
5754 * apart for v2.1+ not being known for requiring merging, this
5755 * guarantees dcbent->index is the index of the entry in the rom image
5757 if (dcb
->version
< 0x21)
5758 merge_like_dcb_entries(dev
, dcb
);
5763 parse_dcb_gpio_table(bios
);
5764 parse_dcb_connector_table(bios
);
5769 fixup_legacy_connector(struct nvbios
*bios
)
5771 struct dcb_table
*dcb
= &bios
->dcb
;
5772 int i
, i2c
, i2c_conn
[DCB_MAX_NUM_I2C_ENTRIES
] = { };
5775 * DCB 3.0 also has the table in most cases, but there are some cards
5776 * where the table is filled with stub entries, and the DCB entriy
5777 * indices are all 0. We don't need the connector indices on pre-G80
5778 * chips (yet?) so limit the use to DCB 4.0 and above.
5780 if (dcb
->version
>= 0x40)
5783 dcb
->connector
.entries
= 0;
5786 * No known connector info before v3.0, so make it up. the rule here
5787 * is: anything on the same i2c bus is considered to be on the same
5788 * connector. any output without an associated i2c bus is assigned
5789 * its own unique connector index.
5791 for (i
= 0; i
< dcb
->entries
; i
++) {
5793 * Ignore the I2C index for on-chip TV-out, as there
5794 * are cards with bogus values (nv31m in bug 23212),
5795 * and it's otherwise useless.
5797 if (dcb
->entry
[i
].type
== OUTPUT_TV
&&
5798 dcb
->entry
[i
].location
== DCB_LOC_ON_CHIP
)
5799 dcb
->entry
[i
].i2c_index
= 0xf;
5800 i2c
= dcb
->entry
[i
].i2c_index
;
5802 if (i2c_conn
[i2c
]) {
5803 dcb
->entry
[i
].connector
= i2c_conn
[i2c
] - 1;
5807 dcb
->entry
[i
].connector
= dcb
->connector
.entries
++;
5809 i2c_conn
[i2c
] = dcb
->connector
.entries
;
5812 /* Fake the connector table as well as just connector indices */
5813 for (i
= 0; i
< dcb
->connector
.entries
; i
++) {
5814 dcb
->connector
.entry
[i
].index
= i
;
5815 dcb
->connector
.entry
[i
].type
= divine_connector_type(bios
, i
);
5816 dcb
->connector
.entry
[i
].gpio_tag
= 0xff;
5821 fixup_legacy_i2c(struct nvbios
*bios
)
5823 struct dcb_table
*dcb
= &bios
->dcb
;
5826 for (i
= 0; i
< dcb
->entries
; i
++) {
5827 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_CRT
)
5828 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.crt
;
5829 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_PANEL
)
5830 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.panel
;
5831 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_TV
)
5832 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.tv
;
5836 static int load_nv17_hwsq_ucode_entry(struct drm_device
*dev
, struct nvbios
*bios
, uint16_t hwsq_offset
, int entry
)
5839 * The header following the "HWSQ" signature has the number of entries,
5840 * and the entry size
5842 * An entry consists of a dword to write to the sequencer control reg
5843 * (0x00001304), followed by the ucode bytes, written sequentially,
5844 * starting at reg 0x00001400
5847 uint8_t bytes_to_write
;
5848 uint16_t hwsq_entry_offset
;
5851 if (bios
->data
[hwsq_offset
] <= entry
) {
5852 NV_ERROR(dev
, "Too few entries in HW sequencer table for "
5853 "requested entry\n");
5857 bytes_to_write
= bios
->data
[hwsq_offset
+ 1];
5859 if (bytes_to_write
!= 36) {
5860 NV_ERROR(dev
, "Unknown HW sequencer entry size\n");
5864 NV_TRACE(dev
, "Loading NV17 power sequencing microcode\n");
5866 hwsq_entry_offset
= hwsq_offset
+ 2 + entry
* bytes_to_write
;
5868 /* set sequencer control */
5869 bios_wr32(bios
, 0x00001304, ROM32(bios
->data
[hwsq_entry_offset
]));
5870 bytes_to_write
-= 4;
5873 for (i
= 0; i
< bytes_to_write
; i
+= 4)
5874 bios_wr32(bios
, 0x00001400 + i
, ROM32(bios
->data
[hwsq_entry_offset
+ i
+ 4]));
5876 /* twiddle NV_PBUS_DEBUG_4 */
5877 bios_wr32(bios
, NV_PBUS_DEBUG_4
, bios_rd32(bios
, NV_PBUS_DEBUG_4
) | 0x18);
5882 static int load_nv17_hw_sequencer_ucode(struct drm_device
*dev
,
5883 struct nvbios
*bios
)
5886 * BMP based cards, from NV17, need a microcode loading to correctly
5887 * control the GPIO etc for LVDS panels
5889 * BIT based cards seem to do this directly in the init scripts
5891 * The microcode entries are found by the "HWSQ" signature.
5894 const uint8_t hwsq_signature
[] = { 'H', 'W', 'S', 'Q' };
5895 const int sz
= sizeof(hwsq_signature
);
5898 hwsq_offset
= findstr(bios
->data
, bios
->length
, hwsq_signature
, sz
);
5902 /* always use entry 0? */
5903 return load_nv17_hwsq_ucode_entry(dev
, bios
, hwsq_offset
+ sz
, 0);
5906 uint8_t *nouveau_bios_embedded_edid(struct drm_device
*dev
)
5908 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5909 struct nvbios
*bios
= &dev_priv
->vbios
;
5910 const uint8_t edid_sig
[] = {
5911 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
5912 uint16_t offset
= 0;
5914 int searchlen
= NV_PROM_SIZE
;
5917 return bios
->fp
.edid
;
5920 newoffset
= findstr(&bios
->data
[offset
], searchlen
,
5924 offset
+= newoffset
;
5925 if (!nv_cksum(&bios
->data
[offset
], EDID1_LEN
))
5928 searchlen
-= offset
;
5932 NV_TRACE(dev
, "Found EDID in BIOS\n");
5934 return bios
->fp
.edid
= &bios
->data
[offset
];
5938 nouveau_bios_run_init_table(struct drm_device
*dev
, uint16_t table
,
5939 struct dcb_entry
*dcbent
)
5941 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5942 struct nvbios
*bios
= &dev_priv
->vbios
;
5943 struct init_exec iexec
= { true, false };
5945 mutex_lock(&bios
->lock
);
5946 bios
->display
.output
= dcbent
;
5947 parse_init_table(bios
, table
, &iexec
);
5948 bios
->display
.output
= NULL
;
5949 mutex_unlock(&bios
->lock
);
5952 static bool NVInitVBIOS(struct drm_device
*dev
)
5954 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5955 struct nvbios
*bios
= &dev_priv
->vbios
;
5957 memset(bios
, 0, sizeof(struct nvbios
));
5958 mutex_init(&bios
->lock
);
5961 if (!NVShadowVBIOS(dev
, bios
->data
))
5964 bios
->length
= NV_PROM_SIZE
;
5968 static int nouveau_parse_vbios_struct(struct drm_device
*dev
)
5970 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5971 struct nvbios
*bios
= &dev_priv
->vbios
;
5972 const uint8_t bit_signature
[] = { 0xff, 0xb8, 'B', 'I', 'T' };
5973 const uint8_t bmp_signature
[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
5976 offset
= findstr(bios
->data
, bios
->length
,
5977 bit_signature
, sizeof(bit_signature
));
5979 NV_TRACE(dev
, "BIT BIOS found\n");
5980 return parse_bit_structure(bios
, offset
+ 6);
5983 offset
= findstr(bios
->data
, bios
->length
,
5984 bmp_signature
, sizeof(bmp_signature
));
5986 NV_TRACE(dev
, "BMP BIOS found\n");
5987 return parse_bmp_structure(dev
, bios
, offset
);
5990 NV_ERROR(dev
, "No known BIOS signature found\n");
5995 nouveau_run_vbios_init(struct drm_device
*dev
)
5997 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5998 struct nvbios
*bios
= &dev_priv
->vbios
;
6001 NVLockVgaCrtcs(dev
, false);
6002 if (nv_two_heads(dev
))
6003 NVSetOwner(dev
, bios
->state
.crtchead
);
6005 if (bios
->major_version
< 5) /* BMP only */
6006 load_nv17_hw_sequencer_ucode(dev
, bios
);
6008 if (bios
->execute
) {
6009 bios
->fp
.last_script_invoc
= 0;
6010 bios
->fp
.lvds_init_run
= false;
6013 parse_init_tables(bios
);
6016 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6017 * parser will run this right after the init tables, the binary
6018 * driver appears to run it at some point later.
6020 if (bios
->some_script_ptr
) {
6021 struct init_exec iexec
= {true, false};
6023 NV_INFO(dev
, "Parsing VBIOS init table at offset 0x%04X\n",
6024 bios
->some_script_ptr
);
6025 parse_init_table(bios
, bios
->some_script_ptr
, &iexec
);
6028 if (dev_priv
->card_type
>= NV_50
) {
6029 for (i
= 0; i
< bios
->dcb
.entries
; i
++) {
6030 nouveau_bios_run_display_table(dev
,
6031 &bios
->dcb
.entry
[i
],
6036 NVLockVgaCrtcs(dev
, true);
6042 nouveau_bios_i2c_devices_takedown(struct drm_device
*dev
)
6044 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6045 struct nvbios
*bios
= &dev_priv
->vbios
;
6046 struct dcb_i2c_entry
*entry
;
6049 entry
= &bios
->dcb
.i2c
[0];
6050 for (i
= 0; i
< DCB_MAX_NUM_I2C_ENTRIES
; i
++, entry
++)
6051 nouveau_i2c_fini(dev
, entry
);
6055 nouveau_bios_init(struct drm_device
*dev
)
6057 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6058 struct nvbios
*bios
= &dev_priv
->vbios
;
6059 uint32_t saved_nv_pextdev_boot_0
;
6063 if (!NVInitVBIOS(dev
))
6066 ret
= nouveau_parse_vbios_struct(dev
);
6070 ret
= parse_dcb_table(dev
, bios
, nv_two_heads(dev
));
6074 fixup_legacy_i2c(bios
);
6075 fixup_legacy_connector(bios
);
6077 if (!bios
->major_version
) /* we don't run version 0 bios */
6080 /* these will need remembering across a suspend */
6081 saved_nv_pextdev_boot_0
= bios_rd32(bios
, NV_PEXTDEV_BOOT_0
);
6082 bios
->state
.saved_nv_pfb_cfg0
= bios_rd32(bios
, NV_PFB_CFG0
);
6084 /* init script execution disabled */
6085 bios
->execute
= false;
6087 /* ... unless card isn't POSTed already */
6088 if (dev_priv
->card_type
>= NV_10
&&
6089 NVReadVgaCrtc(dev
, 0, 0x00) == 0 &&
6090 NVReadVgaCrtc(dev
, 0, 0x1a) == 0) {
6091 NV_INFO(dev
, "Adaptor not initialised\n");
6092 if (dev_priv
->card_type
< NV_50
) {
6093 NV_ERROR(dev
, "Unable to POST this chipset\n");
6097 NV_INFO(dev
, "Running VBIOS init tables\n");
6098 bios
->execute
= true;
6101 bios_wr32(bios
, NV_PEXTDEV_BOOT_0
, saved_nv_pextdev_boot_0
);
6103 ret
= nouveau_run_vbios_init(dev
);
6107 /* feature_byte on BMP is poor, but init always sets CR4B */
6108 was_locked
= NVLockVgaCrtcs(dev
, false);
6109 if (bios
->major_version
< 5)
6110 bios
->is_mobile
= NVReadVgaCrtc(dev
, 0, NV_CIO_CRE_4B
) & 0x40;
6112 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6113 if (bios
->is_mobile
|| bios
->major_version
>= 5)
6114 ret
= parse_fp_mode_table(dev
, bios
);
6115 NVLockVgaCrtcs(dev
, was_locked
);
6117 /* allow subsequent scripts to execute */
6118 bios
->execute
= true;
6124 nouveau_bios_takedown(struct drm_device
*dev
)
6126 nouveau_bios_i2c_devices_takedown(dev
);