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Staging: et131x: kill copied PCI fields
[wandboard.git] / drivers / staging / et131x / et1310_phy.c
blob63a23b9e94a10e8b15dfe66ed394ce619c7431e2
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright * 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_phy.c - Routines for configuring and accessing the PHY
12 *
13 *------------------------------------------------------------------------------
14 *
15 * SOFTWARE LICENSE
16 *
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
21 *
22 * Copyright * 2005 Agere Systems Inc.
23 * All rights reserved.
24 *
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
27 *
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
31 * distribution.
32 *
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 *
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * Disclaimer
42 *
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 *
56 */
57
58 #include "et131x_version.h"
59 #include "et131x_debug.h"
60 #include "et131x_defs.h"
61
62 #include <linux/pci.h>
63 #include <linux/init.h>
64 #include <linux/module.h>
65 #include <linux/types.h>
66 #include <linux/kernel.h>
67
68 #include <linux/sched.h>
69 #include <linux/ptrace.h>
70 #include <linux/slab.h>
71 #include <linux/ctype.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/interrupt.h>
75 #include <linux/in.h>
76 #include <linux/delay.h>
77 #include <linux/io.h>
78 #include <linux/bitops.h>
79 #include <asm/system.h>
80
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/if_arp.h>
85 #include <linux/ioport.h>
86 #include <linux/random.h>
87
88 #include "et1310_phy.h"
89 #include "et1310_pm.h"
90 #include "et1310_jagcore.h"
91
92 #include "et131x_adapter.h"
93 #include "et131x_netdev.h"
94 #include "et131x_initpci.h"
95
96 #include "et1310_address_map.h"
97 #include "et1310_tx.h"
98 #include "et1310_rx.h"
99 #include "et1310_mac.h"
100
101 /* Data for debugging facilities */
102 #ifdef CONFIG_ET131X_DEBUG
103 extern dbg_info_t *et131x_dbginfo;
104 #endif /* CONFIG_ET131X_DEBUG */
105
106 /* Prototypes for functions with local scope */
107 static int et131x_xcvr_init(struct et131x_adapter *adapter);
108
109 /**
110 * PhyMiRead - Read from the PHY through the MII Interface on the MAC
111 * @adapter: pointer to our private adapter structure
112 * @xcvrAddr: the address of the transciever
113 * @xcvrReg: the register to read
114 * @value: pointer to a 16-bit value in which the value will be stored
115 *
116 * Returns 0 on success, errno on failure (as defined in errno.h)
117 */
118 int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
119 uint8_t xcvrReg, uint16_t *value)
120 {
121 struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
122 int status = 0;
123 uint32_t delay;
124 MII_MGMT_ADDR_t miiAddr;
125 MII_MGMT_CMD_t miiCmd;
126 MII_MGMT_INDICATOR_t miiIndicator;
127
128 /* Save a local copy of the registers we are dealing with so we can
129 * set them back
130 */
131 miiAddr.value = readl(&mac->mii_mgmt_addr.value);
132 miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
133
134 /* Stop the current operation */
135 writel(0, &mac->mii_mgmt_cmd.value);
136
137 /* Set up the register we need to read from on the correct PHY */
138 {
139 MII_MGMT_ADDR_t mii_mgmt_addr = { 0 };
140
141 mii_mgmt_addr.bits.phy_addr = xcvrAddr;
142 mii_mgmt_addr.bits.reg_addr = xcvrReg;
143 writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
144 }
145
146 /* Kick the read cycle off */
147 delay = 0;
148
149 writel(0x1, &mac->mii_mgmt_cmd.value);
150
151 do {
152 udelay(50);
153 delay++;
154 miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
155 } while ((miiIndicator.bits.not_valid || miiIndicator.bits.busy) &&
156 delay < 50);
157
158 /* If we hit the max delay, we could not read the register */
159 if (delay >= 50) {
160 DBG_WARNING(et131x_dbginfo,
161 "xcvrReg 0x%08x could not be read\n", xcvrReg);
162 DBG_WARNING(et131x_dbginfo, "status is 0x%08x\n",
163 miiIndicator.value);
164
165 status = -EIO;
166 }
167
168 /* If we hit here we were able to read the register and we need to
169 * return the value to the caller
170 */
171 /* TODO: make this stuff a simple readw()?! */
172 {
173 MII_MGMT_STAT_t mii_mgmt_stat;
174
175 mii_mgmt_stat.value = readl(&mac->mii_mgmt_stat.value);
176 *value = (uint16_t) mii_mgmt_stat.bits.phy_stat;
177 }
178
179 /* Stop the read operation */
180 writel(0, &mac->mii_mgmt_cmd.value);
181
182 DBG_VERBOSE(et131x_dbginfo, " xcvr_addr = 0x%02x, "
183 "xcvr_reg = 0x%02x, "
184 "value = 0x%04x.\n", xcvrAddr, xcvrReg, *value);
185
186 /* set the registers we touched back to the state at which we entered
187 * this function
188 */
189 writel(miiAddr.value, &mac->mii_mgmt_addr.value);
190 writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
191
192 return status;
193 }
194
195 /**
196 * MiWrite - Write to a PHY register through the MII interface of the MAC
197 * @adapter: pointer to our private adapter structure
198 * @xcvrReg: the register to read
199 * @value: 16-bit value to write
200 *
201 * Return 0 on success, errno on failure (as defined in errno.h)
202 */
203 int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
204 {
205 struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;
206 int status = 0;
207 uint8_t xcvrAddr = adapter->Stats.xcvr_addr;
208 uint32_t delay;
209 MII_MGMT_ADDR_t miiAddr;
210 MII_MGMT_CMD_t miiCmd;
211 MII_MGMT_INDICATOR_t miiIndicator;
212
213 /* Save a local copy of the registers we are dealing with so we can
214 * set them back
215 */
216 miiAddr.value = readl(&mac->mii_mgmt_addr.value);
217 miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
218
219 /* Stop the current operation */
220 writel(0, &mac->mii_mgmt_cmd.value);
221
222 /* Set up the register we need to write to on the correct PHY */
223 {
224 MII_MGMT_ADDR_t mii_mgmt_addr;
225
226 mii_mgmt_addr.bits.phy_addr = xcvrAddr;
227 mii_mgmt_addr.bits.reg_addr = xcvrReg;
228 writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
229 }
230
231 /* Add the value to write to the registers to the mac */
232 writel(value, &mac->mii_mgmt_ctrl.value);
233 delay = 0;
234
235 do {
236 udelay(50);
237 delay++;
238 miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
239 } while (miiIndicator.bits.busy && delay < 100);
240
241 /* If we hit the max delay, we could not write the register */
242 if (delay == 100) {
243 uint16_t TempValue;
244
245 DBG_WARNING(et131x_dbginfo,
246 "xcvrReg 0x%08x could not be written", xcvrReg);
247 DBG_WARNING(et131x_dbginfo, "status is 0x%08x\n",
248 miiIndicator.value);
249 DBG_WARNING(et131x_dbginfo, "command is 0x%08x\n",
250 readl(&mac->mii_mgmt_cmd.value));
251
252 MiRead(adapter, xcvrReg, &TempValue);
253
254 status = -EIO;
255 }
256
257 /* Stop the write operation */
258 writel(0, &mac->mii_mgmt_cmd.value);
259
260 /* set the registers we touched back to the state at which we entered
261 * this function
262 */
263 writel(miiAddr.value, &mac->mii_mgmt_addr.value);
264 writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
265
266 DBG_VERBOSE(et131x_dbginfo, " xcvr_addr = 0x%02x, "
267 "xcvr_reg = 0x%02x, "
268 "value = 0x%04x.\n", xcvrAddr, xcvrReg, value);
269
270 return status;
271 }
272
273 /**
274 * et131x_xcvr_find - Find the PHY ID
275 * @adapter: pointer to our private adapter structure
276 *
277 * Returns 0 on success, errno on failure (as defined in errno.h)
278 */
279 int et131x_xcvr_find(struct et131x_adapter *adapter)
280 {
281 int status = -ENODEV;
282 uint8_t xcvr_addr;
283 MI_IDR1_t idr1;
284 MI_IDR2_t idr2;
285 uint32_t xcvr_id;
286
287 DBG_ENTER(et131x_dbginfo);
288
289 /* We need to get xcvr id and address we just get the first one */
290 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
291 /* Read the ID from the PHY */
292 PhyMiRead(adapter, xcvr_addr,
293 (uint8_t) offsetof(MI_REGS_t, idr1),
294 &idr1.value);
295 PhyMiRead(adapter, xcvr_addr,
296 (uint8_t) offsetof(MI_REGS_t, idr2),
297 &idr2.value);
298
299 xcvr_id = (uint32_t) ((idr1.value << 16) | idr2.value);
300
301 if ((idr1.value != 0) && (idr1.value != 0xffff)) {
302 DBG_TRACE(et131x_dbginfo,
303 "Xcvr addr: 0x%02x\tXcvr_id: 0x%08x\n",
304 xcvr_addr, xcvr_id);
305
306 adapter->Stats.xcvr_id = xcvr_id;
307 adapter->Stats.xcvr_addr = xcvr_addr;
308
309 status = 0;
310 break;
311 }
312 }
313
314 DBG_LEAVE(et131x_dbginfo);
315 return status;
316 }
317
318 /**
319 * et131x_setphy_normal - Set PHY for normal operation.
320 * @adapter: pointer to our private adapter structure
321 *
322 * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
323 * when going to D3 in WOL mode. Also used during initialization to set the
324 * PHY for normal operation.
325 */
326 int et131x_setphy_normal(struct et131x_adapter *adapter)
327 {
328 int status;
329
330 DBG_ENTER(et131x_dbginfo);
331
332 /* Make sure the PHY is powered up */
333 ET1310_PhyPowerDown(adapter, 0);
334 status = et131x_xcvr_init(adapter);
335
336 DBG_LEAVE(et131x_dbginfo);
337 return status;
338 }
339
340 /**
341 * et131x_xcvr_init - Init the phy if we are setting it into force mode
342 * @adapter: pointer to our private adapter structure
343 *
344 * Returns 0 on success, errno on failure (as defined in errno.h)
345 */
346 static int et131x_xcvr_init(struct et131x_adapter *adapter)
347 {
348 int status = 0;
349 MI_IMR_t imr;
350 MI_ISR_t isr;
351 MI_LCR2_t lcr2;
352
353 DBG_ENTER(et131x_dbginfo);
354
355 /* Zero out the adapter structure variable representing BMSR */
356 adapter->Bmsr.value = 0;
357
358 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, isr), &isr.value);
359
360 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, imr), &imr.value);
361
362 /* Set the link status interrupt only. Bad behavior when link status
363 * and auto neg are set, we run into a nested interrupt problem
364 */
365 imr.bits.int_en = 0x1;
366 imr.bits.link_status = 0x1;
367 imr.bits.autoneg_status = 0x1;
368
369 MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, imr), imr.value);
370
371 /* Set the LED behavior such that LED 1 indicates speed (off =
372 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
373 * link and activity (on for link, blink off for activity).
374 *
375 * NOTE: Some customizations have been added here for specific
376 * vendors; The LED behavior is now determined by vendor data in the
377 * EEPROM. However, the above description is the default.
378 */
379 if ((adapter->eepromData[1] & 0x4) == 0) {
380 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
381 &lcr2.value);
382 if ((adapter->eepromData[1] & 0x8) == 0)
383 lcr2.bits.led_tx_rx = 0x3;
384 else
385 lcr2.bits.led_tx_rx = 0x4;
386 lcr2.bits.led_link = 0xa;
387 MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
388 lcr2.value);
389 }
390
391 /* Determine if we need to go into a force mode and set it */
392 if (adapter->AiForceSpeed == 0 && adapter->AiForceDpx == 0) {
393 if ((adapter->RegistryFlowControl == TxOnly) ||
394 (adapter->RegistryFlowControl == Both)) {
395 ET1310_PhyAccessMiBit(adapter,
396 TRUEPHY_BIT_SET, 4, 11, NULL);
397 } else {
398 ET1310_PhyAccessMiBit(adapter,
399 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
400 }
401
402 if (adapter->RegistryFlowControl == Both) {
403 ET1310_PhyAccessMiBit(adapter,
404 TRUEPHY_BIT_SET, 4, 10, NULL);
405 } else {
406 ET1310_PhyAccessMiBit(adapter,
407 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
408 }
409
410 /* Set the phy to autonegotiation */
411 ET1310_PhyAutoNeg(adapter, true);
412
413 /* NOTE - Do we need this? */
414 ET1310_PhyAccessMiBit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL);
415
416 DBG_LEAVE(et131x_dbginfo);
417 return status;
418 } else {
419 ET1310_PhyAutoNeg(adapter, false);
420
421 /* Set to the correct force mode. */
422 if (adapter->AiForceDpx != 1) {
423 if ((adapter->RegistryFlowControl == TxOnly) ||
424 (adapter->RegistryFlowControl == Both)) {
425 ET1310_PhyAccessMiBit(adapter,
426 TRUEPHY_BIT_SET, 4, 11,
427 NULL);
428 } else {
429 ET1310_PhyAccessMiBit(adapter,
430 TRUEPHY_BIT_CLEAR, 4, 11,
431 NULL);
432 }
433
434 if (adapter->RegistryFlowControl == Both) {
435 ET1310_PhyAccessMiBit(adapter,
436 TRUEPHY_BIT_SET, 4, 10,
437 NULL);
438 } else {
439 ET1310_PhyAccessMiBit(adapter,
440 TRUEPHY_BIT_CLEAR, 4, 10,
441 NULL);
442 }
443 } else {
444 ET1310_PhyAccessMiBit(adapter,
445 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
446 ET1310_PhyAccessMiBit(adapter,
447 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
448 }
449
450 switch (adapter->AiForceSpeed) {
451 case 10:
452 if (adapter->AiForceDpx == 1)
453 TPAL_SetPhy10HalfDuplex(adapter);
454 else if (adapter->AiForceDpx == 2)
455 TPAL_SetPhy10FullDuplex(adapter);
456 else
457 TPAL_SetPhy10Force(adapter);
458 break;
459 case 100:
460 if (adapter->AiForceDpx == 1)
461 TPAL_SetPhy100HalfDuplex(adapter);
462 else if (adapter->AiForceDpx == 2)
463 TPAL_SetPhy100FullDuplex(adapter);
464 else
465 TPAL_SetPhy100Force(adapter);
466 break;
467 case 1000:
468 TPAL_SetPhy1000FullDuplex(adapter);
469 break;
470 }
471
472 DBG_LEAVE(et131x_dbginfo);
473 return status;
474 }
475 }
476
477 void et131x_Mii_check(struct et131x_adapter *etdev,
478 MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
479 {
480 uint8_t ucLinkStatus;
481 uint32_t uiAutoNegStatus;
482 uint32_t uiSpeed;
483 uint32_t uiDuplex;
484 uint32_t uiMdiMdix;
485 uint32_t uiMasterSlave;
486 uint32_t uiPolarity;
487 unsigned long flags;
488
489 DBG_ENTER(et131x_dbginfo);
490
491 if (bmsr_ints.bits.link_status) {
492 if (bmsr.bits.link_status) {
493 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
494
495 /* Update our state variables and indicate the
496 * connected state
497 */
498 spin_lock_irqsave(&etdev->Lock, flags);
499
500 etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
501 MP_CLEAR_FLAG(etdev, fMP_ADAPTER_LINK_DETECTION);
502
503 spin_unlock_irqrestore(&etdev->Lock, flags);
504
505 /* Don't indicate state if we're in loopback mode */
506 if (etdev->RegistryPhyLoopbk == false)
507 netif_carrier_on(etdev->netdev);
508 } else {
509 DBG_WARNING(et131x_dbginfo,
510 "Link down cable problem\n");
511
512 if (etdev->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {
513 /* NOTE - Is there a way to query this without
514 * TruePHY?
515 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
516 */
517 uint16_t Register18;
518
519 MiRead(etdev, 0x12, &Register18);
520 MiWrite(etdev, 0x12, Register18 | 0x4);
521 MiWrite(etdev, 0x10, Register18 | 0x8402);
522 MiWrite(etdev, 0x11, Register18 | 511);
523 MiWrite(etdev, 0x12, Register18);
524 }
525
526 /* For the first N seconds of life, we are in "link
527 * detection" When we are in this state, we should
528 * only report "connected". When the LinkDetection
529 * Timer expires, we can report disconnected (handled
530 * in the LinkDetectionDPC).
531 */
532 if ((MP_IS_FLAG_CLEAR
533 (etdev, fMP_ADAPTER_LINK_DETECTION))
534 || (etdev->MediaState ==
535 NETIF_STATUS_MEDIA_DISCONNECT)) {
536 spin_lock_irqsave(&etdev->Lock, flags);
537 etdev->MediaState =
538 NETIF_STATUS_MEDIA_DISCONNECT;
539 spin_unlock_irqrestore(&etdev->Lock,
540 flags);
541
542 /* Only indicate state if we're in loopback
543 * mode
544 */
545 if (etdev->RegistryPhyLoopbk == false)
546 netif_carrier_off(etdev->netdev);
547 }
548
549 etdev->uiLinkSpeed = 0;
550 etdev->uiDuplexMode = 0;
551
552 /* Free the packets being actively sent & stopped */
553 et131x_free_busy_send_packets(etdev);
554
555 /* Re-initialize the send structures */
556 et131x_init_send(etdev);
557
558 /* Reset the RFD list and re-start RU */
559 et131x_reset_recv(etdev);
560
561 /*
562 * Bring the device back to the state it was during
563 * init prior to autonegotiation being complete. This
564 * way, when we get the auto-neg complete interrupt,
565 * we can complete init by calling ConfigMacREGS2.
566 */
567 et131x_soft_reset(etdev);
568
569 /* Setup ET1310 as per the documentation */
570 et131x_adapter_setup(etdev);
571
572 /* Setup the PHY into coma mode until the cable is
573 * plugged back in
574 */
575 if (etdev->RegistryPhyComa == 1)
576 EnablePhyComa(etdev);
577 }
578 }
579
580 if (bmsr_ints.bits.auto_neg_complete ||
581 (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
582 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
583 ET1310_PhyLinkStatus(etdev,
584 &ucLinkStatus, &uiAutoNegStatus,
585 &uiSpeed, &uiDuplex, &uiMdiMdix,
586 &uiMasterSlave, &uiPolarity);
587
588 etdev->uiLinkSpeed = uiSpeed;
589 etdev->uiDuplexMode = uiDuplex;
590
591 DBG_TRACE(et131x_dbginfo,
592 "etdev->uiLinkSpeed 0x%04x, etdev->uiDuplex 0x%08x\n",
593 etdev->uiLinkSpeed,
594 etdev->uiDuplexMode);
595
596 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
597
598 if (etdev->uiLinkSpeed == TRUEPHY_SPEED_10MBPS) {
599 /*
600 * NOTE - Is there a way to query this without
601 * TruePHY?
602 * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
603 */
604 uint16_t Register18;
605
606 MiRead(etdev, 0x12, &Register18);
607 MiWrite(etdev, 0x12, Register18 | 0x4);
608 MiWrite(etdev, 0x10, Register18 | 0x8402);
609 MiWrite(etdev, 0x11, Register18 | 511);
610 MiWrite(etdev, 0x12, Register18);
611 }
612
613 ConfigFlowControl(etdev);
614
615 if (etdev->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS &&
616 etdev->RegistryJumboPacket > 2048)
617 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
618 0x2000);
619
620 SetRxDmaTimer(etdev);
621 ConfigMACRegs2(etdev);
622 }
623 }
624
625 DBG_LEAVE(et131x_dbginfo);
626 }
627
628 /**
629 * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode.
630 * @etdev: pointer to the adapter structure
631 *
632 * Also sets the MAC so it is syncd up properly
633 */
634 void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *etdev)
635 {
636 DBG_ENTER(et131x_dbginfo);
637
638 /* Power down PHY */
639 ET1310_PhyPowerDown(etdev, 1);
640
641 /* First we need to turn off all other advertisement */
642 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
643
644 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
645
646 /* Set our advertise values accordingly */
647 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_HALF);
648
649 /* Power up PHY */
650 ET1310_PhyPowerDown(etdev, 0);
651
652 DBG_LEAVE(et131x_dbginfo);
653 }
654
655 /**
656 * TPAL_SetPhy10FullDuplex - Force the phy into 10 Base T Full Duplex mode.
657 * @etdev: pointer to the adapter structure
658 *
659 * Also sets the MAC so it is syncd up properly
660 */
661 void TPAL_SetPhy10FullDuplex(struct et131x_adapter *etdev)
662 {
663 DBG_ENTER(et131x_dbginfo);
664
665 /* Power down PHY */
666 ET1310_PhyPowerDown(etdev, 1);
667
668 /* First we need to turn off all other advertisement */
669 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
670
671 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
672
673 /* Set our advertise values accordingly */
674 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
675
676 /* Power up PHY */
677 ET1310_PhyPowerDown(etdev, 0);
678
679 DBG_LEAVE(et131x_dbginfo);
680 }
681
682 /**
683 * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation
684 * @etdev: pointer to the adapter structure
685 */
686 void TPAL_SetPhy10Force(struct et131x_adapter *etdev)
687 {
688 DBG_ENTER(et131x_dbginfo);
689
690 /* Power down PHY */
691 ET1310_PhyPowerDown(etdev, 1);
692
693 /* Disable autoneg */
694 ET1310_PhyAutoNeg(etdev, false);
695
696 /* Disable all advertisement */
697 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
698 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
699 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
700
701 /* Force 10 Mbps */
702 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
703
704 /* Force Full duplex */
705 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
706
707 /* Power up PHY */
708 ET1310_PhyPowerDown(etdev, 0);
709
710 DBG_LEAVE(et131x_dbginfo);
711 }
712
713 /**
714 * TPAL_SetPhy100HalfDuplex - Force 100 Base T Half Duplex mode.
715 * @etdev: pointer to the adapter structure
716 *
717 * Also sets the MAC so it is syncd up properly.
718 */
719 void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *etdev)
720 {
721 DBG_ENTER(et131x_dbginfo);
722
723 /* Power down PHY */
724 ET1310_PhyPowerDown(etdev, 1);
725
726 /* first we need to turn off all other advertisement */
727 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
728
729 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
730
731 /* Set our advertise values accordingly */
732 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_HALF);
733
734 /* Set speed */
735 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
736
737 /* Power up PHY */
738 ET1310_PhyPowerDown(etdev, 0);
739
740 DBG_LEAVE(et131x_dbginfo);
741 }
742
743 /**
744 * TPAL_SetPhy100FullDuplex - Force 100 Base T Full Duplex mode.
745 * @etdev: pointer to the adapter structure
746 *
747 * Also sets the MAC so it is syncd up properly
748 */
749 void TPAL_SetPhy100FullDuplex(struct et131x_adapter *etdev)
750 {
751 DBG_ENTER(et131x_dbginfo);
752
753 /* Power down PHY */
754 ET1310_PhyPowerDown(etdev, 1);
755
756 /* First we need to turn off all other advertisement */
757 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
758
759 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
760
761 /* Set our advertise values accordingly */
762 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
763
764 /* Power up PHY */
765 ET1310_PhyPowerDown(etdev, 0);
766
767 DBG_LEAVE(et131x_dbginfo);
768 }
769
770 /**
771 * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation
772 * @etdev: pointer to the adapter structure
773 */
774 void TPAL_SetPhy100Force(struct et131x_adapter *etdev)
775 {
776 DBG_ENTER(et131x_dbginfo);
777
778 /* Power down PHY */
779 ET1310_PhyPowerDown(etdev, 1);
780
781 /* Disable autoneg */
782 ET1310_PhyAutoNeg(etdev, false);
783
784 /* Disable all advertisement */
785 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
786 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
787 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
788
789 /* Force 100 Mbps */
790 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
791
792 /* Force Full duplex */
793 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
794
795 /* Power up PHY */
796 ET1310_PhyPowerDown(etdev, 0);
797
798 DBG_LEAVE(et131x_dbginfo);
799 }
800
801 /**
802 * TPAL_SetPhy1000FullDuplex - Force 1000 Base T Full Duplex mode
803 * @etdev: pointer to the adapter structure
804 *
805 * Also sets the MAC so it is syncd up properly.
806 */
807 void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *etdev)
808 {
809 DBG_ENTER(et131x_dbginfo);
810
811 /* Power down PHY */
812 ET1310_PhyPowerDown(etdev, 1);
813
814 /* first we need to turn off all other advertisement */
815 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
816
817 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
818
819 /* set our advertise values accordingly */
820 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
821
822 /* power up PHY */
823 ET1310_PhyPowerDown(etdev, 0);
824
825 DBG_LEAVE(et131x_dbginfo);
826 }
827
828 /**
829 * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode.
830 * @etdev: pointer to the adapter structure
831 */
832 void TPAL_SetPhyAutoNeg(struct et131x_adapter *etdev)
833 {
834 DBG_ENTER(et131x_dbginfo);
835
836 /* Power down PHY */
837 ET1310_PhyPowerDown(etdev, 1);
838
839 /* Turn on advertisement of all capabilities */
840 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_BOTH);
841
842 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_BOTH);
843
844 if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
845 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
846 else
847 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
848
849 /* Make sure auto-neg is ON (it is disabled in FORCE modes) */
850 ET1310_PhyAutoNeg(etdev, true);
851
852 /* Power up PHY */
853 ET1310_PhyPowerDown(etdev, 0);
854
855 DBG_LEAVE(et131x_dbginfo);
856 }
857
858
859 /*
860 * The routines which follow provide low-level access to the PHY, and are used
861 * primarily by the routines above (although there are a few places elsewhere
862 * in the driver where this level of access is required).
863 */
864
865 static const uint16_t ConfigPhy[25][2] = {
866 /* Reg Value Register */
867 /* Addr */
868 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
869 {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */
870 {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */
871
872 {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */
873 {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */
874 {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */
875
876 {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */
877 {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */
878 {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */
879
880 {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */
881 {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */
882 {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */
883
884 {0x300D, 1}, /* DisableNorm */
885
886 {0x280C, 0x0180}, /* LinkHoldEnd */
887
888 {0x1C21, 0x0002}, /* AlphaM */
889
890 {0x3821, 6}, /* FfeLkgTx0 */
891 {0x381D, 1}, /* FfeLkg1g4 */
892 {0x381E, 1}, /* FfeLkg1g5 */
893 {0x381F, 1}, /* FfeLkg1g6 */
894 {0x3820, 1}, /* FfeLkg1g7 */
895
896 {0x8402, 0x01F0}, /* Btinact */
897 {0x800E, 20}, /* LftrainTime */
898 {0x800F, 24}, /* DvguardTime */
899 {0x8010, 46}, /* IdlguardTime */
900
901 {0, 0}
902
903 };
904
905 /* condensed version of the phy initialization routine */
906 void ET1310_PhyInit(struct et131x_adapter *etdev)
907 {
908 uint16_t usData, usIndex;
909
910 if (etdev == NULL)
911 return;
912
913 /* get the identity (again ?) */
914 MiRead(etdev, PHY_ID_1, &usData);
915 MiRead(etdev, PHY_ID_2, &usData);
916
917 /* what does this do/achieve ? */
918 MiRead(etdev, PHY_MPHY_CONTROL_REG, &usData); /* should read 0002 */
919 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
920
921 /* read modem register 0402, should I do something with the return
922 data ? */
923 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
924 MiRead(etdev, PHY_DATA_REG, &usData);
925
926 /* what does this do/achieve ? */
927 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
928
929 /* get the identity (again ?) */
930 MiRead(etdev, PHY_ID_1, &usData);
931 MiRead(etdev, PHY_ID_2, &usData);
932
933 /* what does this achieve ? */
934 MiRead(etdev, PHY_MPHY_CONTROL_REG, &usData); /* should read 0002 */
935 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
936
937 /* read modem register 0402, should I do something with
938 the return data? */
939 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
940 MiRead(etdev, PHY_DATA_REG, &usData);
941
942 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
943
944 /* what does this achieve (should return 0x1040) */
945 MiRead(etdev, PHY_CONTROL, &usData);
946 MiRead(etdev, PHY_MPHY_CONTROL_REG, &usData); /* should read 0002 */
947 MiWrite(etdev, PHY_CONTROL, 0x1840);
948
949 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
950
951 /* here the writing of the array starts.... */
952 usIndex = 0;
953 while (ConfigPhy[usIndex][0] != 0x0000) {
954 /* write value */
955 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[usIndex][0]);
956 MiWrite(etdev, PHY_DATA_REG, ConfigPhy[usIndex][1]);
957
958 /* read it back */
959 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[usIndex][0]);
960 MiRead(etdev, PHY_DATA_REG, &usData);
961
962 /* do a check on the value read back ? */
963 usIndex++;
964 }
965 /* here the writing of the array ends... */
966
967 MiRead(etdev, PHY_CONTROL, &usData); /* 0x1840 */
968 MiRead(etdev, PHY_MPHY_CONTROL_REG, &usData);/* should read 0007 */
969 MiWrite(etdev, PHY_CONTROL, 0x1040);
970 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
971 }
972
973 void ET1310_PhyReset(struct et131x_adapter *etdev)
974 {
975 MiWrite(etdev, PHY_CONTROL, 0x8000);
976 }
977
978 void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
979 {
980 uint16_t usData;
981
982 MiRead(etdev, PHY_CONTROL, &usData);
983
984 if (down == false) {
985 /* Power UP */
986 usData &= ~0x0800;
987 MiWrite(etdev, PHY_CONTROL, usData);
988 } else {
989 /* Power DOWN */
990 usData |= 0x0800;
991 MiWrite(etdev, PHY_CONTROL, usData);
992 }
993 }
994
995 void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
996 {
997 uint16_t usData;
998
999 MiRead(etdev, PHY_CONTROL, &usData);
1000
1001 if (enable == true) {
1002 /* Autonegotiation ON */
1003 usData |= 0x1000;
1004 MiWrite(etdev, PHY_CONTROL, usData);
1005 } else {
1006 /* Autonegotiation OFF */
1007 usData &= ~0x1000;
1008 MiWrite(etdev, PHY_CONTROL, usData);
1009 }
1010 }
1011
1012 void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, uint16_t duplex)
1013 {
1014 uint16_t usData;
1015
1016 MiRead(etdev, PHY_CONTROL, &usData);
1017
1018 if (duplex == TRUEPHY_DUPLEX_FULL) {
1019 /* Set Full Duplex */
1020 usData |= 0x100;
1021 MiWrite(etdev, PHY_CONTROL, usData);
1022 } else {
1023 /* Set Half Duplex */
1024 usData &= ~0x100;
1025 MiWrite(etdev, PHY_CONTROL, usData);
1026 }
1027 }
1028
1029 void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, uint16_t speed)
1030 {
1031 uint16_t usData;
1032
1033 /* Read the PHY control register */
1034 MiRead(etdev, PHY_CONTROL, &usData);
1035
1036 /* Clear all Speed settings (Bits 6, 13) */
1037 usData &= ~0x2040;
1038
1039 /* Reset the speed bits based on user selection */
1040 switch (speed) {
1041 case TRUEPHY_SPEED_10MBPS:
1042 /* Bits already cleared above, do nothing */
1043 break;
1044
1045 case TRUEPHY_SPEED_100MBPS:
1046 /* 100M == Set bit 13 */
1047 usData |= 0x2000;
1048 break;
1049
1050 case TRUEPHY_SPEED_1000MBPS:
1051 default:
1052 usData |= 0x0040;
1053 break;
1054 }
1055
1056 /* Write back the new speed */
1057 MiWrite(etdev, PHY_CONTROL, usData);
1058 }
1059
1060 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
1061 uint16_t duplex)
1062 {
1063 uint16_t usData;
1064
1065 /* Read the PHY 1000 Base-T Control Register */
1066 MiRead(etdev, PHY_1000_CONTROL, &usData);
1067
1068 /* Clear Bits 8,9 */
1069 usData &= ~0x0300;
1070
1071 switch (duplex) {
1072 case TRUEPHY_ADV_DUPLEX_NONE:
1073 /* Duplex already cleared, do nothing */
1074 break;
1075
1076 case TRUEPHY_ADV_DUPLEX_FULL:
1077 /* Set Bit 9 */
1078 usData |= 0x0200;
1079 break;
1080
1081 case TRUEPHY_ADV_DUPLEX_HALF:
1082 /* Set Bit 8 */
1083 usData |= 0x0100;
1084 break;
1085
1086 case TRUEPHY_ADV_DUPLEX_BOTH:
1087 default:
1088 usData |= 0x0300;
1089 break;
1090 }
1091
1092 /* Write back advertisement */
1093 MiWrite(etdev, PHY_1000_CONTROL, usData);
1094 }
1095
1096 void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
1097 uint16_t duplex)
1098 {
1099 uint16_t usData;
1100
1101 /* Read the Autonegotiation Register (10/100) */
1102 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &usData);
1103
1104 /* Clear bits 7,8 */
1105 usData &= ~0x0180;
1106
1107 switch (duplex) {
1108 case TRUEPHY_ADV_DUPLEX_NONE:
1109 /* Duplex already cleared, do nothing */
1110 break;
1111
1112 case TRUEPHY_ADV_DUPLEX_FULL:
1113 /* Set Bit 8 */
1114 usData |= 0x0100;
1115 break;
1116
1117 case TRUEPHY_ADV_DUPLEX_HALF:
1118 /* Set Bit 7 */
1119 usData |= 0x0080;
1120 break;
1121
1122 case TRUEPHY_ADV_DUPLEX_BOTH:
1123 default:
1124 /* Set Bits 7,8 */
1125 usData |= 0x0180;
1126 break;
1127 }
1128
1129 /* Write back advertisement */
1130 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, usData);
1131 }
1132
1133 void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
1134 uint16_t duplex)
1135 {
1136 uint16_t usData;
1137
1138 /* Read the Autonegotiation Register (10/100) */
1139 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &usData);
1140
1141 /* Clear bits 5,6 */
1142 usData &= ~0x0060;
1143
1144 switch (duplex) {
1145 case TRUEPHY_ADV_DUPLEX_NONE:
1146 /* Duplex already cleared, do nothing */
1147 break;
1148
1149 case TRUEPHY_ADV_DUPLEX_FULL:
1150 /* Set Bit 6 */
1151 usData |= 0x0040;
1152 break;
1153
1154 case TRUEPHY_ADV_DUPLEX_HALF:
1155 /* Set Bit 5 */
1156 usData |= 0x0020;
1157 break;
1158
1159 case TRUEPHY_ADV_DUPLEX_BOTH:
1160 default:
1161 /* Set Bits 5,6 */
1162 usData |= 0x0060;
1163 break;
1164 }
1165
1166 /* Write back advertisement */
1167 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, usData);
1168 }
1169
1170 void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
1171 uint8_t *ucLinkStatus,
1172 uint32_t *uiAutoNeg,
1173 uint32_t *uiLinkSpeed,
1174 uint32_t *uiDuplexMode,
1175 uint32_t *uiMdiMdix,
1176 uint32_t *uiMasterSlave, uint32_t *uiPolarity)
1177 {
1178 uint16_t usMiStatus = 0;
1179 uint16_t us1000BaseT = 0;
1180 uint16_t usVmiPhyStatus = 0;
1181 uint16_t usControl = 0;
1182
1183 MiRead(etdev, PHY_STATUS, &usMiStatus);
1184 MiRead(etdev, PHY_1000_STATUS, &us1000BaseT);
1185 MiRead(etdev, PHY_PHY_STATUS, &usVmiPhyStatus);
1186 MiRead(etdev, PHY_CONTROL, &usControl);
1187
1188 if (ucLinkStatus) {
1189 *ucLinkStatus =
1190 (unsigned char)((usVmiPhyStatus & 0x0040) ? 1 : 0);
1191 }
1192
1193 if (uiAutoNeg) {
1194 *uiAutoNeg =
1195 (usControl & 0x1000) ? ((usVmiPhyStatus & 0x0020) ?
1196 TRUEPHY_ANEG_COMPLETE :
1197 TRUEPHY_ANEG_NOT_COMPLETE) :
1198 TRUEPHY_ANEG_DISABLED;
1199 }
1200
1201 if (uiLinkSpeed)
1202 *uiLinkSpeed = (usVmiPhyStatus & 0x0300) >> 8;
1203
1204 if (uiDuplexMode)
1205 *uiDuplexMode = (usVmiPhyStatus & 0x0080) >> 7;
1206
1207 if (uiMdiMdix)
1208 /* NOTE: Need to complete this */
1209 *uiMdiMdix = 0;
1210
1211 if (uiMasterSlave) {
1212 *uiMasterSlave =
1213 (us1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :
1214 TRUEPHY_CFG_SLAVE;
1215 }
1216
1217 if (uiPolarity) {
1218 *uiPolarity =
1219 (usVmiPhyStatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :
1220 TRUEPHY_POLARITY_NORMAL;
1221 }
1222 }
1223
1224 void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
1225 uint16_t regnum, uint16_t andMask, uint16_t orMask)
1226 {
1227 uint16_t reg;
1228
1229 /* Read the requested register */
1230 MiRead(etdev, regnum, &reg);
1231
1232 /* Apply the AND mask */
1233 reg &= andMask;
1234
1235 /* Apply the OR mask */
1236 reg |= orMask;
1237
1238 /* Write the value back to the register */
1239 MiWrite(etdev, regnum, reg);
1240 }
1241
1242 void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, uint16_t action,
1243 uint16_t regnum, uint16_t bitnum, uint8_t *value)
1244 {
1245 uint16_t reg;
1246 uint16_t mask = 0;
1247
1248 /* Create a mask to isolate the requested bit */
1249 mask = 0x0001 << bitnum;
1250
1251 /* Read the requested register */
1252 MiRead(etdev, regnum, &reg);
1253
1254 switch (action) {
1255 case TRUEPHY_BIT_READ:
1256 if (value != NULL)
1257 *value = (reg & mask) >> bitnum;
1258 break;
1259
1260 case TRUEPHY_BIT_SET:
1261 reg |= mask;
1262 MiWrite(etdev, regnum, reg);
1263 break;
1264
1265 case TRUEPHY_BIT_CLEAR:
1266 reg &= ~mask;
1267 MiWrite(etdev, regnum, reg);
1268 break;
1269
1270 default:
1271 break;
1272 }
1273 }
WandBoard kernel