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Staging: tidspbridge: Makefile: replace the use of <module>-objs with <module>-y
[wandboard.git] / drivers / char / synclink_gt.c
blobe63b830c86cc0778cb45827dc46a7e207488b586
1 /*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24 /*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 /*#define DBGTBUF(info) dump_tbufs(info)*/
44 /*#define DBGRBUF(info) dump_rbufs(info)*/
45
46
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
62 #include <linux/mm.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/netdevice.h>
66 #include <linux/vmalloc.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/ioctl.h>
70 #include <linux/termios.h>
71 #include <linux/bitops.h>
72 #include <linux/workqueue.h>
73 #include <linux/hdlc.h>
74 #include <linux/synclink.h>
75
76 #include <asm/system.h>
77 #include <asm/io.h>
78 #include <asm/irq.h>
79 #include <asm/dma.h>
80 #include <asm/types.h>
81 #include <asm/uaccess.h>
82
83 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
84 #define SYNCLINK_GENERIC_HDLC 1
85 #else
86 #define SYNCLINK_GENERIC_HDLC 0
87 #endif
88
89 /*
90 * module identification
91 */
92 static char *driver_name = "SyncLink GT";
93 static char *tty_driver_name = "synclink_gt";
94 static char *tty_dev_prefix = "ttySLG";
95 MODULE_LICENSE("GPL");
96 #define MGSL_MAGIC 0x5401
97 #define MAX_DEVICES 32
98
99 static struct pci_device_id pci_table[] = {
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {0,}, /* terminate list */
105 };
106 MODULE_DEVICE_TABLE(pci, pci_table);
107
108 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
109 static void remove_one(struct pci_dev *dev);
110 static struct pci_driver pci_driver = {
111 .name = "synclink_gt",
112 .id_table = pci_table,
113 .probe = init_one,
114 .remove = __devexit_p(remove_one),
115 };
116
117 static bool pci_registered;
118
119 /*
120 * module configuration and status
121 */
122 static struct slgt_info *slgt_device_list;
123 static int slgt_device_count;
124
125 static int ttymajor;
126 static int debug_level;
127 static int maxframe[MAX_DEVICES];
128
129 module_param(ttymajor, int, 0);
130 module_param(debug_level, int, 0);
131 module_param_array(maxframe, int, NULL, 0);
132
133 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
134 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
135 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
136
137 /*
138 * tty support and callbacks
139 */
140 static struct tty_driver *serial_driver;
141
142 static int open(struct tty_struct *tty, struct file * filp);
143 static void close(struct tty_struct *tty, struct file * filp);
144 static void hangup(struct tty_struct *tty);
145 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
146
147 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
148 static int put_char(struct tty_struct *tty, unsigned char ch);
149 static void send_xchar(struct tty_struct *tty, char ch);
150 static void wait_until_sent(struct tty_struct *tty, int timeout);
151 static int write_room(struct tty_struct *tty);
152 static void flush_chars(struct tty_struct *tty);
153 static void flush_buffer(struct tty_struct *tty);
154 static void tx_hold(struct tty_struct *tty);
155 static void tx_release(struct tty_struct *tty);
156
157 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
158 static int chars_in_buffer(struct tty_struct *tty);
159 static void throttle(struct tty_struct * tty);
160 static void unthrottle(struct tty_struct * tty);
161 static int set_break(struct tty_struct *tty, int break_state);
162
163 /*
164 * generic HDLC support and callbacks
165 */
166 #if SYNCLINK_GENERIC_HDLC
167 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
168 static void hdlcdev_tx_done(struct slgt_info *info);
169 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
170 static int hdlcdev_init(struct slgt_info *info);
171 static void hdlcdev_exit(struct slgt_info *info);
172 #endif
173
174
175 /*
176 * device specific structures, macros and functions
177 */
178
179 #define SLGT_MAX_PORTS 4
180 #define SLGT_REG_SIZE 256
181
182 /*
183 * conditional wait facility
184 */
185 struct cond_wait {
186 struct cond_wait *next;
187 wait_queue_head_t q;
188 wait_queue_t wait;
189 unsigned int data;
190 };
191 static void init_cond_wait(struct cond_wait *w, unsigned int data);
192 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
194 static void flush_cond_wait(struct cond_wait **head);
195
196 /*
197 * DMA buffer descriptor and access macros
198 */
199 struct slgt_desc
200 {
201 __le16 count;
202 __le16 status;
203 __le32 pbuf; /* physical address of data buffer */
204 __le32 next; /* physical address of next descriptor */
205
206 /* driver book keeping */
207 char *buf; /* virtual address of data buffer */
208 unsigned int pdesc; /* physical address of this descriptor */
209 dma_addr_t buf_dma_addr;
210 unsigned short buf_count;
211 };
212
213 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
214 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
215 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
216 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
217 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
218 #define desc_count(a) (le16_to_cpu((a).count))
219 #define desc_status(a) (le16_to_cpu((a).status))
220 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
221 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
222 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
223 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
224 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
225
226 struct _input_signal_events {
227 int ri_up;
228 int ri_down;
229 int dsr_up;
230 int dsr_down;
231 int dcd_up;
232 int dcd_down;
233 int cts_up;
234 int cts_down;
235 };
236
237 /*
238 * device instance data structure
239 */
240 struct slgt_info {
241 void *if_ptr; /* General purpose pointer (used by SPPP) */
242 struct tty_port port;
243
244 struct slgt_info *next_device; /* device list link */
245
246 int magic;
247
248 char device_name[25];
249 struct pci_dev *pdev;
250
251 int port_count; /* count of ports on adapter */
252 int adapter_num; /* adapter instance number */
253 int port_num; /* port instance number */
254
255 /* array of pointers to port contexts on this adapter */
256 struct slgt_info *port_array[SLGT_MAX_PORTS];
257
258 int line; /* tty line instance number */
259
260 struct mgsl_icount icount;
261
262 int timeout;
263 int x_char; /* xon/xoff character */
264 unsigned int read_status_mask;
265 unsigned int ignore_status_mask;
266
267 wait_queue_head_t status_event_wait_q;
268 wait_queue_head_t event_wait_q;
269 struct timer_list tx_timer;
270 struct timer_list rx_timer;
271
272 unsigned int gpio_present;
273 struct cond_wait *gpio_wait_q;
274
275 spinlock_t lock; /* spinlock for synchronizing with ISR */
276
277 struct work_struct task;
278 u32 pending_bh;
279 bool bh_requested;
280 bool bh_running;
281
282 int isr_overflow;
283 bool irq_requested; /* true if IRQ requested */
284 bool irq_occurred; /* for diagnostics use */
285
286 /* device configuration */
287
288 unsigned int bus_type;
289 unsigned int irq_level;
290 unsigned long irq_flags;
291
292 unsigned char __iomem * reg_addr; /* memory mapped registers address */
293 u32 phys_reg_addr;
294 bool reg_addr_requested;
295
296 MGSL_PARAMS params; /* communications parameters */
297 u32 idle_mode;
298 u32 max_frame_size; /* as set by device config */
299
300 unsigned int rbuf_fill_level;
301 unsigned int rx_pio;
302 unsigned int if_mode;
303 unsigned int base_clock;
304
305 /* device status */
306
307 bool rx_enabled;
308 bool rx_restart;
309
310 bool tx_enabled;
311 bool tx_active;
312
313 unsigned char signals; /* serial signal states */
314 int init_error; /* initialization error */
315
316 unsigned char *tx_buf;
317 int tx_count;
318
319 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
320 char char_buf[MAX_ASYNC_BUFFER_SIZE];
321 bool drop_rts_on_tx_done;
322 struct _input_signal_events input_signal_events;
323
324 int dcd_chkcount; /* check counts to prevent */
325 int cts_chkcount; /* too many IRQs if a signal */
326 int dsr_chkcount; /* is floating */
327 int ri_chkcount;
328
329 char *bufs; /* virtual address of DMA buffer lists */
330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
331
332 unsigned int rbuf_count;
333 struct slgt_desc *rbufs;
334 unsigned int rbuf_current;
335 unsigned int rbuf_index;
336 unsigned int rbuf_fill_index;
337 unsigned short rbuf_fill_count;
338
339 unsigned int tbuf_count;
340 struct slgt_desc *tbufs;
341 unsigned int tbuf_current;
342 unsigned int tbuf_start;
343
344 unsigned char *tmp_rbuf;
345 unsigned int tmp_rbuf_count;
346
347 /* SPPP/Cisco HDLC device parts */
348
349 int netcount;
350 spinlock_t netlock;
351 #if SYNCLINK_GENERIC_HDLC
352 struct net_device *netdev;
353 #endif
354
355 };
356
357 static MGSL_PARAMS default_params = {
358 .mode = MGSL_MODE_HDLC,
359 .loopback = 0,
360 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
361 .encoding = HDLC_ENCODING_NRZI_SPACE,
362 .clock_speed = 0,
363 .addr_filter = 0xff,
364 .crc_type = HDLC_CRC_16_CCITT,
365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
367 .data_rate = 9600,
368 .data_bits = 8,
369 .stop_bits = 1,
370 .parity = ASYNC_PARITY_NONE
371 };
372
373
374 #define BH_RECEIVE 1
375 #define BH_TRANSMIT 2
376 #define BH_STATUS 4
377 #define IO_PIN_SHUTDOWN_LIMIT 100
378
379 #define DMABUFSIZE 256
380 #define DESC_LIST_SIZE 4096
381
382 #define MASK_PARITY BIT1
383 #define MASK_FRAMING BIT0
384 #define MASK_BREAK BIT14
385 #define MASK_OVERRUN BIT4
386
387 #define GSR 0x00 /* global status */
388 #define JCR 0x04 /* JTAG control */
389 #define IODR 0x08 /* GPIO direction */
390 #define IOER 0x0c /* GPIO interrupt enable */
391 #define IOVR 0x10 /* GPIO value */
392 #define IOSR 0x14 /* GPIO interrupt status */
393 #define TDR 0x80 /* tx data */
394 #define RDR 0x80 /* rx data */
395 #define TCR 0x82 /* tx control */
396 #define TIR 0x84 /* tx idle */
397 #define TPR 0x85 /* tx preamble */
398 #define RCR 0x86 /* rx control */
399 #define VCR 0x88 /* V.24 control */
400 #define CCR 0x89 /* clock control */
401 #define BDR 0x8a /* baud divisor */
402 #define SCR 0x8c /* serial control */
403 #define SSR 0x8e /* serial status */
404 #define RDCSR 0x90 /* rx DMA control/status */
405 #define TDCSR 0x94 /* tx DMA control/status */
406 #define RDDAR 0x98 /* rx DMA descriptor address */
407 #define TDDAR 0x9c /* tx DMA descriptor address */
408
409 #define RXIDLE BIT14
410 #define RXBREAK BIT14
411 #define IRQ_TXDATA BIT13
412 #define IRQ_TXIDLE BIT12
413 #define IRQ_TXUNDER BIT11 /* HDLC */
414 #define IRQ_RXDATA BIT10
415 #define IRQ_RXIDLE BIT9 /* HDLC */
416 #define IRQ_RXBREAK BIT9 /* async */
417 #define IRQ_RXOVER BIT8
418 #define IRQ_DSR BIT7
419 #define IRQ_CTS BIT6
420 #define IRQ_DCD BIT5
421 #define IRQ_RI BIT4
422 #define IRQ_ALL 0x3ff0
423 #define IRQ_MASTER BIT0
424
425 #define slgt_irq_on(info, mask) \
426 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
427 #define slgt_irq_off(info, mask) \
428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
429
430 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
431 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
432 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
433 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
434 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
435 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
436
437 static void msc_set_vcr(struct slgt_info *info);
438
439 static int startup(struct slgt_info *info);
440 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
441 static void shutdown(struct slgt_info *info);
442 static void program_hw(struct slgt_info *info);
443 static void change_params(struct slgt_info *info);
444
445 static int register_test(struct slgt_info *info);
446 static int irq_test(struct slgt_info *info);
447 static int loopback_test(struct slgt_info *info);
448 static int adapter_test(struct slgt_info *info);
449
450 static void reset_adapter(struct slgt_info *info);
451 static void reset_port(struct slgt_info *info);
452 static void async_mode(struct slgt_info *info);
453 static void sync_mode(struct slgt_info *info);
454
455 static void rx_stop(struct slgt_info *info);
456 static void rx_start(struct slgt_info *info);
457 static void reset_rbufs(struct slgt_info *info);
458 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
459 static void rdma_reset(struct slgt_info *info);
460 static bool rx_get_frame(struct slgt_info *info);
461 static bool rx_get_buf(struct slgt_info *info);
462
463 static void tx_start(struct slgt_info *info);
464 static void tx_stop(struct slgt_info *info);
465 static void tx_set_idle(struct slgt_info *info);
466 static unsigned int free_tbuf_count(struct slgt_info *info);
467 static unsigned int tbuf_bytes(struct slgt_info *info);
468 static void reset_tbufs(struct slgt_info *info);
469 static void tdma_reset(struct slgt_info *info);
470 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
471
472 static void get_signals(struct slgt_info *info);
473 static void set_signals(struct slgt_info *info);
474 static void enable_loopback(struct slgt_info *info);
475 static void set_rate(struct slgt_info *info, u32 data_rate);
476
477 static int bh_action(struct slgt_info *info);
478 static void bh_handler(struct work_struct *work);
479 static void bh_transmit(struct slgt_info *info);
480 static void isr_serial(struct slgt_info *info);
481 static void isr_rdma(struct slgt_info *info);
482 static void isr_txeom(struct slgt_info *info, unsigned short status);
483 static void isr_tdma(struct slgt_info *info);
484
485 static int alloc_dma_bufs(struct slgt_info *info);
486 static void free_dma_bufs(struct slgt_info *info);
487 static int alloc_desc(struct slgt_info *info);
488 static void free_desc(struct slgt_info *info);
489 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
490 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
491
492 static int alloc_tmp_rbuf(struct slgt_info *info);
493 static void free_tmp_rbuf(struct slgt_info *info);
494
495 static void tx_timeout(unsigned long context);
496 static void rx_timeout(unsigned long context);
497
498 /*
499 * ioctl handlers
500 */
501 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
502 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
503 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
504 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
505 static int set_txidle(struct slgt_info *info, int idle_mode);
506 static int tx_enable(struct slgt_info *info, int enable);
507 static int tx_abort(struct slgt_info *info);
508 static int rx_enable(struct slgt_info *info, int enable);
509 static int modem_input_wait(struct slgt_info *info,int arg);
510 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
511 static int tiocmget(struct tty_struct *tty, struct file *file);
512 static int tiocmset(struct tty_struct *tty, struct file *file,
513 unsigned int set, unsigned int clear);
514 static int set_break(struct tty_struct *tty, int break_state);
515 static int get_interface(struct slgt_info *info, int __user *if_mode);
516 static int set_interface(struct slgt_info *info, int if_mode);
517 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
518 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
519 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520
521 /*
522 * driver functions
523 */
524 static void add_device(struct slgt_info *info);
525 static void device_init(int adapter_num, struct pci_dev *pdev);
526 static int claim_resources(struct slgt_info *info);
527 static void release_resources(struct slgt_info *info);
528
529 /*
530 * DEBUG OUTPUT CODE
531 */
532 #ifndef DBGINFO
533 #define DBGINFO(fmt)
534 #endif
535 #ifndef DBGERR
536 #define DBGERR(fmt)
537 #endif
538 #ifndef DBGBH
539 #define DBGBH(fmt)
540 #endif
541 #ifndef DBGISR
542 #define DBGISR(fmt)
543 #endif
544
545 #ifdef DBGDATA
546 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
547 {
548 int i;
549 int linecount;
550 printk("%s %s data:\n",info->device_name, label);
551 while(count) {
552 linecount = (count > 16) ? 16 : count;
553 for(i=0; i < linecount; i++)
554 printk("%02X ",(unsigned char)data[i]);
555 for(;i<17;i++)
556 printk(" ");
557 for(i=0;i<linecount;i++) {
558 if (data[i]>=040 && data[i]<=0176)
559 printk("%c",data[i]);
560 else
561 printk(".");
562 }
563 printk("\n");
564 data += linecount;
565 count -= linecount;
566 }
567 }
568 #else
569 #define DBGDATA(info, buf, size, label)
570 #endif
571
572 #ifdef DBGTBUF
573 static void dump_tbufs(struct slgt_info *info)
574 {
575 int i;
576 printk("tbuf_current=%d\n", info->tbuf_current);
577 for (i=0 ; i < info->tbuf_count ; i++) {
578 printk("%d: count=%04X status=%04X\n",
579 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
580 }
581 }
582 #else
583 #define DBGTBUF(info)
584 #endif
585
586 #ifdef DBGRBUF
587 static void dump_rbufs(struct slgt_info *info)
588 {
589 int i;
590 printk("rbuf_current=%d\n", info->rbuf_current);
591 for (i=0 ; i < info->rbuf_count ; i++) {
592 printk("%d: count=%04X status=%04X\n",
593 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
594 }
595 }
596 #else
597 #define DBGRBUF(info)
598 #endif
599
600 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
601 {
602 #ifdef SANITY_CHECK
603 if (!info) {
604 printk("null struct slgt_info for (%s) in %s\n", devname, name);
605 return 1;
606 }
607 if (info->magic != MGSL_MAGIC) {
608 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
609 return 1;
610 }
611 #else
612 if (!info)
613 return 1;
614 #endif
615 return 0;
616 }
617
618 /**
619 * line discipline callback wrappers
620 *
621 * The wrappers maintain line discipline references
622 * while calling into the line discipline.
623 *
624 * ldisc_receive_buf - pass receive data to line discipline
625 */
626 static void ldisc_receive_buf(struct tty_struct *tty,
627 const __u8 *data, char *flags, int count)
628 {
629 struct tty_ldisc *ld;
630 if (!tty)
631 return;
632 ld = tty_ldisc_ref(tty);
633 if (ld) {
634 if (ld->ops->receive_buf)
635 ld->ops->receive_buf(tty, data, flags, count);
636 tty_ldisc_deref(ld);
637 }
638 }
639
640 /* tty callbacks */
641
642 static int open(struct tty_struct *tty, struct file *filp)
643 {
644 struct slgt_info *info;
645 int retval, line;
646 unsigned long flags;
647
648 line = tty->index;
649 if ((line < 0) || (line >= slgt_device_count)) {
650 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
651 return -ENODEV;
652 }
653
654 info = slgt_device_list;
655 while(info && info->line != line)
656 info = info->next_device;
657 if (sanity_check(info, tty->name, "open"))
658 return -ENODEV;
659 if (info->init_error) {
660 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
661 return -ENODEV;
662 }
663
664 tty->driver_data = info;
665 info->port.tty = tty;
666
667 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
668
669 /* If port is closing, signal caller to try again */
670 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
671 if (info->port.flags & ASYNC_CLOSING)
672 interruptible_sleep_on(&info->port.close_wait);
673 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
674 -EAGAIN : -ERESTARTSYS);
675 goto cleanup;
676 }
677
678 mutex_lock(&info->port.mutex);
679 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
680
681 spin_lock_irqsave(&info->netlock, flags);
682 if (info->netcount) {
683 retval = -EBUSY;
684 spin_unlock_irqrestore(&info->netlock, flags);
685 mutex_unlock(&info->port.mutex);
686 goto cleanup;
687 }
688 info->port.count++;
689 spin_unlock_irqrestore(&info->netlock, flags);
690
691 if (info->port.count == 1) {
692 /* 1st open on this device, init hardware */
693 retval = startup(info);
694 if (retval < 0) {
695 mutex_unlock(&info->port.mutex);
696 goto cleanup;
697 }
698 }
699 mutex_unlock(&info->port.mutex);
700 retval = block_til_ready(tty, filp, info);
701 if (retval) {
702 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
703 goto cleanup;
704 }
705
706 retval = 0;
707
708 cleanup:
709 if (retval) {
710 if (tty->count == 1)
711 info->port.tty = NULL; /* tty layer will release tty struct */
712 if(info->port.count)
713 info->port.count--;
714 }
715
716 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
717 return retval;
718 }
719
720 static void close(struct tty_struct *tty, struct file *filp)
721 {
722 struct slgt_info *info = tty->driver_data;
723
724 if (sanity_check(info, tty->name, "close"))
725 return;
726 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
727
728 if (tty_port_close_start(&info->port, tty, filp) == 0)
729 goto cleanup;
730
731 mutex_lock(&info->port.mutex);
732 if (info->port.flags & ASYNC_INITIALIZED)
733 wait_until_sent(tty, info->timeout);
734 flush_buffer(tty);
735 tty_ldisc_flush(tty);
736
737 shutdown(info);
738 mutex_unlock(&info->port.mutex);
739
740 tty_port_close_end(&info->port, tty);
741 info->port.tty = NULL;
742 cleanup:
743 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
744 }
745
746 static void hangup(struct tty_struct *tty)
747 {
748 struct slgt_info *info = tty->driver_data;
749 unsigned long flags;
750
751 if (sanity_check(info, tty->name, "hangup"))
752 return;
753 DBGINFO(("%s hangup\n", info->device_name));
754
755 flush_buffer(tty);
756
757 mutex_lock(&info->port.mutex);
758 shutdown(info);
759
760 spin_lock_irqsave(&info->port.lock, flags);
761 info->port.count = 0;
762 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
763 info->port.tty = NULL;
764 spin_unlock_irqrestore(&info->port.lock, flags);
765 mutex_unlock(&info->port.mutex);
766
767 wake_up_interruptible(&info->port.open_wait);
768 }
769
770 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
771 {
772 struct slgt_info *info = tty->driver_data;
773 unsigned long flags;
774
775 DBGINFO(("%s set_termios\n", tty->driver->name));
776
777 change_params(info);
778
779 /* Handle transition to B0 status */
780 if (old_termios->c_cflag & CBAUD &&
781 !(tty->termios->c_cflag & CBAUD)) {
782 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
783 spin_lock_irqsave(&info->lock,flags);
784 set_signals(info);
785 spin_unlock_irqrestore(&info->lock,flags);
786 }
787
788 /* Handle transition away from B0 status */
789 if (!(old_termios->c_cflag & CBAUD) &&
790 tty->termios->c_cflag & CBAUD) {
791 info->signals |= SerialSignal_DTR;
792 if (!(tty->termios->c_cflag & CRTSCTS) ||
793 !test_bit(TTY_THROTTLED, &tty->flags)) {
794 info->signals |= SerialSignal_RTS;
795 }
796 spin_lock_irqsave(&info->lock,flags);
797 set_signals(info);
798 spin_unlock_irqrestore(&info->lock,flags);
799 }
800
801 /* Handle turning off CRTSCTS */
802 if (old_termios->c_cflag & CRTSCTS &&
803 !(tty->termios->c_cflag & CRTSCTS)) {
804 tty->hw_stopped = 0;
805 tx_release(tty);
806 }
807 }
808
809 static void update_tx_timer(struct slgt_info *info)
810 {
811 /*
812 * use worst case speed of 1200bps to calculate transmit timeout
813 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
814 */
815 if (info->params.mode == MGSL_MODE_HDLC) {
816 int timeout = (tbuf_bytes(info) * 7) + 1000;
817 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
818 }
819 }
820
821 static int write(struct tty_struct *tty,
822 const unsigned char *buf, int count)
823 {
824 int ret = 0;
825 struct slgt_info *info = tty->driver_data;
826 unsigned long flags;
827
828 if (sanity_check(info, tty->name, "write"))
829 return -EIO;
830
831 DBGINFO(("%s write count=%d\n", info->device_name, count));
832
833 if (!info->tx_buf || (count > info->max_frame_size))
834 return -EIO;
835
836 if (!count || tty->stopped || tty->hw_stopped)
837 return 0;
838
839 spin_lock_irqsave(&info->lock, flags);
840
841 if (info->tx_count) {
842 /* send accumulated data from send_char() */
843 if (!tx_load(info, info->tx_buf, info->tx_count))
844 goto cleanup;
845 info->tx_count = 0;
846 }
847
848 if (tx_load(info, buf, count))
849 ret = count;
850
851 cleanup:
852 spin_unlock_irqrestore(&info->lock, flags);
853 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
854 return ret;
855 }
856
857 static int put_char(struct tty_struct *tty, unsigned char ch)
858 {
859 struct slgt_info *info = tty->driver_data;
860 unsigned long flags;
861 int ret = 0;
862
863 if (sanity_check(info, tty->name, "put_char"))
864 return 0;
865 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
866 if (!info->tx_buf)
867 return 0;
868 spin_lock_irqsave(&info->lock,flags);
869 if (info->tx_count < info->max_frame_size) {
870 info->tx_buf[info->tx_count++] = ch;
871 ret = 1;
872 }
873 spin_unlock_irqrestore(&info->lock,flags);
874 return ret;
875 }
876
877 static void send_xchar(struct tty_struct *tty, char ch)
878 {
879 struct slgt_info *info = tty->driver_data;
880 unsigned long flags;
881
882 if (sanity_check(info, tty->name, "send_xchar"))
883 return;
884 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
885 info->x_char = ch;
886 if (ch) {
887 spin_lock_irqsave(&info->lock,flags);
888 if (!info->tx_enabled)
889 tx_start(info);
890 spin_unlock_irqrestore(&info->lock,flags);
891 }
892 }
893
894 static void wait_until_sent(struct tty_struct *tty, int timeout)
895 {
896 struct slgt_info *info = tty->driver_data;
897 unsigned long orig_jiffies, char_time;
898
899 if (!info )
900 return;
901 if (sanity_check(info, tty->name, "wait_until_sent"))
902 return;
903 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
904 if (!(info->port.flags & ASYNC_INITIALIZED))
905 goto exit;
906
907 orig_jiffies = jiffies;
908
909 /* Set check interval to 1/5 of estimated time to
910 * send a character, and make it at least 1. The check
911 * interval should also be less than the timeout.
912 * Note: use tight timings here to satisfy the NIST-PCTS.
913 */
914
915 if (info->params.data_rate) {
916 char_time = info->timeout/(32 * 5);
917 if (!char_time)
918 char_time++;
919 } else
920 char_time = 1;
921
922 if (timeout)
923 char_time = min_t(unsigned long, char_time, timeout);
924
925 while (info->tx_active) {
926 msleep_interruptible(jiffies_to_msecs(char_time));
927 if (signal_pending(current))
928 break;
929 if (timeout && time_after(jiffies, orig_jiffies + timeout))
930 break;
931 }
932 exit:
933 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
934 }
935
936 static int write_room(struct tty_struct *tty)
937 {
938 struct slgt_info *info = tty->driver_data;
939 int ret;
940
941 if (sanity_check(info, tty->name, "write_room"))
942 return 0;
943 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
944 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
945 return ret;
946 }
947
948 static void flush_chars(struct tty_struct *tty)
949 {
950 struct slgt_info *info = tty->driver_data;
951 unsigned long flags;
952
953 if (sanity_check(info, tty->name, "flush_chars"))
954 return;
955 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
956
957 if (info->tx_count <= 0 || tty->stopped ||
958 tty->hw_stopped || !info->tx_buf)
959 return;
960
961 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
962
963 spin_lock_irqsave(&info->lock,flags);
964 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
965 info->tx_count = 0;
966 spin_unlock_irqrestore(&info->lock,flags);
967 }
968
969 static void flush_buffer(struct tty_struct *tty)
970 {
971 struct slgt_info *info = tty->driver_data;
972 unsigned long flags;
973
974 if (sanity_check(info, tty->name, "flush_buffer"))
975 return;
976 DBGINFO(("%s flush_buffer\n", info->device_name));
977
978 spin_lock_irqsave(&info->lock, flags);
979 info->tx_count = 0;
980 spin_unlock_irqrestore(&info->lock, flags);
981
982 tty_wakeup(tty);
983 }
984
985 /*
986 * throttle (stop) transmitter
987 */
988 static void tx_hold(struct tty_struct *tty)
989 {
990 struct slgt_info *info = tty->driver_data;
991 unsigned long flags;
992
993 if (sanity_check(info, tty->name, "tx_hold"))
994 return;
995 DBGINFO(("%s tx_hold\n", info->device_name));
996 spin_lock_irqsave(&info->lock,flags);
997 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
998 tx_stop(info);
999 spin_unlock_irqrestore(&info->lock,flags);
1000 }
1001
1002 /*
1003 * release (start) transmitter
1004 */
1005 static void tx_release(struct tty_struct *tty)
1006 {
1007 struct slgt_info *info = tty->driver_data;
1008 unsigned long flags;
1009
1010 if (sanity_check(info, tty->name, "tx_release"))
1011 return;
1012 DBGINFO(("%s tx_release\n", info->device_name));
1013 spin_lock_irqsave(&info->lock, flags);
1014 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1015 info->tx_count = 0;
1016 spin_unlock_irqrestore(&info->lock, flags);
1017 }
1018
1019 /*
1020 * Service an IOCTL request
1021 *
1022 * Arguments
1023 *
1024 * tty pointer to tty instance data
1025 * file pointer to associated file object for device
1026 * cmd IOCTL command code
1027 * arg command argument/context
1028 *
1029 * Return 0 if success, otherwise error code
1030 */
1031 static int ioctl(struct tty_struct *tty, struct file *file,
1032 unsigned int cmd, unsigned long arg)
1033 {
1034 struct slgt_info *info = tty->driver_data;
1035 struct mgsl_icount cnow; /* kernel counter temps */
1036 struct serial_icounter_struct __user *p_cuser; /* user space */
1037 unsigned long flags;
1038 void __user *argp = (void __user *)arg;
1039 int ret;
1040
1041 if (sanity_check(info, tty->name, "ioctl"))
1042 return -ENODEV;
1043 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1044
1045 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1046 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1047 if (tty->flags & (1 << TTY_IO_ERROR))
1048 return -EIO;
1049 }
1050
1051 switch (cmd) {
1052 case MGSL_IOCWAITEVENT:
1053 return wait_mgsl_event(info, argp);
1054 case TIOCMIWAIT:
1055 return modem_input_wait(info,(int)arg);
1056 case TIOCGICOUNT:
1057 spin_lock_irqsave(&info->lock,flags);
1058 cnow = info->icount;
1059 spin_unlock_irqrestore(&info->lock,flags);
1060 p_cuser = argp;
1061 if (put_user(cnow.cts, &p_cuser->cts) ||
1062 put_user(cnow.dsr, &p_cuser->dsr) ||
1063 put_user(cnow.rng, &p_cuser->rng) ||
1064 put_user(cnow.dcd, &p_cuser->dcd) ||
1065 put_user(cnow.rx, &p_cuser->rx) ||
1066 put_user(cnow.tx, &p_cuser->tx) ||
1067 put_user(cnow.frame, &p_cuser->frame) ||
1068 put_user(cnow.overrun, &p_cuser->overrun) ||
1069 put_user(cnow.parity, &p_cuser->parity) ||
1070 put_user(cnow.brk, &p_cuser->brk) ||
1071 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1072 return -EFAULT;
1073 return 0;
1074 case MGSL_IOCSGPIO:
1075 return set_gpio(info, argp);
1076 case MGSL_IOCGGPIO:
1077 return get_gpio(info, argp);
1078 case MGSL_IOCWAITGPIO:
1079 return wait_gpio(info, argp);
1080 }
1081 mutex_lock(&info->port.mutex);
1082 switch (cmd) {
1083 case MGSL_IOCGPARAMS:
1084 ret = get_params(info, argp);
1085 break;
1086 case MGSL_IOCSPARAMS:
1087 ret = set_params(info, argp);
1088 break;
1089 case MGSL_IOCGTXIDLE:
1090 ret = get_txidle(info, argp);
1091 break;
1092 case MGSL_IOCSTXIDLE:
1093 ret = set_txidle(info, (int)arg);
1094 break;
1095 case MGSL_IOCTXENABLE:
1096 ret = tx_enable(info, (int)arg);
1097 break;
1098 case MGSL_IOCRXENABLE:
1099 ret = rx_enable(info, (int)arg);
1100 break;
1101 case MGSL_IOCTXABORT:
1102 ret = tx_abort(info);
1103 break;
1104 case MGSL_IOCGSTATS:
1105 ret = get_stats(info, argp);
1106 break;
1107 case MGSL_IOCGIF:
1108 ret = get_interface(info, argp);
1109 break;
1110 case MGSL_IOCSIF:
1111 ret = set_interface(info,(int)arg);
1112 break;
1113 default:
1114 ret = -ENOIOCTLCMD;
1115 }
1116 mutex_unlock(&info->port.mutex);
1117 return ret;
1118 }
1119
1120 /*
1121 * support for 32 bit ioctl calls on 64 bit systems
1122 */
1123 #ifdef CONFIG_COMPAT
1124 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1125 {
1126 struct MGSL_PARAMS32 tmp_params;
1127
1128 DBGINFO(("%s get_params32\n", info->device_name));
1129 tmp_params.mode = (compat_ulong_t)info->params.mode;
1130 tmp_params.loopback = info->params.loopback;
1131 tmp_params.flags = info->params.flags;
1132 tmp_params.encoding = info->params.encoding;
1133 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1134 tmp_params.addr_filter = info->params.addr_filter;
1135 tmp_params.crc_type = info->params.crc_type;
1136 tmp_params.preamble_length = info->params.preamble_length;
1137 tmp_params.preamble = info->params.preamble;
1138 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1139 tmp_params.data_bits = info->params.data_bits;
1140 tmp_params.stop_bits = info->params.stop_bits;
1141 tmp_params.parity = info->params.parity;
1142 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1143 return -EFAULT;
1144 return 0;
1145 }
1146
1147 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1148 {
1149 struct MGSL_PARAMS32 tmp_params;
1150
1151 DBGINFO(("%s set_params32\n", info->device_name));
1152 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1153 return -EFAULT;
1154
1155 spin_lock(&info->lock);
1156 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1157 info->base_clock = tmp_params.clock_speed;
1158 } else {
1159 info->params.mode = tmp_params.mode;
1160 info->params.loopback = tmp_params.loopback;
1161 info->params.flags = tmp_params.flags;
1162 info->params.encoding = tmp_params.encoding;
1163 info->params.clock_speed = tmp_params.clock_speed;
1164 info->params.addr_filter = tmp_params.addr_filter;
1165 info->params.crc_type = tmp_params.crc_type;
1166 info->params.preamble_length = tmp_params.preamble_length;
1167 info->params.preamble = tmp_params.preamble;
1168 info->params.data_rate = tmp_params.data_rate;
1169 info->params.data_bits = tmp_params.data_bits;
1170 info->params.stop_bits = tmp_params.stop_bits;
1171 info->params.parity = tmp_params.parity;
1172 }
1173 spin_unlock(&info->lock);
1174
1175 program_hw(info);
1176
1177 return 0;
1178 }
1179
1180 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1181 unsigned int cmd, unsigned long arg)
1182 {
1183 struct slgt_info *info = tty->driver_data;
1184 int rc = -ENOIOCTLCMD;
1185
1186 if (sanity_check(info, tty->name, "compat_ioctl"))
1187 return -ENODEV;
1188 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1189
1190 switch (cmd) {
1191
1192 case MGSL_IOCSPARAMS32:
1193 rc = set_params32(info, compat_ptr(arg));
1194 break;
1195
1196 case MGSL_IOCGPARAMS32:
1197 rc = get_params32(info, compat_ptr(arg));
1198 break;
1199
1200 case MGSL_IOCGPARAMS:
1201 case MGSL_IOCSPARAMS:
1202 case MGSL_IOCGTXIDLE:
1203 case MGSL_IOCGSTATS:
1204 case MGSL_IOCWAITEVENT:
1205 case MGSL_IOCGIF:
1206 case MGSL_IOCSGPIO:
1207 case MGSL_IOCGGPIO:
1208 case MGSL_IOCWAITGPIO:
1209 case TIOCGICOUNT:
1210 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1211 break;
1212
1213 case MGSL_IOCSTXIDLE:
1214 case MGSL_IOCTXENABLE:
1215 case MGSL_IOCRXENABLE:
1216 case MGSL_IOCTXABORT:
1217 case TIOCMIWAIT:
1218 case MGSL_IOCSIF:
1219 rc = ioctl(tty, file, cmd, arg);
1220 break;
1221 }
1222
1223 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1224 return rc;
1225 }
1226 #else
1227 #define slgt_compat_ioctl NULL
1228 #endif /* ifdef CONFIG_COMPAT */
1229
1230 /*
1231 * proc fs support
1232 */
1233 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1234 {
1235 char stat_buf[30];
1236 unsigned long flags;
1237
1238 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1239 info->device_name, info->phys_reg_addr,
1240 info->irq_level, info->max_frame_size);
1241
1242 /* output current serial signal states */
1243 spin_lock_irqsave(&info->lock,flags);
1244 get_signals(info);
1245 spin_unlock_irqrestore(&info->lock,flags);
1246
1247 stat_buf[0] = 0;
1248 stat_buf[1] = 0;
1249 if (info->signals & SerialSignal_RTS)
1250 strcat(stat_buf, "|RTS");
1251 if (info->signals & SerialSignal_CTS)
1252 strcat(stat_buf, "|CTS");
1253 if (info->signals & SerialSignal_DTR)
1254 strcat(stat_buf, "|DTR");
1255 if (info->signals & SerialSignal_DSR)
1256 strcat(stat_buf, "|DSR");
1257 if (info->signals & SerialSignal_DCD)
1258 strcat(stat_buf, "|CD");
1259 if (info->signals & SerialSignal_RI)
1260 strcat(stat_buf, "|RI");
1261
1262 if (info->params.mode != MGSL_MODE_ASYNC) {
1263 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1264 info->icount.txok, info->icount.rxok);
1265 if (info->icount.txunder)
1266 seq_printf(m, " txunder:%d", info->icount.txunder);
1267 if (info->icount.txabort)
1268 seq_printf(m, " txabort:%d", info->icount.txabort);
1269 if (info->icount.rxshort)
1270 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1271 if (info->icount.rxlong)
1272 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1273 if (info->icount.rxover)
1274 seq_printf(m, " rxover:%d", info->icount.rxover);
1275 if (info->icount.rxcrc)
1276 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1277 } else {
1278 seq_printf(m, "\tASYNC tx:%d rx:%d",
1279 info->icount.tx, info->icount.rx);
1280 if (info->icount.frame)
1281 seq_printf(m, " fe:%d", info->icount.frame);
1282 if (info->icount.parity)
1283 seq_printf(m, " pe:%d", info->icount.parity);
1284 if (info->icount.brk)
1285 seq_printf(m, " brk:%d", info->icount.brk);
1286 if (info->icount.overrun)
1287 seq_printf(m, " oe:%d", info->icount.overrun);
1288 }
1289
1290 /* Append serial signal status to end */
1291 seq_printf(m, " %s\n", stat_buf+1);
1292
1293 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1294 info->tx_active,info->bh_requested,info->bh_running,
1295 info->pending_bh);
1296 }
1297
1298 /* Called to print information about devices
1299 */
1300 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1301 {
1302 struct slgt_info *info;
1303
1304 seq_puts(m, "synclink_gt driver\n");
1305
1306 info = slgt_device_list;
1307 while( info ) {
1308 line_info(m, info);
1309 info = info->next_device;
1310 }
1311 return 0;
1312 }
1313
1314 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1315 {
1316 return single_open(file, synclink_gt_proc_show, NULL);
1317 }
1318
1319 static const struct file_operations synclink_gt_proc_fops = {
1320 .owner = THIS_MODULE,
1321 .open = synclink_gt_proc_open,
1322 .read = seq_read,
1323 .llseek = seq_lseek,
1324 .release = single_release,
1325 };
1326
1327 /*
1328 * return count of bytes in transmit buffer
1329 */
1330 static int chars_in_buffer(struct tty_struct *tty)
1331 {
1332 struct slgt_info *info = tty->driver_data;
1333 int count;
1334 if (sanity_check(info, tty->name, "chars_in_buffer"))
1335 return 0;
1336 count = tbuf_bytes(info);
1337 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1338 return count;
1339 }
1340
1341 /*
1342 * signal remote device to throttle send data (our receive data)
1343 */
1344 static void throttle(struct tty_struct * tty)
1345 {
1346 struct slgt_info *info = tty->driver_data;
1347 unsigned long flags;
1348
1349 if (sanity_check(info, tty->name, "throttle"))
1350 return;
1351 DBGINFO(("%s throttle\n", info->device_name));
1352 if (I_IXOFF(tty))
1353 send_xchar(tty, STOP_CHAR(tty));
1354 if (tty->termios->c_cflag & CRTSCTS) {
1355 spin_lock_irqsave(&info->lock,flags);
1356 info->signals &= ~SerialSignal_RTS;
1357 set_signals(info);
1358 spin_unlock_irqrestore(&info->lock,flags);
1359 }
1360 }
1361
1362 /*
1363 * signal remote device to stop throttling send data (our receive data)
1364 */
1365 static void unthrottle(struct tty_struct * tty)
1366 {
1367 struct slgt_info *info = tty->driver_data;
1368 unsigned long flags;
1369
1370 if (sanity_check(info, tty->name, "unthrottle"))
1371 return;
1372 DBGINFO(("%s unthrottle\n", info->device_name));
1373 if (I_IXOFF(tty)) {
1374 if (info->x_char)
1375 info->x_char = 0;
1376 else
1377 send_xchar(tty, START_CHAR(tty));
1378 }
1379 if (tty->termios->c_cflag & CRTSCTS) {
1380 spin_lock_irqsave(&info->lock,flags);
1381 info->signals |= SerialSignal_RTS;
1382 set_signals(info);
1383 spin_unlock_irqrestore(&info->lock,flags);
1384 }
1385 }
1386
1387 /*
1388 * set or clear transmit break condition
1389 * break_state -1=set break condition, 0=clear
1390 */
1391 static int set_break(struct tty_struct *tty, int break_state)
1392 {
1393 struct slgt_info *info = tty->driver_data;
1394 unsigned short value;
1395 unsigned long flags;
1396
1397 if (sanity_check(info, tty->name, "set_break"))
1398 return -EINVAL;
1399 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1400
1401 spin_lock_irqsave(&info->lock,flags);
1402 value = rd_reg16(info, TCR);
1403 if (break_state == -1)
1404 value |= BIT6;
1405 else
1406 value &= ~BIT6;
1407 wr_reg16(info, TCR, value);
1408 spin_unlock_irqrestore(&info->lock,flags);
1409 return 0;
1410 }
1411
1412 #if SYNCLINK_GENERIC_HDLC
1413
1414 /**
1415 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1416 * set encoding and frame check sequence (FCS) options
1417 *
1418 * dev pointer to network device structure
1419 * encoding serial encoding setting
1420 * parity FCS setting
1421 *
1422 * returns 0 if success, otherwise error code
1423 */
1424 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1425 unsigned short parity)
1426 {
1427 struct slgt_info *info = dev_to_port(dev);
1428 unsigned char new_encoding;
1429 unsigned short new_crctype;
1430
1431 /* return error if TTY interface open */
1432 if (info->port.count)
1433 return -EBUSY;
1434
1435 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1436
1437 switch (encoding)
1438 {
1439 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1440 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1441 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1442 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1443 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1444 default: return -EINVAL;
1445 }
1446
1447 switch (parity)
1448 {
1449 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1450 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1451 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1452 default: return -EINVAL;
1453 }
1454
1455 info->params.encoding = new_encoding;
1456 info->params.crc_type = new_crctype;
1457
1458 /* if network interface up, reprogram hardware */
1459 if (info->netcount)
1460 program_hw(info);
1461
1462 return 0;
1463 }
1464
1465 /**
1466 * called by generic HDLC layer to send frame
1467 *
1468 * skb socket buffer containing HDLC frame
1469 * dev pointer to network device structure
1470 */
1471 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1472 struct net_device *dev)
1473 {
1474 struct slgt_info *info = dev_to_port(dev);
1475 unsigned long flags;
1476
1477 DBGINFO(("%s hdlc_xmit\n", dev->name));
1478
1479 if (!skb->len)
1480 return NETDEV_TX_OK;
1481
1482 /* stop sending until this frame completes */
1483 netif_stop_queue(dev);
1484
1485 /* update network statistics */
1486 dev->stats.tx_packets++;
1487 dev->stats.tx_bytes += skb->len;
1488
1489 /* save start time for transmit timeout detection */
1490 dev->trans_start = jiffies;
1491
1492 spin_lock_irqsave(&info->lock, flags);
1493 tx_load(info, skb->data, skb->len);
1494 spin_unlock_irqrestore(&info->lock, flags);
1495
1496 /* done with socket buffer, so free it */
1497 dev_kfree_skb(skb);
1498
1499 return NETDEV_TX_OK;
1500 }
1501
1502 /**
1503 * called by network layer when interface enabled
1504 * claim resources and initialize hardware
1505 *
1506 * dev pointer to network device structure
1507 *
1508 * returns 0 if success, otherwise error code
1509 */
1510 static int hdlcdev_open(struct net_device *dev)
1511 {
1512 struct slgt_info *info = dev_to_port(dev);
1513 int rc;
1514 unsigned long flags;
1515
1516 if (!try_module_get(THIS_MODULE))
1517 return -EBUSY;
1518
1519 DBGINFO(("%s hdlcdev_open\n", dev->name));
1520
1521 /* generic HDLC layer open processing */
1522 if ((rc = hdlc_open(dev)))
1523 return rc;
1524
1525 /* arbitrate between network and tty opens */
1526 spin_lock_irqsave(&info->netlock, flags);
1527 if (info->port.count != 0 || info->netcount != 0) {
1528 DBGINFO(("%s hdlc_open busy\n", dev->name));
1529 spin_unlock_irqrestore(&info->netlock, flags);
1530 return -EBUSY;
1531 }
1532 info->netcount=1;
1533 spin_unlock_irqrestore(&info->netlock, flags);
1534
1535 /* claim resources and init adapter */
1536 if ((rc = startup(info)) != 0) {
1537 spin_lock_irqsave(&info->netlock, flags);
1538 info->netcount=0;
1539 spin_unlock_irqrestore(&info->netlock, flags);
1540 return rc;
1541 }
1542
1543 /* assert DTR and RTS, apply hardware settings */
1544 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1545 program_hw(info);
1546
1547 /* enable network layer transmit */
1548 dev->trans_start = jiffies;
1549 netif_start_queue(dev);
1550
1551 /* inform generic HDLC layer of current DCD status */
1552 spin_lock_irqsave(&info->lock, flags);
1553 get_signals(info);
1554 spin_unlock_irqrestore(&info->lock, flags);
1555 if (info->signals & SerialSignal_DCD)
1556 netif_carrier_on(dev);
1557 else
1558 netif_carrier_off(dev);
1559 return 0;
1560 }
1561
1562 /**
1563 * called by network layer when interface is disabled
1564 * shutdown hardware and release resources
1565 *
1566 * dev pointer to network device structure
1567 *
1568 * returns 0 if success, otherwise error code
1569 */
1570 static int hdlcdev_close(struct net_device *dev)
1571 {
1572 struct slgt_info *info = dev_to_port(dev);
1573 unsigned long flags;
1574
1575 DBGINFO(("%s hdlcdev_close\n", dev->name));
1576
1577 netif_stop_queue(dev);
1578
1579 /* shutdown adapter and release resources */
1580 shutdown(info);
1581
1582 hdlc_close(dev);
1583
1584 spin_lock_irqsave(&info->netlock, flags);
1585 info->netcount=0;
1586 spin_unlock_irqrestore(&info->netlock, flags);
1587
1588 module_put(THIS_MODULE);
1589 return 0;
1590 }
1591
1592 /**
1593 * called by network layer to process IOCTL call to network device
1594 *
1595 * dev pointer to network device structure
1596 * ifr pointer to network interface request structure
1597 * cmd IOCTL command code
1598 *
1599 * returns 0 if success, otherwise error code
1600 */
1601 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1602 {
1603 const size_t size = sizeof(sync_serial_settings);
1604 sync_serial_settings new_line;
1605 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1606 struct slgt_info *info = dev_to_port(dev);
1607 unsigned int flags;
1608
1609 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1610
1611 /* return error if TTY interface open */
1612 if (info->port.count)
1613 return -EBUSY;
1614
1615 if (cmd != SIOCWANDEV)
1616 return hdlc_ioctl(dev, ifr, cmd);
1617
1618 switch(ifr->ifr_settings.type) {
1619 case IF_GET_IFACE: /* return current sync_serial_settings */
1620
1621 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1622 if (ifr->ifr_settings.size < size) {
1623 ifr->ifr_settings.size = size; /* data size wanted */
1624 return -ENOBUFS;
1625 }
1626
1627 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1628 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1629 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1630 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1631
1632 switch (flags){
1633 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1634 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1635 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1636 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1637 default: new_line.clock_type = CLOCK_DEFAULT;
1638 }
1639
1640 new_line.clock_rate = info->params.clock_speed;
1641 new_line.loopback = info->params.loopback ? 1:0;
1642
1643 if (copy_to_user(line, &new_line, size))
1644 return -EFAULT;
1645 return 0;
1646
1647 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1648
1649 if(!capable(CAP_NET_ADMIN))
1650 return -EPERM;
1651 if (copy_from_user(&new_line, line, size))
1652 return -EFAULT;
1653
1654 switch (new_line.clock_type)
1655 {
1656 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1657 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1658 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1659 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1660 case CLOCK_DEFAULT: flags = info->params.flags &
1661 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1662 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1663 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1664 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1665 default: return -EINVAL;
1666 }
1667
1668 if (new_line.loopback != 0 && new_line.loopback != 1)
1669 return -EINVAL;
1670
1671 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1672 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1673 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1674 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1675 info->params.flags |= flags;
1676
1677 info->params.loopback = new_line.loopback;
1678
1679 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1680 info->params.clock_speed = new_line.clock_rate;
1681 else
1682 info->params.clock_speed = 0;
1683
1684 /* if network interface up, reprogram hardware */
1685 if (info->netcount)
1686 program_hw(info);
1687 return 0;
1688
1689 default:
1690 return hdlc_ioctl(dev, ifr, cmd);
1691 }
1692 }
1693
1694 /**
1695 * called by network layer when transmit timeout is detected
1696 *
1697 * dev pointer to network device structure
1698 */
1699 static void hdlcdev_tx_timeout(struct net_device *dev)
1700 {
1701 struct slgt_info *info = dev_to_port(dev);
1702 unsigned long flags;
1703
1704 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1705
1706 dev->stats.tx_errors++;
1707 dev->stats.tx_aborted_errors++;
1708
1709 spin_lock_irqsave(&info->lock,flags);
1710 tx_stop(info);
1711 spin_unlock_irqrestore(&info->lock,flags);
1712
1713 netif_wake_queue(dev);
1714 }
1715
1716 /**
1717 * called by device driver when transmit completes
1718 * reenable network layer transmit if stopped
1719 *
1720 * info pointer to device instance information
1721 */
1722 static void hdlcdev_tx_done(struct slgt_info *info)
1723 {
1724 if (netif_queue_stopped(info->netdev))
1725 netif_wake_queue(info->netdev);
1726 }
1727
1728 /**
1729 * called by device driver when frame received
1730 * pass frame to network layer
1731 *
1732 * info pointer to device instance information
1733 * buf pointer to buffer contianing frame data
1734 * size count of data bytes in buf
1735 */
1736 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1737 {
1738 struct sk_buff *skb = dev_alloc_skb(size);
1739 struct net_device *dev = info->netdev;
1740
1741 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1742
1743 if (skb == NULL) {
1744 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1745 dev->stats.rx_dropped++;
1746 return;
1747 }
1748
1749 memcpy(skb_put(skb, size), buf, size);
1750
1751 skb->protocol = hdlc_type_trans(skb, dev);
1752
1753 dev->stats.rx_packets++;
1754 dev->stats.rx_bytes += size;
1755
1756 netif_rx(skb);
1757 }
1758
1759 static const struct net_device_ops hdlcdev_ops = {
1760 .ndo_open = hdlcdev_open,
1761 .ndo_stop = hdlcdev_close,
1762 .ndo_change_mtu = hdlc_change_mtu,
1763 .ndo_start_xmit = hdlc_start_xmit,
1764 .ndo_do_ioctl = hdlcdev_ioctl,
1765 .ndo_tx_timeout = hdlcdev_tx_timeout,
1766 };
1767
1768 /**
1769 * called by device driver when adding device instance
1770 * do generic HDLC initialization
1771 *
1772 * info pointer to device instance information
1773 *
1774 * returns 0 if success, otherwise error code
1775 */
1776 static int hdlcdev_init(struct slgt_info *info)
1777 {
1778 int rc;
1779 struct net_device *dev;
1780 hdlc_device *hdlc;
1781
1782 /* allocate and initialize network and HDLC layer objects */
1783
1784 if (!(dev = alloc_hdlcdev(info))) {
1785 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1786 return -ENOMEM;
1787 }
1788
1789 /* for network layer reporting purposes only */
1790 dev->mem_start = info->phys_reg_addr;
1791 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1792 dev->irq = info->irq_level;
1793
1794 /* network layer callbacks and settings */
1795 dev->netdev_ops = &hdlcdev_ops;
1796 dev->watchdog_timeo = 10 * HZ;
1797 dev->tx_queue_len = 50;
1798
1799 /* generic HDLC layer callbacks and settings */
1800 hdlc = dev_to_hdlc(dev);
1801 hdlc->attach = hdlcdev_attach;
1802 hdlc->xmit = hdlcdev_xmit;
1803
1804 /* register objects with HDLC layer */
1805 if ((rc = register_hdlc_device(dev))) {
1806 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1807 free_netdev(dev);
1808 return rc;
1809 }
1810
1811 info->netdev = dev;
1812 return 0;
1813 }
1814
1815 /**
1816 * called by device driver when removing device instance
1817 * do generic HDLC cleanup
1818 *
1819 * info pointer to device instance information
1820 */
1821 static void hdlcdev_exit(struct slgt_info *info)
1822 {
1823 unregister_hdlc_device(info->netdev);
1824 free_netdev(info->netdev);
1825 info->netdev = NULL;
1826 }
1827
1828 #endif /* ifdef CONFIG_HDLC */
1829
1830 /*
1831 * get async data from rx DMA buffers
1832 */
1833 static void rx_async(struct slgt_info *info)
1834 {
1835 struct tty_struct *tty = info->port.tty;
1836 struct mgsl_icount *icount = &info->icount;
1837 unsigned int start, end;
1838 unsigned char *p;
1839 unsigned char status;
1840 struct slgt_desc *bufs = info->rbufs;
1841 int i, count;
1842 int chars = 0;
1843 int stat;
1844 unsigned char ch;
1845
1846 start = end = info->rbuf_current;
1847
1848 while(desc_complete(bufs[end])) {
1849 count = desc_count(bufs[end]) - info->rbuf_index;
1850 p = bufs[end].buf + info->rbuf_index;
1851
1852 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1853 DBGDATA(info, p, count, "rx");
1854
1855 for(i=0 ; i < count; i+=2, p+=2) {
1856 ch = *p;
1857 icount->rx++;
1858
1859 stat = 0;
1860
1861 if ((status = *(p+1) & (BIT1 + BIT0))) {
1862 if (status & BIT1)
1863 icount->parity++;
1864 else if (status & BIT0)
1865 icount->frame++;
1866 /* discard char if tty control flags say so */
1867 if (status & info->ignore_status_mask)
1868 continue;
1869 if (status & BIT1)
1870 stat = TTY_PARITY;
1871 else if (status & BIT0)
1872 stat = TTY_FRAME;
1873 }
1874 if (tty) {
1875 tty_insert_flip_char(tty, ch, stat);
1876 chars++;
1877 }
1878 }
1879
1880 if (i < count) {
1881 /* receive buffer not completed */
1882 info->rbuf_index += i;
1883 mod_timer(&info->rx_timer, jiffies + 1);
1884 break;
1885 }
1886
1887 info->rbuf_index = 0;
1888 free_rbufs(info, end, end);
1889
1890 if (++end == info->rbuf_count)
1891 end = 0;
1892
1893 /* if entire list searched then no frame available */
1894 if (end == start)
1895 break;
1896 }
1897
1898 if (tty && chars)
1899 tty_flip_buffer_push(tty);
1900 }
1901
1902 /*
1903 * return next bottom half action to perform
1904 */
1905 static int bh_action(struct slgt_info *info)
1906 {
1907 unsigned long flags;
1908 int rc;
1909
1910 spin_lock_irqsave(&info->lock,flags);
1911
1912 if (info->pending_bh & BH_RECEIVE) {
1913 info->pending_bh &= ~BH_RECEIVE;
1914 rc = BH_RECEIVE;
1915 } else if (info->pending_bh & BH_TRANSMIT) {
1916 info->pending_bh &= ~BH_TRANSMIT;
1917 rc = BH_TRANSMIT;
1918 } else if (info->pending_bh & BH_STATUS) {
1919 info->pending_bh &= ~BH_STATUS;
1920 rc = BH_STATUS;
1921 } else {
1922 /* Mark BH routine as complete */
1923 info->bh_running = false;
1924 info->bh_requested = false;
1925 rc = 0;
1926 }
1927
1928 spin_unlock_irqrestore(&info->lock,flags);
1929
1930 return rc;
1931 }
1932
1933 /*
1934 * perform bottom half processing
1935 */
1936 static void bh_handler(struct work_struct *work)
1937 {
1938 struct slgt_info *info = container_of(work, struct slgt_info, task);
1939 int action;
1940
1941 if (!info)
1942 return;
1943 info->bh_running = true;
1944
1945 while((action = bh_action(info))) {
1946 switch (action) {
1947 case BH_RECEIVE:
1948 DBGBH(("%s bh receive\n", info->device_name));
1949 switch(info->params.mode) {
1950 case MGSL_MODE_ASYNC:
1951 rx_async(info);
1952 break;
1953 case MGSL_MODE_HDLC:
1954 while(rx_get_frame(info));
1955 break;
1956 case MGSL_MODE_RAW:
1957 case MGSL_MODE_MONOSYNC:
1958 case MGSL_MODE_BISYNC:
1959 while(rx_get_buf(info));
1960 break;
1961 }
1962 /* restart receiver if rx DMA buffers exhausted */
1963 if (info->rx_restart)
1964 rx_start(info);
1965 break;
1966 case BH_TRANSMIT:
1967 bh_transmit(info);
1968 break;
1969 case BH_STATUS:
1970 DBGBH(("%s bh status\n", info->device_name));
1971 info->ri_chkcount = 0;
1972 info->dsr_chkcount = 0;
1973 info->dcd_chkcount = 0;
1974 info->cts_chkcount = 0;
1975 break;
1976 default:
1977 DBGBH(("%s unknown action\n", info->device_name));
1978 break;
1979 }
1980 }
1981 DBGBH(("%s bh_handler exit\n", info->device_name));
1982 }
1983
1984 static void bh_transmit(struct slgt_info *info)
1985 {
1986 struct tty_struct *tty = info->port.tty;
1987
1988 DBGBH(("%s bh_transmit\n", info->device_name));
1989 if (tty)
1990 tty_wakeup(tty);
1991 }
1992
1993 static void dsr_change(struct slgt_info *info, unsigned short status)
1994 {
1995 if (status & BIT3) {
1996 info->signals |= SerialSignal_DSR;
1997 info->input_signal_events.dsr_up++;
1998 } else {
1999 info->signals &= ~SerialSignal_DSR;
2000 info->input_signal_events.dsr_down++;
2001 }
2002 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2003 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2004 slgt_irq_off(info, IRQ_DSR);
2005 return;
2006 }
2007 info->icount.dsr++;
2008 wake_up_interruptible(&info->status_event_wait_q);
2009 wake_up_interruptible(&info->event_wait_q);
2010 info->pending_bh |= BH_STATUS;
2011 }
2012
2013 static void cts_change(struct slgt_info *info, unsigned short status)
2014 {
2015 if (status & BIT2) {
2016 info->signals |= SerialSignal_CTS;
2017 info->input_signal_events.cts_up++;
2018 } else {
2019 info->signals &= ~SerialSignal_CTS;
2020 info->input_signal_events.cts_down++;
2021 }
2022 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2023 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2024 slgt_irq_off(info, IRQ_CTS);
2025 return;
2026 }
2027 info->icount.cts++;
2028 wake_up_interruptible(&info->status_event_wait_q);
2029 wake_up_interruptible(&info->event_wait_q);
2030 info->pending_bh |= BH_STATUS;
2031
2032 if (info->port.flags & ASYNC_CTS_FLOW) {
2033 if (info->port.tty) {
2034 if (info->port.tty->hw_stopped) {
2035 if (info->signals & SerialSignal_CTS) {
2036 info->port.tty->hw_stopped = 0;
2037 info->pending_bh |= BH_TRANSMIT;
2038 return;
2039 }
2040 } else {
2041 if (!(info->signals & SerialSignal_CTS))
2042 info->port.tty->hw_stopped = 1;
2043 }
2044 }
2045 }
2046 }
2047
2048 static void dcd_change(struct slgt_info *info, unsigned short status)
2049 {
2050 if (status & BIT1) {
2051 info->signals |= SerialSignal_DCD;
2052 info->input_signal_events.dcd_up++;
2053 } else {
2054 info->signals &= ~SerialSignal_DCD;
2055 info->input_signal_events.dcd_down++;
2056 }
2057 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2058 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2059 slgt_irq_off(info, IRQ_DCD);
2060 return;
2061 }
2062 info->icount.dcd++;
2063 #if SYNCLINK_GENERIC_HDLC
2064 if (info->netcount) {
2065 if (info->signals & SerialSignal_DCD)
2066 netif_carrier_on(info->netdev);
2067 else
2068 netif_carrier_off(info->netdev);
2069 }
2070 #endif
2071 wake_up_interruptible(&info->status_event_wait_q);
2072 wake_up_interruptible(&info->event_wait_q);
2073 info->pending_bh |= BH_STATUS;
2074
2075 if (info->port.flags & ASYNC_CHECK_CD) {
2076 if (info->signals & SerialSignal_DCD)
2077 wake_up_interruptible(&info->port.open_wait);
2078 else {
2079 if (info->port.tty)
2080 tty_hangup(info->port.tty);
2081 }
2082 }
2083 }
2084
2085 static void ri_change(struct slgt_info *info, unsigned short status)
2086 {
2087 if (status & BIT0) {
2088 info->signals |= SerialSignal_RI;
2089 info->input_signal_events.ri_up++;
2090 } else {
2091 info->signals &= ~SerialSignal_RI;
2092 info->input_signal_events.ri_down++;
2093 }
2094 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2095 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2096 slgt_irq_off(info, IRQ_RI);
2097 return;
2098 }
2099 info->icount.rng++;
2100 wake_up_interruptible(&info->status_event_wait_q);
2101 wake_up_interruptible(&info->event_wait_q);
2102 info->pending_bh |= BH_STATUS;
2103 }
2104
2105 static void isr_rxdata(struct slgt_info *info)
2106 {
2107 unsigned int count = info->rbuf_fill_count;
2108 unsigned int i = info->rbuf_fill_index;
2109 unsigned short reg;
2110
2111 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2112 reg = rd_reg16(info, RDR);
2113 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2114 if (desc_complete(info->rbufs[i])) {
2115 /* all buffers full */
2116 rx_stop(info);
2117 info->rx_restart = 1;
2118 continue;
2119 }
2120 info->rbufs[i].buf[count++] = (unsigned char)reg;
2121 /* async mode saves status byte to buffer for each data byte */
2122 if (info->params.mode == MGSL_MODE_ASYNC)
2123 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2124 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2125 /* buffer full or end of frame */
2126 set_desc_count(info->rbufs[i], count);
2127 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2128 info->rbuf_fill_count = count = 0;
2129 if (++i == info->rbuf_count)
2130 i = 0;
2131 info->pending_bh |= BH_RECEIVE;
2132 }
2133 }
2134
2135 info->rbuf_fill_index = i;
2136 info->rbuf_fill_count = count;
2137 }
2138
2139 static void isr_serial(struct slgt_info *info)
2140 {
2141 unsigned short status = rd_reg16(info, SSR);
2142
2143 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2144
2145 wr_reg16(info, SSR, status); /* clear pending */
2146
2147 info->irq_occurred = true;
2148
2149 if (info->params.mode == MGSL_MODE_ASYNC) {
2150 if (status & IRQ_TXIDLE) {
2151 if (info->tx_active)
2152 isr_txeom(info, status);
2153 }
2154 if (info->rx_pio && (status & IRQ_RXDATA))
2155 isr_rxdata(info);
2156 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2157 info->icount.brk++;
2158 /* process break detection if tty control allows */
2159 if (info->port.tty) {
2160 if (!(status & info->ignore_status_mask)) {
2161 if (info->read_status_mask & MASK_BREAK) {
2162 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2163 if (info->port.flags & ASYNC_SAK)
2164 do_SAK(info->port.tty);
2165 }
2166 }
2167 }
2168 }
2169 } else {
2170 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2171 isr_txeom(info, status);
2172 if (info->rx_pio && (status & IRQ_RXDATA))
2173 isr_rxdata(info);
2174 if (status & IRQ_RXIDLE) {
2175 if (status & RXIDLE)
2176 info->icount.rxidle++;
2177 else
2178 info->icount.exithunt++;
2179 wake_up_interruptible(&info->event_wait_q);
2180 }
2181
2182 if (status & IRQ_RXOVER)
2183 rx_start(info);
2184 }
2185
2186 if (status & IRQ_DSR)
2187 dsr_change(info, status);
2188 if (status & IRQ_CTS)
2189 cts_change(info, status);
2190 if (status & IRQ_DCD)
2191 dcd_change(info, status);
2192 if (status & IRQ_RI)
2193 ri_change(info, status);
2194 }
2195
2196 static void isr_rdma(struct slgt_info *info)
2197 {
2198 unsigned int status = rd_reg32(info, RDCSR);
2199
2200 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2201
2202 /* RDCSR (rx DMA control/status)
2203 *
2204 * 31..07 reserved
2205 * 06 save status byte to DMA buffer
2206 * 05 error
2207 * 04 eol (end of list)
2208 * 03 eob (end of buffer)
2209 * 02 IRQ enable
2210 * 01 reset
2211 * 00 enable
2212 */
2213 wr_reg32(info, RDCSR, status); /* clear pending */
2214
2215 if (status & (BIT5 + BIT4)) {
2216 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2217 info->rx_restart = true;
2218 }
2219 info->pending_bh |= BH_RECEIVE;
2220 }
2221
2222 static void isr_tdma(struct slgt_info *info)
2223 {
2224 unsigned int status = rd_reg32(info, TDCSR);
2225
2226 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2227
2228 /* TDCSR (tx DMA control/status)
2229 *
2230 * 31..06 reserved
2231 * 05 error
2232 * 04 eol (end of list)
2233 * 03 eob (end of buffer)
2234 * 02 IRQ enable
2235 * 01 reset
2236 * 00 enable
2237 */
2238 wr_reg32(info, TDCSR, status); /* clear pending */
2239
2240 if (status & (BIT5 + BIT4 + BIT3)) {
2241 // another transmit buffer has completed
2242 // run bottom half to get more send data from user
2243 info->pending_bh |= BH_TRANSMIT;
2244 }
2245 }
2246
2247 /*
2248 * return true if there are unsent tx DMA buffers, otherwise false
2249 *
2250 * if there are unsent buffers then info->tbuf_start
2251 * is set to index of first unsent buffer
2252 */
2253 static bool unsent_tbufs(struct slgt_info *info)
2254 {
2255 unsigned int i = info->tbuf_current;
2256 bool rc = false;
2257
2258 /*
2259 * search backwards from last loaded buffer (precedes tbuf_current)
2260 * for first unsent buffer (desc_count > 0)
2261 */
2262
2263 do {
2264 if (i)
2265 i--;
2266 else
2267 i = info->tbuf_count - 1;
2268 if (!desc_count(info->tbufs[i]))
2269 break;
2270 info->tbuf_start = i;
2271 rc = true;
2272 } while (i != info->tbuf_current);
2273
2274 return rc;
2275 }
2276
2277 static void isr_txeom(struct slgt_info *info, unsigned short status)
2278 {
2279 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2280
2281 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2282 tdma_reset(info);
2283 if (status & IRQ_TXUNDER) {
2284 unsigned short val = rd_reg16(info, TCR);
2285 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2286 wr_reg16(info, TCR, val); /* clear reset bit */
2287 }
2288
2289 if (info->tx_active) {
2290 if (info->params.mode != MGSL_MODE_ASYNC) {
2291 if (status & IRQ_TXUNDER)
2292 info->icount.txunder++;
2293 else if (status & IRQ_TXIDLE)
2294 info->icount.txok++;
2295 }
2296
2297 if (unsent_tbufs(info)) {
2298 tx_start(info);
2299 update_tx_timer(info);
2300 return;
2301 }
2302 info->tx_active = false;
2303
2304 del_timer(&info->tx_timer);
2305
2306 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2307 info->signals &= ~SerialSignal_RTS;
2308 info->drop_rts_on_tx_done = false;
2309 set_signals(info);
2310 }
2311
2312 #if SYNCLINK_GENERIC_HDLC
2313 if (info->netcount)
2314 hdlcdev_tx_done(info);
2315 else
2316 #endif
2317 {
2318 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2319 tx_stop(info);
2320 return;
2321 }
2322 info->pending_bh |= BH_TRANSMIT;
2323 }
2324 }
2325 }
2326
2327 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2328 {
2329 struct cond_wait *w, *prev;
2330
2331 /* wake processes waiting for specific transitions */
2332 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2333 if (w->data & changed) {
2334 w->data = state;
2335 wake_up_interruptible(&w->q);
2336 if (prev != NULL)
2337 prev->next = w->next;
2338 else
2339 info->gpio_wait_q = w->next;
2340 } else
2341 prev = w;
2342 }
2343 }
2344
2345 /* interrupt service routine
2346 *
2347 * irq interrupt number
2348 * dev_id device ID supplied during interrupt registration
2349 */
2350 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2351 {
2352 struct slgt_info *info = dev_id;
2353 unsigned int gsr;
2354 unsigned int i;
2355
2356 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2357
2358 spin_lock(&info->lock);
2359
2360 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2361 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2362 info->irq_occurred = true;
2363 for(i=0; i < info->port_count ; i++) {
2364 if (info->port_array[i] == NULL)
2365 continue;
2366 if (gsr & (BIT8 << i))
2367 isr_serial(info->port_array[i]);
2368 if (gsr & (BIT16 << (i*2)))
2369 isr_rdma(info->port_array[i]);
2370 if (gsr & (BIT17 << (i*2)))
2371 isr_tdma(info->port_array[i]);
2372 }
2373 }
2374
2375 if (info->gpio_present) {
2376 unsigned int state;
2377 unsigned int changed;
2378 while ((changed = rd_reg32(info, IOSR)) != 0) {
2379 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2380 /* read latched state of GPIO signals */
2381 state = rd_reg32(info, IOVR);
2382 /* clear pending GPIO interrupt bits */
2383 wr_reg32(info, IOSR, changed);
2384 for (i=0 ; i < info->port_count ; i++) {
2385 if (info->port_array[i] != NULL)
2386 isr_gpio(info->port_array[i], changed, state);
2387 }
2388 }
2389 }
2390
2391 for(i=0; i < info->port_count ; i++) {
2392 struct slgt_info *port = info->port_array[i];
2393
2394 if (port && (port->port.count || port->netcount) &&
2395 port->pending_bh && !port->bh_running &&
2396 !port->bh_requested) {
2397 DBGISR(("%s bh queued\n", port->device_name));
2398 schedule_work(&port->task);
2399 port->bh_requested = true;
2400 }
2401 }
2402
2403 spin_unlock(&info->lock);
2404
2405 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2406 return IRQ_HANDLED;
2407 }
2408
2409 static int startup(struct slgt_info *info)
2410 {
2411 DBGINFO(("%s startup\n", info->device_name));
2412
2413 if (info->port.flags & ASYNC_INITIALIZED)
2414 return 0;
2415
2416 if (!info->tx_buf) {
2417 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2418 if (!info->tx_buf) {
2419 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2420 return -ENOMEM;
2421 }
2422 }
2423
2424 info->pending_bh = 0;
2425
2426 memset(&info->icount, 0, sizeof(info->icount));
2427
2428 /* program hardware for current parameters */
2429 change_params(info);
2430
2431 if (info->port.tty)
2432 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2433
2434 info->port.flags |= ASYNC_INITIALIZED;
2435
2436 return 0;
2437 }
2438
2439 /*
2440 * called by close() and hangup() to shutdown hardware
2441 */
2442 static void shutdown(struct slgt_info *info)
2443 {
2444 unsigned long flags;
2445
2446 if (!(info->port.flags & ASYNC_INITIALIZED))
2447 return;
2448
2449 DBGINFO(("%s shutdown\n", info->device_name));
2450
2451 /* clear status wait queue because status changes */
2452 /* can't happen after shutting down the hardware */
2453 wake_up_interruptible(&info->status_event_wait_q);
2454 wake_up_interruptible(&info->event_wait_q);
2455
2456 del_timer_sync(&info->tx_timer);
2457 del_timer_sync(&info->rx_timer);
2458
2459 kfree(info->tx_buf);
2460 info->tx_buf = NULL;
2461
2462 spin_lock_irqsave(&info->lock,flags);
2463
2464 tx_stop(info);
2465 rx_stop(info);
2466
2467 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2468
2469 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2470 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2471 set_signals(info);
2472 }
2473
2474 flush_cond_wait(&info->gpio_wait_q);
2475
2476 spin_unlock_irqrestore(&info->lock,flags);
2477
2478 if (info->port.tty)
2479 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2480
2481 info->port.flags &= ~ASYNC_INITIALIZED;
2482 }
2483
2484 static void program_hw(struct slgt_info *info)
2485 {
2486 unsigned long flags;
2487
2488 spin_lock_irqsave(&info->lock,flags);
2489
2490 rx_stop(info);
2491 tx_stop(info);
2492
2493 if (info->params.mode != MGSL_MODE_ASYNC ||
2494 info->netcount)
2495 sync_mode(info);
2496 else
2497 async_mode(info);
2498
2499 set_signals(info);
2500
2501 info->dcd_chkcount = 0;
2502 info->cts_chkcount = 0;
2503 info->ri_chkcount = 0;
2504 info->dsr_chkcount = 0;
2505
2506 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2507 get_signals(info);
2508
2509 if (info->netcount ||
2510 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2511 rx_start(info);
2512
2513 spin_unlock_irqrestore(&info->lock,flags);
2514 }
2515
2516 /*
2517 * reconfigure adapter based on new parameters
2518 */
2519 static void change_params(struct slgt_info *info)
2520 {
2521 unsigned cflag;
2522 int bits_per_char;
2523
2524 if (!info->port.tty || !info->port.tty->termios)
2525 return;
2526 DBGINFO(("%s change_params\n", info->device_name));
2527
2528 cflag = info->port.tty->termios->c_cflag;
2529
2530 /* if B0 rate (hangup) specified then negate DTR and RTS */
2531 /* otherwise assert DTR and RTS */
2532 if (cflag & CBAUD)
2533 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2534 else
2535 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2536
2537 /* byte size and parity */
2538
2539 switch (cflag & CSIZE) {
2540 case CS5: info->params.data_bits = 5; break;
2541 case CS6: info->params.data_bits = 6; break;
2542 case CS7: info->params.data_bits = 7; break;
2543 case CS8: info->params.data_bits = 8; break;
2544 default: info->params.data_bits = 7; break;
2545 }
2546
2547 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2548
2549 if (cflag & PARENB)
2550 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2551 else
2552 info->params.parity = ASYNC_PARITY_NONE;
2553
2554 /* calculate number of jiffies to transmit a full
2555 * FIFO (32 bytes) at specified data rate
2556 */
2557 bits_per_char = info->params.data_bits +
2558 info->params.stop_bits + 1;
2559
2560 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2561
2562 if (info->params.data_rate) {
2563 info->timeout = (32*HZ*bits_per_char) /
2564 info->params.data_rate;
2565 }
2566 info->timeout += HZ/50; /* Add .02 seconds of slop */
2567
2568 if (cflag & CRTSCTS)
2569 info->port.flags |= ASYNC_CTS_FLOW;
2570 else
2571 info->port.flags &= ~ASYNC_CTS_FLOW;
2572
2573 if (cflag & CLOCAL)
2574 info->port.flags &= ~ASYNC_CHECK_CD;
2575 else
2576 info->port.flags |= ASYNC_CHECK_CD;
2577
2578 /* process tty input control flags */
2579
2580 info->read_status_mask = IRQ_RXOVER;
2581 if (I_INPCK(info->port.tty))
2582 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2583 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2584 info->read_status_mask |= MASK_BREAK;
2585 if (I_IGNPAR(info->port.tty))
2586 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2587 if (I_IGNBRK(info->port.tty)) {
2588 info->ignore_status_mask |= MASK_BREAK;
2589 /* If ignoring parity and break indicators, ignore
2590 * overruns too. (For real raw support).
2591 */
2592 if (I_IGNPAR(info->port.tty))
2593 info->ignore_status_mask |= MASK_OVERRUN;
2594 }
2595
2596 program_hw(info);
2597 }
2598
2599 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2600 {
2601 DBGINFO(("%s get_stats\n", info->device_name));
2602 if (!user_icount) {
2603 memset(&info->icount, 0, sizeof(info->icount));
2604 } else {
2605 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2606 return -EFAULT;
2607 }
2608 return 0;
2609 }
2610
2611 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2612 {
2613 DBGINFO(("%s get_params\n", info->device_name));
2614 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2615 return -EFAULT;
2616 return 0;
2617 }
2618
2619 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2620 {
2621 unsigned long flags;
2622 MGSL_PARAMS tmp_params;
2623
2624 DBGINFO(("%s set_params\n", info->device_name));
2625 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2626 return -EFAULT;
2627
2628 spin_lock_irqsave(&info->lock, flags);
2629 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2630 info->base_clock = tmp_params.clock_speed;
2631 else
2632 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2633 spin_unlock_irqrestore(&info->lock, flags);
2634
2635 program_hw(info);
2636
2637 return 0;
2638 }
2639
2640 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2641 {
2642 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2643 if (put_user(info->idle_mode, idle_mode))
2644 return -EFAULT;
2645 return 0;
2646 }
2647
2648 static int set_txidle(struct slgt_info *info, int idle_mode)
2649 {
2650 unsigned long flags;
2651 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2652 spin_lock_irqsave(&info->lock,flags);
2653 info->idle_mode = idle_mode;
2654 if (info->params.mode != MGSL_MODE_ASYNC)
2655 tx_set_idle(info);
2656 spin_unlock_irqrestore(&info->lock,flags);
2657 return 0;
2658 }
2659
2660 static int tx_enable(struct slgt_info *info, int enable)
2661 {
2662 unsigned long flags;
2663 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2664 spin_lock_irqsave(&info->lock,flags);
2665 if (enable) {
2666 if (!info->tx_enabled)
2667 tx_start(info);
2668 } else {
2669 if (info->tx_enabled)
2670 tx_stop(info);
2671 }
2672 spin_unlock_irqrestore(&info->lock,flags);
2673 return 0;
2674 }
2675
2676 /*
2677 * abort transmit HDLC frame
2678 */
2679 static int tx_abort(struct slgt_info *info)
2680 {
2681 unsigned long flags;
2682 DBGINFO(("%s tx_abort\n", info->device_name));
2683 spin_lock_irqsave(&info->lock,flags);
2684 tdma_reset(info);
2685 spin_unlock_irqrestore(&info->lock,flags);
2686 return 0;
2687 }
2688
2689 static int rx_enable(struct slgt_info *info, int enable)
2690 {
2691 unsigned long flags;
2692 unsigned int rbuf_fill_level;
2693 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2694 spin_lock_irqsave(&info->lock,flags);
2695 /*
2696 * enable[31..16] = receive DMA buffer fill level
2697 * 0 = noop (leave fill level unchanged)
2698 * fill level must be multiple of 4 and <= buffer size
2699 */
2700 rbuf_fill_level = ((unsigned int)enable) >> 16;
2701 if (rbuf_fill_level) {
2702 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2703 spin_unlock_irqrestore(&info->lock, flags);
2704 return -EINVAL;
2705 }
2706 info->rbuf_fill_level = rbuf_fill_level;
2707 if (rbuf_fill_level < 128)
2708 info->rx_pio = 1; /* PIO mode */
2709 else
2710 info->rx_pio = 0; /* DMA mode */
2711 rx_stop(info); /* restart receiver to use new fill level */
2712 }
2713
2714 /*
2715 * enable[1..0] = receiver enable command
2716 * 0 = disable
2717 * 1 = enable
2718 * 2 = enable or force hunt mode if already enabled
2719 */
2720 enable &= 3;
2721 if (enable) {
2722 if (!info->rx_enabled)
2723 rx_start(info);
2724 else if (enable == 2) {
2725 /* force hunt mode (write 1 to RCR[3]) */
2726 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2727 }
2728 } else {
2729 if (info->rx_enabled)
2730 rx_stop(info);
2731 }
2732 spin_unlock_irqrestore(&info->lock,flags);
2733 return 0;
2734 }
2735
2736 /*
2737 * wait for specified event to occur
2738 */
2739 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2740 {
2741 unsigned long flags;
2742 int s;
2743 int rc=0;
2744 struct mgsl_icount cprev, cnow;
2745 int events;
2746 int mask;
2747 struct _input_signal_events oldsigs, newsigs;
2748 DECLARE_WAITQUEUE(wait, current);
2749
2750 if (get_user(mask, mask_ptr))
2751 return -EFAULT;
2752
2753 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2754
2755 spin_lock_irqsave(&info->lock,flags);
2756
2757 /* return immediately if state matches requested events */
2758 get_signals(info);
2759 s = info->signals;
2760
2761 events = mask &
2762 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2763 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2764 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2765 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2766 if (events) {
2767 spin_unlock_irqrestore(&info->lock,flags);
2768 goto exit;
2769 }
2770
2771 /* save current irq counts */
2772 cprev = info->icount;
2773 oldsigs = info->input_signal_events;
2774
2775 /* enable hunt and idle irqs if needed */
2776 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2777 unsigned short val = rd_reg16(info, SCR);
2778 if (!(val & IRQ_RXIDLE))
2779 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2780 }
2781
2782 set_current_state(TASK_INTERRUPTIBLE);
2783 add_wait_queue(&info->event_wait_q, &wait);
2784
2785 spin_unlock_irqrestore(&info->lock,flags);
2786
2787 for(;;) {
2788 schedule();
2789 if (signal_pending(current)) {
2790 rc = -ERESTARTSYS;
2791 break;
2792 }
2793
2794 /* get current irq counts */
2795 spin_lock_irqsave(&info->lock,flags);
2796 cnow = info->icount;
2797 newsigs = info->input_signal_events;
2798 set_current_state(TASK_INTERRUPTIBLE);
2799 spin_unlock_irqrestore(&info->lock,flags);
2800
2801 /* if no change, wait aborted for some reason */
2802 if (newsigs.dsr_up == oldsigs.dsr_up &&
2803 newsigs.dsr_down == oldsigs.dsr_down &&
2804 newsigs.dcd_up == oldsigs.dcd_up &&
2805 newsigs.dcd_down == oldsigs.dcd_down &&
2806 newsigs.cts_up == oldsigs.cts_up &&
2807 newsigs.cts_down == oldsigs.cts_down &&
2808 newsigs.ri_up == oldsigs.ri_up &&
2809 newsigs.ri_down == oldsigs.ri_down &&
2810 cnow.exithunt == cprev.exithunt &&
2811 cnow.rxidle == cprev.rxidle) {
2812 rc = -EIO;
2813 break;
2814 }
2815
2816 events = mask &
2817 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2818 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2819 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2820 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2821 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2822 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2823 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2824 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2825 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2826 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2827 if (events)
2828 break;
2829
2830 cprev = cnow;
2831 oldsigs = newsigs;
2832 }
2833
2834 remove_wait_queue(&info->event_wait_q, &wait);
2835 set_current_state(TASK_RUNNING);
2836
2837
2838 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2839 spin_lock_irqsave(&info->lock,flags);
2840 if (!waitqueue_active(&info->event_wait_q)) {
2841 /* disable enable exit hunt mode/idle rcvd IRQs */
2842 wr_reg16(info, SCR,
2843 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2844 }
2845 spin_unlock_irqrestore(&info->lock,flags);
2846 }
2847 exit:
2848 if (rc == 0)
2849 rc = put_user(events, mask_ptr);
2850 return rc;
2851 }
2852
2853 static int get_interface(struct slgt_info *info, int __user *if_mode)
2854 {
2855 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2856 if (put_user(info->if_mode, if_mode))
2857 return -EFAULT;
2858 return 0;
2859 }
2860
2861 static int set_interface(struct slgt_info *info, int if_mode)
2862 {
2863 unsigned long flags;
2864 unsigned short val;
2865
2866 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2867 spin_lock_irqsave(&info->lock,flags);
2868 info->if_mode = if_mode;
2869
2870 msc_set_vcr(info);
2871
2872 /* TCR (tx control) 07 1=RTS driver control */
2873 val = rd_reg16(info, TCR);
2874 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2875 val |= BIT7;
2876 else
2877 val &= ~BIT7;
2878 wr_reg16(info, TCR, val);
2879
2880 spin_unlock_irqrestore(&info->lock,flags);
2881 return 0;
2882 }
2883
2884 /*
2885 * set general purpose IO pin state and direction
2886 *
2887 * user_gpio fields:
2888 * state each bit indicates a pin state
2889 * smask set bit indicates pin state to set
2890 * dir each bit indicates a pin direction (0=input, 1=output)
2891 * dmask set bit indicates pin direction to set
2892 */
2893 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2894 {
2895 unsigned long flags;
2896 struct gpio_desc gpio;
2897 __u32 data;
2898
2899 if (!info->gpio_present)
2900 return -EINVAL;
2901 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2902 return -EFAULT;
2903 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2904 info->device_name, gpio.state, gpio.smask,
2905 gpio.dir, gpio.dmask));
2906
2907 spin_lock_irqsave(&info->lock,flags);
2908 if (gpio.dmask) {
2909 data = rd_reg32(info, IODR);
2910 data |= gpio.dmask & gpio.dir;
2911 data &= ~(gpio.dmask & ~gpio.dir);
2912 wr_reg32(info, IODR, data);
2913 }
2914 if (gpio.smask) {
2915 data = rd_reg32(info, IOVR);
2916 data |= gpio.smask & gpio.state;
2917 data &= ~(gpio.smask & ~gpio.state);
2918 wr_reg32(info, IOVR, data);
2919 }
2920 spin_unlock_irqrestore(&info->lock,flags);
2921
2922 return 0;
2923 }
2924
2925 /*
2926 * get general purpose IO pin state and direction
2927 */
2928 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2929 {
2930 struct gpio_desc gpio;
2931 if (!info->gpio_present)
2932 return -EINVAL;
2933 gpio.state = rd_reg32(info, IOVR);
2934 gpio.smask = 0xffffffff;
2935 gpio.dir = rd_reg32(info, IODR);
2936 gpio.dmask = 0xffffffff;
2937 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2938 return -EFAULT;
2939 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2940 info->device_name, gpio.state, gpio.dir));
2941 return 0;
2942 }
2943
2944 /*
2945 * conditional wait facility
2946 */
2947 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2948 {
2949 init_waitqueue_head(&w->q);
2950 init_waitqueue_entry(&w->wait, current);
2951 w->data = data;
2952 }
2953
2954 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2955 {
2956 set_current_state(TASK_INTERRUPTIBLE);
2957 add_wait_queue(&w->q, &w->wait);
2958 w->next = *head;
2959 *head = w;
2960 }
2961
2962 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2963 {
2964 struct cond_wait *w, *prev;
2965 remove_wait_queue(&cw->q, &cw->wait);
2966 set_current_state(TASK_RUNNING);
2967 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2968 if (w == cw) {
2969 if (prev != NULL)
2970 prev->next = w->next;
2971 else
2972 *head = w->next;
2973 break;
2974 }
2975 }
2976 }
2977
2978 static void flush_cond_wait(struct cond_wait **head)
2979 {
2980 while (*head != NULL) {
2981 wake_up_interruptible(&(*head)->q);
2982 *head = (*head)->next;
2983 }
2984 }
2985
2986 /*
2987 * wait for general purpose I/O pin(s) to enter specified state
2988 *
2989 * user_gpio fields:
2990 * state - bit indicates target pin state
2991 * smask - set bit indicates watched pin
2992 *
2993 * The wait ends when at least one watched pin enters the specified
2994 * state. When 0 (no error) is returned, user_gpio->state is set to the
2995 * state of all GPIO pins when the wait ends.
2996 *
2997 * Note: Each pin may be a dedicated input, dedicated output, or
2998 * configurable input/output. The number and configuration of pins
2999 * varies with the specific adapter model. Only input pins (dedicated
3000 * or configured) can be monitored with this function.
3001 */
3002 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3003 {
3004 unsigned long flags;
3005 int rc = 0;
3006 struct gpio_desc gpio;
3007 struct cond_wait wait;
3008 u32 state;
3009
3010 if (!info->gpio_present)
3011 return -EINVAL;
3012 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3013 return -EFAULT;
3014 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3015 info->device_name, gpio.state, gpio.smask));
3016 /* ignore output pins identified by set IODR bit */
3017 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3018 return -EINVAL;
3019 init_cond_wait(&wait, gpio.smask);
3020
3021 spin_lock_irqsave(&info->lock, flags);
3022 /* enable interrupts for watched pins */
3023 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3024 /* get current pin states */
3025 state = rd_reg32(info, IOVR);
3026
3027 if (gpio.smask & ~(state ^ gpio.state)) {
3028 /* already in target state */
3029 gpio.state = state;
3030 } else {
3031 /* wait for target state */
3032 add_cond_wait(&info->gpio_wait_q, &wait);
3033 spin_unlock_irqrestore(&info->lock, flags);
3034 schedule();
3035 if (signal_pending(current))
3036 rc = -ERESTARTSYS;
3037 else
3038 gpio.state = wait.data;
3039 spin_lock_irqsave(&info->lock, flags);
3040 remove_cond_wait(&info->gpio_wait_q, &wait);
3041 }
3042
3043 /* disable all GPIO interrupts if no waiting processes */
3044 if (info->gpio_wait_q == NULL)
3045 wr_reg32(info, IOER, 0);
3046 spin_unlock_irqrestore(&info->lock,flags);
3047
3048 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3049 rc = -EFAULT;
3050 return rc;
3051 }
3052
3053 static int modem_input_wait(struct slgt_info *info,int arg)
3054 {
3055 unsigned long flags;
3056 int rc;
3057 struct mgsl_icount cprev, cnow;
3058 DECLARE_WAITQUEUE(wait, current);
3059
3060 /* save current irq counts */
3061 spin_lock_irqsave(&info->lock,flags);
3062 cprev = info->icount;
3063 add_wait_queue(&info->status_event_wait_q, &wait);
3064 set_current_state(TASK_INTERRUPTIBLE);
3065 spin_unlock_irqrestore(&info->lock,flags);
3066
3067 for(;;) {
3068 schedule();
3069 if (signal_pending(current)) {
3070 rc = -ERESTARTSYS;
3071 break;
3072 }
3073
3074 /* get new irq counts */
3075 spin_lock_irqsave(&info->lock,flags);
3076 cnow = info->icount;
3077 set_current_state(TASK_INTERRUPTIBLE);
3078 spin_unlock_irqrestore(&info->lock,flags);
3079
3080 /* if no change, wait aborted for some reason */
3081 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3082 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3083 rc = -EIO;
3084 break;
3085 }
3086
3087 /* check for change in caller specified modem input */
3088 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3089 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3090 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3091 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3092 rc = 0;
3093 break;
3094 }
3095
3096 cprev = cnow;
3097 }
3098 remove_wait_queue(&info->status_event_wait_q, &wait);
3099 set_current_state(TASK_RUNNING);
3100 return rc;
3101 }
3102
3103 /*
3104 * return state of serial control and status signals
3105 */
3106 static int tiocmget(struct tty_struct *tty, struct file *file)
3107 {
3108 struct slgt_info *info = tty->driver_data;
3109 unsigned int result;
3110 unsigned long flags;
3111
3112 spin_lock_irqsave(&info->lock,flags);
3113 get_signals(info);
3114 spin_unlock_irqrestore(&info->lock,flags);
3115
3116 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3117 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3118 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3119 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3120 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3121 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3122
3123 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3124 return result;
3125 }
3126
3127 /*
3128 * set modem control signals (DTR/RTS)
3129 *
3130 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3131 * TIOCMSET = set/clear signal values
3132 * value bit mask for command
3133 */
3134 static int tiocmset(struct tty_struct *tty, struct file *file,
3135 unsigned int set, unsigned int clear)
3136 {
3137 struct slgt_info *info = tty->driver_data;
3138 unsigned long flags;
3139
3140 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3141
3142 if (set & TIOCM_RTS)
3143 info->signals |= SerialSignal_RTS;
3144 if (set & TIOCM_DTR)
3145 info->signals |= SerialSignal_DTR;
3146 if (clear & TIOCM_RTS)
3147 info->signals &= ~SerialSignal_RTS;
3148 if (clear & TIOCM_DTR)
3149 info->signals &= ~SerialSignal_DTR;
3150
3151 spin_lock_irqsave(&info->lock,flags);
3152 set_signals(info);
3153 spin_unlock_irqrestore(&info->lock,flags);
3154 return 0;
3155 }
3156
3157 static int carrier_raised(struct tty_port *port)
3158 {
3159 unsigned long flags;
3160 struct slgt_info *info = container_of(port, struct slgt_info, port);
3161
3162 spin_lock_irqsave(&info->lock,flags);
3163 get_signals(info);
3164 spin_unlock_irqrestore(&info->lock,flags);
3165 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3166 }
3167
3168 static void dtr_rts(struct tty_port *port, int on)
3169 {
3170 unsigned long flags;
3171 struct slgt_info *info = container_of(port, struct slgt_info, port);
3172
3173 spin_lock_irqsave(&info->lock,flags);
3174 if (on)
3175 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3176 else
3177 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3178 set_signals(info);
3179 spin_unlock_irqrestore(&info->lock,flags);
3180 }
3181
3182
3183 /*
3184 * block current process until the device is ready to open
3185 */
3186 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3187 struct slgt_info *info)
3188 {
3189 DECLARE_WAITQUEUE(wait, current);
3190 int retval;
3191 bool do_clocal = false;
3192 bool extra_count = false;
3193 unsigned long flags;
3194 int cd;
3195 struct tty_port *port = &info->port;
3196
3197 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3198
3199 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3200 /* nonblock mode is set or port is not enabled */
3201 port->flags |= ASYNC_NORMAL_ACTIVE;
3202 return 0;
3203 }
3204
3205 if (tty->termios->c_cflag & CLOCAL)
3206 do_clocal = true;
3207
3208 /* Wait for carrier detect and the line to become
3209 * free (i.e., not in use by the callout). While we are in
3210 * this loop, port->count is dropped by one, so that
3211 * close() knows when to free things. We restore it upon
3212 * exit, either normal or abnormal.
3213 */
3214
3215 retval = 0;
3216 add_wait_queue(&port->open_wait, &wait);
3217
3218 spin_lock_irqsave(&info->lock, flags);
3219 if (!tty_hung_up_p(filp)) {
3220 extra_count = true;
3221 port->count--;
3222 }
3223 spin_unlock_irqrestore(&info->lock, flags);
3224 port->blocked_open++;
3225
3226 while (1) {
3227 if ((tty->termios->c_cflag & CBAUD))
3228 tty_port_raise_dtr_rts(port);
3229
3230 set_current_state(TASK_INTERRUPTIBLE);
3231
3232 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3233 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3234 -EAGAIN : -ERESTARTSYS;
3235 break;
3236 }
3237
3238 cd = tty_port_carrier_raised(port);
3239
3240 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3241 break;
3242
3243 if (signal_pending(current)) {
3244 retval = -ERESTARTSYS;
3245 break;
3246 }
3247
3248 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3249 tty_unlock();
3250 schedule();
3251 tty_lock();
3252 }
3253
3254 set_current_state(TASK_RUNNING);
3255 remove_wait_queue(&port->open_wait, &wait);
3256
3257 if (extra_count)
3258 port->count++;
3259 port->blocked_open--;
3260
3261 if (!retval)
3262 port->flags |= ASYNC_NORMAL_ACTIVE;
3263
3264 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3265 return retval;
3266 }
3267
3268 static int alloc_tmp_rbuf(struct slgt_info *info)
3269 {
3270 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3271 if (info->tmp_rbuf == NULL)
3272 return -ENOMEM;
3273 return 0;
3274 }
3275
3276 static void free_tmp_rbuf(struct slgt_info *info)
3277 {
3278 kfree(info->tmp_rbuf);
3279 info->tmp_rbuf = NULL;
3280 }
3281
3282 /*
3283 * allocate DMA descriptor lists.
3284 */
3285 static int alloc_desc(struct slgt_info *info)
3286 {
3287 unsigned int i;
3288 unsigned int pbufs;
3289
3290 /* allocate memory to hold descriptor lists */
3291 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3292 if (info->bufs == NULL)
3293 return -ENOMEM;
3294
3295 memset(info->bufs, 0, DESC_LIST_SIZE);
3296
3297 info->rbufs = (struct slgt_desc*)info->bufs;
3298 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3299
3300 pbufs = (unsigned int)info->bufs_dma_addr;
3301
3302 /*
3303 * Build circular lists of descriptors
3304 */
3305
3306 for (i=0; i < info->rbuf_count; i++) {
3307 /* physical address of this descriptor */
3308 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3309
3310 /* physical address of next descriptor */
3311 if (i == info->rbuf_count - 1)
3312 info->rbufs[i].next = cpu_to_le32(pbufs);
3313 else
3314 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3315 set_desc_count(info->rbufs[i], DMABUFSIZE);
3316 }
3317
3318 for (i=0; i < info->tbuf_count; i++) {
3319 /* physical address of this descriptor */
3320 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3321
3322 /* physical address of next descriptor */
3323 if (i == info->tbuf_count - 1)
3324 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3325 else
3326 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3327 }
3328
3329 return 0;
3330 }
3331
3332 static void free_desc(struct slgt_info *info)
3333 {
3334 if (info->bufs != NULL) {
3335 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3336 info->bufs = NULL;
3337 info->rbufs = NULL;
3338 info->tbufs = NULL;
3339 }
3340 }
3341
3342 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3343 {
3344 int i;
3345 for (i=0; i < count; i++) {
3346 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3347 return -ENOMEM;
3348 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3349 }
3350 return 0;
3351 }
3352
3353 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3354 {
3355 int i;
3356 for (i=0; i < count; i++) {
3357 if (bufs[i].buf == NULL)
3358 continue;
3359 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3360 bufs[i].buf = NULL;
3361 }
3362 }
3363
3364 static int alloc_dma_bufs(struct slgt_info *info)
3365 {
3366 info->rbuf_count = 32;
3367 info->tbuf_count = 32;
3368
3369 if (alloc_desc(info) < 0 ||
3370 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3371 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3372 alloc_tmp_rbuf(info) < 0) {
3373 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3374 return -ENOMEM;
3375 }
3376 reset_rbufs(info);
3377 return 0;
3378 }
3379
3380 static void free_dma_bufs(struct slgt_info *info)
3381 {
3382 if (info->bufs) {
3383 free_bufs(info, info->rbufs, info->rbuf_count);
3384 free_bufs(info, info->tbufs, info->tbuf_count);
3385 free_desc(info);
3386 }
3387 free_tmp_rbuf(info);
3388 }
3389
3390 static int claim_resources(struct slgt_info *info)
3391 {
3392 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3393 DBGERR(("%s reg addr conflict, addr=%08X\n",
3394 info->device_name, info->phys_reg_addr));
3395 info->init_error = DiagStatus_AddressConflict;
3396 goto errout;
3397 }
3398 else
3399 info->reg_addr_requested = true;
3400
3401 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3402 if (!info->reg_addr) {
3403 DBGERR(("%s cant map device registers, addr=%08X\n",
3404 info->device_name, info->phys_reg_addr));
3405 info->init_error = DiagStatus_CantAssignPciResources;
3406 goto errout;
3407 }
3408 return 0;
3409
3410 errout:
3411 release_resources(info);
3412 return -ENODEV;
3413 }
3414
3415 static void release_resources(struct slgt_info *info)
3416 {
3417 if (info->irq_requested) {
3418 free_irq(info->irq_level, info);
3419 info->irq_requested = false;
3420 }
3421
3422 if (info->reg_addr_requested) {
3423 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3424 info->reg_addr_requested = false;
3425 }
3426
3427 if (info->reg_addr) {
3428 iounmap(info->reg_addr);
3429 info->reg_addr = NULL;
3430 }
3431 }
3432
3433 /* Add the specified device instance data structure to the
3434 * global linked list of devices and increment the device count.
3435 */
3436 static void add_device(struct slgt_info *info)
3437 {
3438 char *devstr;
3439
3440 info->next_device = NULL;
3441 info->line = slgt_device_count;
3442 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3443
3444 if (info->line < MAX_DEVICES) {
3445 if (maxframe[info->line])
3446 info->max_frame_size = maxframe[info->line];
3447 }
3448
3449 slgt_device_count++;
3450
3451 if (!slgt_device_list)
3452 slgt_device_list = info;
3453 else {
3454 struct slgt_info *current_dev = slgt_device_list;
3455 while(current_dev->next_device)
3456 current_dev = current_dev->next_device;
3457 current_dev->next_device = info;
3458 }
3459
3460 if (info->max_frame_size < 4096)
3461 info->max_frame_size = 4096;
3462 else if (info->max_frame_size > 65535)
3463 info->max_frame_size = 65535;
3464
3465 switch(info->pdev->device) {
3466 case SYNCLINK_GT_DEVICE_ID:
3467 devstr = "GT";
3468 break;
3469 case SYNCLINK_GT2_DEVICE_ID:
3470 devstr = "GT2";
3471 break;
3472 case SYNCLINK_GT4_DEVICE_ID:
3473 devstr = "GT4";
3474 break;
3475 case SYNCLINK_AC_DEVICE_ID:
3476 devstr = "AC";
3477 info->params.mode = MGSL_MODE_ASYNC;
3478 break;
3479 default:
3480 devstr = "(unknown model)";
3481 }
3482 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3483 devstr, info->device_name, info->phys_reg_addr,
3484 info->irq_level, info->max_frame_size);
3485
3486 #if SYNCLINK_GENERIC_HDLC
3487 hdlcdev_init(info);
3488 #endif
3489 }
3490
3491 static const struct tty_port_operations slgt_port_ops = {
3492 .carrier_raised = carrier_raised,
3493 .dtr_rts = dtr_rts,
3494 };
3495
3496 /*
3497 * allocate device instance structure, return NULL on failure
3498 */
3499 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3500 {
3501 struct slgt_info *info;
3502
3503 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3504
3505 if (!info) {
3506 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3507 driver_name, adapter_num, port_num));
3508 } else {
3509 tty_port_init(&info->port);
3510 info->port.ops = &slgt_port_ops;
3511 info->magic = MGSL_MAGIC;
3512 INIT_WORK(&info->task, bh_handler);
3513 info->max_frame_size = 4096;
3514 info->base_clock = 14745600;
3515 info->rbuf_fill_level = DMABUFSIZE;
3516 info->port.close_delay = 5*HZ/10;
3517 info->port.closing_wait = 30*HZ;
3518 init_waitqueue_head(&info->status_event_wait_q);
3519 init_waitqueue_head(&info->event_wait_q);
3520 spin_lock_init(&info->netlock);
3521 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3522 info->idle_mode = HDLC_TXIDLE_FLAGS;
3523 info->adapter_num = adapter_num;
3524 info->port_num = port_num;
3525
3526 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3527 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3528
3529 /* Copy configuration info to device instance data */
3530 info->pdev = pdev;
3531 info->irq_level = pdev->irq;
3532 info->phys_reg_addr = pci_resource_start(pdev,0);
3533
3534 info->bus_type = MGSL_BUS_TYPE_PCI;
3535 info->irq_flags = IRQF_SHARED;
3536
3537 info->init_error = -1; /* assume error, set to 0 on successful init */
3538 }
3539
3540 return info;
3541 }
3542
3543 static void device_init(int adapter_num, struct pci_dev *pdev)
3544 {
3545 struct slgt_info *port_array[SLGT_MAX_PORTS];
3546 int i;
3547 int port_count = 1;
3548
3549 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3550 port_count = 2;
3551 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3552 port_count = 4;
3553
3554 /* allocate device instances for all ports */
3555 for (i=0; i < port_count; ++i) {
3556 port_array[i] = alloc_dev(adapter_num, i, pdev);
3557 if (port_array[i] == NULL) {
3558 for (--i; i >= 0; --i)
3559 kfree(port_array[i]);
3560 return;
3561 }
3562 }
3563
3564 /* give copy of port_array to all ports and add to device list */
3565 for (i=0; i < port_count; ++i) {
3566 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3567 add_device(port_array[i]);
3568 port_array[i]->port_count = port_count;
3569 spin_lock_init(&port_array[i]->lock);
3570 }
3571
3572 /* Allocate and claim adapter resources */
3573 if (!claim_resources(port_array[0])) {
3574
3575 alloc_dma_bufs(port_array[0]);
3576
3577 /* copy resource information from first port to others */
3578 for (i = 1; i < port_count; ++i) {
3579 port_array[i]->lock = port_array[0]->lock;
3580 port_array[i]->irq_level = port_array[0]->irq_level;
3581 port_array[i]->reg_addr = port_array[0]->reg_addr;
3582 alloc_dma_bufs(port_array[i]);
3583 }
3584
3585 if (request_irq(port_array[0]->irq_level,
3586 slgt_interrupt,
3587 port_array[0]->irq_flags,
3588 port_array[0]->device_name,
3589 port_array[0]) < 0) {
3590 DBGERR(("%s request_irq failed IRQ=%d\n",
3591 port_array[0]->device_name,
3592 port_array[0]->irq_level));
3593 } else {
3594 port_array[0]->irq_requested = true;
3595 adapter_test(port_array[0]);
3596 for (i=1 ; i < port_count ; i++) {
3597 port_array[i]->init_error = port_array[0]->init_error;
3598 port_array[i]->gpio_present = port_array[0]->gpio_present;
3599 }
3600 }
3601 }
3602
3603 for (i=0; i < port_count; ++i)
3604 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3605 }
3606
3607 static int __devinit init_one(struct pci_dev *dev,
3608 const struct pci_device_id *ent)
3609 {
3610 if (pci_enable_device(dev)) {
3611 printk("error enabling pci device %p\n", dev);
3612 return -EIO;
3613 }
3614 pci_set_master(dev);
3615 device_init(slgt_device_count, dev);
3616 return 0;
3617 }
3618
3619 static void __devexit remove_one(struct pci_dev *dev)
3620 {
3621 }
3622
3623 static const struct tty_operations ops = {
3624 .open = open,
3625 .close = close,
3626 .write = write,
3627 .put_char = put_char,
3628 .flush_chars = flush_chars,
3629 .write_room = write_room,
3630 .chars_in_buffer = chars_in_buffer,
3631 .flush_buffer = flush_buffer,
3632 .ioctl = ioctl,
3633 .compat_ioctl = slgt_compat_ioctl,
3634 .throttle = throttle,
3635 .unthrottle = unthrottle,
3636 .send_xchar = send_xchar,
3637 .break_ctl = set_break,
3638 .wait_until_sent = wait_until_sent,
3639 .set_termios = set_termios,
3640 .stop = tx_hold,
3641 .start = tx_release,
3642 .hangup = hangup,
3643 .tiocmget = tiocmget,
3644 .tiocmset = tiocmset,
3645 .proc_fops = &synclink_gt_proc_fops,
3646 };
3647
3648 static void slgt_cleanup(void)
3649 {
3650 int rc;
3651 struct slgt_info *info;
3652 struct slgt_info *tmp;
3653
3654 printk(KERN_INFO "unload %s\n", driver_name);
3655
3656 if (serial_driver) {
3657 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3658 tty_unregister_device(serial_driver, info->line);
3659 if ((rc = tty_unregister_driver(serial_driver)))
3660 DBGERR(("tty_unregister_driver error=%d\n", rc));
3661 put_tty_driver(serial_driver);
3662 }
3663
3664 /* reset devices */
3665 info = slgt_device_list;
3666 while(info) {
3667 reset_port(info);
3668 info = info->next_device;
3669 }
3670
3671 /* release devices */
3672 info = slgt_device_list;
3673 while(info) {
3674 #if SYNCLINK_GENERIC_HDLC
3675 hdlcdev_exit(info);
3676 #endif
3677 free_dma_bufs(info);
3678 free_tmp_rbuf(info);
3679 if (info->port_num == 0)
3680 release_resources(info);
3681 tmp = info;
3682 info = info->next_device;
3683 kfree(tmp);
3684 }
3685
3686 if (pci_registered)
3687 pci_unregister_driver(&pci_driver);
3688 }
3689
3690 /*
3691 * Driver initialization entry point.
3692 */
3693 static int __init slgt_init(void)
3694 {
3695 int rc;
3696
3697 printk(KERN_INFO "%s\n", driver_name);
3698
3699 serial_driver = alloc_tty_driver(MAX_DEVICES);
3700 if (!serial_driver) {
3701 printk("%s can't allocate tty driver\n", driver_name);
3702 return -ENOMEM;
3703 }
3704
3705 /* Initialize the tty_driver structure */
3706
3707 serial_driver->owner = THIS_MODULE;
3708 serial_driver->driver_name = tty_driver_name;
3709 serial_driver->name = tty_dev_prefix;
3710 serial_driver->major = ttymajor;
3711 serial_driver->minor_start = 64;
3712 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3713 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3714 serial_driver->init_termios = tty_std_termios;
3715 serial_driver->init_termios.c_cflag =
3716 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3717 serial_driver->init_termios.c_ispeed = 9600;
3718 serial_driver->init_termios.c_ospeed = 9600;
3719 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3720 tty_set_operations(serial_driver, &ops);
3721 if ((rc = tty_register_driver(serial_driver)) < 0) {
3722 DBGERR(("%s can't register serial driver\n", driver_name));
3723 put_tty_driver(serial_driver);
3724 serial_driver = NULL;
3725 goto error;
3726 }
3727
3728 printk(KERN_INFO "%s, tty major#%d\n",
3729 driver_name, serial_driver->major);
3730
3731 slgt_device_count = 0;
3732 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3733 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3734 goto error;
3735 }
3736 pci_registered = true;
3737
3738 if (!slgt_device_list)
3739 printk("%s no devices found\n",driver_name);
3740
3741 return 0;
3742
3743 error:
3744 slgt_cleanup();
3745 return rc;
3746 }
3747
3748 static void __exit slgt_exit(void)
3749 {
3750 slgt_cleanup();
3751 }
3752
3753 module_init(slgt_init);
3754 module_exit(slgt_exit);
3755
3756 /*
3757 * register access routines
3758 */
3759
3760 #define CALC_REGADDR() \
3761 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3762 if (addr >= 0x80) \
3763 reg_addr += (info->port_num) * 32;
3764
3765 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3766 {
3767 CALC_REGADDR();
3768 return readb((void __iomem *)reg_addr);
3769 }
3770
3771 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3772 {
3773 CALC_REGADDR();
3774 writeb(value, (void __iomem *)reg_addr);
3775 }
3776
3777 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3778 {
3779 CALC_REGADDR();
3780 return readw((void __iomem *)reg_addr);
3781 }
3782
3783 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3784 {
3785 CALC_REGADDR();
3786 writew(value, (void __iomem *)reg_addr);
3787 }
3788
3789 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3790 {
3791 CALC_REGADDR();
3792 return readl((void __iomem *)reg_addr);
3793 }
3794
3795 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3796 {
3797 CALC_REGADDR();
3798 writel(value, (void __iomem *)reg_addr);
3799 }
3800
3801 static void rdma_reset(struct slgt_info *info)
3802 {
3803 unsigned int i;
3804
3805 /* set reset bit */
3806 wr_reg32(info, RDCSR, BIT1);
3807
3808 /* wait for enable bit cleared */
3809 for(i=0 ; i < 1000 ; i++)
3810 if (!(rd_reg32(info, RDCSR) & BIT0))
3811 break;
3812 }
3813
3814 static void tdma_reset(struct slgt_info *info)
3815 {
3816 unsigned int i;
3817
3818 /* set reset bit */
3819 wr_reg32(info, TDCSR, BIT1);
3820
3821 /* wait for enable bit cleared */
3822 for(i=0 ; i < 1000 ; i++)
3823 if (!(rd_reg32(info, TDCSR) & BIT0))
3824 break;
3825 }
3826
3827 /*
3828 * enable internal loopback
3829 * TxCLK and RxCLK are generated from BRG
3830 * and TxD is looped back to RxD internally.
3831 */
3832 static void enable_loopback(struct slgt_info *info)
3833 {
3834 /* SCR (serial control) BIT2=looopback enable */
3835 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3836
3837 if (info->params.mode != MGSL_MODE_ASYNC) {
3838 /* CCR (clock control)
3839 * 07..05 tx clock source (010 = BRG)
3840 * 04..02 rx clock source (010 = BRG)
3841 * 01 auxclk enable (0 = disable)
3842 * 00 BRG enable (1 = enable)
3843 *
3844 * 0100 1001
3845 */
3846 wr_reg8(info, CCR, 0x49);
3847
3848 /* set speed if available, otherwise use default */
3849 if (info->params.clock_speed)
3850 set_rate(info, info->params.clock_speed);
3851 else
3852 set_rate(info, 3686400);
3853 }
3854 }
3855
3856 /*
3857 * set baud rate generator to specified rate
3858 */
3859 static void set_rate(struct slgt_info *info, u32 rate)
3860 {
3861 unsigned int div;
3862 unsigned int osc = info->base_clock;
3863
3864 /* div = osc/rate - 1
3865 *
3866 * Round div up if osc/rate is not integer to
3867 * force to next slowest rate.
3868 */
3869
3870 if (rate) {
3871 div = osc/rate;
3872 if (!(osc % rate) && div)
3873 div--;
3874 wr_reg16(info, BDR, (unsigned short)div);
3875 }
3876 }
3877
3878 static void rx_stop(struct slgt_info *info)
3879 {
3880 unsigned short val;
3881
3882 /* disable and reset receiver */
3883 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3884 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3885 wr_reg16(info, RCR, val); /* clear reset bit */
3886
3887 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3888
3889 /* clear pending rx interrupts */
3890 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3891
3892 rdma_reset(info);
3893
3894 info->rx_enabled = false;
3895 info->rx_restart = false;
3896 }
3897
3898 static void rx_start(struct slgt_info *info)
3899 {
3900 unsigned short val;
3901
3902 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3903
3904 /* clear pending rx overrun IRQ */
3905 wr_reg16(info, SSR, IRQ_RXOVER);
3906
3907 /* reset and disable receiver */
3908 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3909 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3910 wr_reg16(info, RCR, val); /* clear reset bit */
3911
3912 rdma_reset(info);
3913 reset_rbufs(info);
3914
3915 if (info->rx_pio) {
3916 /* rx request when rx FIFO not empty */
3917 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3918 slgt_irq_on(info, IRQ_RXDATA);
3919 if (info->params.mode == MGSL_MODE_ASYNC) {
3920 /* enable saving of rx status */
3921 wr_reg32(info, RDCSR, BIT6);
3922 }
3923 } else {
3924 /* rx request when rx FIFO half full */
3925 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3926 /* set 1st descriptor address */
3927 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3928
3929 if (info->params.mode != MGSL_MODE_ASYNC) {
3930 /* enable rx DMA and DMA interrupt */
3931 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3932 } else {
3933 /* enable saving of rx status, rx DMA and DMA interrupt */
3934 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3935 }
3936 }
3937
3938 slgt_irq_on(info, IRQ_RXOVER);
3939
3940 /* enable receiver */
3941 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3942
3943 info->rx_restart = false;
3944 info->rx_enabled = true;
3945 }
3946
3947 static void tx_start(struct slgt_info *info)
3948 {
3949 if (!info->tx_enabled) {
3950 wr_reg16(info, TCR,
3951 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3952 info->tx_enabled = true;
3953 }
3954
3955 if (desc_count(info->tbufs[info->tbuf_start])) {
3956 info->drop_rts_on_tx_done = false;
3957
3958 if (info->params.mode != MGSL_MODE_ASYNC) {
3959 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3960 get_signals(info);
3961 if (!(info->signals & SerialSignal_RTS)) {
3962 info->signals |= SerialSignal_RTS;
3963 set_signals(info);
3964 info->drop_rts_on_tx_done = true;
3965 }
3966 }
3967
3968 slgt_irq_off(info, IRQ_TXDATA);
3969 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3970 /* clear tx idle and underrun status bits */
3971 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3972 } else {
3973 slgt_irq_off(info, IRQ_TXDATA);
3974 slgt_irq_on(info, IRQ_TXIDLE);
3975 /* clear tx idle status bit */
3976 wr_reg16(info, SSR, IRQ_TXIDLE);
3977 }
3978 /* set 1st descriptor address and start DMA */
3979 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3980 wr_reg32(info, TDCSR, BIT2 + BIT0);
3981 info->tx_active = true;
3982 }
3983 }
3984
3985 static void tx_stop(struct slgt_info *info)
3986 {
3987 unsigned short val;
3988
3989 del_timer(&info->tx_timer);
3990
3991 tdma_reset(info);
3992
3993 /* reset and disable transmitter */
3994 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3995 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3996
3997 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3998
3999 /* clear tx idle and underrun status bit */
4000 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4001
4002 reset_tbufs(info);
4003
4004 info->tx_enabled = false;
4005 info->tx_active = false;
4006 }
4007
4008 static void reset_port(struct slgt_info *info)
4009 {
4010 if (!info->reg_addr)
4011 return;
4012
4013 tx_stop(info);
4014 rx_stop(info);
4015
4016 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4017 set_signals(info);
4018
4019 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4020 }
4021
4022 static void reset_adapter(struct slgt_info *info)
4023 {
4024 int i;
4025 for (i=0; i < info->port_count; ++i) {
4026 if (info->port_array[i])
4027 reset_port(info->port_array[i]);
4028 }
4029 }
4030
4031 static void async_mode(struct slgt_info *info)
4032 {
4033 unsigned short val;
4034
4035 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4036 tx_stop(info);
4037 rx_stop(info);
4038
4039 /* TCR (tx control)
4040 *
4041 * 15..13 mode, 010=async
4042 * 12..10 encoding, 000=NRZ
4043 * 09 parity enable
4044 * 08 1=odd parity, 0=even parity
4045 * 07 1=RTS driver control
4046 * 06 1=break enable
4047 * 05..04 character length
4048 * 00=5 bits
4049 * 01=6 bits
4050 * 10=7 bits
4051 * 11=8 bits
4052 * 03 0=1 stop bit, 1=2 stop bits
4053 * 02 reset
4054 * 01 enable
4055 * 00 auto-CTS enable
4056 */
4057 val = 0x4000;
4058
4059 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4060 val |= BIT7;
4061
4062 if (info->params.parity != ASYNC_PARITY_NONE) {
4063 val |= BIT9;
4064 if (info->params.parity == ASYNC_PARITY_ODD)
4065 val |= BIT8;
4066 }
4067
4068 switch (info->params.data_bits)
4069 {
4070 case 6: val |= BIT4; break;
4071 case 7: val |= BIT5; break;
4072 case 8: val |= BIT5 + BIT4; break;
4073 }
4074
4075 if (info->params.stop_bits != 1)
4076 val |= BIT3;
4077
4078 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4079 val |= BIT0;
4080
4081 wr_reg16(info, TCR, val);
4082
4083 /* RCR (rx control)
4084 *
4085 * 15..13 mode, 010=async
4086 * 12..10 encoding, 000=NRZ
4087 * 09 parity enable
4088 * 08 1=odd parity, 0=even parity
4089 * 07..06 reserved, must be 0
4090 * 05..04 character length
4091 * 00=5 bits
4092 * 01=6 bits
4093 * 10=7 bits
4094 * 11=8 bits
4095 * 03 reserved, must be zero
4096 * 02 reset
4097 * 01 enable
4098 * 00 auto-DCD enable
4099 */
4100 val = 0x4000;
4101
4102 if (info->params.parity != ASYNC_PARITY_NONE) {
4103 val |= BIT9;
4104 if (info->params.parity == ASYNC_PARITY_ODD)
4105 val |= BIT8;
4106 }
4107
4108 switch (info->params.data_bits)
4109 {
4110 case 6: val |= BIT4; break;
4111 case 7: val |= BIT5; break;
4112 case 8: val |= BIT5 + BIT4; break;
4113 }
4114
4115 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4116 val |= BIT0;
4117
4118 wr_reg16(info, RCR, val);
4119
4120 /* CCR (clock control)
4121 *
4122 * 07..05 011 = tx clock source is BRG/16
4123 * 04..02 010 = rx clock source is BRG
4124 * 01 0 = auxclk disabled
4125 * 00 1 = BRG enabled
4126 *
4127 * 0110 1001
4128 */
4129 wr_reg8(info, CCR, 0x69);
4130
4131 msc_set_vcr(info);
4132
4133 /* SCR (serial control)
4134 *
4135 * 15 1=tx req on FIFO half empty
4136 * 14 1=rx req on FIFO half full
4137 * 13 tx data IRQ enable
4138 * 12 tx idle IRQ enable
4139 * 11 rx break on IRQ enable
4140 * 10 rx data IRQ enable
4141 * 09 rx break off IRQ enable
4142 * 08 overrun IRQ enable
4143 * 07 DSR IRQ enable
4144 * 06 CTS IRQ enable
4145 * 05 DCD IRQ enable
4146 * 04 RI IRQ enable
4147 * 03 0=16x sampling, 1=8x sampling
4148 * 02 1=txd->rxd internal loopback enable
4149 * 01 reserved, must be zero
4150 * 00 1=master IRQ enable
4151 */
4152 val = BIT15 + BIT14 + BIT0;
4153 /* JCR[8] : 1 = x8 async mode feature available */
4154 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4155 ((info->base_clock < (info->params.data_rate * 16)) ||
4156 (info->base_clock % (info->params.data_rate * 16)))) {
4157 /* use 8x sampling */
4158 val |= BIT3;
4159 set_rate(info, info->params.data_rate * 8);
4160 } else {
4161 /* use 16x sampling */
4162 set_rate(info, info->params.data_rate * 16);
4163 }
4164 wr_reg16(info, SCR, val);
4165
4166 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4167
4168 if (info->params.loopback)
4169 enable_loopback(info);
4170 }
4171
4172 static void sync_mode(struct slgt_info *info)
4173 {
4174 unsigned short val;
4175
4176 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4177 tx_stop(info);
4178 rx_stop(info);
4179
4180 /* TCR (tx control)
4181 *
4182 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4183 * 12..10 encoding
4184 * 09 CRC enable
4185 * 08 CRC32
4186 * 07 1=RTS driver control
4187 * 06 preamble enable
4188 * 05..04 preamble length
4189 * 03 share open/close flag
4190 * 02 reset
4191 * 01 enable
4192 * 00 auto-CTS enable
4193 */
4194 val = BIT2;
4195
4196 switch(info->params.mode) {
4197 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4198 case MGSL_MODE_BISYNC: val |= BIT15; break;
4199 case MGSL_MODE_RAW: val |= BIT13; break;
4200 }
4201 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4202 val |= BIT7;
4203
4204 switch(info->params.encoding)
4205 {
4206 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4207 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4208 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4209 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4210 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4211 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4212 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4213 }
4214
4215 switch (info->params.crc_type & HDLC_CRC_MASK)
4216 {
4217 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4218 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4219 }
4220
4221 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4222 val |= BIT6;
4223
4224 switch (info->params.preamble_length)
4225 {
4226 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4227 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4228 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4229 }
4230
4231 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4232 val |= BIT0;
4233
4234 wr_reg16(info, TCR, val);
4235
4236 /* TPR (transmit preamble) */
4237
4238 switch (info->params.preamble)
4239 {
4240 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4241 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4242 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4243 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4244 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4245 default: val = 0x7e; break;
4246 }
4247 wr_reg8(info, TPR, (unsigned char)val);
4248
4249 /* RCR (rx control)
4250 *
4251 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4252 * 12..10 encoding
4253 * 09 CRC enable
4254 * 08 CRC32
4255 * 07..03 reserved, must be 0
4256 * 02 reset
4257 * 01 enable
4258 * 00 auto-DCD enable
4259 */
4260 val = 0;
4261
4262 switch(info->params.mode) {
4263 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4264 case MGSL_MODE_BISYNC: val |= BIT15; break;
4265 case MGSL_MODE_RAW: val |= BIT13; break;
4266 }
4267
4268 switch(info->params.encoding)
4269 {
4270 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4271 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4272 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4273 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4274 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4275 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4276 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4277 }
4278
4279 switch (info->params.crc_type & HDLC_CRC_MASK)
4280 {
4281 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4282 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4283 }
4284
4285 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4286 val |= BIT0;
4287
4288 wr_reg16(info, RCR, val);
4289
4290 /* CCR (clock control)
4291 *
4292 * 07..05 tx clock source
4293 * 04..02 rx clock source
4294 * 01 auxclk enable
4295 * 00 BRG enable
4296 */
4297 val = 0;
4298
4299 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4300 {
4301 // when RxC source is DPLL, BRG generates 16X DPLL
4302 // reference clock, so take TxC from BRG/16 to get
4303 // transmit clock at actual data rate
4304 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4305 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4306 else
4307 val |= BIT6; /* 010, txclk = BRG */
4308 }
4309 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4310 val |= BIT7; /* 100, txclk = DPLL Input */
4311 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4312 val |= BIT5; /* 001, txclk = RXC Input */
4313
4314 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4315 val |= BIT3; /* 010, rxclk = BRG */
4316 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4317 val |= BIT4; /* 100, rxclk = DPLL */
4318 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4319 val |= BIT2; /* 001, rxclk = TXC Input */
4320
4321 if (info->params.clock_speed)
4322 val |= BIT1 + BIT0;
4323
4324 wr_reg8(info, CCR, (unsigned char)val);
4325
4326 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4327 {
4328 // program DPLL mode
4329 switch(info->params.encoding)
4330 {
4331 case HDLC_ENCODING_BIPHASE_MARK:
4332 case HDLC_ENCODING_BIPHASE_SPACE:
4333 val = BIT7; break;
4334 case HDLC_ENCODING_BIPHASE_LEVEL:
4335 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4336 val = BIT7 + BIT6; break;
4337 default: val = BIT6; // NRZ encodings
4338 }
4339 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4340
4341 // DPLL requires a 16X reference clock from BRG
4342 set_rate(info, info->params.clock_speed * 16);
4343 }
4344 else
4345 set_rate(info, info->params.clock_speed);
4346
4347 tx_set_idle(info);
4348
4349 msc_set_vcr(info);
4350
4351 /* SCR (serial control)
4352 *
4353 * 15 1=tx req on FIFO half empty
4354 * 14 1=rx req on FIFO half full
4355 * 13 tx data IRQ enable
4356 * 12 tx idle IRQ enable
4357 * 11 underrun IRQ enable
4358 * 10 rx data IRQ enable
4359 * 09 rx idle IRQ enable
4360 * 08 overrun IRQ enable
4361 * 07 DSR IRQ enable
4362 * 06 CTS IRQ enable
4363 * 05 DCD IRQ enable
4364 * 04 RI IRQ enable
4365 * 03 reserved, must be zero
4366 * 02 1=txd->rxd internal loopback enable
4367 * 01 reserved, must be zero
4368 * 00 1=master IRQ enable
4369 */
4370 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4371
4372 if (info->params.loopback)
4373 enable_loopback(info);
4374 }
4375
4376 /*
4377 * set transmit idle mode
4378 */
4379 static void tx_set_idle(struct slgt_info *info)
4380 {
4381 unsigned char val;
4382 unsigned short tcr;
4383
4384 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4385 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4386 */
4387 tcr = rd_reg16(info, TCR);
4388 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4389 /* disable preamble, set idle size to 16 bits */
4390 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4391 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4392 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4393 } else if (!(tcr & BIT6)) {
4394 /* preamble is disabled, set idle size to 8 bits */
4395 tcr &= ~(BIT5 + BIT4);
4396 }
4397 wr_reg16(info, TCR, tcr);
4398
4399 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4400 /* LSB of custom tx idle specified in tx idle register */
4401 val = (unsigned char)(info->idle_mode & 0xff);
4402 } else {
4403 /* standard 8 bit idle patterns */
4404 switch(info->idle_mode)
4405 {
4406 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4407 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4408 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4409 case HDLC_TXIDLE_ZEROS:
4410 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4411 default: val = 0xff;
4412 }
4413 }
4414
4415 wr_reg8(info, TIR, val);
4416 }
4417
4418 /*
4419 * get state of V24 status (input) signals
4420 */
4421 static void get_signals(struct slgt_info *info)
4422 {
4423 unsigned short status = rd_reg16(info, SSR);
4424
4425 /* clear all serial signals except DTR and RTS */
4426 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4427
4428 if (status & BIT3)
4429 info->signals |= SerialSignal_DSR;
4430 if (status & BIT2)
4431 info->signals |= SerialSignal_CTS;
4432 if (status & BIT1)
4433 info->signals |= SerialSignal_DCD;
4434 if (status & BIT0)
4435 info->signals |= SerialSignal_RI;
4436 }
4437
4438 /*
4439 * set V.24 Control Register based on current configuration
4440 */
4441 static void msc_set_vcr(struct slgt_info *info)
4442 {
4443 unsigned char val = 0;
4444
4445 /* VCR (V.24 control)
4446 *
4447 * 07..04 serial IF select
4448 * 03 DTR
4449 * 02 RTS
4450 * 01 LL
4451 * 00 RL
4452 */
4453
4454 switch(info->if_mode & MGSL_INTERFACE_MASK)
4455 {
4456 case MGSL_INTERFACE_RS232:
4457 val |= BIT5; /* 0010 */
4458 break;
4459 case MGSL_INTERFACE_V35:
4460 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4461 break;
4462 case MGSL_INTERFACE_RS422:
4463 val |= BIT6; /* 0100 */
4464 break;
4465 }
4466
4467 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4468 val |= BIT4;
4469 if (info->signals & SerialSignal_DTR)
4470 val |= BIT3;
4471 if (info->signals & SerialSignal_RTS)
4472 val |= BIT2;
4473 if (info->if_mode & MGSL_INTERFACE_LL)
4474 val |= BIT1;
4475 if (info->if_mode & MGSL_INTERFACE_RL)
4476 val |= BIT0;
4477 wr_reg8(info, VCR, val);
4478 }
4479
4480 /*
4481 * set state of V24 control (output) signals
4482 */
4483 static void set_signals(struct slgt_info *info)
4484 {
4485 unsigned char val = rd_reg8(info, VCR);
4486 if (info->signals & SerialSignal_DTR)
4487 val |= BIT3;
4488 else
4489 val &= ~BIT3;
4490 if (info->signals & SerialSignal_RTS)
4491 val |= BIT2;
4492 else
4493 val &= ~BIT2;
4494 wr_reg8(info, VCR, val);
4495 }
4496
4497 /*
4498 * free range of receive DMA buffers (i to last)
4499 */
4500 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4501 {
4502 int done = 0;
4503
4504 while(!done) {
4505 /* reset current buffer for reuse */
4506 info->rbufs[i].status = 0;
4507 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4508 if (i == last)
4509 done = 1;
4510 if (++i == info->rbuf_count)
4511 i = 0;
4512 }
4513 info->rbuf_current = i;
4514 }
4515
4516 /*
4517 * mark all receive DMA buffers as free
4518 */
4519 static void reset_rbufs(struct slgt_info *info)
4520 {
4521 free_rbufs(info, 0, info->rbuf_count - 1);
4522 info->rbuf_fill_index = 0;
4523 info->rbuf_fill_count = 0;
4524 }
4525
4526 /*
4527 * pass receive HDLC frame to upper layer
4528 *
4529 * return true if frame available, otherwise false
4530 */
4531 static bool rx_get_frame(struct slgt_info *info)
4532 {
4533 unsigned int start, end;
4534 unsigned short status;
4535 unsigned int framesize = 0;
4536 unsigned long flags;
4537 struct tty_struct *tty = info->port.tty;
4538 unsigned char addr_field = 0xff;
4539 unsigned int crc_size = 0;
4540
4541 switch (info->params.crc_type & HDLC_CRC_MASK) {
4542 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4543 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4544 }
4545
4546 check_again:
4547
4548 framesize = 0;
4549 addr_field = 0xff;
4550 start = end = info->rbuf_current;
4551
4552 for (;;) {
4553 if (!desc_complete(info->rbufs[end]))
4554 goto cleanup;
4555
4556 if (framesize == 0 && info->params.addr_filter != 0xff)
4557 addr_field = info->rbufs[end].buf[0];
4558
4559 framesize += desc_count(info->rbufs[end]);
4560
4561 if (desc_eof(info->rbufs[end]))
4562 break;
4563
4564 if (++end == info->rbuf_count)
4565 end = 0;
4566
4567 if (end == info->rbuf_current) {
4568 if (info->rx_enabled){
4569 spin_lock_irqsave(&info->lock,flags);
4570 rx_start(info);
4571 spin_unlock_irqrestore(&info->lock,flags);
4572 }
4573 goto cleanup;
4574 }
4575 }
4576
4577 /* status
4578 *
4579 * 15 buffer complete
4580 * 14..06 reserved
4581 * 05..04 residue
4582 * 02 eof (end of frame)
4583 * 01 CRC error
4584 * 00 abort
4585 */
4586 status = desc_status(info->rbufs[end]);
4587
4588 /* ignore CRC bit if not using CRC (bit is undefined) */
4589 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4590 status &= ~BIT1;
4591
4592 if (framesize == 0 ||
4593 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4594 free_rbufs(info, start, end);
4595 goto check_again;
4596 }
4597
4598 if (framesize < (2 + crc_size) || status & BIT0) {
4599 info->icount.rxshort++;
4600 framesize = 0;
4601 } else if (status & BIT1) {
4602 info->icount.rxcrc++;
4603 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4604 framesize = 0;
4605 }
4606
4607 #if SYNCLINK_GENERIC_HDLC
4608 if (framesize == 0) {
4609 info->netdev->stats.rx_errors++;
4610 info->netdev->stats.rx_frame_errors++;
4611 }
4612 #endif
4613
4614 DBGBH(("%s rx frame status=%04X size=%d\n",
4615 info->device_name, status, framesize));
4616 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4617
4618 if (framesize) {
4619 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4620 framesize -= crc_size;
4621 crc_size = 0;
4622 }
4623
4624 if (framesize > info->max_frame_size + crc_size)
4625 info->icount.rxlong++;
4626 else {
4627 /* copy dma buffer(s) to contiguous temp buffer */
4628 int copy_count = framesize;
4629 int i = start;
4630 unsigned char *p = info->tmp_rbuf;
4631 info->tmp_rbuf_count = framesize;
4632
4633 info->icount.rxok++;
4634
4635 while(copy_count) {
4636 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4637 memcpy(p, info->rbufs[i].buf, partial_count);
4638 p += partial_count;
4639 copy_count -= partial_count;
4640 if (++i == info->rbuf_count)
4641 i = 0;
4642 }
4643
4644 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4645 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4646 framesize++;
4647 }
4648
4649 #if SYNCLINK_GENERIC_HDLC
4650 if (info->netcount)
4651 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4652 else
4653 #endif
4654 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4655 }
4656 }
4657 free_rbufs(info, start, end);
4658 return true;
4659
4660 cleanup:
4661 return false;
4662 }
4663
4664 /*
4665 * pass receive buffer (RAW synchronous mode) to tty layer
4666 * return true if buffer available, otherwise false
4667 */
4668 static bool rx_get_buf(struct slgt_info *info)
4669 {
4670 unsigned int i = info->rbuf_current;
4671 unsigned int count;
4672
4673 if (!desc_complete(info->rbufs[i]))
4674 return false;
4675 count = desc_count(info->rbufs[i]);
4676 switch(info->params.mode) {
4677 case MGSL_MODE_MONOSYNC:
4678 case MGSL_MODE_BISYNC:
4679 /* ignore residue in byte synchronous modes */
4680 if (desc_residue(info->rbufs[i]))
4681 count--;
4682 break;
4683 }
4684 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4685 DBGINFO(("rx_get_buf size=%d\n", count));
4686 if (count)
4687 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4688 info->flag_buf, count);
4689 free_rbufs(info, i, i);
4690 return true;
4691 }
4692
4693 static void reset_tbufs(struct slgt_info *info)
4694 {
4695 unsigned int i;
4696 info->tbuf_current = 0;
4697 for (i=0 ; i < info->tbuf_count ; i++) {
4698 info->tbufs[i].status = 0;
4699 info->tbufs[i].count = 0;
4700 }
4701 }
4702
4703 /*
4704 * return number of free transmit DMA buffers
4705 */
4706 static unsigned int free_tbuf_count(struct slgt_info *info)
4707 {
4708 unsigned int count = 0;
4709 unsigned int i = info->tbuf_current;
4710
4711 do
4712 {
4713 if (desc_count(info->tbufs[i]))
4714 break; /* buffer in use */
4715 ++count;
4716 if (++i == info->tbuf_count)
4717 i=0;
4718 } while (i != info->tbuf_current);
4719
4720 /* if tx DMA active, last zero count buffer is in use */
4721 if (count && (rd_reg32(info, TDCSR) & BIT0))
4722 --count;
4723
4724 return count;
4725 }
4726
4727 /*
4728 * return number of bytes in unsent transmit DMA buffers
4729 * and the serial controller tx FIFO
4730 */
4731 static unsigned int tbuf_bytes(struct slgt_info *info)
4732 {
4733 unsigned int total_count = 0;
4734 unsigned int i = info->tbuf_current;
4735 unsigned int reg_value;
4736 unsigned int count;
4737 unsigned int active_buf_count = 0;
4738
4739 /*
4740 * Add descriptor counts for all tx DMA buffers.
4741 * If count is zero (cleared by DMA controller after read),
4742 * the buffer is complete or is actively being read from.
4743 *
4744 * Record buf_count of last buffer with zero count starting
4745 * from current ring position. buf_count is mirror
4746 * copy of count and is not cleared by serial controller.
4747 * If DMA controller is active, that buffer is actively
4748 * being read so add to total.
4749 */
4750 do {
4751 count = desc_count(info->tbufs[i]);
4752 if (count)
4753 total_count += count;
4754 else if (!total_count)
4755 active_buf_count = info->tbufs[i].buf_count;
4756 if (++i == info->tbuf_count)
4757 i = 0;
4758 } while (i != info->tbuf_current);
4759
4760 /* read tx DMA status register */
4761 reg_value = rd_reg32(info, TDCSR);
4762
4763 /* if tx DMA active, last zero count buffer is in use */
4764 if (reg_value & BIT0)
4765 total_count += active_buf_count;
4766
4767 /* add tx FIFO count = reg_value[15..8] */
4768 total_count += (reg_value >> 8) & 0xff;
4769
4770 /* if transmitter active add one byte for shift register */
4771 if (info->tx_active)
4772 total_count++;
4773
4774 return total_count;
4775 }
4776
4777 /*
4778 * load data into transmit DMA buffer ring and start transmitter if needed
4779 * return true if data accepted, otherwise false (buffers full)
4780 */
4781 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4782 {
4783 unsigned short count;
4784 unsigned int i;
4785 struct slgt_desc *d;
4786
4787 /* check required buffer space */
4788 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4789 return false;
4790
4791 DBGDATA(info, buf, size, "tx");
4792
4793 /*
4794 * copy data to one or more DMA buffers in circular ring
4795 * tbuf_start = first buffer for this data
4796 * tbuf_current = next free buffer
4797 *
4798 * Copy all data before making data visible to DMA controller by
4799 * setting descriptor count of the first buffer.
4800 * This prevents an active DMA controller from reading the first DMA
4801 * buffers of a frame and stopping before the final buffers are filled.
4802 */
4803
4804 info->tbuf_start = i = info->tbuf_current;
4805
4806 while (size) {
4807 d = &info->tbufs[i];
4808
4809 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4810 memcpy(d->buf, buf, count);
4811
4812 size -= count;
4813 buf += count;
4814
4815 /*
4816 * set EOF bit for last buffer of HDLC frame or
4817 * for every buffer in raw mode
4818 */
4819 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4820 info->params.mode == MGSL_MODE_RAW)
4821 set_desc_eof(*d, 1);
4822 else
4823 set_desc_eof(*d, 0);
4824
4825 /* set descriptor count for all but first buffer */
4826 if (i != info->tbuf_start)
4827 set_desc_count(*d, count);
4828 d->buf_count = count;
4829
4830 if (++i == info->tbuf_count)
4831 i = 0;
4832 }
4833
4834 info->tbuf_current = i;
4835
4836 /* set first buffer count to make new data visible to DMA controller */
4837 d = &info->tbufs[info->tbuf_start];
4838 set_desc_count(*d, d->buf_count);
4839
4840 /* start transmitter if needed and update transmit timeout */
4841 if (!info->tx_active)
4842 tx_start(info);
4843 update_tx_timer(info);
4844
4845 return true;
4846 }
4847
4848 static int register_test(struct slgt_info *info)
4849 {
4850 static unsigned short patterns[] =
4851 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4852 static unsigned int count = ARRAY_SIZE(patterns);
4853 unsigned int i;
4854 int rc = 0;
4855
4856 for (i=0 ; i < count ; i++) {
4857 wr_reg16(info, TIR, patterns[i]);
4858 wr_reg16(info, BDR, patterns[(i+1)%count]);
4859 if ((rd_reg16(info, TIR) != patterns[i]) ||
4860 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4861 rc = -ENODEV;
4862 break;
4863 }
4864 }
4865 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4866 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4867 return rc;
4868 }
4869
4870 static int irq_test(struct slgt_info *info)
4871 {
4872 unsigned long timeout;
4873 unsigned long flags;
4874 struct tty_struct *oldtty = info->port.tty;
4875 u32 speed = info->params.data_rate;
4876
4877 info->params.data_rate = 921600;
4878 info->port.tty = NULL;
4879
4880 spin_lock_irqsave(&info->lock, flags);
4881 async_mode(info);
4882 slgt_irq_on(info, IRQ_TXIDLE);
4883
4884 /* enable transmitter */
4885 wr_reg16(info, TCR,
4886 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4887
4888 /* write one byte and wait for tx idle */
4889 wr_reg16(info, TDR, 0);
4890
4891 /* assume failure */
4892 info->init_error = DiagStatus_IrqFailure;
4893 info->irq_occurred = false;
4894
4895 spin_unlock_irqrestore(&info->lock, flags);
4896
4897 timeout=100;
4898 while(timeout-- && !info->irq_occurred)
4899 msleep_interruptible(10);
4900
4901 spin_lock_irqsave(&info->lock,flags);
4902 reset_port(info);
4903 spin_unlock_irqrestore(&info->lock,flags);
4904
4905 info->params.data_rate = speed;
4906 info->port.tty = oldtty;
4907
4908 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4909 return info->irq_occurred ? 0 : -ENODEV;
4910 }
4911
4912 static int loopback_test_rx(struct slgt_info *info)
4913 {
4914 unsigned char *src, *dest;
4915 int count;
4916
4917 if (desc_complete(info->rbufs[0])) {
4918 count = desc_count(info->rbufs[0]);
4919 src = info->rbufs[0].buf;
4920 dest = info->tmp_rbuf;
4921
4922 for( ; count ; count-=2, src+=2) {
4923 /* src=data byte (src+1)=status byte */
4924 if (!(*(src+1) & (BIT9 + BIT8))) {
4925 *dest = *src;
4926 dest++;
4927 info->tmp_rbuf_count++;
4928 }
4929 }
4930 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4931 return 1;
4932 }
4933 return 0;
4934 }
4935
4936 static int loopback_test(struct slgt_info *info)
4937 {
4938 #define TESTFRAMESIZE 20
4939
4940 unsigned long timeout;
4941 u16 count = TESTFRAMESIZE;
4942 unsigned char buf[TESTFRAMESIZE];
4943 int rc = -ENODEV;
4944 unsigned long flags;
4945
4946 struct tty_struct *oldtty = info->port.tty;
4947 MGSL_PARAMS params;
4948
4949 memcpy(&params, &info->params, sizeof(params));
4950
4951 info->params.mode = MGSL_MODE_ASYNC;
4952 info->params.data_rate = 921600;
4953 info->params.loopback = 1;
4954 info->port.tty = NULL;
4955
4956 /* build and send transmit frame */
4957 for (count = 0; count < TESTFRAMESIZE; ++count)
4958 buf[count] = (unsigned char)count;
4959
4960 info->tmp_rbuf_count = 0;
4961 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4962
4963 /* program hardware for HDLC and enabled receiver */
4964 spin_lock_irqsave(&info->lock,flags);
4965 async_mode(info);
4966 rx_start(info);
4967 tx_load(info, buf, count);
4968 spin_unlock_irqrestore(&info->lock, flags);
4969
4970 /* wait for receive complete */
4971 for (timeout = 100; timeout; --timeout) {
4972 msleep_interruptible(10);
4973 if (loopback_test_rx(info)) {
4974 rc = 0;
4975 break;
4976 }
4977 }
4978
4979 /* verify received frame length and contents */
4980 if (!rc && (info->tmp_rbuf_count != count ||
4981 memcmp(buf, info->tmp_rbuf, count))) {
4982 rc = -ENODEV;
4983 }
4984
4985 spin_lock_irqsave(&info->lock,flags);
4986 reset_adapter(info);
4987 spin_unlock_irqrestore(&info->lock,flags);
4988
4989 memcpy(&info->params, &params, sizeof(info->params));
4990 info->port.tty = oldtty;
4991
4992 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4993 return rc;
4994 }
4995
4996 static int adapter_test(struct slgt_info *info)
4997 {
4998 DBGINFO(("testing %s\n", info->device_name));
4999 if (register_test(info) < 0) {
5000 printk("register test failure %s addr=%08X\n",
5001 info->device_name, info->phys_reg_addr);
5002 } else if (irq_test(info) < 0) {
5003 printk("IRQ test failure %s IRQ=%d\n",
5004 info->device_name, info->irq_level);
5005 } else if (loopback_test(info) < 0) {
5006 printk("loopback test failure %s\n", info->device_name);
5007 }
5008 return info->init_error;
5009 }
5010
5011 /*
5012 * transmit timeout handler
5013 */
5014 static void tx_timeout(unsigned long context)
5015 {
5016 struct slgt_info *info = (struct slgt_info*)context;
5017 unsigned long flags;
5018
5019 DBGINFO(("%s tx_timeout\n", info->device_name));
5020 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5021 info->icount.txtimeout++;
5022 }
5023 spin_lock_irqsave(&info->lock,flags);
5024 tx_stop(info);
5025 spin_unlock_irqrestore(&info->lock,flags);
5026
5027 #if SYNCLINK_GENERIC_HDLC
5028 if (info->netcount)
5029 hdlcdev_tx_done(info);
5030 else
5031 #endif
5032 bh_transmit(info);
5033 }
5034
5035 /*
5036 * receive buffer polling timer
5037 */
5038 static void rx_timeout(unsigned long context)
5039 {
5040 struct slgt_info *info = (struct slgt_info*)context;
5041 unsigned long flags;
5042
5043 DBGINFO(("%s rx_timeout\n", info->device_name));
5044 spin_lock_irqsave(&info->lock, flags);
5045 info->pending_bh |= BH_RECEIVE;
5046 spin_unlock_irqrestore(&info->lock, flags);
5047 bh_handler(&info->task);
5048 }
5049
WandBoard kernel