drivers/usb/host/uhci-hcd.h

   1 #ifndef __LINUX_UHCI_HCD_H
   2 #define __LINUX_UHCI_HCD_H
   3
   4 #include <linux/list.h>
   5 #include <linux/usb.h>
   6
   7 #define usb_packetid(pipe)      (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
   8 #define PIPE_DEVEP_MASK         0x0007ff00
   9
  10
  11 /*
  12  * Universal Host Controller Interface data structures and defines
  13  */
  14
  15 /* Command register */
  16 #define USBCMD          0
  17 #define   USBCMD_RS             0x0001  /* Run/Stop */
  18 #define   USBCMD_HCRESET        0x0002  /* Host reset */
  19 #define   USBCMD_GRESET         0x0004  /* Global reset */
  20 #define   USBCMD_EGSM           0x0008  /* Global Suspend Mode */
  21 #define   USBCMD_FGR            0x0010  /* Force Global Resume */
  22 #define   USBCMD_SWDBG          0x0020  /* SW Debug mode */
  23 #define   USBCMD_CF             0x0040  /* Config Flag (sw only) */
  24 #define   USBCMD_MAXP           0x0080  /* Max Packet (0 = 32, 1 = 64) */
  25
  26 /* Status register */
  27 #define USBSTS          2
  28 #define   USBSTS_USBINT         0x0001  /* Interrupt due to IOC */
  29 #define   USBSTS_ERROR          0x0002  /* Interrupt due to error */
  30 #define   USBSTS_RD             0x0004  /* Resume Detect */
  31 #define   USBSTS_HSE            0x0008  /* Host System Error: PCI problems */
  32 #define   USBSTS_HCPE           0x0010  /* Host Controller Process Error:
  33                                          * the schedule is buggy */
  34 #define   USBSTS_HCH            0x0020  /* HC Halted */
  35
  36 /* Interrupt enable register */
  37 #define USBINTR         4
  38 #define   USBINTR_TIMEOUT       0x0001  /* Timeout/CRC error enable */
  39 #define   USBINTR_RESUME        0x0002  /* Resume interrupt enable */
  40 #define   USBINTR_IOC           0x0004  /* Interrupt On Complete enable */
  41 #define   USBINTR_SP            0x0008  /* Short packet interrupt enable */
  42
  43 #define USBFRNUM        6
  44 #define USBFLBASEADD    8
  45 #define USBSOF          12
  46 #define   USBSOF_DEFAULT        64      /* Frame length is exactly 1 ms */
  47
  48 /* USB port status and control registers */
  49 #define USBPORTSC1      16
  50 #define USBPORTSC2      18
  51 #define   USBPORTSC_CCS         0x0001  /* Current Connect Status
  52                                          * ("device present") */
  53 #define   USBPORTSC_CSC         0x0002  /* Connect Status Change */
  54 #define   USBPORTSC_PE          0x0004  /* Port Enable */
  55 #define   USBPORTSC_PEC         0x0008  /* Port Enable Change */
  56 #define   USBPORTSC_DPLUS       0x0010  /* D+ high (line status) */
  57 #define   USBPORTSC_DMINUS      0x0020  /* D- high (line status) */
  58 #define   USBPORTSC_RD          0x0040  /* Resume Detect */
  59 #define   USBPORTSC_RES1        0x0080  /* reserved, always 1 */
  60 #define   USBPORTSC_LSDA        0x0100  /* Low Speed Device Attached */
  61 #define   USBPORTSC_PR          0x0200  /* Port Reset */
  62 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
  63 #define   USBPORTSC_OC          0x0400  /* Over Current condition */
  64 #define   USBPORTSC_OCC         0x0800  /* Over Current Change R/WC */
  65 #define   USBPORTSC_SUSP        0x1000  /* Suspend */
  66 #define   USBPORTSC_RES2        0x2000  /* reserved, write zeroes */
  67 #define   USBPORTSC_RES3        0x4000  /* reserved, write zeroes */
  68 #define   USBPORTSC_RES4        0x8000  /* reserved, write zeroes */
  69
  70 /* Legacy support register */
  71 #define USBLEGSUP               0xc0
  72 #define   USBLEGSUP_DEFAULT     0x2000  /* only PIRQ enable set */
  73 #define   USBLEGSUP_RWC         0x8f00  /* the R/WC bits */
  74 #define   USBLEGSUP_RO          0x5040  /* R/O and reserved bits */
  75
  76 #define UHCI_PTR_BITS           __constant_cpu_to_le32(0x000F)
  77 #define UHCI_PTR_TERM           __constant_cpu_to_le32(0x0001)
  78 #define UHCI_PTR_QH             __constant_cpu_to_le32(0x0002)
  79 #define UHCI_PTR_DEPTH          __constant_cpu_to_le32(0x0004)
  80 #define UHCI_PTR_BREADTH        __constant_cpu_to_le32(0x0000)
  81
  82 #define UHCI_NUMFRAMES          1024    /* in the frame list [array] */
  83 #define UHCI_MAX_SOF_NUMBER     2047    /* in an SOF packet */
  84 #define CAN_SCHEDULE_FRAMES     1000    /* how far in the future frames
  85                                          * can be scheduled */
  86
  87
  88 /*
  89  *      Queue Headers
  90  */
  91
  92 /*
  93  * One role of a QH is to hold a queue of TDs for some endpoint.  One QH goes
  94  * with each endpoint, and qh->element (updated by the HC) is either:
  95  *   - the next unprocessed TD in the endpoint's queue, or
  96  *   - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
  97  *
  98  * The other role of a QH is to serve as a "skeleton" framelist entry, so we
  99  * can easily splice a QH for some endpoint into the schedule at the right
 100  * place.  Then qh->element is UHCI_PTR_TERM.
 101  *
 102  * In the schedule, qh->link maintains a list of QHs seen by the HC:
 103  *     skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
 104  *
 105  * qh->node is the software equivalent of qh->link.  The differences
 106  * are that the software list is doubly-linked and QHs in the UNLINKING
 107  * state are on the software list but not the hardware schedule.
 108  *
 109  * For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
 110  * but they never get added to the hardware schedule.
 111  */
 112 #define QH_STATE_IDLE           1       /* QH is not being used */
 113 #define QH_STATE_UNLINKING      2       /* QH has been removed from the
 114                                          * schedule but the hardware may
 115                                          * still be using it */
 116 #define QH_STATE_ACTIVE         3       /* QH is on the schedule */
 117
 118 struct uhci_qh {
 119         /* Hardware fields */
 120         __le32 link;                    /* Next QH in the schedule */
 121         __le32 element;                 /* Queue element (TD) pointer */
 122
 123         /* Software fields */
 124         dma_addr_t dma_handle;
 125
 126         struct list_head node;          /* Node in the list of QHs */
 127         struct usb_host_endpoint *hep;  /* Endpoint information */
 128         struct usb_device *udev;
 129         struct list_head queue;         /* Queue of urbps for this QH */
 130         struct uhci_qh *skel;           /* Skeleton for this QH */
 131         struct uhci_td *dummy_td;       /* Dummy TD to end the queue */
 132
 133         unsigned int unlink_frame;      /* When the QH was unlinked */
 134         int state;                      /* QH_STATE_xxx; see above */
 135         int type;                       /* Queue type (control, bulk, etc) */
 136
 137         unsigned int initial_toggle:1;  /* Endpoint's current toggle value */
 138         unsigned int needs_fixup:1;     /* Must fix the TD toggle values */
 139         unsigned int is_stopped:1;      /* Queue was stopped by an error */
 140 } __attribute__((aligned(16)));
 141
 142 /*
 143  * We need a special accessor for the element pointer because it is
 144  * subject to asynchronous updates by the controller.
 145  */
 146 static inline __le32 qh_element(struct uhci_qh *qh) {
 147         __le32 element = qh->element;
 148
 149         barrier();
 150         return element;
 151 }
 152
 153
 154 /*
 155  *      Transfer Descriptors
 156  */
 157
 158 /*
 159  * for TD <status>:
 160  */
 161 #define TD_CTRL_SPD             (1 << 29)       /* Short Packet Detect */
 162 #define TD_CTRL_C_ERR_MASK      (3 << 27)       /* Error Counter bits */
 163 #define TD_CTRL_C_ERR_SHIFT     27
 164 #define TD_CTRL_LS              (1 << 26)       /* Low Speed Device */
 165 #define TD_CTRL_IOS             (1 << 25)       /* Isochronous Select */
 166 #define TD_CTRL_IOC             (1 << 24)       /* Interrupt on Complete */
 167 #define TD_CTRL_ACTIVE          (1 << 23)       /* TD Active */
 168 #define TD_CTRL_STALLED         (1 << 22)       /* TD Stalled */
 169 #define TD_CTRL_DBUFERR         (1 << 21)       /* Data Buffer Error */
 170 #define TD_CTRL_BABBLE          (1 << 20)       /* Babble Detected */
 171 #define TD_CTRL_NAK             (1 << 19)       /* NAK Received */
 172 #define TD_CTRL_CRCTIMEO        (1 << 18)       /* CRC/Time Out Error */
 173 #define TD_CTRL_BITSTUFF        (1 << 17)       /* Bit Stuff Error */
 174 #define TD_CTRL_ACTLEN_MASK     0x7FF   /* actual length, encoded as n - 1 */
 175
 176 #define TD_CTRL_ANY_ERROR       (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
 177                                  TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \
 178                                  TD_CTRL_BITSTUFF)
 179
 180 #define uhci_maxerr(err)                ((err) << TD_CTRL_C_ERR_SHIFT)
 181 #define uhci_status_bits(ctrl_sts)      ((ctrl_sts) & 0xF60000)
 182 #define uhci_actual_length(ctrl_sts)    (((ctrl_sts) + 1) & \
 183                         TD_CTRL_ACTLEN_MASK)    /* 1-based */
 184
 185 /*
 186  * for TD <info>: (a.k.a. Token)
 187  */
 188 #define td_token(td)            le32_to_cpu((td)->token)
 189 #define TD_TOKEN_DEVADDR_SHIFT  8
 190 #define TD_TOKEN_TOGGLE_SHIFT   19
 191 #define TD_TOKEN_TOGGLE         (1 << 19)
 192 #define TD_TOKEN_EXPLEN_SHIFT   21
 193 #define TD_TOKEN_EXPLEN_MASK    0x7FF   /* expected length, encoded as n-1 */
 194 #define TD_TOKEN_PID_MASK       0xFF
 195
 196 #define uhci_explen(len)        ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
 197                                         TD_TOKEN_EXPLEN_SHIFT)
 198
 199 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
 200                                         1) & TD_TOKEN_EXPLEN_MASK)
 201 #define uhci_toggle(token)      (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
 202 #define uhci_endpoint(token)    (((token) >> 15) & 0xf)
 203 #define uhci_devaddr(token)     (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
 204 #define uhci_devep(token)       (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
 205 #define uhci_packetid(token)    ((token) & TD_TOKEN_PID_MASK)
 206 #define uhci_packetout(token)   (uhci_packetid(token) != USB_PID_IN)
 207 #define uhci_packetin(token)    (uhci_packetid(token) == USB_PID_IN)
 208
 209 /*
 210  * The documentation says "4 words for hardware, 4 words for software".
 211  *
 212  * That's silly, the hardware doesn't care. The hardware only cares that
 213  * the hardware words are 16-byte aligned, and we can have any amount of
 214  * sw space after the TD entry.
 215  *
 216  * td->link points to either another TD (not necessarily for the same urb or
 217  * even the same endpoint), or nothing (PTR_TERM), or a QH.
 218  */
 219 struct uhci_td {
 220         /* Hardware fields */
 221         __le32 link;
 222         __le32 status;
 223         __le32 token;
 224         __le32 buffer;
 225
 226         /* Software fields */
 227         dma_addr_t dma_handle;
 228
 229         struct list_head list;
 230         struct list_head remove_list;
 231
 232         int frame;                      /* for iso: what frame? */
 233         struct list_head fl_list;
 234 } __attribute__((aligned(16)));
 235
 236 /*
 237  * We need a special accessor for the control/status word because it is
 238  * subject to asynchronous updates by the controller.
 239  */
 240 static inline u32 td_status(struct uhci_td *td) {
 241         __le32 status = td->status;
 242
 243         barrier();
 244         return le32_to_cpu(status);
 245 }
 246
 247
 248 /*
 249  *      Skeleton Queue Headers
 250  */
 251
 252 /*
 253  * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
 254  * automatic queuing. To make it easy to insert entries into the schedule,
 255  * we have a skeleton of QHs for each predefined Interrupt latency,
 256  * low-speed control, full-speed control, bulk, and terminating QH
 257  * (see explanation for the terminating QH below).
 258  *
 259  * When we want to add a new QH, we add it to the end of the list for the
 260  * skeleton QH.  For instance, the schedule list can look like this:
 261  *
 262  * skel int128 QH
 263  * dev 1 interrupt QH
 264  * dev 5 interrupt QH
 265  * skel int64 QH
 266  * skel int32 QH
 267  * ...
 268  * skel int1 QH
 269  * skel low-speed control QH
 270  * dev 5 control QH
 271  * skel full-speed control QH
 272  * skel bulk QH
 273  * dev 1 bulk QH
 274  * dev 2 bulk QH
 275  * skel terminating QH
 276  *
 277  * The terminating QH is used for 2 reasons:
 278  * - To place a terminating TD which is used to workaround a PIIX bug
 279  *   (see Intel errata for explanation), and
 280  * - To loop back to the full-speed control queue for full-speed bandwidth
 281  *   reclamation.
 282  *
 283  * There's a special skeleton QH for Isochronous QHs.  It never appears
 284  * on the schedule, and Isochronous TDs go on the schedule before the
 285  * the skeleton QHs.  The hardware accesses them directly rather than
 286  * through their QH, which is used only for bookkeeping purposes.
 287  * While the UHCI spec doesn't forbid the use of QHs for Isochronous,
 288  * it doesn't use them either.  And the spec says that queues never
 289  * advance on an error completion status, which makes them totally
 290  * unsuitable for Isochronous transfers.
 291  */
 292
 293 #define UHCI_NUM_SKELQH         14
 294 #define skel_unlink_qh          skelqh[0]
 295 #define skel_iso_qh             skelqh[1]
 296 #define skel_int128_qh          skelqh[2]
 297 #define skel_int64_qh           skelqh[3]
 298 #define skel_int32_qh           skelqh[4]
 299 #define skel_int16_qh           skelqh[5]
 300 #define skel_int8_qh            skelqh[6]
 301 #define skel_int4_qh            skelqh[7]
 302 #define skel_int2_qh            skelqh[8]
 303 #define skel_int1_qh            skelqh[9]
 304 #define skel_ls_control_qh      skelqh[10]
 305 #define skel_fs_control_qh      skelqh[11]
 306 #define skel_bulk_qh            skelqh[12]
 307 #define skel_term_qh            skelqh[13]
 308
 309 /*
 310  * Search tree for determining where <interval> fits in the skelqh[]
 311  * skeleton.
 312  *
 313  * An interrupt request should be placed into the slowest skelqh[]
 314  * which meets the interval/period/frequency requirement.
 315  * An interrupt request is allowed to be faster than <interval> but not slower.
 316  *
 317  * For a given <interval>, this function returns the appropriate/matching
 318  * skelqh[] index value.
 319  */
 320 static inline int __interval_to_skel(int interval)
 321 {
 322         if (interval < 16) {
 323                 if (interval < 4) {
 324                         if (interval < 2)
 325                                 return 9;       /* int1 for 0-1 ms */
 326                         return 8;               /* int2 for 2-3 ms */
 327                 }
 328                 if (interval < 8)
 329                         return 7;               /* int4 for 4-7 ms */
 330                 return 6;                       /* int8 for 8-15 ms */
 331         }
 332         if (interval < 64) {
 333                 if (interval < 32)
 334                         return 5;               /* int16 for 16-31 ms */
 335                 return 4;                       /* int32 for 32-63 ms */
 336         }
 337         if (interval < 128)
 338                 return 3;                       /* int64 for 64-127 ms */
 339         return 2;                               /* int128 for 128-255 ms (Max.) */
 340 }
 341
 342
 343 /*
 344  *      The UHCI controller and root hub
 345  */
 346
 347 /*
 348  * States for the root hub:
 349  *
 350  * To prevent "bouncing" in the presence of electrical noise,
 351  * when there are no devices attached we delay for 1 second in the
 352  * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
 353  *
 354  * (Note that the AUTO_STOPPED state won't be necessary once the hub
 355  * driver learns to autosuspend.)
 356  */
 357 enum uhci_rh_state {
 358         /* In the following states the HC must be halted.
 359          * These two must come first. */
 360         UHCI_RH_RESET,
 361         UHCI_RH_SUSPENDED,
 362
 363         UHCI_RH_AUTO_STOPPED,
 364         UHCI_RH_RESUMING,
 365
 366         /* In this state the HC changes from running to halted,
 367          * so it can legally appear either way. */
 368         UHCI_RH_SUSPENDING,
 369
 370         /* In the following states it's an error if the HC is halted.
 371          * These two must come last. */
 372         UHCI_RH_RUNNING,                /* The normal state */
 373         UHCI_RH_RUNNING_NODEVS,         /* Running with no devices attached */
 374 };
 375
 376 /*
 377  * The full UHCI controller information:
 378  */
 379 struct uhci_hcd {
 380
 381         /* debugfs */
 382         struct dentry *dentry;
 383
 384         /* Grabbed from PCI */
 385         unsigned long io_addr;
 386
 387         struct dma_pool *qh_pool;
 388         struct dma_pool *td_pool;
 389
 390         struct uhci_td *term_td;        /* Terminating TD, see UHCI bug */
 391         struct uhci_qh *skelqh[UHCI_NUM_SKELQH];        /* Skeleton QHs */
 392         struct uhci_qh *next_qh;        /* Next QH to scan */
 393
 394         spinlock_t lock;
 395
 396         dma_addr_t frame_dma_handle;    /* Hardware frame list */
 397         __le32 *frame;
 398         void **frame_cpu;               /* CPU's frame list */
 399
 400         int fsbr;                       /* Full-speed bandwidth reclamation */
 401         unsigned long fsbrtimeout;      /* FSBR delay */
 402
 403         enum uhci_rh_state rh_state;
 404         unsigned long auto_stop_time;           /* When to AUTO_STOP */
 405
 406         unsigned int frame_number;              /* As of last check */
 407         unsigned int is_stopped;
 408 #define UHCI_IS_STOPPED         9999            /* Larger than a frame # */
 409
 410         unsigned int scan_in_progress:1;        /* Schedule scan is running */
 411         unsigned int need_rescan:1;             /* Redo the schedule scan */
 412         unsigned int hc_inaccessible:1;         /* HC is suspended or dead */
 413         unsigned int working_RD:1;              /* Suspended root hub doesn't
 414                                                    need to be polled */
 415         unsigned int is_initialized:1;          /* Data structure is usable */
 416
 417         /* Support for port suspend/resume/reset */
 418         unsigned long port_c_suspend;           /* Bit-arrays of ports */
 419         unsigned long resuming_ports;
 420         unsigned long ports_timeout;            /* Time to stop signalling */
 421
 422         /* List of TDs that are done, but waiting to be freed (race) */
 423         struct list_head td_remove_list;
 424         unsigned int td_remove_age;             /* Age in frames */
 425
 426         struct list_head idle_qh_list;          /* Where the idle QHs live */
 427
 428         int rh_numports;                        /* Number of root-hub ports */
 429
 430         wait_queue_head_t waitqh;               /* endpoint_disable waiters */
 431         int num_waiting;                        /* Number of waiters */
 432 };
 433
 434 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
 435 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
 436 {
 437         return (struct uhci_hcd *) (hcd->hcd_priv);
 438 }
 439 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
 440 {
 441         return container_of((void *) uhci, struct usb_hcd, hcd_priv);
 442 }
 443
 444 #define uhci_dev(u)     (uhci_to_hcd(u)->self.controller)
 445
 446
 447 /*
 448  *      Private per-URB data
 449  */
 450 struct urb_priv {
 451         struct list_head node;          /* Node in the QH's urbp list */
 452
 453         struct urb *urb;
 454
 455         struct uhci_qh *qh;             /* QH for this URB */
 456         struct list_head td_list;
 457
 458         unsigned fsbr : 1;              /* URB turned on FSBR */
 459         unsigned short_transfer : 1;    /* URB got a short transfer, no
 460                                          * need to rescan */
 461 };
 462
 463
 464 /*
 465  * Locking in uhci.c
 466  *
 467  * Almost everything relating to the hardware schedule and processing
 468  * of URBs is protected by uhci->lock.  urb->status is protected by
 469  * urb->lock; that's the one exception.
 470  *
 471  * To prevent deadlocks, never lock uhci->lock while holding urb->lock.
 472  * The safe order of locking is:
 473  *
 474  * #1 uhci->lock
 475  * #2 urb->lock
 476  */
 477
 478
 479 /* Some special IDs */
 480
 481 #define PCI_VENDOR_ID_GENESYS           0x17a0
 482 #define PCI_DEVICE_ID_GL880S_UHCI       0x8083
 483
 484 #endif