?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ath9k: clean up enums and unused macros
[wandboard.git] / drivers / net / wireless / ath / ath9k / ath9k.h
blob6636f3c6dcf9f2946ad8b6aff39594c78e631958
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH9K_H
18 #define ATH9K_H
19
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <linux/leds.h>
23 #include <linux/completion.h>
24 #include <linux/pm_qos_params.h>
25
26 #include "debug.h"
27 #include "common.h"
28
29 /*
30 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
31 * should rely on this file or its contents.
32 */
33
34 struct ath_node;
35
36 /* Macro to expand scalars to 64-bit objects */
37
38 #define ito64(x) (sizeof(x) == 1) ? \
39 (((unsigned long long int)(x)) & (0xff)) : \
40 (sizeof(x) == 2) ? \
41 (((unsigned long long int)(x)) & 0xffff) : \
42 ((sizeof(x) == 4) ? \
43 (((unsigned long long int)(x)) & 0xffffffff) : \
44 (unsigned long long int)(x))
45
46 /* increment with wrap-around */
47 #define INCR(_l, _sz) do { \
48 (_l)++; \
49 (_l) &= ((_sz) - 1); \
50 } while (0)
51
52 /* decrement with wrap-around */
53 #define DECR(_l, _sz) do { \
54 (_l)--; \
55 (_l) &= ((_sz) - 1); \
56 } while (0)
57
58 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
59
60 #define ATH9K_PM_QOS_DEFAULT_VALUE 55
61
62 #define TSF_TO_TU(_h,_l) \
63 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64
65 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
66
67 struct ath_config {
68 u32 ath_aggr_prot;
69 u16 txpowlimit;
70 u8 cabqReadytime;
71 };
72
73 /*************************/
74 /* Descriptor Management */
75 /*************************/
76
77 #define ATH_TXBUF_RESET(_bf) do { \
78 (_bf)->bf_stale = false; \
79 (_bf)->bf_lastbf = NULL; \
80 (_bf)->bf_next = NULL; \
81 memset(&((_bf)->bf_state), 0, \
82 sizeof(struct ath_buf_state)); \
83 } while (0)
84
85 #define ATH_RXBUF_RESET(_bf) do { \
86 (_bf)->bf_stale = false; \
87 } while (0)
88
89 /**
90 * enum buffer_type - Buffer type flags
91 *
92 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
93 * @BUF_AGGR: Indicates whether the buffer can be aggregated
94 * (used in aggregation scheduling)
95 * @BUF_XRETRY: To denote excessive retries of the buffer
96 */
97 enum buffer_type {
98 BUF_AMPDU = BIT(0),
99 BUF_AGGR = BIT(1),
100 BUF_XRETRY = BIT(2),
101 };
102
103 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
104 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
105 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
106
107 #define ATH_TXSTATUS_RING_SIZE 64
108
109 struct ath_descdma {
110 void *dd_desc;
111 dma_addr_t dd_desc_paddr;
112 u32 dd_desc_len;
113 struct ath_buf *dd_bufptr;
114 };
115
116 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
117 struct list_head *head, const char *name,
118 int nbuf, int ndesc, bool is_tx);
119 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
120 struct list_head *head);
121
122 /***********/
123 /* RX / TX */
124 /***********/
125
126 #define ATH_MAX_ANTENNA 3
127 #define ATH_RXBUF 512
128 #define ATH_TXBUF 512
129 #define ATH_TXBUF_RESERVE 5
130 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
131 #define ATH_TXMAXTRY 13
132 #define ATH_MGT_TXMAXTRY 4
133
134 #define TID_TO_WME_AC(_tid) \
135 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
136 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
137 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
138 WME_AC_VO)
139
140 #define ATH_AGGR_DELIM_SZ 4
141 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
142 /* number of delimiters for encryption padding */
143 #define ATH_AGGR_ENCRYPTDELIM 10
144 /* minimum h/w qdepth to be sustained to maximize aggregation */
145 #define ATH_AGGR_MIN_QDEPTH 2
146 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
147
148 #define IEEE80211_SEQ_SEQ_SHIFT 4
149 #define IEEE80211_SEQ_MAX 4096
150 #define IEEE80211_WEP_IVLEN 3
151 #define IEEE80211_WEP_KIDLEN 1
152 #define IEEE80211_WEP_CRCLEN 4
153 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
154 (IEEE80211_WEP_IVLEN + \
155 IEEE80211_WEP_KIDLEN + \
156 IEEE80211_WEP_CRCLEN))
157
158 /* return whether a bit at index _n in bitmap _bm is set
159 * _sz is the size of the bitmap */
160 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
161 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
162
163 /* return block-ack bitmap index given sequence and starting sequence */
164 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
165
166 /* returns delimiter padding required given the packet length */
167 #define ATH_AGGR_GET_NDELIM(_len) \
168 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
169 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
170
171 #define BAW_WITHIN(_start, _bawsz, _seqno) \
172 ((((_seqno) - (_start)) & 4095) < (_bawsz))
173
174 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
175
176 #define ATH_TX_COMPLETE_POLL_INT 1000
177
178 enum ATH_AGGR_STATUS {
179 ATH_AGGR_DONE,
180 ATH_AGGR_BAW_CLOSED,
181 ATH_AGGR_LIMITED,
182 };
183
184 #define ATH_TXFIFO_DEPTH 8
185 struct ath_txq {
186 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
187 u32 axq_qnum; /* ath9k hardware queue number */
188 u32 *axq_link;
189 struct list_head axq_q;
190 spinlock_t axq_lock;
191 u32 axq_depth;
192 u32 axq_ampdu_depth;
193 bool stopped;
194 bool axq_tx_inprogress;
195 struct list_head axq_acq;
196 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
197 struct list_head txq_fifo_pending;
198 u8 txq_headidx;
199 u8 txq_tailidx;
200 int pending_frames;
201 };
202
203 struct ath_atx_ac {
204 struct ath_txq *txq;
205 int sched;
206 struct list_head list;
207 struct list_head tid_q;
208 };
209
210 struct ath_frame_info {
211 int framelen;
212 u32 keyix;
213 enum ath9k_key_type keytype;
214 u8 retries;
215 u16 seqno;
216 };
217
218 struct ath_buf_state {
219 u8 bf_type;
220 u8 bfs_paprd;
221 enum ath9k_internal_frame_type bfs_ftype;
222 };
223
224 struct ath_buf {
225 struct list_head list;
226 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
227 an aggregate) */
228 struct ath_buf *bf_next; /* next subframe in the aggregate */
229 struct sk_buff *bf_mpdu; /* enclosing frame structure */
230 void *bf_desc; /* virtual addr of desc */
231 dma_addr_t bf_daddr; /* physical addr of desc */
232 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
233 bool bf_stale;
234 u16 bf_flags;
235 struct ath_buf_state bf_state;
236 struct ath_wiphy *aphy;
237 };
238
239 struct ath_atx_tid {
240 struct list_head list;
241 struct list_head buf_q;
242 struct ath_node *an;
243 struct ath_atx_ac *ac;
244 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
245 u16 seq_start;
246 u16 seq_next;
247 u16 baw_size;
248 int tidno;
249 int baw_head; /* first un-acked tx buffer */
250 int baw_tail; /* next unused tx buffer slot */
251 int sched;
252 int paused;
253 u8 state;
254 };
255
256 struct ath_node {
257 #ifdef CONFIG_ATH9K_DEBUGFS
258 struct list_head list; /* for sc->nodes */
259 struct ieee80211_sta *sta; /* station struct we're part of */
260 #endif
261 struct ath_atx_tid tid[WME_NUM_TID];
262 struct ath_atx_ac ac[WME_NUM_AC];
263 u16 maxampdu;
264 u8 mpdudensity;
265 };
266
267 #define AGGR_CLEANUP BIT(1)
268 #define AGGR_ADDBA_COMPLETE BIT(2)
269 #define AGGR_ADDBA_PROGRESS BIT(3)
270
271 struct ath_tx_control {
272 struct ath_txq *txq;
273 struct ath_node *an;
274 int if_id;
275 enum ath9k_internal_frame_type frame_type;
276 u8 paprd;
277 };
278
279 #define ATH_TX_ERROR 0x01
280 #define ATH_TX_XRETRY 0x02
281 #define ATH_TX_BAR 0x04
282
283 /**
284 * @txq_map: Index is mac80211 queue number. This is
285 * not necessarily the same as the hardware queue number
286 * (axq_qnum).
287 */
288 struct ath_tx {
289 u16 seq_no;
290 u32 txqsetup;
291 spinlock_t txbuflock;
292 struct list_head txbuf;
293 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
294 struct ath_descdma txdma;
295 struct ath_txq *txq_map[WME_NUM_AC];
296 };
297
298 struct ath_rx_edma {
299 struct sk_buff_head rx_fifo;
300 struct sk_buff_head rx_buffers;
301 u32 rx_fifo_hwsize;
302 };
303
304 struct ath_rx {
305 u8 defant;
306 u8 rxotherant;
307 u32 *rxlink;
308 unsigned int rxfilter;
309 spinlock_t rxbuflock;
310 struct list_head rxbuf;
311 struct ath_descdma rxdma;
312 struct ath_buf *rx_bufptr;
313 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
314 };
315
316 int ath_startrecv(struct ath_softc *sc);
317 bool ath_stoprecv(struct ath_softc *sc);
318 void ath_flushrecv(struct ath_softc *sc);
319 u32 ath_calcrxfilter(struct ath_softc *sc);
320 int ath_rx_init(struct ath_softc *sc, int nbufs);
321 void ath_rx_cleanup(struct ath_softc *sc);
322 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
323 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
324 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
325 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
326 void ath_draintxq(struct ath_softc *sc,
327 struct ath_txq *txq, bool retry_tx);
328 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
329 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
330 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
331 int ath_tx_init(struct ath_softc *sc, int nbufs);
332 void ath_tx_cleanup(struct ath_softc *sc);
333 int ath_txq_update(struct ath_softc *sc, int qnum,
334 struct ath9k_tx_queue_info *q);
335 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
336 struct ath_tx_control *txctl);
337 void ath_tx_tasklet(struct ath_softc *sc);
338 void ath_tx_edma_tasklet(struct ath_softc *sc);
339 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
340 u16 tid, u16 *ssn);
341 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
342 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
343
344 /********/
345 /* VIFs */
346 /********/
347
348 struct ath_vif {
349 int av_bslot;
350 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
351 enum nl80211_iftype av_opmode;
352 struct ath_buf *av_bcbuf;
353 u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
354 };
355
356 /*******************/
357 /* Beacon Handling */
358 /*******************/
359
360 /*
361 * Regardless of the number of beacons we stagger, (i.e. regardless of the
362 * number of BSSIDs) if a given beacon does not go out even after waiting this
363 * number of beacon intervals, the game's up.
364 */
365 #define BSTUCK_THRESH (9 * ATH_BCBUF)
366 #define ATH_BCBUF 4
367 #define ATH_DEFAULT_BINTVAL 100 /* TU */
368 #define ATH_DEFAULT_BMISS_LIMIT 10
369 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
370
371 struct ath_beacon_config {
372 u16 beacon_interval;
373 u16 listen_interval;
374 u16 dtim_period;
375 u16 bmiss_timeout;
376 u8 dtim_count;
377 };
378
379 struct ath_beacon {
380 enum {
381 OK, /* no change needed */
382 UPDATE, /* update pending */
383 COMMIT /* beacon sent, commit change */
384 } updateslot; /* slot time update fsm */
385
386 u32 beaconq;
387 u32 bmisscnt;
388 u32 ast_be_xmit;
389 u64 bc_tstamp;
390 struct ieee80211_vif *bslot[ATH_BCBUF];
391 struct ath_wiphy *bslot_aphy[ATH_BCBUF];
392 int slottime;
393 int slotupdate;
394 struct ath9k_tx_queue_info beacon_qi;
395 struct ath_descdma bdma;
396 struct ath_txq *cabq;
397 struct list_head bbuf;
398 };
399
400 void ath_beacon_tasklet(unsigned long data);
401 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
402 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
403 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
404 int ath_beaconq_config(struct ath_softc *sc);
405
406 /*******/
407 /* ANI */
408 /*******/
409
410 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
411 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
412 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
413 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
414 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
415 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
416 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
417
418 #define ATH_PAPRD_TIMEOUT 100 /* msecs */
419
420 void ath_hw_check(struct work_struct *work);
421 void ath_paprd_calibrate(struct work_struct *work);
422 void ath_ani_calibrate(unsigned long data);
423
424 /**********/
425 /* BTCOEX */
426 /**********/
427
428 struct ath_btcoex {
429 bool hw_timer_enabled;
430 spinlock_t btcoex_lock;
431 struct timer_list period_timer; /* Timer for BT period */
432 u32 bt_priority_cnt;
433 unsigned long bt_priority_time;
434 int bt_stomp_type; /* Types of BT stomping */
435 u32 btcoex_no_stomp; /* in usec */
436 u32 btcoex_period; /* in usec */
437 u32 btscan_no_stomp; /* in usec */
438 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
439 };
440
441 int ath_init_btcoex_timer(struct ath_softc *sc);
442 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
443 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
444
445 /********************/
446 /* LED Control */
447 /********************/
448
449 #define ATH_LED_PIN_DEF 1
450 #define ATH_LED_PIN_9287 8
451 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
452 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
453
454 enum ath_led_type {
455 ATH_LED_RADIO,
456 ATH_LED_ASSOC,
457 ATH_LED_TX,
458 ATH_LED_RX
459 };
460
461 struct ath_led {
462 struct ath_softc *sc;
463 struct led_classdev led_cdev;
464 enum ath_led_type led_type;
465 char name[32];
466 bool registered;
467 };
468
469 void ath_init_leds(struct ath_softc *sc);
470 void ath_deinit_leds(struct ath_softc *sc);
471
472 /* Antenna diversity/combining */
473 #define ATH_ANT_RX_CURRENT_SHIFT 4
474 #define ATH_ANT_RX_MAIN_SHIFT 2
475 #define ATH_ANT_RX_MASK 0x3
476
477 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
478 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
479 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
480 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
481 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
482 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
483 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
484
485 #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3
486 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
487 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
488 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
489 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
490
491 enum ath9k_ant_div_comb_lna_conf {
492 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
493 ATH_ANT_DIV_COMB_LNA2,
494 ATH_ANT_DIV_COMB_LNA1,
495 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
496 };
497
498 struct ath_ant_comb {
499 u16 count;
500 u16 total_pkt_count;
501 bool scan;
502 bool scan_not_start;
503 int main_total_rssi;
504 int alt_total_rssi;
505 int alt_recv_cnt;
506 int main_recv_cnt;
507 int rssi_lna1;
508 int rssi_lna2;
509 int rssi_add;
510 int rssi_sub;
511 int rssi_first;
512 int rssi_second;
513 int rssi_third;
514 bool alt_good;
515 int quick_scan_cnt;
516 int main_conf;
517 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
518 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
519 int first_bias;
520 int second_bias;
521 bool first_ratio;
522 bool second_ratio;
523 unsigned long scan_start_time;
524 };
525
526 /********************/
527 /* Main driver core */
528 /********************/
529
530 /*
531 * Default cache line size, in bytes.
532 * Used when PCI device not fully initialized by bootrom/BIOS
533 */
534 #define DEFAULT_CACHELINE 32
535 #define ATH_REGCLASSIDS_MAX 10
536 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
537 #define ATH_MAX_SW_RETRIES 10
538 #define ATH_CHAN_MAX 255
539 #define IEEE80211_WEP_NKID 4 /* number of key ids */
540
541 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
542 #define ATH_RATE_DUMMY_MARKER 0
543
544 #define SC_OP_INVALID BIT(0)
545 #define SC_OP_BEACONS BIT(1)
546 #define SC_OP_RXAGGR BIT(2)
547 #define SC_OP_TXAGGR BIT(3)
548 #define SC_OP_OFFCHANNEL BIT(4)
549 #define SC_OP_PREAMBLE_SHORT BIT(5)
550 #define SC_OP_PROTECT_ENABLE BIT(6)
551 #define SC_OP_RXFLUSH BIT(7)
552 #define SC_OP_LED_ASSOCIATED BIT(8)
553 #define SC_OP_LED_ON BIT(9)
554 #define SC_OP_TSF_RESET BIT(11)
555 #define SC_OP_BT_PRIORITY_DETECTED BIT(12)
556 #define SC_OP_BT_SCAN BIT(13)
557 #define SC_OP_ANI_RUN BIT(14)
558 #define SC_OP_ENABLE_APM BIT(15)
559
560 /* Powersave flags */
561 #define PS_WAIT_FOR_BEACON BIT(0)
562 #define PS_WAIT_FOR_CAB BIT(1)
563 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
564 #define PS_WAIT_FOR_TX_ACK BIT(3)
565 #define PS_BEACON_SYNC BIT(4)
566
567 struct ath_wiphy;
568 struct ath_rate_table;
569
570 struct ath9k_vif_iter_data {
571 const u8 *hw_macaddr; /* phy's hardware address, set
572 * before starting iteration for
573 * valid bssid mask.
574 */
575 u8 mask[ETH_ALEN]; /* bssid mask */
576 int naps; /* number of AP vifs */
577 int nmeshes; /* number of mesh vifs */
578 int nstations; /* number of station vifs */
579 int nwds; /* number of nwd vifs */
580 int nadhocs; /* number of adhoc vifs */
581 int nothers; /* number of vifs not specified above. */
582 };
583
584 struct ath_softc {
585 struct ieee80211_hw *hw;
586 struct device *dev;
587
588 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
589 struct ath_wiphy *pri_wiphy;
590 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
591 * have NULL entries */
592 int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
593 int chan_idx;
594 int chan_is_ht;
595 struct ath_wiphy *next_wiphy;
596 struct work_struct chan_work;
597 int wiphy_select_failures;
598 unsigned long wiphy_select_first_fail;
599 struct delayed_work wiphy_work;
600 unsigned long wiphy_scheduler_int;
601 int wiphy_scheduler_index;
602 struct survey_info *cur_survey;
603 struct survey_info survey[ATH9K_NUM_CHANNELS];
604
605 struct tasklet_struct intr_tq;
606 struct tasklet_struct bcon_tasklet;
607 struct ath_hw *sc_ah;
608 void __iomem *mem;
609 int irq;
610 spinlock_t sc_serial_rw;
611 spinlock_t sc_pm_lock;
612 spinlock_t sc_pcu_lock;
613 struct mutex mutex;
614 struct work_struct paprd_work;
615 struct work_struct hw_check_work;
616 struct completion paprd_complete;
617 bool paprd_pending;
618
619 u32 intrstatus;
620 u32 sc_flags; /* SC_OP_* */
621 u16 ps_flags; /* PS_* */
622 u16 curtxpow;
623 bool ps_enabled;
624 bool ps_idle;
625 short nbcnvifs;
626 short nvifs;
627 unsigned long ps_usecount;
628
629 struct ath_config config;
630 struct ath_rx rx;
631 struct ath_tx tx;
632 struct ath_beacon beacon;
633 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
634
635 struct ath_led radio_led;
636 struct ath_led assoc_led;
637 struct ath_led tx_led;
638 struct ath_led rx_led;
639 struct delayed_work ath_led_blink_work;
640 int led_on_duration;
641 int led_off_duration;
642 int led_on_cnt;
643 int led_off_cnt;
644
645 int beacon_interval;
646
647 #ifdef CONFIG_ATH9K_DEBUGFS
648 struct ath9k_debug debug;
649 spinlock_t nodes_lock;
650 struct list_head nodes; /* basically, stations */
651 unsigned int tx_complete_poll_work_seen;
652 #endif
653 struct ath_beacon_config cur_beacon_conf;
654 struct delayed_work tx_complete_work;
655 struct ath_btcoex btcoex;
656
657 struct ath_descdma txsdma;
658
659 struct ath_ant_comb ant_comb;
660
661 struct pm_qos_request_list pm_qos_req;
662 };
663
664 struct ath_wiphy {
665 struct ath_softc *sc; /* shared for all virtual wiphys */
666 struct ieee80211_hw *hw;
667 struct ath9k_hw_cal_data caldata;
668 enum ath_wiphy_state {
669 ATH_WIPHY_INACTIVE,
670 ATH_WIPHY_ACTIVE,
671 ATH_WIPHY_PAUSING,
672 ATH_WIPHY_PAUSED,
673 ATH_WIPHY_SCAN,
674 } state;
675 bool idle;
676 int chan_idx;
677 int chan_is_ht;
678 int last_rssi;
679 };
680
681 void ath9k_tasklet(unsigned long data);
682 int ath_reset(struct ath_softc *sc, bool retry_tx);
683 int ath_cabq_update(struct ath_softc *);
684
685 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
686 {
687 common->bus_ops->read_cachesize(common, csz);
688 }
689
690 extern struct ieee80211_ops ath9k_ops;
691 extern int ath9k_modparam_nohwcrypt;
692 extern int led_blink;
693 extern int ath9k_pm_qos_value;
694 extern bool is_ath9k_unloaded;
695
696 irqreturn_t ath_isr(int irq, void *dev);
697 void ath9k_init_crypto(struct ath_softc *sc);
698 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
699 const struct ath_bus_ops *bus_ops);
700 void ath9k_deinit_device(struct ath_softc *sc);
701 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
702 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
703 struct ath9k_channel *ichan);
704 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
705 struct ath9k_channel *hchan);
706
707 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
708 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
709 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
710 bool ath9k_uses_beacons(int type);
711
712 #ifdef CONFIG_PCI
713 int ath_pci_init(void);
714 void ath_pci_exit(void);
715 #else
716 static inline int ath_pci_init(void) { return 0; };
717 static inline void ath_pci_exit(void) {};
718 #endif
719
720 #ifdef CONFIG_ATHEROS_AR71XX
721 int ath_ahb_init(void);
722 void ath_ahb_exit(void);
723 #else
724 static inline int ath_ahb_init(void) { return 0; };
725 static inline void ath_ahb_exit(void) {};
726 #endif
727
728 void ath9k_ps_wakeup(struct ath_softc *sc);
729 void ath9k_ps_restore(struct ath_softc *sc);
730
731 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
732
733 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
734 int ath9k_wiphy_add(struct ath_softc *sc);
735 int ath9k_wiphy_del(struct ath_wiphy *aphy);
736 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype);
737 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
738 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
739 int ath9k_wiphy_select(struct ath_wiphy *aphy);
740 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
741 void ath9k_wiphy_chan_work(struct work_struct *work);
742 bool ath9k_wiphy_started(struct ath_softc *sc);
743 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
744 struct ath_wiphy *selected);
745 bool ath9k_wiphy_scanning(struct ath_softc *sc);
746 void ath9k_wiphy_work(struct work_struct *work);
747 bool ath9k_all_wiphys_idle(struct ath_softc *sc);
748 void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
749
750 void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
751 bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
752
753 void ath_start_rfkill_poll(struct ath_softc *sc);
754 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
755 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
756 struct ieee80211_vif *vif,
757 struct ath9k_vif_iter_data *iter_data);
758
759
760 #endif /* ATH9K_H */
WandBoard kernel