drivers/char/rocket.c

   1 /*
   2  * RocketPort device driver for Linux
   3  *
   4  * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
   5  *
   6  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of the
  11  * License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Kernel Synchronization:
  25  *
  26  * This driver has 2 kernel control paths - exception handlers (calls into the driver
  27  * from user mode) and the timer bottom half (tasklet).  This is a polled driver, interrupts
  28  * are not used.
  29  *
  30  * Critical data:
  31  * -  rp_table[], accessed through passed "info" pointers, is a global (static) array of
  32  *    serial port state information and the xmit_buf circular buffer.  Protected by
  33  *    a per port spinlock.
  34  * -  xmit_flags[], an array of ints indexed by line (port) number, indicating that there
  35  *    is data to be transmitted.  Protected by atomic bit operations.
  36  * -  rp_num_ports, int indicating number of open ports, protected by atomic operations.
  37  *
  38  * rp_write() and rp_write_char() functions use a per port semaphore to protect against
  39  * simultaneous access to the same port by more than one process.
  40  */
  41
  42 /****** Defines ******/
  43 #define ROCKET_PARANOIA_CHECK
  44 #define ROCKET_DISABLE_SIMUSAGE
  45
  46 #undef ROCKET_SOFT_FLOW
  47 #undef ROCKET_DEBUG_OPEN
  48 #undef ROCKET_DEBUG_INTR
  49 #undef ROCKET_DEBUG_WRITE
  50 #undef ROCKET_DEBUG_FLOW
  51 #undef ROCKET_DEBUG_THROTTLE
  52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
  53 #undef ROCKET_DEBUG_RECEIVE
  54 #undef ROCKET_DEBUG_HANGUP
  55 #undef REV_PCI_ORDER
  56 #undef ROCKET_DEBUG_IO
  57
  58 #define POLL_PERIOD HZ/100      /*  Polling period .01 seconds (10ms) */
  59
  60 /****** Kernel includes ******/
  61
  62 #include <linux/module.h>
  63 #include <linux/errno.h>
  64 #include <linux/major.h>
  65 #include <linux/kernel.h>
  66 #include <linux/signal.h>
  67 #include <linux/slab.h>
  68 #include <linux/mm.h>
  69 #include <linux/sched.h>
  70 #include <linux/timer.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/tty.h>
  73 #include <linux/tty_driver.h>
  74 #include <linux/tty_flip.h>
  75 #include <linux/serial.h>
  76 #include <linux/string.h>
  77 #include <linux/fcntl.h>
  78 #include <linux/ptrace.h>
  79 #include <linux/mutex.h>
  80 #include <linux/ioport.h>
  81 #include <linux/delay.h>
  82 #include <linux/completion.h>
  83 #include <linux/wait.h>
  84 #include <linux/pci.h>
  85 #include <linux/uaccess.h>
  86 #include <asm/atomic.h>
  87 #include <asm/unaligned.h>
  88 #include <linux/bitops.h>
  89 #include <linux/spinlock.h>
  90 #include <linux/init.h>
  91
  92 /****** RocketPort includes ******/
  93
  94 #include "rocket_int.h"
  95 #include "rocket.h"
  96
  97 #define ROCKET_VERSION "2.09"
  98 #define ROCKET_DATE "12-June-2003"
  99
 100 /****** RocketPort Local Variables ******/
 101
 102 static void rp_do_poll(unsigned long dummy);
 103
 104 static struct tty_driver *rocket_driver;
 105
 106 static struct rocket_version driver_version = {
 107         ROCKET_VERSION, ROCKET_DATE
 108 };
 109
 110 static struct r_port *rp_table[MAX_RP_PORTS];          /*  The main repository of serial port state information. */
 111 static unsigned int xmit_flags[NUM_BOARDS];            /*  Bit significant, indicates port had data to transmit. */
 112                                                        /*  eg.  Bit 0 indicates port 0 has xmit data, ...        */
 113 static atomic_t rp_num_ports_open;                     /*  Number of serial ports open                           */
 114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
 115
 116 static unsigned long board1;                           /* ISA addresses, retrieved from rocketport.conf          */
 117 static unsigned long board2;
 118 static unsigned long board3;
 119 static unsigned long board4;
 120 static unsigned long controller;
 121 static int support_low_speed;
 122 static unsigned long modem1;
 123 static unsigned long modem2;
 124 static unsigned long modem3;
 125 static unsigned long modem4;
 126 static unsigned long pc104_1[8];
 127 static unsigned long pc104_2[8];
 128 static unsigned long pc104_3[8];
 129 static unsigned long pc104_4[8];
 130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
 131
 132 static int rp_baud_base[NUM_BOARDS];                   /*  Board config info (Someday make a per-board structure)  */
 133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
 134 static int rcktpt_type[NUM_BOARDS];
 135 static int is_PCI[NUM_BOARDS];
 136 static rocketModel_t rocketModel[NUM_BOARDS];
 137 static int max_board;
 138 static const struct tty_port_operations rocket_port_ops;
 139
 140 /*
 141  * The following arrays define the interrupt bits corresponding to each AIOP.
 142  * These bits are different between the ISA and regular PCI boards and the
 143  * Universal PCI boards.
 144  */
 145
 146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
 147         AIOP_INTR_BIT_0,
 148         AIOP_INTR_BIT_1,
 149         AIOP_INTR_BIT_2,
 150         AIOP_INTR_BIT_3
 151 };
 152
 153 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
 154         UPCI_AIOP_INTR_BIT_0,
 155         UPCI_AIOP_INTR_BIT_1,
 156         UPCI_AIOP_INTR_BIT_2,
 157         UPCI_AIOP_INTR_BIT_3
 158 };
 159
 160 static Byte_t RData[RDATASIZE] = {
 161         0x00, 0x09, 0xf6, 0x82,
 162         0x02, 0x09, 0x86, 0xfb,
 163         0x04, 0x09, 0x00, 0x0a,
 164         0x06, 0x09, 0x01, 0x0a,
 165         0x08, 0x09, 0x8a, 0x13,
 166         0x0a, 0x09, 0xc5, 0x11,
 167         0x0c, 0x09, 0x86, 0x85,
 168         0x0e, 0x09, 0x20, 0x0a,
 169         0x10, 0x09, 0x21, 0x0a,
 170         0x12, 0x09, 0x41, 0xff,
 171         0x14, 0x09, 0x82, 0x00,
 172         0x16, 0x09, 0x82, 0x7b,
 173         0x18, 0x09, 0x8a, 0x7d,
 174         0x1a, 0x09, 0x88, 0x81,
 175         0x1c, 0x09, 0x86, 0x7a,
 176         0x1e, 0x09, 0x84, 0x81,
 177         0x20, 0x09, 0x82, 0x7c,
 178         0x22, 0x09, 0x0a, 0x0a
 179 };
 180
 181 static Byte_t RRegData[RREGDATASIZE] = {
 182         0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
 183         0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
 184         0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
 185         0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
 186         0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
 187         0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
 188         0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
 189         0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
 190         0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
 191         0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
 192         0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
 193         0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
 194         0x22, 0x09, 0x0a, 0x0a  /* 30: Rx FIFO Enable */
 195 };
 196
 197 static CONTROLLER_T sController[CTL_SIZE] = {
 198         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 199          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 200         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 201          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 202         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 203          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 204         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 205          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
 206 };
 207
 208 static Byte_t sBitMapClrTbl[8] = {
 209         0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
 210 };
 211
 212 static Byte_t sBitMapSetTbl[8] = {
 213         0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
 214 };
 215
 216 static int sClockPrescale = 0x14;
 217
 218 /*
 219  *  Line number is the ttySIx number (x), the Minor number.  We
 220  *  assign them sequentially, starting at zero.  The following
 221  *  array keeps track of the line number assigned to a given board/aiop/channel.
 222  */
 223 static unsigned char lineNumbers[MAX_RP_PORTS];
 224 static unsigned long nextLineNumber;
 225
 226 /*****  RocketPort Static Prototypes   *********/
 227 static int __init init_ISA(int i);
 228 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
 229 static void rp_flush_buffer(struct tty_struct *tty);
 230 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
 231 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
 232 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
 233 static void rp_start(struct tty_struct *tty);
 234 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
 235                      int ChanNum);
 236 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
 237 static void sFlushRxFIFO(CHANNEL_T * ChP);
 238 static void sFlushTxFIFO(CHANNEL_T * ChP);
 239 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
 240 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
 241 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
 242 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
 243 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
 244 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
 245                               ByteIO_t * AiopIOList, int AiopIOListSize,
 246                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
 247                               int PeriodicOnly, int altChanRingIndicator,
 248                               int UPCIRingInd);
 249 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
 250                            ByteIO_t * AiopIOList, int AiopIOListSize,
 251                            int IRQNum, Byte_t Frequency, int PeriodicOnly);
 252 static int sReadAiopID(ByteIO_t io);
 253 static int sReadAiopNumChan(WordIO_t io);
 254
 255 MODULE_AUTHOR("Theodore Ts'o");
 256 MODULE_DESCRIPTION("Comtrol RocketPort driver");
 257 module_param(board1, ulong, 0);
 258 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
 259 module_param(board2, ulong, 0);
 260 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
 261 module_param(board3, ulong, 0);
 262 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
 263 module_param(board4, ulong, 0);
 264 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
 265 module_param(controller, ulong, 0);
 266 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
 267 module_param(support_low_speed, bool, 0);
 268 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
 269 module_param(modem1, ulong, 0);
 270 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
 271 module_param(modem2, ulong, 0);
 272 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
 273 module_param(modem3, ulong, 0);
 274 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
 275 module_param(modem4, ulong, 0);
 276 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
 277 module_param_array(pc104_1, ulong, NULL, 0);
 278 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
 279 module_param_array(pc104_2, ulong, NULL, 0);
 280 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
 281 module_param_array(pc104_3, ulong, NULL, 0);
 282 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
 283 module_param_array(pc104_4, ulong, NULL, 0);
 284 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
 285
 286 static int rp_init(void);
 287 static void rp_cleanup_module(void);
 288
 289 module_init(rp_init);
 290 module_exit(rp_cleanup_module);
 291
 292
 293 MODULE_LICENSE("Dual BSD/GPL");
 294
 295 /*************************************************************************/
 296 /*                     Module code starts here                           */
 297
 298 static inline int rocket_paranoia_check(struct r_port *info,
 299                                         const char *routine)
 300 {
 301 #ifdef ROCKET_PARANOIA_CHECK
 302         if (!info)
 303                 return 1;
 304         if (info->magic != RPORT_MAGIC) {
 305                 printk(KERN_WARNING "Warning: bad magic number for rocketport "
 306                                 "struct in %s\n", routine);
 307                 return 1;
 308         }
 309 #endif
 310         return 0;
 311 }
 312
 313
 314 /*  Serial port receive data function.  Called (from timer poll) when an AIOPIC signals
 315  *  that receive data is present on a serial port.  Pulls data from FIFO, moves it into the
 316  *  tty layer.
 317  */
 318 static void rp_do_receive(struct r_port *info,
 319                           struct tty_struct *tty,
 320                           CHANNEL_t * cp, unsigned int ChanStatus)
 321 {
 322         unsigned int CharNStat;
 323         int ToRecv, wRecv, space;
 324         unsigned char *cbuf;
 325
 326         ToRecv = sGetRxCnt(cp);
 327 #ifdef ROCKET_DEBUG_INTR
 328         printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
 329 #endif
 330         if (ToRecv == 0)
 331                 return;
 332
 333         /*
 334          * if status indicates there are errored characters in the
 335          * FIFO, then enter status mode (a word in FIFO holds
 336          * character and status).
 337          */
 338         if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
 339                 if (!(ChanStatus & STATMODE)) {
 340 #ifdef ROCKET_DEBUG_RECEIVE
 341                         printk(KERN_INFO "Entering STATMODE...\n");
 342 #endif
 343                         ChanStatus |= STATMODE;
 344                         sEnRxStatusMode(cp);
 345                 }
 346         }
 347
 348         /*
 349          * if we previously entered status mode, then read down the
 350          * FIFO one word at a time, pulling apart the character and
 351          * the status.  Update error counters depending on status
 352          */
 353         if (ChanStatus & STATMODE) {
 354 #ifdef ROCKET_DEBUG_RECEIVE
 355                 printk(KERN_INFO "Ignore %x, read %x...\n",
 356                         info->ignore_status_mask, info->read_status_mask);
 357 #endif
 358                 while (ToRecv) {
 359                         char flag;
 360
 361                         CharNStat = sInW(sGetTxRxDataIO(cp));
 362 #ifdef ROCKET_DEBUG_RECEIVE
 363                         printk(KERN_INFO "%x...\n", CharNStat);
 364 #endif
 365                         if (CharNStat & STMBREAKH)
 366                                 CharNStat &= ~(STMFRAMEH | STMPARITYH);
 367                         if (CharNStat & info->ignore_status_mask) {
 368                                 ToRecv--;
 369                                 continue;
 370                         }
 371                         CharNStat &= info->read_status_mask;
 372                         if (CharNStat & STMBREAKH)
 373                                 flag = TTY_BREAK;
 374                         else if (CharNStat & STMPARITYH)
 375                                 flag = TTY_PARITY;
 376                         else if (CharNStat & STMFRAMEH)
 377                                 flag = TTY_FRAME;
 378                         else if (CharNStat & STMRCVROVRH)
 379                                 flag = TTY_OVERRUN;
 380                         else
 381                                 flag = TTY_NORMAL;
 382                         tty_insert_flip_char(tty, CharNStat & 0xff, flag);
 383                         ToRecv--;
 384                 }
 385
 386                 /*
 387                  * after we've emptied the FIFO in status mode, turn
 388                  * status mode back off
 389                  */
 390                 if (sGetRxCnt(cp) == 0) {
 391 #ifdef ROCKET_DEBUG_RECEIVE
 392                         printk(KERN_INFO "Status mode off.\n");
 393 #endif
 394                         sDisRxStatusMode(cp);
 395                 }
 396         } else {
 397                 /*
 398                  * we aren't in status mode, so read down the FIFO two
 399                  * characters at time by doing repeated word IO
 400                  * transfer.
 401                  */
 402                 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
 403                 if (space < ToRecv) {
 404 #ifdef ROCKET_DEBUG_RECEIVE
 405                         printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
 406 #endif
 407                         if (space <= 0)
 408                                 return;
 409                         ToRecv = space;
 410                 }
 411                 wRecv = ToRecv >> 1;
 412                 if (wRecv)
 413                         sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
 414                 if (ToRecv & 1)
 415                         cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
 416         }
 417         /*  Push the data up to the tty layer */
 418         tty_flip_buffer_push(tty);
 419 }
 420
 421 /*
 422  *  Serial port transmit data function.  Called from the timer polling loop as a
 423  *  result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
 424  *  to be sent out the serial port.  Data is buffered in rp_table[line].xmit_buf, it is
 425  *  moved to the port's xmit FIFO.  *info is critical data, protected by spinlocks.
 426  */
 427 static void rp_do_transmit(struct r_port *info)
 428 {
 429         int c;
 430         CHANNEL_t *cp = &info->channel;
 431         struct tty_struct *tty;
 432         unsigned long flags;
 433
 434 #ifdef ROCKET_DEBUG_INTR
 435         printk(KERN_DEBUG "%s\n", __func__);
 436 #endif
 437         if (!info)
 438                 return;
 439         tty = tty_port_tty_get(&info->port);
 440
 441         if (tty == NULL) {
 442                 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
 443                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 444                 return;
 445         }
 446
 447         spin_lock_irqsave(&info->slock, flags);
 448         info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
 449
 450         /*  Loop sending data to FIFO until done or FIFO full */
 451         while (1) {
 452                 if (tty->stopped || tty->hw_stopped)
 453                         break;
 454                 c = min(info->xmit_fifo_room, info->xmit_cnt);
 455                 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
 456                 if (c <= 0 || info->xmit_fifo_room <= 0)
 457                         break;
 458                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
 459                 if (c & 1)
 460                         sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
 461                 info->xmit_tail += c;
 462                 info->xmit_tail &= XMIT_BUF_SIZE - 1;
 463                 info->xmit_cnt -= c;
 464                 info->xmit_fifo_room -= c;
 465 #ifdef ROCKET_DEBUG_INTR
 466                 printk(KERN_INFO "tx %d chars...\n", c);
 467 #endif
 468         }
 469
 470         if (info->xmit_cnt == 0)
 471                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 472
 473         if (info->xmit_cnt < WAKEUP_CHARS) {
 474                 tty_wakeup(tty);
 475 #ifdef ROCKETPORT_HAVE_POLL_WAIT
 476                 wake_up_interruptible(&tty->poll_wait);
 477 #endif
 478         }
 479
 480         spin_unlock_irqrestore(&info->slock, flags);
 481         tty_kref_put(tty);
 482
 483 #ifdef ROCKET_DEBUG_INTR
 484         printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
 485                info->xmit_tail, info->xmit_fifo_room);
 486 #endif
 487 }
 488
 489 /*
 490  *  Called when a serial port signals it has read data in it's RX FIFO.
 491  *  It checks what interrupts are pending and services them, including
 492  *  receiving serial data.
 493  */
 494 static void rp_handle_port(struct r_port *info)
 495 {
 496         CHANNEL_t *cp;
 497         struct tty_struct *tty;
 498         unsigned int IntMask, ChanStatus;
 499
 500         if (!info)
 501                 return;
 502
 503         if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
 504                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
 505                                 "info->flags & NOT_INIT\n");
 506                 return;
 507         }
 508         tty = tty_port_tty_get(&info->port);
 509         if (!tty) {
 510                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
 511                                 "tty==NULL\n");
 512                 return;
 513         }
 514         cp = &info->channel;
 515
 516         IntMask = sGetChanIntID(cp) & info->intmask;
 517 #ifdef ROCKET_DEBUG_INTR
 518         printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
 519 #endif
 520         ChanStatus = sGetChanStatus(cp);
 521         if (IntMask & RXF_TRIG) {       /* Rx FIFO trigger level */
 522                 rp_do_receive(info, tty, cp, ChanStatus);
 523         }
 524         if (IntMask & DELTA_CD) {       /* CD change  */
 525 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
 526                 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
 527                        (ChanStatus & CD_ACT) ? "on" : "off");
 528 #endif
 529                 if (!(ChanStatus & CD_ACT) && info->cd_status) {
 530 #ifdef ROCKET_DEBUG_HANGUP
 531                         printk(KERN_INFO "CD drop, calling hangup.\n");
 532 #endif
 533                         tty_hangup(tty);
 534                 }
 535                 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
 536                 wake_up_interruptible(&info->port.open_wait);
 537         }
 538 #ifdef ROCKET_DEBUG_INTR
 539         if (IntMask & DELTA_CTS) {      /* CTS change */
 540                 printk(KERN_INFO "CTS change...\n");
 541         }
 542         if (IntMask & DELTA_DSR) {      /* DSR change */
 543                 printk(KERN_INFO "DSR change...\n");
 544         }
 545 #endif
 546         tty_kref_put(tty);
 547 }
 548
 549 /*
 550  *  The top level polling routine.  Repeats every 1/100 HZ (10ms).
 551  */
 552 static void rp_do_poll(unsigned long dummy)
 553 {
 554         CONTROLLER_t *ctlp;
 555         int ctrl, aiop, ch, line;
 556         unsigned int xmitmask, i;
 557         unsigned int CtlMask;
 558         unsigned char AiopMask;
 559         Word_t bit;
 560
 561         /*  Walk through all the boards (ctrl's) */
 562         for (ctrl = 0; ctrl < max_board; ctrl++) {
 563                 if (rcktpt_io_addr[ctrl] <= 0)
 564                         continue;
 565
 566                 /*  Get a ptr to the board's control struct */
 567                 ctlp = sCtlNumToCtlPtr(ctrl);
 568
 569                 /*  Get the interrupt status from the board */
 570 #ifdef CONFIG_PCI
 571                 if (ctlp->BusType == isPCI)
 572                         CtlMask = sPCIGetControllerIntStatus(ctlp);
 573                 else
 574 #endif
 575                         CtlMask = sGetControllerIntStatus(ctlp);
 576
 577                 /*  Check if any AIOP read bits are set */
 578                 for (aiop = 0; CtlMask; aiop++) {
 579                         bit = ctlp->AiopIntrBits[aiop];
 580                         if (CtlMask & bit) {
 581                                 CtlMask &= ~bit;
 582                                 AiopMask = sGetAiopIntStatus(ctlp, aiop);
 583
 584                                 /*  Check if any port read bits are set */
 585                                 for (ch = 0; AiopMask;  AiopMask >>= 1, ch++) {
 586                                         if (AiopMask & 1) {
 587
 588                                                 /*  Get the line number (/dev/ttyRx number). */
 589                                                 /*  Read the data from the port. */
 590                                                 line = GetLineNumber(ctrl, aiop, ch);
 591                                                 rp_handle_port(rp_table[line]);
 592                                         }
 593                                 }
 594                         }
 595                 }
 596
 597                 xmitmask = xmit_flags[ctrl];
 598
 599                 /*
 600                  *  xmit_flags contains bit-significant flags, indicating there is data
 601                  *  to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
 602                  *  1, ... (32 total possible).  The variable i has the aiop and ch
 603                  *  numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
 604                  */
 605                 if (xmitmask) {
 606                         for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
 607                                 if (xmitmask & (1 << i)) {
 608                                         aiop = (i & 0x18) >> 3;
 609                                         ch = i & 0x07;
 610                                         line = GetLineNumber(ctrl, aiop, ch);
 611                                         rp_do_transmit(rp_table[line]);
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         /*
 618          * Reset the timer so we get called at the next clock tick (10ms).
 619          */
 620         if (atomic_read(&rp_num_ports_open))
 621                 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
 622 }
 623
 624 /*
 625  *  Initializes the r_port structure for a port, as well as enabling the port on
 626  *  the board.
 627  *  Inputs:  board, aiop, chan numbers
 628  */
 629 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
 630 {
 631         unsigned rocketMode;
 632         struct r_port *info;
 633         int line;
 634         CONTROLLER_T *ctlp;
 635
 636         /*  Get the next available line number */
 637         line = SetLineNumber(board, aiop, chan);
 638
 639         ctlp = sCtlNumToCtlPtr(board);
 640
 641         /*  Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
 642         info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
 643         if (!info) {
 644                 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
 645                                 line);
 646                 return;
 647         }
 648
 649         info->magic = RPORT_MAGIC;
 650         info->line = line;
 651         info->ctlp = ctlp;
 652         info->board = board;
 653         info->aiop = aiop;
 654         info->chan = chan;
 655         tty_port_init(&info->port);
 656         info->port.ops = &rocket_port_ops;
 657         init_completion(&info->close_wait);
 658         info->flags &= ~ROCKET_MODE_MASK;
 659         switch (pc104[board][line]) {
 660         case 422:
 661                 info->flags |= ROCKET_MODE_RS422;
 662                 break;
 663         case 485:
 664                 info->flags |= ROCKET_MODE_RS485;
 665                 break;
 666         case 232:
 667         default:
 668                 info->flags |= ROCKET_MODE_RS232;
 669                 break;
 670         }
 671
 672         info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
 673         if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
 674                 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
 675                                 board, aiop, chan);
 676                 kfree(info);
 677                 return;
 678         }
 679
 680         rocketMode = info->flags & ROCKET_MODE_MASK;
 681
 682         if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
 683                 sEnRTSToggle(&info->channel);
 684         else
 685                 sDisRTSToggle(&info->channel);
 686
 687         if (ctlp->boardType == ROCKET_TYPE_PC104) {
 688                 switch (rocketMode) {
 689                 case ROCKET_MODE_RS485:
 690                         sSetInterfaceMode(&info->channel, InterfaceModeRS485);
 691                         break;
 692                 case ROCKET_MODE_RS422:
 693                         sSetInterfaceMode(&info->channel, InterfaceModeRS422);
 694                         break;
 695                 case ROCKET_MODE_RS232:
 696                 default:
 697                         if (info->flags & ROCKET_RTS_TOGGLE)
 698                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
 699                         else
 700                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
 701                         break;
 702                 }
 703         }
 704         spin_lock_init(&info->slock);
 705         mutex_init(&info->write_mtx);
 706         rp_table[line] = info;
 707         tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
 708                         NULL);
 709 }
 710
 711 /*
 712  *  Configures a rocketport port according to its termio settings.  Called from
 713  *  user mode into the driver (exception handler).  *info CD manipulation is spinlock protected.
 714  */
 715 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
 716                              struct ktermios *old_termios)
 717 {
 718         unsigned cflag;
 719         unsigned long flags;
 720         unsigned rocketMode;
 721         int bits, baud, divisor;
 722         CHANNEL_t *cp;
 723         struct ktermios *t = tty->termios;
 724
 725         cp = &info->channel;
 726         cflag = t->c_cflag;
 727
 728         /* Byte size and parity */
 729         if ((cflag & CSIZE) == CS8) {
 730                 sSetData8(cp);
 731                 bits = 10;
 732         } else {
 733                 sSetData7(cp);
 734                 bits = 9;
 735         }
 736         if (cflag & CSTOPB) {
 737                 sSetStop2(cp);
 738                 bits++;
 739         } else {
 740                 sSetStop1(cp);
 741         }
 742
 743         if (cflag & PARENB) {
 744                 sEnParity(cp);
 745                 bits++;
 746                 if (cflag & PARODD) {
 747                         sSetOddParity(cp);
 748                 } else {
 749                         sSetEvenParity(cp);
 750                 }
 751         } else {
 752                 sDisParity(cp);
 753         }
 754
 755         /* baud rate */
 756         baud = tty_get_baud_rate(tty);
 757         if (!baud)
 758                 baud = 9600;
 759         divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
 760         if ((divisor >= 8192 || divisor < 0) && old_termios) {
 761                 baud = tty_termios_baud_rate(old_termios);
 762                 if (!baud)
 763                         baud = 9600;
 764                 divisor = (rp_baud_base[info->board] / baud) - 1;
 765         }
 766         if (divisor >= 8192 || divisor < 0) {
 767                 baud = 9600;
 768                 divisor = (rp_baud_base[info->board] / baud) - 1;
 769         }
 770         info->cps = baud / bits;
 771         sSetBaud(cp, divisor);
 772
 773         /* FIXME: Should really back compute a baud rate from the divisor */
 774         tty_encode_baud_rate(tty, baud, baud);
 775
 776         if (cflag & CRTSCTS) {
 777                 info->intmask |= DELTA_CTS;
 778                 sEnCTSFlowCtl(cp);
 779         } else {
 780                 info->intmask &= ~DELTA_CTS;
 781                 sDisCTSFlowCtl(cp);
 782         }
 783         if (cflag & CLOCAL) {
 784                 info->intmask &= ~DELTA_CD;
 785         } else {
 786                 spin_lock_irqsave(&info->slock, flags);
 787                 if (sGetChanStatus(cp) & CD_ACT)
 788                         info->cd_status = 1;
 789                 else
 790                         info->cd_status = 0;
 791                 info->intmask |= DELTA_CD;
 792                 spin_unlock_irqrestore(&info->slock, flags);
 793         }
 794
 795         /*
 796          * Handle software flow control in the board
 797          */
 798 #ifdef ROCKET_SOFT_FLOW
 799         if (I_IXON(tty)) {
 800                 sEnTxSoftFlowCtl(cp);
 801                 if (I_IXANY(tty)) {
 802                         sEnIXANY(cp);
 803                 } else {
 804                         sDisIXANY(cp);
 805                 }
 806                 sSetTxXONChar(cp, START_CHAR(tty));
 807                 sSetTxXOFFChar(cp, STOP_CHAR(tty));
 808         } else {
 809                 sDisTxSoftFlowCtl(cp);
 810                 sDisIXANY(cp);
 811                 sClrTxXOFF(cp);
 812         }
 813 #endif
 814
 815         /*
 816          * Set up ignore/read mask words
 817          */
 818         info->read_status_mask = STMRCVROVRH | 0xFF;
 819         if (I_INPCK(tty))
 820                 info->read_status_mask |= STMFRAMEH | STMPARITYH;
 821         if (I_BRKINT(tty) || I_PARMRK(tty))
 822                 info->read_status_mask |= STMBREAKH;
 823
 824         /*
 825          * Characters to ignore
 826          */
 827         info->ignore_status_mask = 0;
 828         if (I_IGNPAR(tty))
 829                 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
 830         if (I_IGNBRK(tty)) {
 831                 info->ignore_status_mask |= STMBREAKH;
 832                 /*
 833                  * If we're ignoring parity and break indicators,
 834                  * ignore overruns too.  (For real raw support).
 835                  */
 836                 if (I_IGNPAR(tty))
 837                         info->ignore_status_mask |= STMRCVROVRH;
 838         }
 839
 840         rocketMode = info->flags & ROCKET_MODE_MASK;
 841
 842         if ((info->flags & ROCKET_RTS_TOGGLE)
 843             || (rocketMode == ROCKET_MODE_RS485))
 844                 sEnRTSToggle(cp);
 845         else
 846                 sDisRTSToggle(cp);
 847
 848         sSetRTS(&info->channel);
 849
 850         if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
 851                 switch (rocketMode) {
 852                 case ROCKET_MODE_RS485:
 853                         sSetInterfaceMode(cp, InterfaceModeRS485);
 854                         break;
 855                 case ROCKET_MODE_RS422:
 856                         sSetInterfaceMode(cp, InterfaceModeRS422);
 857                         break;
 858                 case ROCKET_MODE_RS232:
 859                 default:
 860                         if (info->flags & ROCKET_RTS_TOGGLE)
 861                                 sSetInterfaceMode(cp, InterfaceModeRS232T);
 862                         else
 863                                 sSetInterfaceMode(cp, InterfaceModeRS232);
 864                         break;
 865                 }
 866         }
 867 }
 868
 869 static int carrier_raised(struct tty_port *port)
 870 {
 871         struct r_port *info = container_of(port, struct r_port, port);
 872         return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
 873 }
 874
 875 static void raise_dtr_rts(struct tty_port *port)
 876 {
 877         struct r_port *info = container_of(port, struct r_port, port);
 878         sSetDTR(&info->channel);
 879         sSetRTS(&info->channel);
 880 }
 881
 882 /*
 883  *  Exception handler that opens a serial port.  Creates xmit_buf storage, fills in
 884  *  port's r_port struct.  Initializes the port hardware.
 885  */
 886 static int rp_open(struct tty_struct *tty, struct file *filp)
 887 {
 888         struct r_port *info;
 889         struct tty_port *port;
 890         int line = 0, retval;
 891         CHANNEL_t *cp;
 892         unsigned long page;
 893
 894         line = tty->index;
 895         if (line < 0 || line >= MAX_RP_PORTS || ((info = rp_table[line]) == NULL))
 896                 return -ENXIO;
 897         port = &info->port;
 898
 899         page = __get_free_page(GFP_KERNEL);
 900         if (!page)
 901                 return -ENOMEM;
 902
 903         if (port->flags & ASYNC_CLOSING) {
 904                 retval = wait_for_completion_interruptible(&info->close_wait);
 905                 free_page(page);
 906                 if (retval)
 907                         return retval;
 908                 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 909         }
 910
 911         /*
 912          * We must not sleep from here until the port is marked fully in use.
 913          */
 914         if (info->xmit_buf)
 915                 free_page(page);
 916         else
 917                 info->xmit_buf = (unsigned char *) page;
 918
 919         tty->driver_data = info;
 920         tty_port_tty_set(port, tty);
 921
 922         if (port->count++ == 0) {
 923                 atomic_inc(&rp_num_ports_open);
 924
 925 #ifdef ROCKET_DEBUG_OPEN
 926                 printk(KERN_INFO "rocket mod++ = %d...\n",
 927                                 atomic_read(&rp_num_ports_open));
 928 #endif
 929         }
 930 #ifdef ROCKET_DEBUG_OPEN
 931         printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
 932 #endif
 933
 934         /*
 935          * Info->count is now 1; so it's safe to sleep now.
 936          */
 937         if (!test_bit(ASYNC_INITIALIZED, &port->flags)) {
 938                 cp = &info->channel;
 939                 sSetRxTrigger(cp, TRIG_1);
 940                 if (sGetChanStatus(cp) & CD_ACT)
 941                         info->cd_status = 1;
 942                 else
 943                         info->cd_status = 0;
 944                 sDisRxStatusMode(cp);
 945                 sFlushRxFIFO(cp);
 946                 sFlushTxFIFO(cp);
 947
 948                 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
 949                 sSetRxTrigger(cp, TRIG_1);
 950
 951                 sGetChanStatus(cp);
 952                 sDisRxStatusMode(cp);
 953                 sClrTxXOFF(cp);
 954
 955                 sDisCTSFlowCtl(cp);
 956                 sDisTxSoftFlowCtl(cp);
 957
 958                 sEnRxFIFO(cp);
 959                 sEnTransmit(cp);
 960
 961                 set_bit(ASYNC_INITIALIZED, &info->port.flags);
 962
 963                 /*
 964                  * Set up the tty->alt_speed kludge
 965                  */
 966                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
 967                         tty->alt_speed = 57600;
 968                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
 969                         tty->alt_speed = 115200;
 970                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
 971                         tty->alt_speed = 230400;
 972                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
 973                         tty->alt_speed = 460800;
 974
 975                 configure_r_port(tty, info, NULL);
 976                 if (tty->termios->c_cflag & CBAUD) {
 977                         sSetDTR(cp);
 978                         sSetRTS(cp);
 979                 }
 980         }
 981         /*  Starts (or resets) the maint polling loop */
 982         mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
 983
 984         retval = tty_port_block_til_ready(port, tty, filp);
 985         if (retval) {
 986 #ifdef ROCKET_DEBUG_OPEN
 987                 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
 988 #endif
 989                 return retval;
 990         }
 991         return 0;
 992 }
 993
 994 /*
 995  *  Exception handler that closes a serial port. info->port.count is considered critical.
 996  */
 997 static void rp_close(struct tty_struct *tty, struct file *filp)
 998 {
 999         struct r_port *info = tty->driver_data;
1000         struct tty_port *port = &info->port;
1001         int timeout;
1002         CHANNEL_t *cp;
1003
1004         if (rocket_paranoia_check(info, "rp_close"))
1005                 return;
1006
1007 #ifdef ROCKET_DEBUG_OPEN
1008         printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1009 #endif
1010
1011         if (tty_port_close_start(port, tty, filp) == 0)
1012                 return;
1013
1014         cp = &info->channel;
1015         /*
1016          * Before we drop DTR, make sure the UART transmitter
1017          * has completely drained; this is especially
1018          * important if there is a transmit FIFO!
1019          */
1020         timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1021         if (timeout == 0)
1022                 timeout = 1;
1023         rp_wait_until_sent(tty, timeout);
1024         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1025
1026         sDisTransmit(cp);
1027         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1028         sDisCTSFlowCtl(cp);
1029         sDisTxSoftFlowCtl(cp);
1030         sClrTxXOFF(cp);
1031         sFlushRxFIFO(cp);
1032         sFlushTxFIFO(cp);
1033         sClrRTS(cp);
1034         if (C_HUPCL(tty))
1035                 sClrDTR(cp);
1036
1037         rp_flush_buffer(tty);
1038
1039         tty_ldisc_flush(tty);
1040
1041         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1042
1043         /* We can't yet use tty_port_close_end as the buffer handling in this
1044            driver is a bit different to the usual */
1045
1046         if (port->blocked_open) {
1047                 if (port->close_delay) {
1048                         msleep_interruptible(jiffies_to_msecs(port->close_delay));
1049                 }
1050                 wake_up_interruptible(&port->open_wait);
1051         } else {
1052                 if (info->xmit_buf) {
1053                         free_page((unsigned long) info->xmit_buf);
1054                         info->xmit_buf = NULL;
1055                 }
1056         }
1057         info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1058         tty->closing = 0;
1059         tty_port_tty_set(port, NULL);
1060         wake_up_interruptible(&port->close_wait);
1061         complete_all(&info->close_wait);
1062         atomic_dec(&rp_num_ports_open);
1063
1064 #ifdef ROCKET_DEBUG_OPEN
1065         printk(KERN_INFO "rocket mod-- = %d...\n",
1066                         atomic_read(&rp_num_ports_open));
1067         printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1068 #endif
1069
1070 }
1071
1072 static void rp_set_termios(struct tty_struct *tty,
1073                            struct ktermios *old_termios)
1074 {
1075         struct r_port *info = tty->driver_data;
1076         CHANNEL_t *cp;
1077         unsigned cflag;
1078
1079         if (rocket_paranoia_check(info, "rp_set_termios"))
1080                 return;
1081
1082         cflag = tty->termios->c_cflag;
1083
1084         /*
1085          * This driver doesn't support CS5 or CS6
1086          */
1087         if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1088                 tty->termios->c_cflag =
1089                     ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1090         /* Or CMSPAR */
1091         tty->termios->c_cflag &= ~CMSPAR;
1092
1093         configure_r_port(tty, info, old_termios);
1094
1095         cp = &info->channel;
1096
1097         /* Handle transition to B0 status */
1098         if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1099                 sClrDTR(cp);
1100                 sClrRTS(cp);
1101         }
1102
1103         /* Handle transition away from B0 status */
1104         if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1105                 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1106                         sSetRTS(cp);
1107                 sSetDTR(cp);
1108         }
1109
1110         if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1111                 tty->hw_stopped = 0;
1112                 rp_start(tty);
1113         }
1114 }
1115
1116 static int rp_break(struct tty_struct *tty, int break_state)
1117 {
1118         struct r_port *info = tty->driver_data;
1119         unsigned long flags;
1120
1121         if (rocket_paranoia_check(info, "rp_break"))
1122                 return -EINVAL;
1123
1124         spin_lock_irqsave(&info->slock, flags);
1125         if (break_state == -1)
1126                 sSendBreak(&info->channel);
1127         else
1128                 sClrBreak(&info->channel);
1129         spin_unlock_irqrestore(&info->slock, flags);
1130         return 0;
1131 }
1132
1133 /*
1134  * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1135  * the UPCI boards was added, it was decided to make this a function because
1136  * the macro was getting too complicated. All cases except the first one
1137  * (UPCIRingInd) are taken directly from the original macro.
1138  */
1139 static int sGetChanRI(CHANNEL_T * ChP)
1140 {
1141         CONTROLLER_t *CtlP = ChP->CtlP;
1142         int ChanNum = ChP->ChanNum;
1143         int RingInd = 0;
1144
1145         if (CtlP->UPCIRingInd)
1146                 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1147         else if (CtlP->AltChanRingIndicator)
1148                 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1149         else if (CtlP->boardType == ROCKET_TYPE_PC104)
1150                 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1151
1152         return RingInd;
1153 }
1154
1155 /********************************************************************************************/
1156 /*  Here are the routines used by rp_ioctl.  These are all called from exception handlers.  */
1157
1158 /*
1159  *  Returns the state of the serial modem control lines.  These next 2 functions
1160  *  are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1161  */
1162 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1163 {
1164         struct r_port *info = tty->driver_data;
1165         unsigned int control, result, ChanStatus;
1166
1167         ChanStatus = sGetChanStatusLo(&info->channel);
1168         control = info->channel.TxControl[3];
1169         result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1170                 ((control & SET_DTR) ?  TIOCM_DTR : 0) |
1171                 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1172                 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1173                 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1174                 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1175
1176         return result;
1177 }
1178
1179 /*
1180  *  Sets the modem control lines
1181  */
1182 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1183                     unsigned int set, unsigned int clear)
1184 {
1185         struct r_port *info = tty->driver_data;
1186
1187         if (set & TIOCM_RTS)
1188                 info->channel.TxControl[3] |= SET_RTS;
1189         if (set & TIOCM_DTR)
1190                 info->channel.TxControl[3] |= SET_DTR;
1191         if (clear & TIOCM_RTS)
1192                 info->channel.TxControl[3] &= ~SET_RTS;
1193         if (clear & TIOCM_DTR)
1194                 info->channel.TxControl[3] &= ~SET_DTR;
1195
1196         out32(info->channel.IndexAddr, info->channel.TxControl);
1197         return 0;
1198 }
1199
1200 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1201 {
1202         struct rocket_config tmp;
1203
1204         if (!retinfo)
1205                 return -EFAULT;
1206         memset(&tmp, 0, sizeof (tmp));
1207         tmp.line = info->line;
1208         tmp.flags = info->flags;
1209         tmp.close_delay = info->port.close_delay;
1210         tmp.closing_wait = info->port.closing_wait;
1211         tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1212
1213         if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1214                 return -EFAULT;
1215         return 0;
1216 }
1217
1218 static int set_config(struct tty_struct *tty, struct r_port *info,
1219                                         struct rocket_config __user *new_info)
1220 {
1221         struct rocket_config new_serial;
1222
1223         if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1224                 return -EFAULT;
1225
1226         if (!capable(CAP_SYS_ADMIN))
1227         {
1228                 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1229                         return -EPERM;
1230                 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1231                 configure_r_port(tty, info, NULL);
1232                 return 0;
1233         }
1234
1235         info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1236         info->port.close_delay = new_serial.close_delay;
1237         info->port.closing_wait = new_serial.closing_wait;
1238
1239         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1240                 tty->alt_speed = 57600;
1241         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1242                 tty->alt_speed = 115200;
1243         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1244                 tty->alt_speed = 230400;
1245         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1246                 tty->alt_speed = 460800;
1247
1248         configure_r_port(tty, info, NULL);
1249         return 0;
1250 }
1251
1252 /*
1253  *  This function fills in a rocket_ports struct with information
1254  *  about what boards/ports are in the system.  This info is passed
1255  *  to user space.  See setrocket.c where the info is used to create
1256  *  the /dev/ttyRx ports.
1257  */
1258 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1259 {
1260         struct rocket_ports tmp;
1261         int board;
1262
1263         if (!retports)
1264                 return -EFAULT;
1265         memset(&tmp, 0, sizeof (tmp));
1266         tmp.tty_major = rocket_driver->major;
1267
1268         for (board = 0; board < 4; board++) {
1269                 tmp.rocketModel[board].model = rocketModel[board].model;
1270                 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1271                 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1272                 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1273                 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1274         }
1275         if (copy_to_user(retports, &tmp, sizeof (*retports)))
1276                 return -EFAULT;
1277         return 0;
1278 }
1279
1280 static int reset_rm2(struct r_port *info, void __user *arg)
1281 {
1282         int reset;
1283
1284         if (!capable(CAP_SYS_ADMIN))
1285                 return -EPERM;
1286
1287         if (copy_from_user(&reset, arg, sizeof (int)))
1288                 return -EFAULT;
1289         if (reset)
1290                 reset = 1;
1291
1292         if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1293             rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1294                 return -EINVAL;
1295
1296         if (info->ctlp->BusType == isISA)
1297                 sModemReset(info->ctlp, info->chan, reset);
1298         else
1299                 sPCIModemReset(info->ctlp, info->chan, reset);
1300
1301         return 0;
1302 }
1303
1304 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1305 {
1306         if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1307                 return -EFAULT;
1308         return 0;
1309 }
1310
1311 /*  IOCTL call handler into the driver */
1312 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1313                     unsigned int cmd, unsigned long arg)
1314 {
1315         struct r_port *info = tty->driver_data;
1316         void __user *argp = (void __user *)arg;
1317         int ret = 0;
1318
1319         if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1320                 return -ENXIO;
1321
1322         lock_kernel();
1323
1324         switch (cmd) {
1325         case RCKP_GET_STRUCT:
1326                 if (copy_to_user(argp, info, sizeof (struct r_port)))
1327                         ret = -EFAULT;
1328                 break;
1329         case RCKP_GET_CONFIG:
1330                 ret = get_config(info, argp);
1331                 break;
1332         case RCKP_SET_CONFIG:
1333                 ret = set_config(tty, info, argp);
1334                 break;
1335         case RCKP_GET_PORTS:
1336                 ret = get_ports(info, argp);
1337                 break;
1338         case RCKP_RESET_RM2:
1339                 ret = reset_rm2(info, argp);
1340                 break;
1341         case RCKP_GET_VERSION:
1342                 ret = get_version(info, argp);
1343                 break;
1344         default:
1345                 ret = -ENOIOCTLCMD;
1346         }
1347         unlock_kernel();
1348         return ret;
1349 }
1350
1351 static void rp_send_xchar(struct tty_struct *tty, char ch)
1352 {
1353         struct r_port *info = tty->driver_data;
1354         CHANNEL_t *cp;
1355
1356         if (rocket_paranoia_check(info, "rp_send_xchar"))
1357                 return;
1358
1359         cp = &info->channel;
1360         if (sGetTxCnt(cp))
1361                 sWriteTxPrioByte(cp, ch);
1362         else
1363                 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1364 }
1365
1366 static void rp_throttle(struct tty_struct *tty)
1367 {
1368         struct r_port *info = tty->driver_data;
1369         CHANNEL_t *cp;
1370
1371 #ifdef ROCKET_DEBUG_THROTTLE
1372         printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1373                tty->ldisc.chars_in_buffer(tty));
1374 #endif
1375
1376         if (rocket_paranoia_check(info, "rp_throttle"))
1377                 return;
1378
1379         cp = &info->channel;
1380         if (I_IXOFF(tty))
1381                 rp_send_xchar(tty, STOP_CHAR(tty));
1382
1383         sClrRTS(&info->channel);
1384 }
1385
1386 static void rp_unthrottle(struct tty_struct *tty)
1387 {
1388         struct r_port *info = tty->driver_data;
1389         CHANNEL_t *cp;
1390 #ifdef ROCKET_DEBUG_THROTTLE
1391         printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1392                tty->ldisc.chars_in_buffer(tty));
1393 #endif
1394
1395         if (rocket_paranoia_check(info, "rp_throttle"))
1396                 return;
1397
1398         cp = &info->channel;
1399         if (I_IXOFF(tty))
1400                 rp_send_xchar(tty, START_CHAR(tty));
1401
1402         sSetRTS(&info->channel);
1403 }
1404
1405 /*
1406  * ------------------------------------------------------------
1407  * rp_stop() and rp_start()
1408  *
1409  * This routines are called before setting or resetting tty->stopped.
1410  * They enable or disable transmitter interrupts, as necessary.
1411  * ------------------------------------------------------------
1412  */
1413 static void rp_stop(struct tty_struct *tty)
1414 {
1415         struct r_port *info = tty->driver_data;
1416
1417 #ifdef ROCKET_DEBUG_FLOW
1418         printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1419                info->xmit_cnt, info->xmit_fifo_room);
1420 #endif
1421
1422         if (rocket_paranoia_check(info, "rp_stop"))
1423                 return;
1424
1425         if (sGetTxCnt(&info->channel))
1426                 sDisTransmit(&info->channel);
1427 }
1428
1429 static void rp_start(struct tty_struct *tty)
1430 {
1431         struct r_port *info = tty->driver_data;
1432
1433 #ifdef ROCKET_DEBUG_FLOW
1434         printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1435                info->xmit_cnt, info->xmit_fifo_room);
1436 #endif
1437
1438         if (rocket_paranoia_check(info, "rp_stop"))
1439                 return;
1440
1441         sEnTransmit(&info->channel);
1442         set_bit((info->aiop * 8) + info->chan,
1443                 (void *) &xmit_flags[info->board]);
1444 }
1445
1446 /*
1447  * rp_wait_until_sent() --- wait until the transmitter is empty
1448  */
1449 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1450 {
1451         struct r_port *info = tty->driver_data;
1452         CHANNEL_t *cp;
1453         unsigned long orig_jiffies;
1454         int check_time, exit_time;
1455         int txcnt;
1456
1457         if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1458                 return;
1459
1460         cp = &info->channel;
1461
1462         orig_jiffies = jiffies;
1463 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1464         printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1465                jiffies);
1466         printk(KERN_INFO "cps=%d...\n", info->cps);
1467 #endif
1468         lock_kernel();
1469         while (1) {
1470                 txcnt = sGetTxCnt(cp);
1471                 if (!txcnt) {
1472                         if (sGetChanStatusLo(cp) & TXSHRMT)
1473                                 break;
1474                         check_time = (HZ / info->cps) / 5;
1475                 } else {
1476                         check_time = HZ * txcnt / info->cps;
1477                 }
1478                 if (timeout) {
1479                         exit_time = orig_jiffies + timeout - jiffies;
1480                         if (exit_time <= 0)
1481                                 break;
1482                         if (exit_time < check_time)
1483                                 check_time = exit_time;
1484                 }
1485                 if (check_time == 0)
1486                         check_time = 1;
1487 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1488                 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1489                                 jiffies, check_time);
1490 #endif
1491                 msleep_interruptible(jiffies_to_msecs(check_time));
1492                 if (signal_pending(current))
1493                         break;
1494         }
1495         __set_current_state(TASK_RUNNING);
1496         unlock_kernel();
1497 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1498         printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1499 #endif
1500 }
1501
1502 /*
1503  * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1504  */
1505 static void rp_hangup(struct tty_struct *tty)
1506 {
1507         CHANNEL_t *cp;
1508         struct r_port *info = tty->driver_data;
1509
1510         if (rocket_paranoia_check(info, "rp_hangup"))
1511                 return;
1512
1513 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1514         printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1515 #endif
1516         rp_flush_buffer(tty);
1517         if (info->port.flags & ASYNC_CLOSING)
1518                 return;
1519         if (info->port.count)
1520                 atomic_dec(&rp_num_ports_open);
1521         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1522
1523         tty_port_hangup(&info->port);
1524
1525         cp = &info->channel;
1526         sDisRxFIFO(cp);
1527         sDisTransmit(cp);
1528         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1529         sDisCTSFlowCtl(cp);
1530         sDisTxSoftFlowCtl(cp);
1531         sClrTxXOFF(cp);
1532         info->port.flags &= ~ASYNC_INITIALIZED;
1533
1534         wake_up_interruptible(&info->port.open_wait);
1535 }
1536
1537 /*
1538  *  Exception handler - write char routine.  The RocketPort driver uses a
1539  *  double-buffering strategy, with the twist that if the in-memory CPU
1540  *  buffer is empty, and there's space in the transmit FIFO, the
1541  *  writing routines will write directly to transmit FIFO.
1542  *  Write buffer and counters protected by spinlocks
1543  */
1544 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1545 {
1546         struct r_port *info = tty->driver_data;
1547         CHANNEL_t *cp;
1548         unsigned long flags;
1549
1550         if (rocket_paranoia_check(info, "rp_put_char"))
1551                 return 0;
1552
1553         /*
1554          * Grab the port write mutex, locking out other processes that try to
1555          * write to this port
1556          */
1557         mutex_lock(&info->write_mtx);
1558
1559 #ifdef ROCKET_DEBUG_WRITE
1560         printk(KERN_INFO "rp_put_char %c...\n", ch);
1561 #endif
1562
1563         spin_lock_irqsave(&info->slock, flags);
1564         cp = &info->channel;
1565
1566         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1567                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1568
1569         if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1570                 info->xmit_buf[info->xmit_head++] = ch;
1571                 info->xmit_head &= XMIT_BUF_SIZE - 1;
1572                 info->xmit_cnt++;
1573                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1574         } else {
1575                 sOutB(sGetTxRxDataIO(cp), ch);
1576                 info->xmit_fifo_room--;
1577         }
1578         spin_unlock_irqrestore(&info->slock, flags);
1579         mutex_unlock(&info->write_mtx);
1580         return 1;
1581 }
1582
1583 /*
1584  *  Exception handler - write routine, called when user app writes to the device.
1585  *  A per port write mutex is used to protect from another process writing to
1586  *  this port at the same time.  This other process could be running on the other CPU
1587  *  or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1588  *  Spinlocks protect the info xmit members.
1589  */
1590 static int rp_write(struct tty_struct *tty,
1591                     const unsigned char *buf, int count)
1592 {
1593         struct r_port *info = tty->driver_data;
1594         CHANNEL_t *cp;
1595         const unsigned char *b;
1596         int c, retval = 0;
1597         unsigned long flags;
1598
1599         if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1600                 return 0;
1601
1602         if (mutex_lock_interruptible(&info->write_mtx))
1603                 return -ERESTARTSYS;
1604
1605 #ifdef ROCKET_DEBUG_WRITE
1606         printk(KERN_INFO "rp_write %d chars...\n", count);
1607 #endif
1608         cp = &info->channel;
1609
1610         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1611                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1612
1613         /*
1614          *  If the write queue for the port is empty, and there is FIFO space, stuff bytes
1615          *  into FIFO.  Use the write queue for temp storage.
1616          */
1617         if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1618                 c = min(count, info->xmit_fifo_room);
1619                 b = buf;
1620
1621                 /*  Push data into FIFO, 2 bytes at a time */
1622                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1623
1624                 /*  If there is a byte remaining, write it */
1625                 if (c & 1)
1626                         sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1627
1628                 retval += c;
1629                 buf += c;
1630                 count -= c;
1631
1632                 spin_lock_irqsave(&info->slock, flags);
1633                 info->xmit_fifo_room -= c;
1634                 spin_unlock_irqrestore(&info->slock, flags);
1635         }
1636
1637         /* If count is zero, we wrote it all and are done */
1638         if (!count)
1639                 goto end;
1640
1641         /*  Write remaining data into the port's xmit_buf */
1642         while (1) {
1643                 /* Hung up ? */
1644                 if (!test_bit(ASYNC_NORMAL_ACTIVE, &info->port.flags))
1645                         goto end;
1646                 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1647                 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1648                 if (c <= 0)
1649                         break;
1650
1651                 b = buf;
1652                 memcpy(info->xmit_buf + info->xmit_head, b, c);
1653
1654                 spin_lock_irqsave(&info->slock, flags);
1655                 info->xmit_head =
1656                     (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1657                 info->xmit_cnt += c;
1658                 spin_unlock_irqrestore(&info->slock, flags);
1659
1660                 buf += c;
1661                 count -= c;
1662                 retval += c;
1663         }
1664
1665         if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1666                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1667
1668 end:
1669         if (info->xmit_cnt < WAKEUP_CHARS) {
1670                 tty_wakeup(tty);
1671 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1672                 wake_up_interruptible(&tty->poll_wait);
1673 #endif
1674         }
1675         mutex_unlock(&info->write_mtx);
1676         return retval;
1677 }
1678
1679 /*
1680  * Return the number of characters that can be sent.  We estimate
1681  * only using the in-memory transmit buffer only, and ignore the
1682  * potential space in the transmit FIFO.
1683  */
1684 static int rp_write_room(struct tty_struct *tty)
1685 {
1686         struct r_port *info = tty->driver_data;
1687         int ret;
1688
1689         if (rocket_paranoia_check(info, "rp_write_room"))
1690                 return 0;
1691
1692         ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1693         if (ret < 0)
1694                 ret = 0;
1695 #ifdef ROCKET_DEBUG_WRITE
1696         printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1697 #endif
1698         return ret;
1699 }
1700
1701 /*
1702  * Return the number of characters in the buffer.  Again, this only
1703  * counts those characters in the in-memory transmit buffer.
1704  */
1705 static int rp_chars_in_buffer(struct tty_struct *tty)
1706 {
1707         struct r_port *info = tty->driver_data;
1708         CHANNEL_t *cp;
1709
1710         if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1711                 return 0;
1712
1713         cp = &info->channel;
1714
1715 #ifdef ROCKET_DEBUG_WRITE
1716         printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1717 #endif
1718         return info->xmit_cnt;
1719 }
1720
1721 /*
1722  *  Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1723  *  r_port struct for the port.  Note that spinlock are used to protect info members,
1724  *  do not call this function if the spinlock is already held.
1725  */
1726 static void rp_flush_buffer(struct tty_struct *tty)
1727 {
1728         struct r_port *info = tty->driver_data;
1729         CHANNEL_t *cp;
1730         unsigned long flags;
1731
1732         if (rocket_paranoia_check(info, "rp_flush_buffer"))
1733                 return;
1734
1735         spin_lock_irqsave(&info->slock, flags);
1736         info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1737         spin_unlock_irqrestore(&info->slock, flags);
1738
1739 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1740         wake_up_interruptible(&tty->poll_wait);
1741 #endif
1742         tty_wakeup(tty);
1743
1744         cp = &info->channel;
1745         sFlushTxFIFO(cp);
1746 }
1747
1748 #ifdef CONFIG_PCI
1749
1750 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1751         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1752         { }
1753 };
1754 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1755
1756 /*
1757  *  Called when a PCI card is found.  Retrieves and stores model information,
1758  *  init's aiopic and serial port hardware.
1759  *  Inputs:  i is the board number (0-n)
1760  */
1761 static __init int register_PCI(int i, struct pci_dev *dev)
1762 {
1763         int num_aiops, aiop, max_num_aiops, num_chan, chan;
1764         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1765         char *str, *board_type;
1766         CONTROLLER_t *ctlp;
1767
1768         int fast_clock = 0;
1769         int altChanRingIndicator = 0;
1770         int ports_per_aiop = 8;
1771         WordIO_t ConfigIO = 0;
1772         ByteIO_t UPCIRingInd = 0;
1773
1774         if (!dev || pci_enable_device(dev))
1775                 return 0;
1776
1777         rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1778
1779         rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1780         rocketModel[i].loadrm2 = 0;
1781         rocketModel[i].startingPortNumber = nextLineNumber;
1782
1783         /*  Depending on the model, set up some config variables */
1784         switch (dev->device) {
1785         case PCI_DEVICE_ID_RP4QUAD:
1786                 str = "Quadcable";
1787                 max_num_aiops = 1;
1788                 ports_per_aiop = 4;
1789                 rocketModel[i].model = MODEL_RP4QUAD;
1790                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1791                 rocketModel[i].numPorts = 4;
1792                 break;
1793         case PCI_DEVICE_ID_RP8OCTA:
1794                 str = "Octacable";
1795                 max_num_aiops = 1;
1796                 rocketModel[i].model = MODEL_RP8OCTA;
1797                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1798                 rocketModel[i].numPorts = 8;
1799                 break;
1800         case PCI_DEVICE_ID_URP8OCTA:
1801                 str = "Octacable";
1802                 max_num_aiops = 1;
1803                 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1804                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1805                 rocketModel[i].numPorts = 8;
1806                 break;
1807         case PCI_DEVICE_ID_RP8INTF:
1808                 str = "8";
1809                 max_num_aiops = 1;
1810                 rocketModel[i].model = MODEL_RP8INTF;
1811                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1812                 rocketModel[i].numPorts = 8;
1813                 break;
1814         case PCI_DEVICE_ID_URP8INTF:
1815                 str = "8";
1816                 max_num_aiops = 1;
1817                 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1818                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1819                 rocketModel[i].numPorts = 8;
1820                 break;
1821         case PCI_DEVICE_ID_RP8J:
1822                 str = "8J";
1823                 max_num_aiops = 1;
1824                 rocketModel[i].model = MODEL_RP8J;
1825                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1826                 rocketModel[i].numPorts = 8;
1827                 break;
1828         case PCI_DEVICE_ID_RP4J:
1829                 str = "4J";
1830                 max_num_aiops = 1;
1831                 ports_per_aiop = 4;
1832                 rocketModel[i].model = MODEL_RP4J;
1833                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1834                 rocketModel[i].numPorts = 4;
1835                 break;
1836         case PCI_DEVICE_ID_RP8SNI:
1837                 str = "8 (DB78 Custom)";
1838                 max_num_aiops = 1;
1839                 rocketModel[i].model = MODEL_RP8SNI;
1840                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1841                 rocketModel[i].numPorts = 8;
1842                 break;
1843         case PCI_DEVICE_ID_RP16SNI:
1844                 str = "16 (DB78 Custom)";
1845                 max_num_aiops = 2;
1846                 rocketModel[i].model = MODEL_RP16SNI;
1847                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1848                 rocketModel[i].numPorts = 16;
1849                 break;
1850         case PCI_DEVICE_ID_RP16INTF:
1851                 str = "16";
1852                 max_num_aiops = 2;
1853                 rocketModel[i].model = MODEL_RP16INTF;
1854                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1855                 rocketModel[i].numPorts = 16;
1856                 break;
1857         case PCI_DEVICE_ID_URP16INTF:
1858                 str = "16";
1859                 max_num_aiops = 2;
1860                 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1861                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1862                 rocketModel[i].numPorts = 16;
1863                 break;
1864         case PCI_DEVICE_ID_CRP16INTF:
1865                 str = "16";
1866                 max_num_aiops = 2;
1867                 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1868                 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1869                 rocketModel[i].numPorts = 16;
1870                 break;
1871         case PCI_DEVICE_ID_RP32INTF:
1872                 str = "32";
1873                 max_num_aiops = 4;
1874                 rocketModel[i].model = MODEL_RP32INTF;
1875                 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1876                 rocketModel[i].numPorts = 32;
1877                 break;
1878         case PCI_DEVICE_ID_URP32INTF:
1879                 str = "32";
1880                 max_num_aiops = 4;
1881                 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1882                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1883                 rocketModel[i].numPorts = 32;
1884                 break;
1885         case PCI_DEVICE_ID_RPP4:
1886                 str = "Plus Quadcable";
1887                 max_num_aiops = 1;
1888                 ports_per_aiop = 4;
1889                 altChanRingIndicator++;
1890                 fast_clock++;
1891                 rocketModel[i].model = MODEL_RPP4;
1892                 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1893                 rocketModel[i].numPorts = 4;
1894                 break;
1895         case PCI_DEVICE_ID_RPP8:
1896                 str = "Plus Octacable";
1897                 max_num_aiops = 2;
1898                 ports_per_aiop = 4;
1899                 altChanRingIndicator++;
1900                 fast_clock++;
1901                 rocketModel[i].model = MODEL_RPP8;
1902                 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1903                 rocketModel[i].numPorts = 8;
1904                 break;
1905         case PCI_DEVICE_ID_RP2_232:
1906                 str = "Plus 2 (RS-232)";
1907                 max_num_aiops = 1;
1908                 ports_per_aiop = 2;
1909                 altChanRingIndicator++;
1910                 fast_clock++;
1911                 rocketModel[i].model = MODEL_RP2_232;
1912                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1913                 rocketModel[i].numPorts = 2;
1914                 break;
1915         case PCI_DEVICE_ID_RP2_422:
1916                 str = "Plus 2 (RS-422)";
1917                 max_num_aiops = 1;
1918                 ports_per_aiop = 2;
1919                 altChanRingIndicator++;
1920                 fast_clock++;
1921                 rocketModel[i].model = MODEL_RP2_422;
1922                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1923                 rocketModel[i].numPorts = 2;
1924                 break;
1925         case PCI_DEVICE_ID_RP6M:
1926
1927                 max_num_aiops = 1;
1928                 ports_per_aiop = 6;
1929                 str = "6-port";
1930
1931                 /*  If revision is 1, the rocketmodem flash must be loaded.
1932                  *  If it is 2 it is a "socketed" version. */
1933                 if (dev->revision == 1) {
1934                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1935                         rocketModel[i].loadrm2 = 1;
1936                 } else {
1937                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
1938                 }
1939
1940                 rocketModel[i].model = MODEL_RP6M;
1941                 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
1942                 rocketModel[i].numPorts = 6;
1943                 break;
1944         case PCI_DEVICE_ID_RP4M:
1945                 max_num_aiops = 1;
1946                 ports_per_aiop = 4;
1947                 str = "4-port";
1948                 if (dev->revision == 1) {
1949                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1950                         rocketModel[i].loadrm2 = 1;
1951                 } else {
1952                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
1953                 }
1954
1955                 rocketModel[i].model = MODEL_RP4M;
1956                 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
1957                 rocketModel[i].numPorts = 4;
1958                 break;
1959         default:
1960                 str = "(unknown/unsupported)";
1961                 max_num_aiops = 0;
1962                 break;
1963         }
1964
1965         /*
1966          * Check for UPCI boards.
1967          */
1968
1969         switch (dev->device) {
1970         case PCI_DEVICE_ID_URP32INTF:
1971         case PCI_DEVICE_ID_URP8INTF:
1972         case PCI_DEVICE_ID_URP16INTF:
1973         case PCI_DEVICE_ID_CRP16INTF:
1974         case PCI_DEVICE_ID_URP8OCTA:
1975                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1976                 ConfigIO = pci_resource_start(dev, 1);
1977                 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
1978                         UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1979
1980                         /*
1981                          * Check for octa or quad cable.
1982                          */
1983                         if (!
1984                             (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
1985                              PCI_GPIO_CTRL_8PORT)) {
1986                                 str = "Quadcable";
1987                                 ports_per_aiop = 4;
1988                                 rocketModel[i].numPorts = 4;
1989                         }
1990                 }
1991                 break;
1992         case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1993                 str = "8 ports";
1994                 max_num_aiops = 1;
1995                 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
1996                 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
1997                 rocketModel[i].numPorts = 8;
1998                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1999                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2000                 ConfigIO = pci_resource_start(dev, 1);
2001                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2002                 break;
2003         case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2004                 str = "4 ports";
2005                 max_num_aiops = 1;
2006                 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2007                 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2008                 rocketModel[i].numPorts = 4;
2009                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2010                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2011                 ConfigIO = pci_resource_start(dev, 1);
2012                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2013                 break;
2014         default:
2015                 break;
2016         }
2017
2018         switch (rcktpt_type[i]) {
2019         case ROCKET_TYPE_MODEM:
2020                 board_type = "RocketModem";
2021                 break;
2022         case ROCKET_TYPE_MODEMII:
2023                 board_type = "RocketModem II";
2024                 break;
2025         case ROCKET_TYPE_MODEMIII:
2026                 board_type = "RocketModem III";
2027                 break;
2028         default:
2029                 board_type = "RocketPort";
2030                 break;
2031         }
2032
2033         if (fast_clock) {
2034                 sClockPrescale = 0x12;  /* mod 2 (divide by 3) */
2035                 rp_baud_base[i] = 921600;
2036         } else {
2037                 /*
2038                  * If support_low_speed is set, use the slow clock
2039                  * prescale, which supports 50 bps
2040                  */
2041                 if (support_low_speed) {
2042                         /* mod 9 (divide by 10) prescale */
2043                         sClockPrescale = 0x19;
2044                         rp_baud_base[i] = 230400;
2045                 } else {
2046                         /* mod 4 (devide by 5) prescale */
2047                         sClockPrescale = 0x14;
2048                         rp_baud_base[i] = 460800;
2049                 }
2050         }
2051
2052         for (aiop = 0; aiop < max_num_aiops; aiop++)
2053                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2054         ctlp = sCtlNumToCtlPtr(i);
2055         num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2056         for (aiop = 0; aiop < max_num_aiops; aiop++)
2057                 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2058
2059         dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2060                 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2061                 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2062                 rocketModel[i].startingPortNumber,
2063                 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2064
2065         if (num_aiops <= 0) {
2066                 rcktpt_io_addr[i] = 0;
2067                 return (0);
2068         }
2069         is_PCI[i] = 1;
2070
2071         /*  Reset the AIOPIC, init the serial ports */
2072         for (aiop = 0; aiop < num_aiops; aiop++) {
2073                 sResetAiopByNum(ctlp, aiop);
2074                 num_chan = ports_per_aiop;
2075                 for (chan = 0; chan < num_chan; chan++)
2076                         init_r_port(i, aiop, chan, dev);
2077         }
2078
2079         /*  Rocket modems must be reset */
2080         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2081             (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2082             (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2083                 num_chan = ports_per_aiop;
2084                 for (chan = 0; chan < num_chan; chan++)
2085                         sPCIModemReset(ctlp, chan, 1);
2086                 msleep(500);
2087                 for (chan = 0; chan < num_chan; chan++)
2088                         sPCIModemReset(ctlp, chan, 0);
2089                 msleep(500);
2090                 rmSpeakerReset(ctlp, rocketModel[i].model);
2091         }
2092         return (1);
2093 }
2094
2095 /*
2096  *  Probes for PCI cards, inits them if found
2097  *  Input:   board_found = number of ISA boards already found, or the
2098  *           starting board number
2099  *  Returns: Number of PCI boards found
2100  */
2101 static int __init init_PCI(int boards_found)
2102 {
2103         struct pci_dev *dev = NULL;
2104         int count = 0;
2105
2106         /*  Work through the PCI device list, pulling out ours */
2107         while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2108                 if (register_PCI(count + boards_found, dev))
2109                         count++;
2110         }
2111         return (count);
2112 }
2113
2114 #endif                          /* CONFIG_PCI */
2115
2116 /*
2117  *  Probes for ISA cards
2118  *  Input:   i = the board number to look for
2119  *  Returns: 1 if board found, 0 else
2120  */
2121 static int __init init_ISA(int i)
2122 {
2123         int num_aiops, num_chan = 0, total_num_chan = 0;
2124         int aiop, chan;
2125         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2126         CONTROLLER_t *ctlp;
2127         char *type_string;
2128
2129         /*  If io_addr is zero, no board configured */
2130         if (rcktpt_io_addr[i] == 0)
2131                 return (0);
2132
2133         /*  Reserve the IO region */
2134         if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2135                 printk(KERN_ERR "Unable to reserve IO region for configured "
2136                                 "ISA RocketPort at address 0x%lx, board not "
2137                                 "installed...\n", rcktpt_io_addr[i]);
2138                 rcktpt_io_addr[i] = 0;
2139                 return (0);
2140         }
2141
2142         ctlp = sCtlNumToCtlPtr(i);
2143
2144         ctlp->boardType = rcktpt_type[i];
2145
2146         switch (rcktpt_type[i]) {
2147         case ROCKET_TYPE_PC104:
2148                 type_string = "(PC104)";
2149                 break;
2150         case ROCKET_TYPE_MODEM:
2151                 type_string = "(RocketModem)";
2152                 break;
2153         case ROCKET_TYPE_MODEMII:
2154                 type_string = "(RocketModem II)";
2155                 break;
2156         default:
2157                 type_string = "";
2158                 break;
2159         }
2160
2161         /*
2162          * If support_low_speed is set, use the slow clock prescale,
2163          * which supports 50 bps
2164          */
2165         if (support_low_speed) {
2166                 sClockPrescale = 0x19;  /* mod 9 (divide by 10) prescale */
2167                 rp_baud_base[i] = 230400;
2168         } else {
2169                 sClockPrescale = 0x14;  /* mod 4 (devide by 5) prescale */
2170                 rp_baud_base[i] = 460800;
2171         }
2172
2173         for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2174                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2175
2176         num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio,  MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2177
2178         if (ctlp->boardType == ROCKET_TYPE_PC104) {
2179                 sEnAiop(ctlp, 2);       /* only one AIOPIC, but these */
2180                 sEnAiop(ctlp, 3);       /* CSels used for other stuff */
2181         }
2182
2183         /*  If something went wrong initing the AIOP's release the ISA IO memory */
2184         if (num_aiops <= 0) {
2185                 release_region(rcktpt_io_addr[i], 64);
2186                 rcktpt_io_addr[i] = 0;
2187                 return (0);
2188         }
2189
2190         rocketModel[i].startingPortNumber = nextLineNumber;
2191
2192         for (aiop = 0; aiop < num_aiops; aiop++) {
2193                 sResetAiopByNum(ctlp, aiop);
2194                 sEnAiop(ctlp, aiop);
2195                 num_chan = sGetAiopNumChan(ctlp, aiop);
2196                 total_num_chan += num_chan;
2197                 for (chan = 0; chan < num_chan; chan++)
2198                         init_r_port(i, aiop, chan, NULL);
2199         }
2200         is_PCI[i] = 0;
2201         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2202                 num_chan = sGetAiopNumChan(ctlp, 0);
2203                 total_num_chan = num_chan;
2204                 for (chan = 0; chan < num_chan; chan++)
2205                         sModemReset(ctlp, chan, 1);
2206                 msleep(500);
2207                 for (chan = 0; chan < num_chan; chan++)
2208                         sModemReset(ctlp, chan, 0);
2209                 msleep(500);
2210                 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2211         } else {
2212                 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2213         }
2214         rocketModel[i].numPorts = total_num_chan;
2215         rocketModel[i].model = MODEL_ISA;
2216
2217         printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2218                i, rcktpt_io_addr[i], num_aiops, type_string);
2219
2220         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2221                rocketModel[i].modelString,
2222                rocketModel[i].startingPortNumber,
2223                rocketModel[i].startingPortNumber +
2224                rocketModel[i].numPorts - 1);
2225
2226         return (1);
2227 }
2228
2229 static const struct tty_operations rocket_ops = {
2230         .open = rp_open,
2231         .close = rp_close,
2232         .write = rp_write,
2233         .put_char = rp_put_char,
2234         .write_room = rp_write_room,
2235         .chars_in_buffer = rp_chars_in_buffer,
2236         .flush_buffer = rp_flush_buffer,
2237         .ioctl = rp_ioctl,
2238         .throttle = rp_throttle,
2239         .unthrottle = rp_unthrottle,
2240         .set_termios = rp_set_termios,
2241         .stop = rp_stop,
2242         .start = rp_start,
2243         .hangup = rp_hangup,
2244         .break_ctl = rp_break,
2245         .send_xchar = rp_send_xchar,
2246         .wait_until_sent = rp_wait_until_sent,
2247         .tiocmget = rp_tiocmget,
2248         .tiocmset = rp_tiocmset,
2249 };
2250
2251 static const struct tty_port_operations rocket_port_ops = {
2252         .carrier_raised = carrier_raised,
2253         .raise_dtr_rts = raise_dtr_rts,
2254 };
2255
2256 /*
2257  * The module "startup" routine; it's run when the module is loaded.
2258  */
2259 static int __init rp_init(void)
2260 {
2261         int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2262
2263         printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2264                ROCKET_VERSION, ROCKET_DATE);
2265
2266         rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2267         if (!rocket_driver)
2268                 goto err;
2269
2270         /*
2271          *  If board 1 is non-zero, there is at least one ISA configured.  If controller is
2272          *  zero, use the default controller IO address of board1 + 0x40.
2273          */
2274         if (board1) {
2275                 if (controller == 0)
2276                         controller = board1 + 0x40;
2277         } else {
2278                 controller = 0;  /*  Used as a flag, meaning no ISA boards */
2279         }
2280
2281         /*  If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2282         if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2283                 printk(KERN_ERR "Unable to reserve IO region for first "
2284                         "configured ISA RocketPort controller 0x%lx.  "
2285                         "Driver exiting\n", controller);
2286                 ret = -EBUSY;
2287                 goto err_tty;
2288         }
2289
2290         /*  Store ISA variable retrieved from command line or .conf file. */
2291         rcktpt_io_addr[0] = board1;
2292         rcktpt_io_addr[1] = board2;
2293         rcktpt_io_addr[2] = board3;
2294         rcktpt_io_addr[3] = board4;
2295
2296         rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2297         rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2298         rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2299         rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2300         rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2301         rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2302         rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2303         rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2304
2305         /*
2306          * Set up the tty driver structure and then register this
2307          * driver with the tty layer.
2308          */
2309
2310         rocket_driver->owner = THIS_MODULE;
2311         rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2312         rocket_driver->name = "ttyR";
2313         rocket_driver->driver_name = "Comtrol RocketPort";
2314         rocket_driver->major = TTY_ROCKET_MAJOR;
2315         rocket_driver->minor_start = 0;
2316         rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2317         rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2318         rocket_driver->init_termios = tty_std_termios;
2319         rocket_driver->init_termios.c_cflag =
2320             B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2321         rocket_driver->init_termios.c_ispeed = 9600;
2322         rocket_driver->init_termios.c_ospeed = 9600;
2323 #ifdef ROCKET_SOFT_FLOW
2324         rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2325 #endif
2326         tty_set_operations(rocket_driver, &rocket_ops);
2327
2328         ret = tty_register_driver(rocket_driver);
2329         if (ret < 0) {
2330                 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2331                 goto err_tty;
2332         }
2333
2334 #ifdef ROCKET_DEBUG_OPEN
2335         printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2336 #endif
2337
2338         /*
2339          *  OK, let's probe each of the controllers looking for boards.  Any boards found
2340          *  will be initialized here.
2341          */
2342         isa_boards_found = 0;
2343         pci_boards_found = 0;
2344
2345         for (i = 0; i < NUM_BOARDS; i++) {
2346                 if (init_ISA(i))
2347                         isa_boards_found++;
2348         }
2349
2350 #ifdef CONFIG_PCI
2351         if (isa_boards_found < NUM_BOARDS)
2352                 pci_boards_found = init_PCI(isa_boards_found);
2353 #endif
2354
2355         max_board = pci_boards_found + isa_boards_found;
2356
2357         if (max_board == 0) {
2358                 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2359                 ret = -ENXIO;
2360                 goto err_ttyu;
2361         }
2362
2363         return 0;
2364 err_ttyu:
2365         tty_unregister_driver(rocket_driver);
2366 err_tty:
2367         put_tty_driver(rocket_driver);
2368 err:
2369         return ret;
2370 }
2371
2372
2373 static void rp_cleanup_module(void)
2374 {
2375         int retval;
2376         int i;
2377
2378         del_timer_sync(&rocket_timer);
2379
2380         retval = tty_unregister_driver(rocket_driver);
2381         if (retval)
2382                 printk(KERN_ERR "Error %d while trying to unregister "
2383                        "rocketport driver\n", -retval);
2384
2385         for (i = 0; i < MAX_RP_PORTS; i++)
2386                 if (rp_table[i]) {
2387                         tty_unregister_device(rocket_driver, i);
2388                         kfree(rp_table[i]);
2389                 }
2390
2391         put_tty_driver(rocket_driver);
2392
2393         for (i = 0; i < NUM_BOARDS; i++) {
2394                 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2395                         continue;
2396                 release_region(rcktpt_io_addr[i], 64);
2397         }
2398         if (controller)
2399                 release_region(controller, 4);
2400 }
2401
2402 /***************************************************************************
2403 Function: sInitController
2404 Purpose:  Initialization of controller global registers and controller
2405           structure.
2406 Call:     sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2407                           IRQNum,Frequency,PeriodicOnly)
2408           CONTROLLER_T *CtlP; Ptr to controller structure
2409           int CtlNum; Controller number
2410           ByteIO_t MudbacIO; Mudbac base I/O address.
2411           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2412              This list must be in the order the AIOPs will be found on the
2413              controller.  Once an AIOP in the list is not found, it is
2414              assumed that there are no more AIOPs on the controller.
2415           int AiopIOListSize; Number of addresses in AiopIOList
2416           int IRQNum; Interrupt Request number.  Can be any of the following:
2417                          0: Disable global interrupts
2418                          3: IRQ 3
2419                          4: IRQ 4
2420                          5: IRQ 5
2421                          9: IRQ 9
2422                          10: IRQ 10
2423                          11: IRQ 11
2424                          12: IRQ 12
2425                          15: IRQ 15
2426           Byte_t Frequency: A flag identifying the frequency
2427                    of the periodic interrupt, can be any one of the following:
2428                       FREQ_DIS - periodic interrupt disabled
2429                       FREQ_137HZ - 137 Hertz
2430                       FREQ_69HZ - 69 Hertz
2431                       FREQ_34HZ - 34 Hertz
2432                       FREQ_17HZ - 17 Hertz
2433                       FREQ_9HZ - 9 Hertz
2434                       FREQ_4HZ - 4 Hertz
2435                    If IRQNum is set to 0 the Frequency parameter is
2436                    overidden, it is forced to a value of FREQ_DIS.
2437           int PeriodicOnly: 1 if all interrupts except the periodic
2438                                interrupt are to be blocked.
2439                             0 is both the periodic interrupt and
2440                                other channel interrupts are allowed.
2441                             If IRQNum is set to 0 the PeriodicOnly parameter is
2442                                overidden, it is forced to a value of 0.
2443 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2444                initialization failed.
2445
2446 Comments:
2447           If periodic interrupts are to be disabled but AIOP interrupts
2448           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2449
2450           If interrupts are to be completely disabled set IRQNum to 0.
2451
2452           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2453           invalid combination.
2454
2455           This function performs initialization of global interrupt modes,
2456           but it does not actually enable global interrupts.  To enable
2457           and disable global interrupts use functions sEnGlobalInt() and
2458           sDisGlobalInt().  Enabling of global interrupts is normally not
2459           done until all other initializations are complete.
2460
2461           Even if interrupts are globally enabled, they must also be
2462           individually enabled for each channel that is to generate
2463           interrupts.
2464
2465 Warnings: No range checking on any of the parameters is done.
2466
2467           No context switches are allowed while executing this function.
2468
2469           After this function all AIOPs on the controller are disabled,
2470           they can be enabled with sEnAiop().
2471 */
2472 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2473                            ByteIO_t * AiopIOList, int AiopIOListSize,
2474                            int IRQNum, Byte_t Frequency, int PeriodicOnly)
2475 {
2476         int i;
2477         ByteIO_t io;
2478         int done;
2479
2480         CtlP->AiopIntrBits = aiop_intr_bits;
2481         CtlP->AltChanRingIndicator = 0;
2482         CtlP->CtlNum = CtlNum;
2483         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2484         CtlP->BusType = isISA;
2485         CtlP->MBaseIO = MudbacIO;
2486         CtlP->MReg1IO = MudbacIO + 1;
2487         CtlP->MReg2IO = MudbacIO + 2;
2488         CtlP->MReg3IO = MudbacIO + 3;
2489 #if 1
2490         CtlP->MReg2 = 0;        /* interrupt disable */
2491         CtlP->MReg3 = 0;        /* no periodic interrupts */
2492 #else
2493         if (sIRQMap[IRQNum] == 0) {     /* interrupts globally disabled */
2494                 CtlP->MReg2 = 0;        /* interrupt disable */
2495                 CtlP->MReg3 = 0;        /* no periodic interrupts */
2496         } else {
2497                 CtlP->MReg2 = sIRQMap[IRQNum];  /* set IRQ number */
2498                 CtlP->MReg3 = Frequency;        /* set frequency */
2499                 if (PeriodicOnly) {     /* periodic interrupt only */
2500                         CtlP->MReg3 |= PERIODIC_ONLY;
2501                 }
2502         }
2503 #endif
2504         sOutB(CtlP->MReg2IO, CtlP->MReg2);
2505         sOutB(CtlP->MReg3IO, CtlP->MReg3);
2506         sControllerEOI(CtlP);   /* clear EOI if warm init */
2507         /* Init AIOPs */
2508         CtlP->NumAiop = 0;
2509         for (i = done = 0; i < AiopIOListSize; i++) {
2510                 io = AiopIOList[i];
2511                 CtlP->AiopIO[i] = (WordIO_t) io;
2512                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2513                 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2514                 sOutB(MudbacIO, (Byte_t) (io >> 6));    /* set up AIOP I/O in MUDBAC */
2515                 if (done)
2516                         continue;
2517                 sEnAiop(CtlP, i);       /* enable the AIOP */
2518                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2519                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2520                         done = 1;       /* done looking for AIOPs */
2521                 else {
2522                         CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2523                         sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2524                         sOutB(io + _INDX_DATA, sClockPrescale);
2525                         CtlP->NumAiop++;        /* bump count of AIOPs */
2526                 }
2527                 sDisAiop(CtlP, i);      /* disable AIOP */
2528         }
2529
2530         if (CtlP->NumAiop == 0)
2531                 return (-1);
2532         else
2533                 return (CtlP->NumAiop);
2534 }
2535
2536 /***************************************************************************
2537 Function: sPCIInitController
2538 Purpose:  Initialization of controller global registers and controller
2539           structure.
2540 Call:     sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2541                           IRQNum,Frequency,PeriodicOnly)
2542           CONTROLLER_T *CtlP; Ptr to controller structure
2543           int CtlNum; Controller number
2544           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2545              This list must be in the order the AIOPs will be found on the
2546              controller.  Once an AIOP in the list is not found, it is
2547              assumed that there are no more AIOPs on the controller.
2548           int AiopIOListSize; Number of addresses in AiopIOList
2549           int IRQNum; Interrupt Request number.  Can be any of the following:
2550                          0: Disable global interrupts
2551                          3: IRQ 3
2552                          4: IRQ 4
2553                          5: IRQ 5
2554                          9: IRQ 9
2555                          10: IRQ 10
2556                          11: IRQ 11
2557                          12: IRQ 12
2558                          15: IRQ 15
2559           Byte_t Frequency: A flag identifying the frequency
2560                    of the periodic interrupt, can be any one of the following:
2561                       FREQ_DIS - periodic interrupt disabled
2562                       FREQ_137HZ - 137 Hertz
2563                       FREQ_69HZ - 69 Hertz
2564                       FREQ_34HZ - 34 Hertz
2565                       FREQ_17HZ - 17 Hertz
2566                       FREQ_9HZ - 9 Hertz
2567                       FREQ_4HZ - 4 Hertz
2568                    If IRQNum is set to 0 the Frequency parameter is
2569                    overidden, it is forced to a value of FREQ_DIS.
2570           int PeriodicOnly: 1 if all interrupts except the periodic
2571                                interrupt are to be blocked.
2572                             0 is both the periodic interrupt and
2573                                other channel interrupts are allowed.
2574                             If IRQNum is set to 0 the PeriodicOnly parameter is
2575                                overidden, it is forced to a value of 0.
2576 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2577                initialization failed.
2578
2579 Comments:
2580           If periodic interrupts are to be disabled but AIOP interrupts
2581           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2582
2583           If interrupts are to be completely disabled set IRQNum to 0.
2584
2585           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2586           invalid combination.
2587
2588           This function performs initialization of global interrupt modes,
2589           but it does not actually enable global interrupts.  To enable
2590           and disable global interrupts use functions sEnGlobalInt() and
2591           sDisGlobalInt().  Enabling of global interrupts is normally not
2592           done until all other initializations are complete.
2593
2594           Even if interrupts are globally enabled, they must also be
2595           individually enabled for each channel that is to generate
2596           interrupts.
2597
2598 Warnings: No range checking on any of the parameters is done.
2599
2600           No context switches are allowed while executing this function.
2601
2602           After this function all AIOPs on the controller are disabled,
2603           they can be enabled with sEnAiop().
2604 */
2605 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2606                               ByteIO_t * AiopIOList, int AiopIOListSize,
2607                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2608                               int PeriodicOnly, int altChanRingIndicator,
2609                               int UPCIRingInd)
2610 {
2611         int i;
2612         ByteIO_t io;
2613
2614         CtlP->AltChanRingIndicator = altChanRingIndicator;
2615         CtlP->UPCIRingInd = UPCIRingInd;
2616         CtlP->CtlNum = CtlNum;
2617         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2618         CtlP->BusType = isPCI;  /* controller release 1 */
2619
2620         if (ConfigIO) {
2621                 CtlP->isUPCI = 1;
2622                 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2623                 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2624                 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2625         } else {
2626                 CtlP->isUPCI = 0;
2627                 CtlP->PCIIO =
2628                     (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2629                 CtlP->AiopIntrBits = aiop_intr_bits;
2630         }
2631
2632         sPCIControllerEOI(CtlP);        /* clear EOI if warm init */
2633         /* Init AIOPs */
2634         CtlP->NumAiop = 0;
2635         for (i = 0; i < AiopIOListSize; i++) {
2636                 io = AiopIOList[i];
2637                 CtlP->AiopIO[i] = (WordIO_t) io;
2638                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2639
2640                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2641                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2642                         break;  /* done looking for AIOPs */
2643
2644                 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2645                 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2646                 sOutB(io + _INDX_DATA, sClockPrescale);
2647                 CtlP->NumAiop++;        /* bump count of AIOPs */
2648         }
2649
2650         if (CtlP->NumAiop == 0)
2651                 return (-1);
2652         else
2653                 return (CtlP->NumAiop);
2654 }
2655
2656 /***************************************************************************
2657 Function: sReadAiopID
2658 Purpose:  Read the AIOP idenfication number directly from an AIOP.
2659 Call:     sReadAiopID(io)
2660           ByteIO_t io: AIOP base I/O address
2661 Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2662                  is replace by an identifying number.
2663           Flag AIOPID_NULL if no valid AIOP is found
2664 Warnings: No context switches are allowed while executing this function.
2665
2666 */
2667 static int sReadAiopID(ByteIO_t io)
2668 {
2669         Byte_t AiopID;          /* ID byte from AIOP */
2670
2671         sOutB(io + _CMD_REG, RESET_ALL);        /* reset AIOP */
2672         sOutB(io + _CMD_REG, 0x0);
2673         AiopID = sInW(io + _CHN_STAT0) & 0x07;
2674         if (AiopID == 0x06)
2675                 return (1);
2676         else                    /* AIOP does not exist */
2677                 return (-1);
2678 }
2679
2680 /***************************************************************************
2681 Function: sReadAiopNumChan
2682 Purpose:  Read the number of channels available in an AIOP directly from
2683           an AIOP.
2684 Call:     sReadAiopNumChan(io)
2685           WordIO_t io: AIOP base I/O address
2686 Return:   int: The number of channels available
2687 Comments: The number of channels is determined by write/reads from identical
2688           offsets within the SRAM address spaces for channels 0 and 4.
2689           If the channel 4 space is mirrored to channel 0 it is a 4 channel
2690           AIOP, otherwise it is an 8 channel.
2691 Warnings: No context switches are allowed while executing this function.
2692 */
2693 static int sReadAiopNumChan(WordIO_t io)
2694 {
2695         Word_t x;
2696         static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2697
2698         /* write to chan 0 SRAM */
2699         out32((DWordIO_t) io + _INDX_ADDR, R);
2700         sOutW(io + _INDX_ADDR, 0);      /* read from SRAM, chan 0 */
2701         x = sInW(io + _INDX_DATA);
2702         sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2703         if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2704                 return (8);
2705         else
2706                 return (4);
2707 }
2708
2709 /***************************************************************************
2710 Function: sInitChan
2711 Purpose:  Initialization of a channel and channel structure
2712 Call:     sInitChan(CtlP,ChP,AiopNum,ChanNum)
2713           CONTROLLER_T *CtlP; Ptr to controller structure
2714           CHANNEL_T *ChP; Ptr to channel structure
2715           int AiopNum; AIOP number within controller
2716           int ChanNum; Channel number within AIOP
2717 Return:   int: 1 if initialization succeeded, 0 if it fails because channel
2718                number exceeds number of channels available in AIOP.
2719 Comments: This function must be called before a channel can be used.
2720 Warnings: No range checking on any of the parameters is done.
2721
2722           No context switches are allowed while executing this function.
2723 */
2724 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2725                      int ChanNum)
2726 {
2727         int i;
2728         WordIO_t AiopIO;
2729         WordIO_t ChIOOff;
2730         Byte_t *ChR;
2731         Word_t ChOff;
2732         static Byte_t R[4];
2733         int brd9600;
2734
2735         if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2736                 return 0;       /* exceeds num chans in AIOP */
2737
2738         /* Channel, AIOP, and controller identifiers */
2739         ChP->CtlP = CtlP;
2740         ChP->ChanID = CtlP->AiopID[AiopNum];
2741         ChP->AiopNum = AiopNum;
2742         ChP->ChanNum = ChanNum;
2743
2744         /* Global direct addresses */
2745         AiopIO = CtlP->AiopIO[AiopNum];
2746         ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2747         ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2748         ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2749         ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2750         ChP->IndexData = AiopIO + _INDX_DATA;
2751
2752         /* Channel direct addresses */
2753         ChIOOff = AiopIO + ChP->ChanNum * 2;
2754         ChP->TxRxData = ChIOOff + _TD0;
2755         ChP->ChanStat = ChIOOff + _CHN_STAT0;
2756         ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2757         ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2758
2759         /* Initialize the channel from the RData array */
2760         for (i = 0; i < RDATASIZE; i += 4) {
2761                 R[0] = RData[i];
2762                 R[1] = RData[i + 1] + 0x10 * ChanNum;
2763                 R[2] = RData[i + 2];
2764                 R[3] = RData[i + 3];
2765                 out32(ChP->IndexAddr, R);
2766         }
2767
2768         ChR = ChP->R;
2769         for (i = 0; i < RREGDATASIZE; i += 4) {
2770                 ChR[i] = RRegData[i];
2771                 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2772                 ChR[i + 2] = RRegData[i + 2];
2773                 ChR[i + 3] = RRegData[i + 3];
2774         }
2775
2776         /* Indexed registers */
2777         ChOff = (Word_t) ChanNum *0x1000;
2778
2779         if (sClockPrescale == 0x14)
2780                 brd9600 = 47;
2781         else
2782                 brd9600 = 23;
2783
2784         ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2785         ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2786         ChP->BaudDiv[2] = (Byte_t) brd9600;
2787         ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2788         out32(ChP->IndexAddr, ChP->BaudDiv);
2789
2790         ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2791         ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2792         ChP->TxControl[2] = 0;
2793         ChP->TxControl[3] = 0;
2794         out32(ChP->IndexAddr, ChP->TxControl);
2795
2796         ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2797         ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2798         ChP->RxControl[2] = 0;
2799         ChP->RxControl[3] = 0;
2800         out32(ChP->IndexAddr, ChP->RxControl);
2801
2802         ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2803         ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2804         ChP->TxEnables[2] = 0;
2805         ChP->TxEnables[3] = 0;
2806         out32(ChP->IndexAddr, ChP->TxEnables);
2807
2808         ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2809         ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2810         ChP->TxCompare[2] = 0;
2811         ChP->TxCompare[3] = 0;
2812         out32(ChP->IndexAddr, ChP->TxCompare);
2813
2814         ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2815         ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2816         ChP->TxReplace1[2] = 0;
2817         ChP->TxReplace1[3] = 0;
2818         out32(ChP->IndexAddr, ChP->TxReplace1);
2819
2820         ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2821         ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2822         ChP->TxReplace2[2] = 0;
2823         ChP->TxReplace2[3] = 0;
2824         out32(ChP->IndexAddr, ChP->TxReplace2);
2825
2826         ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2827         ChP->TxFIFO = ChOff + _TX_FIFO;
2828
2829         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT);  /* apply reset Tx FIFO count */
2830         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Tx FIFO count */
2831         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2832         sOutW(ChP->IndexData, 0);
2833         ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2834         ChP->RxFIFO = ChOff + _RX_FIFO;
2835
2836         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT);  /* apply reset Rx FIFO count */
2837         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Rx FIFO count */
2838         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2839         sOutW(ChP->IndexData, 0);
2840         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2841         sOutW(ChP->IndexData, 0);
2842         ChP->TxPrioCnt = ChOff + _TXP_CNT;
2843         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2844         sOutB(ChP->IndexData, 0);
2845         ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2846         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2847         sOutB(ChP->IndexData, 0);
2848         ChP->TxPrioBuf = ChOff + _TXP_BUF;
2849         sEnRxProcessor(ChP);    /* start the Rx processor */
2850
2851         return 1;
2852 }
2853
2854 /***************************************************************************
2855 Function: sStopRxProcessor
2856 Purpose:  Stop the receive processor from processing a channel.
2857 Call:     sStopRxProcessor(ChP)
2858           CHANNEL_T *ChP; Ptr to channel structure
2859
2860 Comments: The receive processor can be started again with sStartRxProcessor().
2861           This function causes the receive processor to skip over the
2862           stopped channel.  It does not stop it from processing other channels.
2863
2864 Warnings: No context switches are allowed while executing this function.
2865
2866           Do not leave the receive processor stopped for more than one
2867           character time.
2868
2869           After calling this function a delay of 4 uS is required to ensure
2870           that the receive processor is no longer processing this channel.
2871 */
2872 static void sStopRxProcessor(CHANNEL_T * ChP)
2873 {
2874         Byte_t R[4];
2875
2876         R[0] = ChP->R[0];
2877         R[1] = ChP->R[1];
2878         R[2] = 0x0a;
2879         R[3] = ChP->R[3];
2880         out32(ChP->IndexAddr, R);
2881 }
2882
2883 /***************************************************************************
2884 Function: sFlushRxFIFO
2885 Purpose:  Flush the Rx FIFO
2886 Call:     sFlushRxFIFO(ChP)
2887           CHANNEL_T *ChP; Ptr to channel structure
2888 Return:   void
2889 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2890           while it is being flushed the receive processor is stopped
2891           and the transmitter is disabled.  After these operations a
2892           4 uS delay is done before clearing the pointers to allow
2893           the receive processor to stop.  These items are handled inside
2894           this function.
2895 Warnings: No context switches are allowed while executing this function.
2896 */
2897 static void sFlushRxFIFO(CHANNEL_T * ChP)
2898 {
2899         int i;
2900         Byte_t Ch;              /* channel number within AIOP */
2901         int RxFIFOEnabled;      /* 1 if Rx FIFO enabled */
2902
2903         if (sGetRxCnt(ChP) == 0)        /* Rx FIFO empty */
2904                 return;         /* don't need to flush */
2905
2906         RxFIFOEnabled = 0;
2907         if (ChP->R[0x32] == 0x08) {     /* Rx FIFO is enabled */
2908                 RxFIFOEnabled = 1;
2909                 sDisRxFIFO(ChP);        /* disable it */
2910                 for (i = 0; i < 2000 / 200; i++)        /* delay 2 uS to allow proc to disable FIFO */
2911                         sInB(ChP->IntChan);     /* depends on bus i/o timing */
2912         }
2913         sGetChanStatus(ChP);    /* clear any pending Rx errors in chan stat */
2914         Ch = (Byte_t) sGetChanNum(ChP);
2915         sOutB(ChP->Cmd, Ch | RESRXFCNT);        /* apply reset Rx FIFO count */
2916         sOutB(ChP->Cmd, Ch);    /* remove reset Rx FIFO count */
2917         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2918         sOutW(ChP->IndexData, 0);
2919         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2920         sOutW(ChP->IndexData, 0);
2921         if (RxFIFOEnabled)
2922                 sEnRxFIFO(ChP); /* enable Rx FIFO */
2923 }
2924
2925 /***************************************************************************
2926 Function: sFlushTxFIFO
2927 Purpose:  Flush the Tx FIFO
2928 Call:     sFlushTxFIFO(ChP)
2929           CHANNEL_T *ChP; Ptr to channel structure
2930 Return:   void
2931 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2932           while it is being flushed the receive processor is stopped
2933           and the transmitter is disabled.  After these operations a
2934           4 uS delay is done before clearing the pointers to allow
2935           the receive processor to stop.  These items are handled inside
2936           this function.
2937 Warnings: No context switches are allowed while executing this function.
2938 */
2939 static void sFlushTxFIFO(CHANNEL_T * ChP)
2940 {
2941         int i;
2942         Byte_t Ch;              /* channel number within AIOP */
2943         int TxEnabled;          /* 1 if transmitter enabled */
2944
2945         if (sGetTxCnt(ChP) == 0)        /* Tx FIFO empty */
2946                 return;         /* don't need to flush */
2947
2948         TxEnabled = 0;
2949         if (ChP->TxControl[3] & TX_ENABLE) {
2950                 TxEnabled = 1;
2951                 sDisTransmit(ChP);      /* disable transmitter */
2952         }
2953         sStopRxProcessor(ChP);  /* stop Rx processor */
2954         for (i = 0; i < 4000 / 200; i++)        /* delay 4 uS to allow proc to stop */
2955                 sInB(ChP->IntChan);     /* depends on bus i/o timing */
2956         Ch = (Byte_t) sGetChanNum(ChP);
2957         sOutB(ChP->Cmd, Ch | RESTXFCNT);        /* apply reset Tx FIFO count */
2958         sOutB(ChP->Cmd, Ch);    /* remove reset Tx FIFO count */
2959         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2960         sOutW(ChP->IndexData, 0);
2961         if (TxEnabled)
2962                 sEnTransmit(ChP);       /* enable transmitter */
2963         sStartRxProcessor(ChP); /* restart Rx processor */
2964 }
2965
2966 /***************************************************************************
2967 Function: sWriteTxPrioByte
2968 Purpose:  Write a byte of priority transmit data to a channel
2969 Call:     sWriteTxPrioByte(ChP,Data)
2970           CHANNEL_T *ChP; Ptr to channel structure
2971           Byte_t Data; The transmit data byte
2972
2973 Return:   int: 1 if the bytes is successfully written, otherwise 0.
2974
2975 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2976
2977 Warnings: No context switches are allowed while executing this function.
2978 */
2979 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2980 {
2981         Byte_t DWBuf[4];        /* buffer for double word writes */
2982         Word_t *WordPtr;        /* must be far because Win SS != DS */
2983         register DWordIO_t IndexAddr;
2984
2985         if (sGetTxCnt(ChP) > 1) {       /* write it to Tx priority buffer */
2986                 IndexAddr = ChP->IndexAddr;
2987                 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt);    /* get priority buffer status */
2988                 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2989                         return (0);     /* nothing sent */
2990
2991                 WordPtr = (Word_t *) (&DWBuf[0]);
2992                 *WordPtr = ChP->TxPrioBuf;      /* data byte address */
2993
2994                 DWBuf[2] = Data;        /* data byte value */
2995                 out32(IndexAddr, DWBuf);        /* write it out */
2996
2997                 *WordPtr = ChP->TxPrioCnt;      /* Tx priority count address */
2998
2999                 DWBuf[2] = PRI_PEND + 1;        /* indicate 1 byte pending */
3000                 DWBuf[3] = 0;   /* priority buffer pointer */
3001                 out32(IndexAddr, DWBuf);        /* write it out */
3002         } else {                /* write it to Tx FIFO */
3003
3004                 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3005         }
3006         return (1);             /* 1 byte sent */
3007 }
3008
3009 /***************************************************************************
3010 Function: sEnInterrupts
3011 Purpose:  Enable one or more interrupts for a channel
3012 Call:     sEnInterrupts(ChP,Flags)
3013           CHANNEL_T *ChP; Ptr to channel structure
3014           Word_t Flags: Interrupt enable flags, can be any combination
3015              of the following flags:
3016                 TXINT_EN:   Interrupt on Tx FIFO empty
3017                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3018                             sSetRxTrigger())
3019                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3020                 MCINT_EN:   Interrupt on modem input change
3021                 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3022                             Interrupt Channel Register.
3023 Return:   void
3024 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3025           enabled.  If an interrupt enable flag is not set in Flags, that
3026           interrupt will not be changed.  Interrupts can be disabled with
3027           function sDisInterrupts().
3028
3029           This function sets the appropriate bit for the channel in the AIOP's
3030           Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
3031           this channel's bit to be set in the AIOP's Interrupt Channel Register.
3032
3033           Interrupts must also be globally enabled before channel interrupts
3034           will be passed on to the host.  This is done with function
3035           sEnGlobalInt().
3036
3037           In some cases it may be desirable to disable interrupts globally but
3038           enable channel interrupts.  This would allow the global interrupt
3039           status register to be used to determine which AIOPs need service.
3040 */
3041 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3042 {
3043         Byte_t Mask;            /* Interrupt Mask Register */
3044
3045         ChP->RxControl[2] |=
3046             ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3047
3048         out32(ChP->IndexAddr, ChP->RxControl);
3049
3050         ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3051
3052         out32(ChP->IndexAddr, ChP->TxControl);
3053
3054         if (Flags & CHANINT_EN) {
3055                 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3056                 sOutB(ChP->IntMask, Mask);
3057         }
3058 }
3059
3060 /***************************************************************************
3061 Function: sDisInterrupts
3062 Purpose:  Disable one or more interrupts for a channel
3063 Call:     sDisInterrupts(ChP,Flags)
3064           CHANNEL_T *ChP; Ptr to channel structure
3065           Word_t Flags: Interrupt flags, can be any combination
3066              of the following flags:
3067                 TXINT_EN:   Interrupt on Tx FIFO empty
3068                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3069                             sSetRxTrigger())
3070                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3071                 MCINT_EN:   Interrupt on modem input change
3072                 CHANINT_EN: Disable channel interrupt signal to the
3073                             AIOP's Interrupt Channel Register.
3074 Return:   void
3075 Comments: If an interrupt flag is set in Flags, that interrupt will be
3076           disabled.  If an interrupt flag is not set in Flags, that
3077           interrupt will not be changed.  Interrupts can be enabled with
3078           function sEnInterrupts().
3079
3080           This function clears the appropriate bit for the channel in the AIOP's
3081           Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
3082           this channel's bit from being set in the AIOP's Interrupt Channel
3083           Register.
3084 */
3085 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3086 {
3087         Byte_t Mask;            /* Interrupt Mask Register */
3088
3089         ChP->RxControl[2] &=
3090             ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3091         out32(ChP->IndexAddr, ChP->RxControl);
3092         ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3093         out32(ChP->IndexAddr, ChP->TxControl);
3094
3095         if (Flags & CHANINT_EN) {
3096                 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3097                 sOutB(ChP->IntMask, Mask);
3098         }
3099 }
3100
3101 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3102 {
3103         sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3104 }
3105
3106 /*
3107  *  Not an official SSCI function, but how to reset RocketModems.
3108  *  ISA bus version
3109  */
3110 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3111 {
3112         ByteIO_t addr;
3113         Byte_t val;
3114
3115         addr = CtlP->AiopIO[0] + 0x400;
3116         val = sInB(CtlP->MReg3IO);
3117         /* if AIOP[1] is not enabled, enable it */
3118         if ((val & 2) == 0) {
3119                 val = sInB(CtlP->MReg2IO);
3120                 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3121                 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3122         }
3123
3124         sEnAiop(CtlP, 1);
3125         if (!on)
3126                 addr += 8;
3127         sOutB(addr + chan, 0);  /* apply or remove reset */
3128         sDisAiop(CtlP, 1);
3129 }
3130
3131 /*
3132  *  Not an official SSCI function, but how to reset RocketModems.
3133  *  PCI bus version
3134  */
3135 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3136 {
3137         ByteIO_t addr;
3138
3139         addr = CtlP->AiopIO[0] + 0x40;  /* 2nd AIOP */
3140         if (!on)
3141                 addr += 8;
3142         sOutB(addr + chan, 0);  /* apply or remove reset */
3143 }
3144
3145 /*  Resets the speaker controller on RocketModem II and III devices */
3146 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3147 {
3148         ByteIO_t addr;
3149
3150         /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3151         if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3152                 addr = CtlP->AiopIO[0] + 0x4F;
3153                 sOutB(addr, 0);
3154         }
3155
3156         /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3157         if ((model == MODEL_UPCI_RM3_8PORT)
3158             || (model == MODEL_UPCI_RM3_4PORT)) {
3159                 addr = CtlP->AiopIO[0] + 0x88;
3160                 sOutB(addr, 0);
3161         }
3162 }
3163
3164 /*  Returns the line number given the controller (board), aiop and channel number */
3165 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3166 {
3167         return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3168 }
3169
3170 /*
3171  *  Stores the line number associated with a given controller (board), aiop
3172  *  and channel number.
3173  *  Returns:  The line number assigned
3174  */
3175 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3176 {
3177         lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3178         return (nextLineNumber - 1);
3179 }