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iwlwifi: Thermal Throttling Management - Part 1
[wandboard.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
blobddd64fef3039218bd592cb66996ce5ba929f9c81
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
38
39 #include "iwl-eeprom.h"
40 #include "iwl-dev.h"
41 #include "iwl-core.h"
42 #include "iwl-io.h"
43 #include "iwl-sta.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
46 #include "iwl-6000-hw.h"
47
48 /* Highest firmware API version supported */
49 #define IWL5000_UCODE_API_MAX 2
50 #define IWL5150_UCODE_API_MAX 2
51
52 /* Lowest firmware API version supported */
53 #define IWL5000_UCODE_API_MIN 1
54 #define IWL5150_UCODE_API_MIN 1
55
56 #define IWL5000_FW_PRE "iwlwifi-5000-"
57 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
58 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
59
60 #define IWL5150_FW_PRE "iwlwifi-5150-"
61 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
62 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
63
64 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
65 IWL_TX_FIFO_AC3,
66 IWL_TX_FIFO_AC2,
67 IWL_TX_FIFO_AC1,
68 IWL_TX_FIFO_AC0,
69 IWL50_CMD_FIFO_NUM,
70 IWL_TX_FIFO_HCCA_1,
71 IWL_TX_FIFO_HCCA_2
72 };
73
74 /* FIXME: same implementation as 4965 */
75 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
76 {
77 unsigned long flags;
78
79 spin_lock_irqsave(&priv->lock, flags);
80
81 /* set stop master bit */
82 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
83
84 iwl_poll_direct_bit(priv, CSR_RESET,
85 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
86
87 spin_unlock_irqrestore(&priv->lock, flags);
88 IWL_DEBUG_INFO(priv, "stop master\n");
89
90 return 0;
91 }
92
93
94 int iwl5000_apm_init(struct iwl_priv *priv)
95 {
96 int ret = 0;
97
98 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
99 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
100
101 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
102 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
104
105 /* Set FH wait threshold to maximum (HW error during stress W/A) */
106 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
107
108 /* enable HAP INTA to move device L1a -> L0s */
109 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
110 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
111
112 if (priv->cfg->need_pll_cfg)
113 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
114
115 /* set "initialization complete" bit to move adapter
116 * D0U* --> D0A* state */
117 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
118
119 /* wait for clock stabilization */
120 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
121 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
122 if (ret < 0) {
123 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
124 return ret;
125 }
126
127 /* enable DMA */
128 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
129
130 udelay(20);
131
132 /* disable L1-Active */
133 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
134 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
135
136 return ret;
137 }
138
139 /* FIXME: this is identical to 4965 */
140 void iwl5000_apm_stop(struct iwl_priv *priv)
141 {
142 unsigned long flags;
143
144 iwl5000_apm_stop_master(priv);
145
146 spin_lock_irqsave(&priv->lock, flags);
147
148 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
149
150 udelay(10);
151
152 /* clear "init complete" move adapter D0A* --> D0U state */
153 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
154
155 spin_unlock_irqrestore(&priv->lock, flags);
156 }
157
158
159 int iwl5000_apm_reset(struct iwl_priv *priv)
160 {
161 int ret = 0;
162
163 iwl5000_apm_stop_master(priv);
164
165 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
166
167 udelay(10);
168
169
170 /* FIXME: put here L1A -L0S w/a */
171
172 if (priv->cfg->need_pll_cfg)
173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
174
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
178
179 /* wait for clock stabilization */
180 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
182 if (ret < 0) {
183 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
184 goto out;
185 }
186
187 /* enable DMA */
188 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
189
190 udelay(20);
191
192 /* disable L1-Active */
193 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
194 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
195 out:
196
197 return ret;
198 }
199
200
201 void iwl5000_nic_config(struct iwl_priv *priv)
202 {
203 unsigned long flags;
204 u16 radio_cfg;
205 u16 lctl;
206
207 spin_lock_irqsave(&priv->lock, flags);
208
209 lctl = iwl_pcie_link_ctl(priv);
210
211 /* HW bug W/A */
212 /* L1-ASPM is enabled by BIOS */
213 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
214 /* L1-APSM enabled: disable L0S */
215 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
216 else
217 /* L1-ASPM disabled: enable L0S */
218 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
219
220 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
221
222 /* write radio config values to register */
223 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
224 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
225 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
226 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
227 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
228
229 /* set CSR_HW_CONFIG_REG for uCode use */
230 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
231 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
232 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
233
234 /* W/A : NIC is stuck in a reset state after Early PCIe power off
235 * (PCIe power is lost before PERST# is asserted),
236 * causing ME FW to lose ownership and not being able to obtain it back.
237 */
238 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
239 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
240 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
241
242 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_1000) {
243 /* Setting digital SVR for 1000 card to 1.32V */
244 iwl_set_bits_mask_prph(priv, APMG_DIGITAL_SVR_REG,
245 APMG_SVR_DIGITAL_VOLTAGE_1_32,
246 ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
247 }
248
249 spin_unlock_irqrestore(&priv->lock, flags);
250 }
251
252
253
254 /*
255 * EEPROM
256 */
257 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
258 {
259 u16 offset = 0;
260
261 if ((address & INDIRECT_ADDRESS) == 0)
262 return address;
263
264 switch (address & INDIRECT_TYPE_MSK) {
265 case INDIRECT_HOST:
266 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
267 break;
268 case INDIRECT_GENERAL:
269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
270 break;
271 case INDIRECT_REGULATORY:
272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
273 break;
274 case INDIRECT_CALIBRATION:
275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
276 break;
277 case INDIRECT_PROCESS_ADJST:
278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
279 break;
280 case INDIRECT_OTHERS:
281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
282 break;
283 default:
284 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
285 address & INDIRECT_TYPE_MSK);
286 break;
287 }
288
289 /* translate the offset from words to byte */
290 return (address & ADDRESS_MSK) + (offset << 1);
291 }
292
293 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
294 {
295 struct iwl_eeprom_calib_hdr {
296 u8 version;
297 u8 pa_type;
298 u16 voltage;
299 } *hdr;
300
301 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
302 EEPROM_5000_CALIB_ALL);
303 return hdr->version;
304
305 }
306
307 static void iwl5000_gain_computation(struct iwl_priv *priv,
308 u32 average_noise[NUM_RX_CHAINS],
309 u16 min_average_noise_antenna_i,
310 u32 min_average_noise)
311 {
312 int i;
313 s32 delta_g;
314 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
315
316 /* Find Gain Code for the antennas B and C */
317 for (i = 1; i < NUM_RX_CHAINS; i++) {
318 if ((data->disconn_array[i])) {
319 data->delta_gain_code[i] = 0;
320 continue;
321 }
322 delta_g = (1000 * ((s32)average_noise[0] -
323 (s32)average_noise[i])) / 1500;
324 /* bound gain by 2 bits value max, 3rd bit is sign */
325 data->delta_gain_code[i] =
326 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
327
328 if (delta_g < 0)
329 /* set negative sign */
330 data->delta_gain_code[i] |= (1 << 2);
331 }
332
333 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
334 data->delta_gain_code[1], data->delta_gain_code[2]);
335
336 if (!data->radio_write) {
337 struct iwl_calib_chain_noise_gain_cmd cmd;
338
339 memset(&cmd, 0, sizeof(cmd));
340
341 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
342 cmd.hdr.first_group = 0;
343 cmd.hdr.groups_num = 1;
344 cmd.hdr.data_valid = 1;
345 cmd.delta_gain_1 = data->delta_gain_code[1];
346 cmd.delta_gain_2 = data->delta_gain_code[2];
347 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
348 sizeof(cmd), &cmd, NULL);
349
350 data->radio_write = 1;
351 data->state = IWL_CHAIN_NOISE_CALIBRATED;
352 }
353
354 data->chain_noise_a = 0;
355 data->chain_noise_b = 0;
356 data->chain_noise_c = 0;
357 data->chain_signal_a = 0;
358 data->chain_signal_b = 0;
359 data->chain_signal_c = 0;
360 data->beacon_count = 0;
361 }
362
363 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
364 {
365 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
366 int ret;
367
368 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
369 struct iwl_calib_chain_noise_reset_cmd cmd;
370 memset(&cmd, 0, sizeof(cmd));
371
372 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
373 cmd.hdr.first_group = 0;
374 cmd.hdr.groups_num = 1;
375 cmd.hdr.data_valid = 1;
376 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
377 sizeof(cmd), &cmd);
378 if (ret)
379 IWL_ERR(priv,
380 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
381 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
382 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
383 }
384 }
385
386 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
387 __le32 *tx_flags)
388 {
389 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
390 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
391 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
392 else
393 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
394 }
395
396 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
397 .min_nrg_cck = 95,
398 .max_nrg_cck = 0, /* not used, set to 0 */
399 .auto_corr_min_ofdm = 90,
400 .auto_corr_min_ofdm_mrc = 170,
401 .auto_corr_min_ofdm_x1 = 120,
402 .auto_corr_min_ofdm_mrc_x1 = 240,
403
404 .auto_corr_max_ofdm = 120,
405 .auto_corr_max_ofdm_mrc = 210,
406 .auto_corr_max_ofdm_x1 = 155,
407 .auto_corr_max_ofdm_mrc_x1 = 290,
408
409 .auto_corr_min_cck = 125,
410 .auto_corr_max_cck = 200,
411 .auto_corr_min_cck_mrc = 170,
412 .auto_corr_max_cck_mrc = 400,
413 .nrg_th_cck = 95,
414 .nrg_th_ofdm = 95,
415 };
416
417 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
418 .min_nrg_cck = 95,
419 .max_nrg_cck = 0, /* not used, set to 0 */
420 .auto_corr_min_ofdm = 90,
421 .auto_corr_min_ofdm_mrc = 170,
422 .auto_corr_min_ofdm_x1 = 105,
423 .auto_corr_min_ofdm_mrc_x1 = 220,
424
425 .auto_corr_max_ofdm = 120,
426 .auto_corr_max_ofdm_mrc = 210,
427 /* max = min for performance bug in 5150 DSP */
428 .auto_corr_max_ofdm_x1 = 105,
429 .auto_corr_max_ofdm_mrc_x1 = 220,
430
431 .auto_corr_min_cck = 125,
432 .auto_corr_max_cck = 200,
433 .auto_corr_min_cck_mrc = 170,
434 .auto_corr_max_cck_mrc = 400,
435 .nrg_th_cck = 95,
436 .nrg_th_ofdm = 95,
437 };
438
439 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
440 size_t offset)
441 {
442 u32 address = eeprom_indirect_address(priv, offset);
443 BUG_ON(address >= priv->cfg->eeprom_size);
444 return &priv->eeprom[address];
445 }
446
447 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
448 {
449 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
450 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
451 iwl_temp_calib_to_offset(priv);
452
453 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
454 }
455
456 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
457 {
458 /* want Celsius */
459 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
460 }
461
462 /*
463 * Calibration
464 */
465 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
466 {
467 struct iwl_calib_xtal_freq_cmd cmd;
468 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
469
470 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
471 cmd.hdr.first_group = 0;
472 cmd.hdr.groups_num = 1;
473 cmd.hdr.data_valid = 1;
474 cmd.cap_pin1 = (u8)xtal_calib[0];
475 cmd.cap_pin2 = (u8)xtal_calib[1];
476 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
477 (u8 *)&cmd, sizeof(cmd));
478 }
479
480 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
481 {
482 struct iwl_calib_cfg_cmd calib_cfg_cmd;
483 struct iwl_host_cmd cmd = {
484 .id = CALIBRATION_CFG_CMD,
485 .len = sizeof(struct iwl_calib_cfg_cmd),
486 .data = &calib_cfg_cmd,
487 };
488
489 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
490 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
491 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
492 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
493 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
494
495 return iwl_send_cmd(priv, &cmd);
496 }
497
498 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
499 struct iwl_rx_mem_buffer *rxb)
500 {
501 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
502 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
503 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
504 int index;
505
506 /* reduce the size of the length field itself */
507 len -= 4;
508
509 /* Define the order in which the results will be sent to the runtime
510 * uCode. iwl_send_calib_results sends them in a row according to their
511 * index. We sort them here */
512 switch (hdr->op_code) {
513 case IWL_PHY_CALIBRATE_DC_CMD:
514 index = IWL_CALIB_DC;
515 break;
516 case IWL_PHY_CALIBRATE_LO_CMD:
517 index = IWL_CALIB_LO;
518 break;
519 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
520 index = IWL_CALIB_TX_IQ;
521 break;
522 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
523 index = IWL_CALIB_TX_IQ_PERD;
524 break;
525 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
526 index = IWL_CALIB_BASE_BAND;
527 break;
528 default:
529 IWL_ERR(priv, "Unknown calibration notification %d\n",
530 hdr->op_code);
531 return;
532 }
533 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
534 }
535
536 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
537 struct iwl_rx_mem_buffer *rxb)
538 {
539 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
540 queue_work(priv->workqueue, &priv->restart);
541 }
542
543 /*
544 * ucode
545 */
546 static int iwl5000_load_section(struct iwl_priv *priv,
547 struct fw_desc *image,
548 u32 dst_addr)
549 {
550 dma_addr_t phy_addr = image->p_addr;
551 u32 byte_cnt = image->len;
552
553 iwl_write_direct32(priv,
554 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
555 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
556
557 iwl_write_direct32(priv,
558 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
559
560 iwl_write_direct32(priv,
561 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
562 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
563
564 iwl_write_direct32(priv,
565 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
566 (iwl_get_dma_hi_addr(phy_addr)
567 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
568
569 iwl_write_direct32(priv,
570 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
571 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
572 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
573 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
574
575 iwl_write_direct32(priv,
576 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
577 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
578 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
579 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
580
581 return 0;
582 }
583
584 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
585 struct fw_desc *inst_image,
586 struct fw_desc *data_image)
587 {
588 int ret = 0;
589
590 ret = iwl5000_load_section(priv, inst_image,
591 IWL50_RTC_INST_LOWER_BOUND);
592 if (ret)
593 return ret;
594
595 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
596 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
597 priv->ucode_write_complete, 5 * HZ);
598 if (ret == -ERESTARTSYS) {
599 IWL_ERR(priv, "Could not load the INST uCode section due "
600 "to interrupt\n");
601 return ret;
602 }
603 if (!ret) {
604 IWL_ERR(priv, "Could not load the INST uCode section\n");
605 return -ETIMEDOUT;
606 }
607
608 priv->ucode_write_complete = 0;
609
610 ret = iwl5000_load_section(
611 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
612 if (ret)
613 return ret;
614
615 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
616
617 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
618 priv->ucode_write_complete, 5 * HZ);
619 if (ret == -ERESTARTSYS) {
620 IWL_ERR(priv, "Could not load the INST uCode section due "
621 "to interrupt\n");
622 return ret;
623 } else if (!ret) {
624 IWL_ERR(priv, "Could not load the DATA uCode section\n");
625 return -ETIMEDOUT;
626 } else
627 ret = 0;
628
629 priv->ucode_write_complete = 0;
630
631 return ret;
632 }
633
634 int iwl5000_load_ucode(struct iwl_priv *priv)
635 {
636 int ret = 0;
637
638 /* check whether init ucode should be loaded, or rather runtime ucode */
639 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
640 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
641 ret = iwl5000_load_given_ucode(priv,
642 &priv->ucode_init, &priv->ucode_init_data);
643 if (!ret) {
644 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
645 priv->ucode_type = UCODE_INIT;
646 }
647 } else {
648 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
649 "Loading runtime ucode...\n");
650 ret = iwl5000_load_given_ucode(priv,
651 &priv->ucode_code, &priv->ucode_data);
652 if (!ret) {
653 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
654 priv->ucode_type = UCODE_RT;
655 }
656 }
657
658 return ret;
659 }
660
661 void iwl5000_init_alive_start(struct iwl_priv *priv)
662 {
663 int ret = 0;
664
665 /* Check alive response for "valid" sign from uCode */
666 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
667 /* We had an error bringing up the hardware, so take it
668 * all the way back down so we can try again */
669 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
670 goto restart;
671 }
672
673 /* initialize uCode was loaded... verify inst image.
674 * This is a paranoid check, because we would not have gotten the
675 * "initialize" alive if code weren't properly loaded. */
676 if (iwl_verify_ucode(priv)) {
677 /* Runtime instruction load was bad;
678 * take it all the way back down so we can try again */
679 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
680 goto restart;
681 }
682
683 iwl_clear_stations_table(priv);
684 ret = priv->cfg->ops->lib->alive_notify(priv);
685 if (ret) {
686 IWL_WARN(priv,
687 "Could not complete ALIVE transition: %d\n", ret);
688 goto restart;
689 }
690
691 iwl5000_send_calib_cfg(priv);
692 return;
693
694 restart:
695 /* real restart (first load init_ucode) */
696 queue_work(priv->workqueue, &priv->restart);
697 }
698
699 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
700 int txq_id, u32 index)
701 {
702 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
703 (index & 0xff) | (txq_id << 8));
704 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
705 }
706
707 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
708 struct iwl_tx_queue *txq,
709 int tx_fifo_id, int scd_retry)
710 {
711 int txq_id = txq->q.id;
712 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
713
714 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
715 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
716 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
717 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
718 IWL50_SCD_QUEUE_STTS_REG_MSK);
719
720 txq->sched_retry = scd_retry;
721
722 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
723 active ? "Activate" : "Deactivate",
724 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
725 }
726
727 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
728 {
729 struct iwl_wimax_coex_cmd coex_cmd;
730
731 memset(&coex_cmd, 0, sizeof(coex_cmd));
732
733 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
734 sizeof(coex_cmd), &coex_cmd);
735 }
736
737 int iwl5000_alive_notify(struct iwl_priv *priv)
738 {
739 u32 a;
740 unsigned long flags;
741 int i, chan;
742 u32 reg_val;
743
744 spin_lock_irqsave(&priv->lock, flags);
745
746 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
747 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
748 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
749 a += 4)
750 iwl_write_targ_mem(priv, a, 0);
751 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
752 a += 4)
753 iwl_write_targ_mem(priv, a, 0);
754 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
755 iwl_write_targ_mem(priv, a, 0);
756
757 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
758 priv->scd_bc_tbls.dma >> 10);
759
760 /* Enable DMA channel */
761 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
762 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
763 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
764 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
765
766 /* Update FH chicken bits */
767 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
768 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
769 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
770
771 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
772 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
773 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
774
775 /* initiate the queues */
776 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
777 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
778 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
779 iwl_write_targ_mem(priv, priv->scd_base_addr +
780 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
781 iwl_write_targ_mem(priv, priv->scd_base_addr +
782 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
783 sizeof(u32),
784 ((SCD_WIN_SIZE <<
785 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
786 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
787 ((SCD_FRAME_LIMIT <<
788 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
789 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
790 }
791
792 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
793 IWL_MASK(0, priv->hw_params.max_txq_num));
794
795 /* Activate all Tx DMA/FIFO channels */
796 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
797
798 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
799
800 /* map qos queues to fifos one-to-one */
801 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
802 int ac = iwl5000_default_queue_to_tx_fifo[i];
803 iwl_txq_ctx_activate(priv, i);
804 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
805 }
806 /* TODO - need to initialize those FIFOs inside the loop above,
807 * not only mark them as active */
808 iwl_txq_ctx_activate(priv, 4);
809 iwl_txq_ctx_activate(priv, 7);
810 iwl_txq_ctx_activate(priv, 8);
811 iwl_txq_ctx_activate(priv, 9);
812
813 spin_unlock_irqrestore(&priv->lock, flags);
814
815
816 iwl5000_send_wimax_coex(priv);
817
818 iwl5000_set_Xtal_calib(priv);
819 iwl_send_calib_results(priv);
820
821 return 0;
822 }
823
824 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
825 {
826 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
827 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
828 IWL_ERR(priv,
829 "invalid queues_num, should be between %d and %d\n",
830 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
831 return -EINVAL;
832 }
833
834 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
835 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
836 priv->hw_params.scd_bc_tbls_size =
837 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
838 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
839 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
840 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
841
842 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
843 case CSR_HW_REV_TYPE_6x00:
844 case CSR_HW_REV_TYPE_6x50:
845 priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
846 priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
847 break;
848 default:
849 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
850 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
851 }
852
853 priv->hw_params.max_bsm_size = 0;
854 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
855 BIT(IEEE80211_BAND_5GHZ);
856 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
857
858 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
859 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
860 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
861 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
862
863 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
864 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
865
866 /* Set initial sensitivity parameters */
867 /* Set initial calibration set */
868 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
869 case CSR_HW_REV_TYPE_5150:
870 priv->hw_params.sens = &iwl5150_sensitivity;
871 priv->hw_params.calib_init_cfg =
872 BIT(IWL_CALIB_DC) |
873 BIT(IWL_CALIB_LO) |
874 BIT(IWL_CALIB_TX_IQ) |
875 BIT(IWL_CALIB_BASE_BAND);
876
877 break;
878 default:
879 priv->hw_params.sens = &iwl5000_sensitivity;
880 priv->hw_params.calib_init_cfg =
881 BIT(IWL_CALIB_XTAL) |
882 BIT(IWL_CALIB_LO) |
883 BIT(IWL_CALIB_TX_IQ) |
884 BIT(IWL_CALIB_TX_IQ_PERD) |
885 BIT(IWL_CALIB_BASE_BAND);
886 break;
887 }
888
889 return 0;
890 }
891
892 /**
893 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
894 */
895 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
896 struct iwl_tx_queue *txq,
897 u16 byte_cnt)
898 {
899 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
900 int write_ptr = txq->q.write_ptr;
901 int txq_id = txq->q.id;
902 u8 sec_ctl = 0;
903 u8 sta_id = 0;
904 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
905 __le16 bc_ent;
906
907 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
908
909 if (txq_id != IWL_CMD_QUEUE_NUM) {
910 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
911 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
912
913 switch (sec_ctl & TX_CMD_SEC_MSK) {
914 case TX_CMD_SEC_CCM:
915 len += CCMP_MIC_LEN;
916 break;
917 case TX_CMD_SEC_TKIP:
918 len += TKIP_ICV_LEN;
919 break;
920 case TX_CMD_SEC_WEP:
921 len += WEP_IV_LEN + WEP_ICV_LEN;
922 break;
923 }
924 }
925
926 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
927
928 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
929
930 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
931 scd_bc_tbl[txq_id].
932 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
933 }
934
935 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
936 struct iwl_tx_queue *txq)
937 {
938 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
939 int txq_id = txq->q.id;
940 int read_ptr = txq->q.read_ptr;
941 u8 sta_id = 0;
942 __le16 bc_ent;
943
944 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
945
946 if (txq_id != IWL_CMD_QUEUE_NUM)
947 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
948
949 bc_ent = cpu_to_le16(1 | (sta_id << 12));
950 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
951
952 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
953 scd_bc_tbl[txq_id].
954 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
955 }
956
957 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
958 u16 txq_id)
959 {
960 u32 tbl_dw_addr;
961 u32 tbl_dw;
962 u16 scd_q2ratid;
963
964 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
965
966 tbl_dw_addr = priv->scd_base_addr +
967 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
968
969 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
970
971 if (txq_id & 0x1)
972 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
973 else
974 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
975
976 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
977
978 return 0;
979 }
980 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
981 {
982 /* Simply stop the queue, but don't change any configuration;
983 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
984 iwl_write_prph(priv,
985 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
986 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
987 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
988 }
989
990 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
991 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
992 {
993 unsigned long flags;
994 u16 ra_tid;
995
996 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
997 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
998 IWL_WARN(priv,
999 "queue number out of range: %d, must be %d to %d\n",
1000 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1001 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1002 return -EINVAL;
1003 }
1004
1005 ra_tid = BUILD_RAxTID(sta_id, tid);
1006
1007 /* Modify device's station table to Tx this TID */
1008 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1009
1010 spin_lock_irqsave(&priv->lock, flags);
1011
1012 /* Stop this Tx queue before configuring it */
1013 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1014
1015 /* Map receiver-address / traffic-ID to this queue */
1016 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1017
1018 /* Set this queue as a chain-building queue */
1019 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1020
1021 /* enable aggregations for the queue */
1022 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1023
1024 /* Place first TFD at index corresponding to start sequence number.
1025 * Assumes that ssn_idx is valid (!= 0xFFF) */
1026 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1027 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1028 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1029
1030 /* Set up Tx window size and frame limit for this queue */
1031 iwl_write_targ_mem(priv, priv->scd_base_addr +
1032 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1033 sizeof(u32),
1034 ((SCD_WIN_SIZE <<
1035 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1036 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1037 ((SCD_FRAME_LIMIT <<
1038 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1039 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1040
1041 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1042
1043 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1044 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1045
1046 spin_unlock_irqrestore(&priv->lock, flags);
1047
1048 return 0;
1049 }
1050
1051 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1052 u16 ssn_idx, u8 tx_fifo)
1053 {
1054 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1055 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1056 IWL_ERR(priv,
1057 "queue number out of range: %d, must be %d to %d\n",
1058 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1059 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1060 return -EINVAL;
1061 }
1062
1063 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1064
1065 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1066
1067 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1068 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1069 /* supposes that ssn_idx is valid (!= 0xFFF) */
1070 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1071
1072 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1073 iwl_txq_ctx_deactivate(priv, txq_id);
1074 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1075
1076 return 0;
1077 }
1078
1079 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1080 {
1081 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1082 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1083 memcpy(addsta, cmd, size);
1084 /* resrved in 5000 */
1085 addsta->rate_n_flags = cpu_to_le16(0);
1086 return size;
1087 }
1088
1089
1090 /*
1091 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1092 * must be called under priv->lock and mac access
1093 */
1094 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1095 {
1096 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1097 }
1098
1099
1100 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1101 {
1102 return le32_to_cpup((__le32 *)&tx_resp->status +
1103 tx_resp->frame_count) & MAX_SN;
1104 }
1105
1106 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1107 struct iwl_ht_agg *agg,
1108 struct iwl5000_tx_resp *tx_resp,
1109 int txq_id, u16 start_idx)
1110 {
1111 u16 status;
1112 struct agg_tx_status *frame_status = &tx_resp->status;
1113 struct ieee80211_tx_info *info = NULL;
1114 struct ieee80211_hdr *hdr = NULL;
1115 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1116 int i, sh, idx;
1117 u16 seq;
1118
1119 if (agg->wait_for_ba)
1120 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1121
1122 agg->frame_count = tx_resp->frame_count;
1123 agg->start_idx = start_idx;
1124 agg->rate_n_flags = rate_n_flags;
1125 agg->bitmap = 0;
1126
1127 /* # frames attempted by Tx command */
1128 if (agg->frame_count == 1) {
1129 /* Only one frame was attempted; no block-ack will arrive */
1130 status = le16_to_cpu(frame_status[0].status);
1131 idx = start_idx;
1132
1133 /* FIXME: code repetition */
1134 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1135 agg->frame_count, agg->start_idx, idx);
1136
1137 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1138 info->status.rates[0].count = tx_resp->failure_frame + 1;
1139 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1140 info->flags |= iwl_is_tx_success(status) ?
1141 IEEE80211_TX_STAT_ACK : 0;
1142 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1143
1144 /* FIXME: code repetition end */
1145
1146 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1147 status & 0xff, tx_resp->failure_frame);
1148 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1149
1150 agg->wait_for_ba = 0;
1151 } else {
1152 /* Two or more frames were attempted; expect block-ack */
1153 u64 bitmap = 0;
1154 int start = agg->start_idx;
1155
1156 /* Construct bit-map of pending frames within Tx window */
1157 for (i = 0; i < agg->frame_count; i++) {
1158 u16 sc;
1159 status = le16_to_cpu(frame_status[i].status);
1160 seq = le16_to_cpu(frame_status[i].sequence);
1161 idx = SEQ_TO_INDEX(seq);
1162 txq_id = SEQ_TO_QUEUE(seq);
1163
1164 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1165 AGG_TX_STATE_ABORT_MSK))
1166 continue;
1167
1168 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1169 agg->frame_count, txq_id, idx);
1170
1171 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1172
1173 sc = le16_to_cpu(hdr->seq_ctrl);
1174 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1175 IWL_ERR(priv,
1176 "BUG_ON idx doesn't match seq control"
1177 " idx=%d, seq_idx=%d, seq=%d\n",
1178 idx, SEQ_TO_SN(sc),
1179 hdr->seq_ctrl);
1180 return -1;
1181 }
1182
1183 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1184 i, idx, SEQ_TO_SN(sc));
1185
1186 sh = idx - start;
1187 if (sh > 64) {
1188 sh = (start - idx) + 0xff;
1189 bitmap = bitmap << sh;
1190 sh = 0;
1191 start = idx;
1192 } else if (sh < -64)
1193 sh = 0xff - (start - idx);
1194 else if (sh < 0) {
1195 sh = start - idx;
1196 start = idx;
1197 bitmap = bitmap << sh;
1198 sh = 0;
1199 }
1200 bitmap |= 1ULL << sh;
1201 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1202 start, (unsigned long long)bitmap);
1203 }
1204
1205 agg->bitmap = bitmap;
1206 agg->start_idx = start;
1207 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1208 agg->frame_count, agg->start_idx,
1209 (unsigned long long)agg->bitmap);
1210
1211 if (bitmap)
1212 agg->wait_for_ba = 1;
1213 }
1214 return 0;
1215 }
1216
1217 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1218 struct iwl_rx_mem_buffer *rxb)
1219 {
1220 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1221 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1222 int txq_id = SEQ_TO_QUEUE(sequence);
1223 int index = SEQ_TO_INDEX(sequence);
1224 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1225 struct ieee80211_tx_info *info;
1226 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1227 u32 status = le16_to_cpu(tx_resp->status.status);
1228 int tid;
1229 int sta_id;
1230 int freed;
1231
1232 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1233 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1234 "is out of range [0-%d] %d %d\n", txq_id,
1235 index, txq->q.n_bd, txq->q.write_ptr,
1236 txq->q.read_ptr);
1237 return;
1238 }
1239
1240 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1241 memset(&info->status, 0, sizeof(info->status));
1242
1243 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1244 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1245
1246 if (txq->sched_retry) {
1247 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1248 struct iwl_ht_agg *agg = NULL;
1249
1250 agg = &priv->stations[sta_id].tid[tid].agg;
1251
1252 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1253
1254 /* check if BAR is needed */
1255 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1256 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1257
1258 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1259 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1260 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1261 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1262 scd_ssn , index, txq_id, txq->swq_id);
1263
1264 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1265 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1266
1267 if (priv->mac80211_registered &&
1268 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1269 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1270 if (agg->state == IWL_AGG_OFF)
1271 iwl_wake_queue(priv, txq_id);
1272 else
1273 iwl_wake_queue(priv, txq->swq_id);
1274 }
1275 }
1276 } else {
1277 BUG_ON(txq_id != txq->swq_id);
1278
1279 info->status.rates[0].count = tx_resp->failure_frame + 1;
1280 info->flags |= iwl_is_tx_success(status) ?
1281 IEEE80211_TX_STAT_ACK : 0;
1282 iwl_hwrate_to_tx_control(priv,
1283 le32_to_cpu(tx_resp->rate_n_flags),
1284 info);
1285
1286 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1287 "0x%x retries %d\n",
1288 txq_id,
1289 iwl_get_tx_fail_reason(status), status,
1290 le32_to_cpu(tx_resp->rate_n_flags),
1291 tx_resp->failure_frame);
1292
1293 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1294 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1295 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1296
1297 if (priv->mac80211_registered &&
1298 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1299 iwl_wake_queue(priv, txq_id);
1300 }
1301
1302 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1303 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1304
1305 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1306 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1307 }
1308
1309 /* Currently 5000 is the superset of everything */
1310 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1311 {
1312 return len;
1313 }
1314
1315 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1316 {
1317 /* in 5000 the tx power calibration is done in uCode */
1318 priv->disable_tx_power_cal = 1;
1319 }
1320
1321 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1322 {
1323 /* init calibration handlers */
1324 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1325 iwl5000_rx_calib_result;
1326 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1327 iwl5000_rx_calib_complete;
1328 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1329 }
1330
1331
1332 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1333 {
1334 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1335 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1336 }
1337
1338 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1339 {
1340 int ret = 0;
1341 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1342 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1343 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1344
1345 if ((rxon1->flags == rxon2->flags) &&
1346 (rxon1->filter_flags == rxon2->filter_flags) &&
1347 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1348 (rxon1->ofdm_ht_single_stream_basic_rates ==
1349 rxon2->ofdm_ht_single_stream_basic_rates) &&
1350 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1351 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1352 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1353 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1354 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1355 (rxon1->rx_chain == rxon2->rx_chain) &&
1356 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1357 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1358 return 0;
1359 }
1360
1361 rxon_assoc.flags = priv->staging_rxon.flags;
1362 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1363 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1364 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1365 rxon_assoc.reserved1 = 0;
1366 rxon_assoc.reserved2 = 0;
1367 rxon_assoc.reserved3 = 0;
1368 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1369 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1370 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1371 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1372 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1373 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1374 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1375 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1376
1377 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1378 sizeof(rxon_assoc), &rxon_assoc, NULL);
1379 if (ret)
1380 return ret;
1381
1382 return ret;
1383 }
1384 int iwl5000_send_tx_power(struct iwl_priv *priv)
1385 {
1386 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1387 u8 tx_ant_cfg_cmd;
1388
1389 /* half dBm need to multiply */
1390 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1391 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1392 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1393
1394 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1395 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1396 else
1397 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1398
1399 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1400 sizeof(tx_power_cmd), &tx_power_cmd,
1401 NULL);
1402 }
1403
1404 void iwl5000_temperature(struct iwl_priv *priv)
1405 {
1406 /* store temperature from statistics (in Celsius) */
1407 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1408 iwl_tt_handler(priv);
1409 }
1410
1411 static void iwl5150_temperature(struct iwl_priv *priv)
1412 {
1413 u32 vt = 0;
1414 s32 offset = iwl_temp_calib_to_offset(priv);
1415
1416 vt = le32_to_cpu(priv->statistics.general.temperature);
1417 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1418 /* now vt hold the temperature in Kelvin */
1419 priv->temperature = KELVIN_TO_CELSIUS(vt);
1420 }
1421
1422 /* Calc max signal level (dBm) among 3 possible receivers */
1423 int iwl5000_calc_rssi(struct iwl_priv *priv,
1424 struct iwl_rx_phy_res *rx_resp)
1425 {
1426 /* data from PHY/DSP regarding signal strength, etc.,
1427 * contents are always there, not configurable by host
1428 */
1429 struct iwl5000_non_cfg_phy *ncphy =
1430 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1431 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1432 u8 agc;
1433
1434 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1435 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1436
1437 /* Find max rssi among 3 possible receivers.
1438 * These values are measured by the digital signal processor (DSP).
1439 * They should stay fairly constant even as the signal strength varies,
1440 * if the radio's automatic gain control (AGC) is working right.
1441 * AGC value (see below) will provide the "interesting" info.
1442 */
1443 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1444 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1445 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1446 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1447 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1448
1449 max_rssi = max_t(u32, rssi_a, rssi_b);
1450 max_rssi = max_t(u32, max_rssi, rssi_c);
1451
1452 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1453 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1454
1455 /* dBm = max_rssi dB - agc dB - constant.
1456 * Higher AGC (higher radio gain) means lower signal. */
1457 return max_rssi - agc - IWL49_RSSI_OFFSET;
1458 }
1459
1460 #define IWL5000_UCODE_GET(item) \
1461 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1462 u32 api_ver) \
1463 { \
1464 if (api_ver <= 2) \
1465 return le32_to_cpu(ucode->u.v1.item); \
1466 return le32_to_cpu(ucode->u.v2.item); \
1467 }
1468
1469 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1470 {
1471 if (api_ver <= 2)
1472 return UCODE_HEADER_SIZE(1);
1473 return UCODE_HEADER_SIZE(2);
1474 }
1475
1476 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1477 u32 api_ver)
1478 {
1479 if (api_ver <= 2)
1480 return 0;
1481 return le32_to_cpu(ucode->u.v2.build);
1482 }
1483
1484 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1485 u32 api_ver)
1486 {
1487 if (api_ver <= 2)
1488 return (u8 *) ucode->u.v1.data;
1489 return (u8 *) ucode->u.v2.data;
1490 }
1491
1492 IWL5000_UCODE_GET(inst_size);
1493 IWL5000_UCODE_GET(data_size);
1494 IWL5000_UCODE_GET(init_size);
1495 IWL5000_UCODE_GET(init_data_size);
1496 IWL5000_UCODE_GET(boot_size);
1497
1498 struct iwl_hcmd_ops iwl5000_hcmd = {
1499 .rxon_assoc = iwl5000_send_rxon_assoc,
1500 .commit_rxon = iwl_commit_rxon,
1501 .set_rxon_chain = iwl_set_rxon_chain,
1502 };
1503
1504 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1505 .get_hcmd_size = iwl5000_get_hcmd_size,
1506 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1507 .gain_computation = iwl5000_gain_computation,
1508 .chain_noise_reset = iwl5000_chain_noise_reset,
1509 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1510 .calc_rssi = iwl5000_calc_rssi,
1511 };
1512
1513 struct iwl_ucode_ops iwl5000_ucode = {
1514 .get_header_size = iwl5000_ucode_get_header_size,
1515 .get_build = iwl5000_ucode_get_build,
1516 .get_inst_size = iwl5000_ucode_get_inst_size,
1517 .get_data_size = iwl5000_ucode_get_data_size,
1518 .get_init_size = iwl5000_ucode_get_init_size,
1519 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1520 .get_boot_size = iwl5000_ucode_get_boot_size,
1521 .get_data = iwl5000_ucode_get_data,
1522 };
1523
1524 struct iwl_lib_ops iwl5000_lib = {
1525 .set_hw_params = iwl5000_hw_set_hw_params,
1526 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1527 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1528 .txq_set_sched = iwl5000_txq_set_sched,
1529 .txq_agg_enable = iwl5000_txq_agg_enable,
1530 .txq_agg_disable = iwl5000_txq_agg_disable,
1531 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1532 .txq_free_tfd = iwl_hw_txq_free_tfd,
1533 .txq_init = iwl_hw_tx_queue_init,
1534 .rx_handler_setup = iwl5000_rx_handler_setup,
1535 .setup_deferred_work = iwl5000_setup_deferred_work,
1536 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1537 .load_ucode = iwl5000_load_ucode,
1538 .init_alive_start = iwl5000_init_alive_start,
1539 .alive_notify = iwl5000_alive_notify,
1540 .send_tx_power = iwl5000_send_tx_power,
1541 .update_chain_flags = iwl_update_chain_flags,
1542 .apm_ops = {
1543 .init = iwl5000_apm_init,
1544 .reset = iwl5000_apm_reset,
1545 .stop = iwl5000_apm_stop,
1546 .config = iwl5000_nic_config,
1547 .set_pwr_src = iwl_set_pwr_src,
1548 },
1549 .eeprom_ops = {
1550 .regulatory_bands = {
1551 EEPROM_5000_REG_BAND_1_CHANNELS,
1552 EEPROM_5000_REG_BAND_2_CHANNELS,
1553 EEPROM_5000_REG_BAND_3_CHANNELS,
1554 EEPROM_5000_REG_BAND_4_CHANNELS,
1555 EEPROM_5000_REG_BAND_5_CHANNELS,
1556 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1557 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1558 },
1559 .verify_signature = iwlcore_eeprom_verify_signature,
1560 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1561 .release_semaphore = iwlcore_eeprom_release_semaphore,
1562 .calib_version = iwl5000_eeprom_calib_version,
1563 .query_addr = iwl5000_eeprom_query_addr,
1564 },
1565 .post_associate = iwl_post_associate,
1566 .isr = iwl_isr_ict,
1567 .config_ap = iwl_config_ap,
1568 .temp_ops = {
1569 .temperature = iwl5000_temperature,
1570 .set_ct_kill = iwl5000_set_ct_threshold,
1571 },
1572 };
1573
1574 static struct iwl_lib_ops iwl5150_lib = {
1575 .set_hw_params = iwl5000_hw_set_hw_params,
1576 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1577 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1578 .txq_set_sched = iwl5000_txq_set_sched,
1579 .txq_agg_enable = iwl5000_txq_agg_enable,
1580 .txq_agg_disable = iwl5000_txq_agg_disable,
1581 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1582 .txq_free_tfd = iwl_hw_txq_free_tfd,
1583 .txq_init = iwl_hw_tx_queue_init,
1584 .rx_handler_setup = iwl5000_rx_handler_setup,
1585 .setup_deferred_work = iwl5000_setup_deferred_work,
1586 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1587 .load_ucode = iwl5000_load_ucode,
1588 .init_alive_start = iwl5000_init_alive_start,
1589 .alive_notify = iwl5000_alive_notify,
1590 .send_tx_power = iwl5000_send_tx_power,
1591 .update_chain_flags = iwl_update_chain_flags,
1592 .apm_ops = {
1593 .init = iwl5000_apm_init,
1594 .reset = iwl5000_apm_reset,
1595 .stop = iwl5000_apm_stop,
1596 .config = iwl5000_nic_config,
1597 .set_pwr_src = iwl_set_pwr_src,
1598 },
1599 .eeprom_ops = {
1600 .regulatory_bands = {
1601 EEPROM_5000_REG_BAND_1_CHANNELS,
1602 EEPROM_5000_REG_BAND_2_CHANNELS,
1603 EEPROM_5000_REG_BAND_3_CHANNELS,
1604 EEPROM_5000_REG_BAND_4_CHANNELS,
1605 EEPROM_5000_REG_BAND_5_CHANNELS,
1606 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1607 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1608 },
1609 .verify_signature = iwlcore_eeprom_verify_signature,
1610 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1611 .release_semaphore = iwlcore_eeprom_release_semaphore,
1612 .calib_version = iwl5000_eeprom_calib_version,
1613 .query_addr = iwl5000_eeprom_query_addr,
1614 },
1615 .post_associate = iwl_post_associate,
1616 .isr = iwl_isr_ict,
1617 .config_ap = iwl_config_ap,
1618 .temp_ops = {
1619 .temperature = iwl5150_temperature,
1620 .set_ct_kill = iwl5150_set_ct_threshold,
1621 },
1622 };
1623
1624 struct iwl_ops iwl5000_ops = {
1625 .ucode = &iwl5000_ucode,
1626 .lib = &iwl5000_lib,
1627 .hcmd = &iwl5000_hcmd,
1628 .utils = &iwl5000_hcmd_utils,
1629 };
1630
1631 static struct iwl_ops iwl5150_ops = {
1632 .ucode = &iwl5000_ucode,
1633 .lib = &iwl5150_lib,
1634 .hcmd = &iwl5000_hcmd,
1635 .utils = &iwl5000_hcmd_utils,
1636 };
1637
1638 struct iwl_mod_params iwl50_mod_params = {
1639 .num_of_queues = IWL50_NUM_QUEUES,
1640 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1641 .amsdu_size_8K = 1,
1642 .restart_fw = 1,
1643 /* the rest are 0 by default */
1644 };
1645
1646
1647 struct iwl_cfg iwl5300_agn_cfg = {
1648 .name = "5300AGN",
1649 .fw_name_pre = IWL5000_FW_PRE,
1650 .ucode_api_max = IWL5000_UCODE_API_MAX,
1651 .ucode_api_min = IWL5000_UCODE_API_MIN,
1652 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1653 .ops = &iwl5000_ops,
1654 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1655 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1656 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1657 .mod_params = &iwl50_mod_params,
1658 .valid_tx_ant = ANT_ABC,
1659 .valid_rx_ant = ANT_ABC,
1660 .need_pll_cfg = true,
1661 };
1662
1663 struct iwl_cfg iwl5100_bg_cfg = {
1664 .name = "5100BG",
1665 .fw_name_pre = IWL5000_FW_PRE,
1666 .ucode_api_max = IWL5000_UCODE_API_MAX,
1667 .ucode_api_min = IWL5000_UCODE_API_MIN,
1668 .sku = IWL_SKU_G,
1669 .ops = &iwl5000_ops,
1670 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1671 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1672 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1673 .mod_params = &iwl50_mod_params,
1674 .valid_tx_ant = ANT_B,
1675 .valid_rx_ant = ANT_AB,
1676 .need_pll_cfg = true,
1677 };
1678
1679 struct iwl_cfg iwl5100_abg_cfg = {
1680 .name = "5100ABG",
1681 .fw_name_pre = IWL5000_FW_PRE,
1682 .ucode_api_max = IWL5000_UCODE_API_MAX,
1683 .ucode_api_min = IWL5000_UCODE_API_MIN,
1684 .sku = IWL_SKU_A|IWL_SKU_G,
1685 .ops = &iwl5000_ops,
1686 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1687 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1688 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1689 .mod_params = &iwl50_mod_params,
1690 .valid_tx_ant = ANT_B,
1691 .valid_rx_ant = ANT_AB,
1692 .need_pll_cfg = true,
1693 };
1694
1695 struct iwl_cfg iwl5100_agn_cfg = {
1696 .name = "5100AGN",
1697 .fw_name_pre = IWL5000_FW_PRE,
1698 .ucode_api_max = IWL5000_UCODE_API_MAX,
1699 .ucode_api_min = IWL5000_UCODE_API_MIN,
1700 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1701 .ops = &iwl5000_ops,
1702 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1703 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1704 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1705 .mod_params = &iwl50_mod_params,
1706 .valid_tx_ant = ANT_B,
1707 .valid_rx_ant = ANT_AB,
1708 .need_pll_cfg = true,
1709 };
1710
1711 struct iwl_cfg iwl5350_agn_cfg = {
1712 .name = "5350AGN",
1713 .fw_name_pre = IWL5000_FW_PRE,
1714 .ucode_api_max = IWL5000_UCODE_API_MAX,
1715 .ucode_api_min = IWL5000_UCODE_API_MIN,
1716 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1717 .ops = &iwl5000_ops,
1718 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1719 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1720 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1721 .mod_params = &iwl50_mod_params,
1722 .valid_tx_ant = ANT_ABC,
1723 .valid_rx_ant = ANT_ABC,
1724 .need_pll_cfg = true,
1725 };
1726
1727 struct iwl_cfg iwl5150_agn_cfg = {
1728 .name = "5150AGN",
1729 .fw_name_pre = IWL5150_FW_PRE,
1730 .ucode_api_max = IWL5150_UCODE_API_MAX,
1731 .ucode_api_min = IWL5150_UCODE_API_MIN,
1732 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1733 .ops = &iwl5150_ops,
1734 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1735 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1736 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1737 .mod_params = &iwl50_mod_params,
1738 .valid_tx_ant = ANT_A,
1739 .valid_rx_ant = ANT_AB,
1740 .need_pll_cfg = true,
1741 };
1742
1743 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1744 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1745
1746 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1747 MODULE_PARM_DESC(swcrypto50,
1748 "using software crypto engine (default 0 [hardware])\n");
1749 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1750 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1751 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1752 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1753 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1754 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1755 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1756 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
WandBoard kernel