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mv643xx_eth: introduce per-port register area pointer
[wandboard.git] / drivers / net / mv643xx_eth.c
blob0f73d85a6e9d17924fce5a0d8873bf6ace7a3839
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
54 #include <linux/io.h>
55 #include <linux/types.h>
56 #include <asm/system.h>
57
58 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
59 static char mv643xx_eth_driver_version[] = "1.4";
60
61
62 /*
63 * Registers shared between all ports.
64 */
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
79
80 /*
81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
83 */
84 #define PORT_CONFIG 0x0000
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT 0x0004
87 #define MAC_ADDR_LOW 0x0014
88 #define MAC_ADDR_HIGH 0x0018
89 #define SDMA_CONFIG 0x001c
90 #define PORT_SERIAL_CONTROL 0x003c
91 #define PORT_STATUS 0x0044
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define PORT_SPEED_MASK 0x00000030
95 #define PORT_SPEED_1000 0x00000010
96 #define PORT_SPEED_100 0x00000020
97 #define PORT_SPEED_10 0x00000000
98 #define FLOW_CONTROL_ENABLED 0x00000008
99 #define FULL_DUPLEX 0x00000004
100 #define LINK_UP 0x00000002
101 #define TXQ_COMMAND 0x0048
102 #define TXQ_FIX_PRIO_CONF 0x004c
103 #define TX_BW_RATE 0x0050
104 #define TX_BW_MTU 0x0058
105 #define TX_BW_BURST 0x005c
106 #define INT_CAUSE 0x0060
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x000003fc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT 0x0064
111 #define INT_EXT_LINK_PHY 0x00110000
112 #define INT_EXT_TX 0x000000ff
113 #define INT_MASK 0x0068
114 #define INT_MASK_EXT 0x006c
115 #define TX_FIFO_URGENT_THRESHOLD 0x0074
116 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117 #define TX_BW_RATE_MOVED 0x00e0
118 #define TX_BW_MTU_MOVED 0x00e8
119 #define TX_BW_BURST_MOVED 0x00ec
120 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121 #define RXQ_COMMAND 0x0280
122 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
126
127 /*
128 * Misc per-port registers.
129 */
130 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
134
135
136 /*
137 * SDMA configuration register.
138 */
139 #define RX_BURST_SIZE_16_64BIT (4 << 1)
140 #define BLM_RX_NO_SWAP (1 << 4)
141 #define BLM_TX_NO_SWAP (1 << 5)
142 #define TX_BURST_SIZE_16_64BIT (4 << 22)
143
144 #if defined(__BIG_ENDIAN)
145 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
146 (RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT)
148 #elif defined(__LITTLE_ENDIAN)
149 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
150 (RX_BURST_SIZE_16_64BIT | \
151 BLM_RX_NO_SWAP | \
152 BLM_TX_NO_SWAP | \
153 TX_BURST_SIZE_16_64BIT)
154 #else
155 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156 #endif
157
158
159 /*
160 * Port serial control register.
161 */
162 #define SET_MII_SPEED_TO_100 (1 << 24)
163 #define SET_GMII_SPEED_TO_1000 (1 << 23)
164 #define SET_FULL_DUPLEX_MODE (1 << 21)
165 #define MAX_RX_PACKET_9700BYTE (5 << 17)
166 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171 #define FORCE_LINK_PASS (1 << 1)
172 #define SERIAL_PORT_ENABLE (1 << 0)
173
174 #define DEFAULT_RX_QUEUE_SIZE 128
175 #define DEFAULT_TX_QUEUE_SIZE 256
176
177
178 /*
179 * RX/TX descriptors.
180 */
181 #if defined(__BIG_ENDIAN)
182 struct rx_desc {
183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
188 };
189
190 struct tx_desc {
191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
196 };
197 #elif defined(__LITTLE_ENDIAN)
198 struct rx_desc {
199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
204 };
205
206 struct tx_desc {
207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
212 };
213 #else
214 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
215 #endif
216
217 /* RX & TX descriptor command */
218 #define BUFFER_OWNED_BY_DMA 0x80000000
219
220 /* RX & TX descriptor status */
221 #define ERROR_SUMMARY 0x00000001
222
223 /* RX descriptor status */
224 #define LAYER_4_CHECKSUM_OK 0x40000000
225 #define RX_ENABLE_INTERRUPT 0x20000000
226 #define RX_FIRST_DESC 0x08000000
227 #define RX_LAST_DESC 0x04000000
228
229 /* TX descriptor command */
230 #define TX_ENABLE_INTERRUPT 0x00800000
231 #define GEN_CRC 0x00400000
232 #define TX_FIRST_DESC 0x00200000
233 #define TX_LAST_DESC 0x00100000
234 #define ZERO_PADDING 0x00080000
235 #define GEN_IP_V4_CHECKSUM 0x00040000
236 #define GEN_TCP_UDP_CHECKSUM 0x00020000
237 #define UDP_FRAME 0x00010000
238 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
239 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
240
241 #define TX_IHL_SHIFT 11
242
243
244 /* global *******************************************************************/
245 struct mv643xx_eth_shared_private {
246 /*
247 * Ethernet controller base address.
248 */
249 void __iomem *base;
250
251 /*
252 * Points at the right SMI instance to use.
253 */
254 struct mv643xx_eth_shared_private *smi;
255
256 /*
257 * Provides access to local SMI interface.
258 */
259 struct mii_bus *smi_bus;
260
261 /*
262 * If we have access to the error interrupt pin (which is
263 * somewhat misnamed as it not only reflects internal errors
264 * but also reflects SMI completion), use that to wait for
265 * SMI access completion instead of polling the SMI busy bit.
266 */
267 int err_interrupt;
268 wait_queue_head_t smi_busy_wait;
269
270 /*
271 * Per-port MBUS window access register value.
272 */
273 u32 win_protect;
274
275 /*
276 * Hardware-specific parameters.
277 */
278 unsigned int t_clk;
279 int extended_rx_coal_limit;
280 int tx_bw_control;
281 };
282
283 #define TX_BW_CONTROL_ABSENT 0
284 #define TX_BW_CONTROL_OLD_LAYOUT 1
285 #define TX_BW_CONTROL_NEW_LAYOUT 2
286
287
288 /* per-port *****************************************************************/
289 struct mib_counters {
290 u64 good_octets_received;
291 u32 bad_octets_received;
292 u32 internal_mac_transmit_err;
293 u32 good_frames_received;
294 u32 bad_frames_received;
295 u32 broadcast_frames_received;
296 u32 multicast_frames_received;
297 u32 frames_64_octets;
298 u32 frames_65_to_127_octets;
299 u32 frames_128_to_255_octets;
300 u32 frames_256_to_511_octets;
301 u32 frames_512_to_1023_octets;
302 u32 frames_1024_to_max_octets;
303 u64 good_octets_sent;
304 u32 good_frames_sent;
305 u32 excessive_collision;
306 u32 multicast_frames_sent;
307 u32 broadcast_frames_sent;
308 u32 unrec_mac_control_received;
309 u32 fc_sent;
310 u32 good_fc_received;
311 u32 bad_fc_received;
312 u32 undersize_received;
313 u32 fragments_received;
314 u32 oversize_received;
315 u32 jabber_received;
316 u32 mac_receive_error;
317 u32 bad_crc_event;
318 u32 collision;
319 u32 late_collision;
320 };
321
322 struct rx_queue {
323 int index;
324
325 int rx_ring_size;
326
327 int rx_desc_count;
328 int rx_curr_desc;
329 int rx_used_desc;
330
331 struct rx_desc *rx_desc_area;
332 dma_addr_t rx_desc_dma;
333 int rx_desc_area_size;
334 struct sk_buff **rx_skb;
335 };
336
337 struct tx_queue {
338 int index;
339
340 int tx_ring_size;
341
342 int tx_desc_count;
343 int tx_curr_desc;
344 int tx_used_desc;
345
346 struct tx_desc *tx_desc_area;
347 dma_addr_t tx_desc_dma;
348 int tx_desc_area_size;
349
350 struct sk_buff_head tx_skb;
351
352 unsigned long tx_packets;
353 unsigned long tx_bytes;
354 unsigned long tx_dropped;
355 };
356
357 struct mv643xx_eth_private {
358 struct mv643xx_eth_shared_private *shared;
359 void __iomem *base;
360 int port_num;
361
362 struct net_device *dev;
363
364 struct phy_device *phy;
365
366 struct timer_list mib_counters_timer;
367 spinlock_t mib_counters_lock;
368 struct mib_counters mib_counters;
369
370 struct work_struct tx_timeout_task;
371
372 struct napi_struct napi;
373 u8 work_link;
374 u8 work_tx;
375 u8 work_tx_end;
376 u8 work_rx;
377 u8 work_rx_refill;
378 u8 work_rx_oom;
379
380 int skb_size;
381 struct sk_buff_head rx_recycle;
382
383 /*
384 * RX state.
385 */
386 int default_rx_ring_size;
387 unsigned long rx_desc_sram_addr;
388 int rx_desc_sram_size;
389 int rxq_count;
390 struct timer_list rx_oom;
391 struct rx_queue rxq[8];
392
393 /*
394 * TX state.
395 */
396 int default_tx_ring_size;
397 unsigned long tx_desc_sram_addr;
398 int tx_desc_sram_size;
399 int txq_count;
400 struct tx_queue txq[8];
401 };
402
403
404 /* port register accessors **************************************************/
405 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
406 {
407 return readl(mp->shared->base + offset);
408 }
409
410 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
411 {
412 return readl(mp->base + offset);
413 }
414
415 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
416 {
417 writel(data, mp->shared->base + offset);
418 }
419
420 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
421 {
422 writel(data, mp->base + offset);
423 }
424
425
426 /* rxq/txq helper functions *************************************************/
427 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
428 {
429 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
430 }
431
432 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
433 {
434 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
435 }
436
437 static void rxq_enable(struct rx_queue *rxq)
438 {
439 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
440 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
441 }
442
443 static void rxq_disable(struct rx_queue *rxq)
444 {
445 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
446 u8 mask = 1 << rxq->index;
447
448 wrlp(mp, RXQ_COMMAND, mask << 8);
449 while (rdlp(mp, RXQ_COMMAND) & mask)
450 udelay(10);
451 }
452
453 static void txq_reset_hw_ptr(struct tx_queue *txq)
454 {
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
456 u32 addr;
457
458 addr = (u32)txq->tx_desc_dma;
459 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
460 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
461 }
462
463 static void txq_enable(struct tx_queue *txq)
464 {
465 struct mv643xx_eth_private *mp = txq_to_mp(txq);
466 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
467 }
468
469 static void txq_disable(struct tx_queue *txq)
470 {
471 struct mv643xx_eth_private *mp = txq_to_mp(txq);
472 u8 mask = 1 << txq->index;
473
474 wrlp(mp, TXQ_COMMAND, mask << 8);
475 while (rdlp(mp, TXQ_COMMAND) & mask)
476 udelay(10);
477 }
478
479 static void txq_maybe_wake(struct tx_queue *txq)
480 {
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
482 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
483
484 if (netif_tx_queue_stopped(nq)) {
485 __netif_tx_lock(nq, smp_processor_id());
486 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
487 netif_tx_wake_queue(nq);
488 __netif_tx_unlock(nq);
489 }
490 }
491
492
493 /* rx napi ******************************************************************/
494 static int rxq_process(struct rx_queue *rxq, int budget)
495 {
496 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
497 struct net_device_stats *stats = &mp->dev->stats;
498 int rx;
499
500 rx = 0;
501 while (rx < budget && rxq->rx_desc_count) {
502 struct rx_desc *rx_desc;
503 unsigned int cmd_sts;
504 struct sk_buff *skb;
505 u16 byte_cnt;
506
507 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
508
509 cmd_sts = rx_desc->cmd_sts;
510 if (cmd_sts & BUFFER_OWNED_BY_DMA)
511 break;
512 rmb();
513
514 skb = rxq->rx_skb[rxq->rx_curr_desc];
515 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
516
517 rxq->rx_curr_desc++;
518 if (rxq->rx_curr_desc == rxq->rx_ring_size)
519 rxq->rx_curr_desc = 0;
520
521 dma_unmap_single(NULL, rx_desc->buf_ptr,
522 rx_desc->buf_size, DMA_FROM_DEVICE);
523 rxq->rx_desc_count--;
524 rx++;
525
526 mp->work_rx_refill |= 1 << rxq->index;
527
528 byte_cnt = rx_desc->byte_cnt;
529
530 /*
531 * Update statistics.
532 *
533 * Note that the descriptor byte count includes 2 dummy
534 * bytes automatically inserted by the hardware at the
535 * start of the packet (which we don't count), and a 4
536 * byte CRC at the end of the packet (which we do count).
537 */
538 stats->rx_packets++;
539 stats->rx_bytes += byte_cnt - 2;
540
541 /*
542 * In case we received a packet without first / last bits
543 * on, or the error summary bit is set, the packet needs
544 * to be dropped.
545 */
546 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
547 (RX_FIRST_DESC | RX_LAST_DESC))
548 || (cmd_sts & ERROR_SUMMARY)) {
549 stats->rx_dropped++;
550
551 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
552 (RX_FIRST_DESC | RX_LAST_DESC)) {
553 if (net_ratelimit())
554 dev_printk(KERN_ERR, &mp->dev->dev,
555 "received packet spanning "
556 "multiple descriptors\n");
557 }
558
559 if (cmd_sts & ERROR_SUMMARY)
560 stats->rx_errors++;
561
562 dev_kfree_skb(skb);
563 } else {
564 /*
565 * The -4 is for the CRC in the trailer of the
566 * received packet
567 */
568 skb_put(skb, byte_cnt - 2 - 4);
569
570 if (cmd_sts & LAYER_4_CHECKSUM_OK)
571 skb->ip_summed = CHECKSUM_UNNECESSARY;
572 skb->protocol = eth_type_trans(skb, mp->dev);
573 netif_receive_skb(skb);
574 }
575 }
576
577 if (rx < budget)
578 mp->work_rx &= ~(1 << rxq->index);
579
580 return rx;
581 }
582
583 static int rxq_refill(struct rx_queue *rxq, int budget)
584 {
585 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
586 int refilled;
587
588 refilled = 0;
589 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
590 struct sk_buff *skb;
591 int unaligned;
592 int rx;
593
594 skb = __skb_dequeue(&mp->rx_recycle);
595 if (skb == NULL)
596 skb = dev_alloc_skb(mp->skb_size +
597 dma_get_cache_alignment() - 1);
598
599 if (skb == NULL) {
600 mp->work_rx_oom |= 1 << rxq->index;
601 goto oom;
602 }
603
604 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
605 if (unaligned)
606 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
607
608 refilled++;
609 rxq->rx_desc_count++;
610
611 rx = rxq->rx_used_desc++;
612 if (rxq->rx_used_desc == rxq->rx_ring_size)
613 rxq->rx_used_desc = 0;
614
615 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
616 mp->skb_size, DMA_FROM_DEVICE);
617 rxq->rx_desc_area[rx].buf_size = mp->skb_size;
618 rxq->rx_skb[rx] = skb;
619 wmb();
620 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
621 RX_ENABLE_INTERRUPT;
622 wmb();
623
624 /*
625 * The hardware automatically prepends 2 bytes of
626 * dummy data to each received packet, so that the
627 * IP header ends up 16-byte aligned.
628 */
629 skb_reserve(skb, 2);
630 }
631
632 if (refilled < budget)
633 mp->work_rx_refill &= ~(1 << rxq->index);
634
635 oom:
636 return refilled;
637 }
638
639
640 /* tx ***********************************************************************/
641 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
642 {
643 int frag;
644
645 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
646 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
647 if (fragp->size <= 8 && fragp->page_offset & 7)
648 return 1;
649 }
650
651 return 0;
652 }
653
654 static int txq_alloc_desc_index(struct tx_queue *txq)
655 {
656 int tx_desc_curr;
657
658 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
659
660 tx_desc_curr = txq->tx_curr_desc++;
661 if (txq->tx_curr_desc == txq->tx_ring_size)
662 txq->tx_curr_desc = 0;
663
664 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
665
666 return tx_desc_curr;
667 }
668
669 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
670 {
671 int nr_frags = skb_shinfo(skb)->nr_frags;
672 int frag;
673
674 for (frag = 0; frag < nr_frags; frag++) {
675 skb_frag_t *this_frag;
676 int tx_index;
677 struct tx_desc *desc;
678
679 this_frag = &skb_shinfo(skb)->frags[frag];
680 tx_index = txq_alloc_desc_index(txq);
681 desc = &txq->tx_desc_area[tx_index];
682
683 /*
684 * The last fragment will generate an interrupt
685 * which will free the skb on TX completion.
686 */
687 if (frag == nr_frags - 1) {
688 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
689 ZERO_PADDING | TX_LAST_DESC |
690 TX_ENABLE_INTERRUPT;
691 } else {
692 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
693 }
694
695 desc->l4i_chk = 0;
696 desc->byte_cnt = this_frag->size;
697 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
698 this_frag->page_offset,
699 this_frag->size,
700 DMA_TO_DEVICE);
701 }
702 }
703
704 static inline __be16 sum16_as_be(__sum16 sum)
705 {
706 return (__force __be16)sum;
707 }
708
709 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
710 {
711 struct mv643xx_eth_private *mp = txq_to_mp(txq);
712 int nr_frags = skb_shinfo(skb)->nr_frags;
713 int tx_index;
714 struct tx_desc *desc;
715 u32 cmd_sts;
716 u16 l4i_chk;
717 int length;
718
719 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
720 l4i_chk = 0;
721
722 if (skb->ip_summed == CHECKSUM_PARTIAL) {
723 int tag_bytes;
724
725 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
726 skb->protocol != htons(ETH_P_8021Q));
727
728 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
729 if (unlikely(tag_bytes & ~12)) {
730 if (skb_checksum_help(skb) == 0)
731 goto no_csum;
732 kfree_skb(skb);
733 return 1;
734 }
735
736 if (tag_bytes & 4)
737 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
738 if (tag_bytes & 8)
739 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
740
741 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
742 GEN_IP_V4_CHECKSUM |
743 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
744
745 switch (ip_hdr(skb)->protocol) {
746 case IPPROTO_UDP:
747 cmd_sts |= UDP_FRAME;
748 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
749 break;
750 case IPPROTO_TCP:
751 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
752 break;
753 default:
754 BUG();
755 }
756 } else {
757 no_csum:
758 /* Errata BTS #50, IHL must be 5 if no HW checksum */
759 cmd_sts |= 5 << TX_IHL_SHIFT;
760 }
761
762 tx_index = txq_alloc_desc_index(txq);
763 desc = &txq->tx_desc_area[tx_index];
764
765 if (nr_frags) {
766 txq_submit_frag_skb(txq, skb);
767 length = skb_headlen(skb);
768 } else {
769 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
770 length = skb->len;
771 }
772
773 desc->l4i_chk = l4i_chk;
774 desc->byte_cnt = length;
775 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
776
777 __skb_queue_tail(&txq->tx_skb, skb);
778
779 /* ensure all other descriptors are written before first cmd_sts */
780 wmb();
781 desc->cmd_sts = cmd_sts;
782
783 /* clear TX_END status */
784 mp->work_tx_end &= ~(1 << txq->index);
785
786 /* ensure all descriptors are written before poking hardware */
787 wmb();
788 txq_enable(txq);
789
790 txq->tx_desc_count += nr_frags + 1;
791
792 return 0;
793 }
794
795 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
796 {
797 struct mv643xx_eth_private *mp = netdev_priv(dev);
798 int queue;
799 struct tx_queue *txq;
800 struct netdev_queue *nq;
801
802 queue = skb_get_queue_mapping(skb);
803 txq = mp->txq + queue;
804 nq = netdev_get_tx_queue(dev, queue);
805
806 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
807 txq->tx_dropped++;
808 dev_printk(KERN_DEBUG, &dev->dev,
809 "failed to linearize skb with tiny "
810 "unaligned fragment\n");
811 return NETDEV_TX_BUSY;
812 }
813
814 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
815 if (net_ratelimit())
816 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
817 kfree_skb(skb);
818 return NETDEV_TX_OK;
819 }
820
821 if (!txq_submit_skb(txq, skb)) {
822 int entries_left;
823
824 txq->tx_bytes += skb->len;
825 txq->tx_packets++;
826 dev->trans_start = jiffies;
827
828 entries_left = txq->tx_ring_size - txq->tx_desc_count;
829 if (entries_left < MAX_SKB_FRAGS + 1)
830 netif_tx_stop_queue(nq);
831 }
832
833 return NETDEV_TX_OK;
834 }
835
836
837 /* tx napi ******************************************************************/
838 static void txq_kick(struct tx_queue *txq)
839 {
840 struct mv643xx_eth_private *mp = txq_to_mp(txq);
841 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
842 u32 hw_desc_ptr;
843 u32 expected_ptr;
844
845 __netif_tx_lock(nq, smp_processor_id());
846
847 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
848 goto out;
849
850 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
851 expected_ptr = (u32)txq->tx_desc_dma +
852 txq->tx_curr_desc * sizeof(struct tx_desc);
853
854 if (hw_desc_ptr != expected_ptr)
855 txq_enable(txq);
856
857 out:
858 __netif_tx_unlock(nq);
859
860 mp->work_tx_end &= ~(1 << txq->index);
861 }
862
863 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
864 {
865 struct mv643xx_eth_private *mp = txq_to_mp(txq);
866 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
867 int reclaimed;
868
869 __netif_tx_lock(nq, smp_processor_id());
870
871 reclaimed = 0;
872 while (reclaimed < budget && txq->tx_desc_count > 0) {
873 int tx_index;
874 struct tx_desc *desc;
875 u32 cmd_sts;
876 struct sk_buff *skb;
877
878 tx_index = txq->tx_used_desc;
879 desc = &txq->tx_desc_area[tx_index];
880 cmd_sts = desc->cmd_sts;
881
882 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
883 if (!force)
884 break;
885 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
886 }
887
888 txq->tx_used_desc = tx_index + 1;
889 if (txq->tx_used_desc == txq->tx_ring_size)
890 txq->tx_used_desc = 0;
891
892 reclaimed++;
893 txq->tx_desc_count--;
894
895 skb = NULL;
896 if (cmd_sts & TX_LAST_DESC)
897 skb = __skb_dequeue(&txq->tx_skb);
898
899 if (cmd_sts & ERROR_SUMMARY) {
900 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
901 mp->dev->stats.tx_errors++;
902 }
903
904 if (cmd_sts & TX_FIRST_DESC) {
905 dma_unmap_single(NULL, desc->buf_ptr,
906 desc->byte_cnt, DMA_TO_DEVICE);
907 } else {
908 dma_unmap_page(NULL, desc->buf_ptr,
909 desc->byte_cnt, DMA_TO_DEVICE);
910 }
911
912 if (skb != NULL) {
913 if (skb_queue_len(&mp->rx_recycle) <
914 mp->default_rx_ring_size &&
915 skb_recycle_check(skb, mp->skb_size))
916 __skb_queue_head(&mp->rx_recycle, skb);
917 else
918 dev_kfree_skb(skb);
919 }
920 }
921
922 __netif_tx_unlock(nq);
923
924 if (reclaimed < budget)
925 mp->work_tx &= ~(1 << txq->index);
926
927 return reclaimed;
928 }
929
930
931 /* tx rate control **********************************************************/
932 /*
933 * Set total maximum TX rate (shared by all TX queues for this port)
934 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
935 */
936 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
937 {
938 int token_rate;
939 int mtu;
940 int bucket_size;
941
942 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
943 if (token_rate > 1023)
944 token_rate = 1023;
945
946 mtu = (mp->dev->mtu + 255) >> 8;
947 if (mtu > 63)
948 mtu = 63;
949
950 bucket_size = (burst + 255) >> 8;
951 if (bucket_size > 65535)
952 bucket_size = 65535;
953
954 switch (mp->shared->tx_bw_control) {
955 case TX_BW_CONTROL_OLD_LAYOUT:
956 wrlp(mp, TX_BW_RATE, token_rate);
957 wrlp(mp, TX_BW_MTU, mtu);
958 wrlp(mp, TX_BW_BURST, bucket_size);
959 break;
960 case TX_BW_CONTROL_NEW_LAYOUT:
961 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
962 wrlp(mp, TX_BW_MTU_MOVED, mtu);
963 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
964 break;
965 }
966 }
967
968 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
969 {
970 struct mv643xx_eth_private *mp = txq_to_mp(txq);
971 int token_rate;
972 int bucket_size;
973
974 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
975 if (token_rate > 1023)
976 token_rate = 1023;
977
978 bucket_size = (burst + 255) >> 8;
979 if (bucket_size > 65535)
980 bucket_size = 65535;
981
982 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
983 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
984 }
985
986 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
987 {
988 struct mv643xx_eth_private *mp = txq_to_mp(txq);
989 int off;
990 u32 val;
991
992 /*
993 * Turn on fixed priority mode.
994 */
995 off = 0;
996 switch (mp->shared->tx_bw_control) {
997 case TX_BW_CONTROL_OLD_LAYOUT:
998 off = TXQ_FIX_PRIO_CONF;
999 break;
1000 case TX_BW_CONTROL_NEW_LAYOUT:
1001 off = TXQ_FIX_PRIO_CONF_MOVED;
1002 break;
1003 }
1004
1005 if (off) {
1006 val = rdlp(mp, off);
1007 val |= 1 << txq->index;
1008 wrlp(mp, off, val);
1009 }
1010 }
1011
1012 static void txq_set_wrr(struct tx_queue *txq, int weight)
1013 {
1014 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1015 int off;
1016 u32 val;
1017
1018 /*
1019 * Turn off fixed priority mode.
1020 */
1021 off = 0;
1022 switch (mp->shared->tx_bw_control) {
1023 case TX_BW_CONTROL_OLD_LAYOUT:
1024 off = TXQ_FIX_PRIO_CONF;
1025 break;
1026 case TX_BW_CONTROL_NEW_LAYOUT:
1027 off = TXQ_FIX_PRIO_CONF_MOVED;
1028 break;
1029 }
1030
1031 if (off) {
1032 val = rdlp(mp, off);
1033 val &= ~(1 << txq->index);
1034 wrlp(mp, off, val);
1035
1036 /*
1037 * Configure WRR weight for this queue.
1038 */
1039
1040 val = rdlp(mp, off);
1041 val = (val & ~0xff) | (weight & 0xff);
1042 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
1043 }
1044 }
1045
1046
1047 /* mii management interface *************************************************/
1048 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1049 {
1050 struct mv643xx_eth_shared_private *msp = dev_id;
1051
1052 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1053 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1054 wake_up(&msp->smi_busy_wait);
1055 return IRQ_HANDLED;
1056 }
1057
1058 return IRQ_NONE;
1059 }
1060
1061 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1062 {
1063 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1064 }
1065
1066 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1067 {
1068 if (msp->err_interrupt == NO_IRQ) {
1069 int i;
1070
1071 for (i = 0; !smi_is_done(msp); i++) {
1072 if (i == 10)
1073 return -ETIMEDOUT;
1074 msleep(10);
1075 }
1076
1077 return 0;
1078 }
1079
1080 if (!smi_is_done(msp)) {
1081 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1082 msecs_to_jiffies(100));
1083 if (!smi_is_done(msp))
1084 return -ETIMEDOUT;
1085 }
1086
1087 return 0;
1088 }
1089
1090 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1091 {
1092 struct mv643xx_eth_shared_private *msp = bus->priv;
1093 void __iomem *smi_reg = msp->base + SMI_REG;
1094 int ret;
1095
1096 if (smi_wait_ready(msp)) {
1097 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1098 return -ETIMEDOUT;
1099 }
1100
1101 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1102
1103 if (smi_wait_ready(msp)) {
1104 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1105 return -ETIMEDOUT;
1106 }
1107
1108 ret = readl(smi_reg);
1109 if (!(ret & SMI_READ_VALID)) {
1110 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
1111 return -ENODEV;
1112 }
1113
1114 return ret & 0xffff;
1115 }
1116
1117 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1118 {
1119 struct mv643xx_eth_shared_private *msp = bus->priv;
1120 void __iomem *smi_reg = msp->base + SMI_REG;
1121
1122 if (smi_wait_ready(msp)) {
1123 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1124 return -ETIMEDOUT;
1125 }
1126
1127 writel(SMI_OPCODE_WRITE | (reg << 21) |
1128 (addr << 16) | (val & 0xffff), smi_reg);
1129
1130 if (smi_wait_ready(msp)) {
1131 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1132 return -ETIMEDOUT;
1133 }
1134
1135 return 0;
1136 }
1137
1138
1139 /* statistics ***************************************************************/
1140 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1141 {
1142 struct mv643xx_eth_private *mp = netdev_priv(dev);
1143 struct net_device_stats *stats = &dev->stats;
1144 unsigned long tx_packets = 0;
1145 unsigned long tx_bytes = 0;
1146 unsigned long tx_dropped = 0;
1147 int i;
1148
1149 for (i = 0; i < mp->txq_count; i++) {
1150 struct tx_queue *txq = mp->txq + i;
1151
1152 tx_packets += txq->tx_packets;
1153 tx_bytes += txq->tx_bytes;
1154 tx_dropped += txq->tx_dropped;
1155 }
1156
1157 stats->tx_packets = tx_packets;
1158 stats->tx_bytes = tx_bytes;
1159 stats->tx_dropped = tx_dropped;
1160
1161 return stats;
1162 }
1163
1164 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1165 {
1166 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1167 }
1168
1169 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1170 {
1171 int i;
1172
1173 for (i = 0; i < 0x80; i += 4)
1174 mib_read(mp, i);
1175 }
1176
1177 static void mib_counters_update(struct mv643xx_eth_private *mp)
1178 {
1179 struct mib_counters *p = &mp->mib_counters;
1180
1181 spin_lock(&mp->mib_counters_lock);
1182 p->good_octets_received += mib_read(mp, 0x00);
1183 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1184 p->bad_octets_received += mib_read(mp, 0x08);
1185 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1186 p->good_frames_received += mib_read(mp, 0x10);
1187 p->bad_frames_received += mib_read(mp, 0x14);
1188 p->broadcast_frames_received += mib_read(mp, 0x18);
1189 p->multicast_frames_received += mib_read(mp, 0x1c);
1190 p->frames_64_octets += mib_read(mp, 0x20);
1191 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1192 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1193 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1194 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1195 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1196 p->good_octets_sent += mib_read(mp, 0x38);
1197 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1198 p->good_frames_sent += mib_read(mp, 0x40);
1199 p->excessive_collision += mib_read(mp, 0x44);
1200 p->multicast_frames_sent += mib_read(mp, 0x48);
1201 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1202 p->unrec_mac_control_received += mib_read(mp, 0x50);
1203 p->fc_sent += mib_read(mp, 0x54);
1204 p->good_fc_received += mib_read(mp, 0x58);
1205 p->bad_fc_received += mib_read(mp, 0x5c);
1206 p->undersize_received += mib_read(mp, 0x60);
1207 p->fragments_received += mib_read(mp, 0x64);
1208 p->oversize_received += mib_read(mp, 0x68);
1209 p->jabber_received += mib_read(mp, 0x6c);
1210 p->mac_receive_error += mib_read(mp, 0x70);
1211 p->bad_crc_event += mib_read(mp, 0x74);
1212 p->collision += mib_read(mp, 0x78);
1213 p->late_collision += mib_read(mp, 0x7c);
1214 spin_unlock(&mp->mib_counters_lock);
1215
1216 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1217 }
1218
1219 static void mib_counters_timer_wrapper(unsigned long _mp)
1220 {
1221 struct mv643xx_eth_private *mp = (void *)_mp;
1222
1223 mib_counters_update(mp);
1224 }
1225
1226
1227 /* ethtool ******************************************************************/
1228 struct mv643xx_eth_stats {
1229 char stat_string[ETH_GSTRING_LEN];
1230 int sizeof_stat;
1231 int netdev_off;
1232 int mp_off;
1233 };
1234
1235 #define SSTAT(m) \
1236 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1237 offsetof(struct net_device, stats.m), -1 }
1238
1239 #define MIBSTAT(m) \
1240 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1241 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1242
1243 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1244 SSTAT(rx_packets),
1245 SSTAT(tx_packets),
1246 SSTAT(rx_bytes),
1247 SSTAT(tx_bytes),
1248 SSTAT(rx_errors),
1249 SSTAT(tx_errors),
1250 SSTAT(rx_dropped),
1251 SSTAT(tx_dropped),
1252 MIBSTAT(good_octets_received),
1253 MIBSTAT(bad_octets_received),
1254 MIBSTAT(internal_mac_transmit_err),
1255 MIBSTAT(good_frames_received),
1256 MIBSTAT(bad_frames_received),
1257 MIBSTAT(broadcast_frames_received),
1258 MIBSTAT(multicast_frames_received),
1259 MIBSTAT(frames_64_octets),
1260 MIBSTAT(frames_65_to_127_octets),
1261 MIBSTAT(frames_128_to_255_octets),
1262 MIBSTAT(frames_256_to_511_octets),
1263 MIBSTAT(frames_512_to_1023_octets),
1264 MIBSTAT(frames_1024_to_max_octets),
1265 MIBSTAT(good_octets_sent),
1266 MIBSTAT(good_frames_sent),
1267 MIBSTAT(excessive_collision),
1268 MIBSTAT(multicast_frames_sent),
1269 MIBSTAT(broadcast_frames_sent),
1270 MIBSTAT(unrec_mac_control_received),
1271 MIBSTAT(fc_sent),
1272 MIBSTAT(good_fc_received),
1273 MIBSTAT(bad_fc_received),
1274 MIBSTAT(undersize_received),
1275 MIBSTAT(fragments_received),
1276 MIBSTAT(oversize_received),
1277 MIBSTAT(jabber_received),
1278 MIBSTAT(mac_receive_error),
1279 MIBSTAT(bad_crc_event),
1280 MIBSTAT(collision),
1281 MIBSTAT(late_collision),
1282 };
1283
1284 static int
1285 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1286 {
1287 struct mv643xx_eth_private *mp = netdev_priv(dev);
1288 int err;
1289
1290 err = phy_read_status(mp->phy);
1291 if (err == 0)
1292 err = phy_ethtool_gset(mp->phy, cmd);
1293
1294 /*
1295 * The MAC does not support 1000baseT_Half.
1296 */
1297 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1298 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1299
1300 return err;
1301 }
1302
1303 static int
1304 mv643xx_eth_get_settings_phyless(struct net_device *dev,
1305 struct ethtool_cmd *cmd)
1306 {
1307 struct mv643xx_eth_private *mp = netdev_priv(dev);
1308 u32 port_status;
1309
1310 port_status = rdlp(mp, PORT_STATUS);
1311
1312 cmd->supported = SUPPORTED_MII;
1313 cmd->advertising = ADVERTISED_MII;
1314 switch (port_status & PORT_SPEED_MASK) {
1315 case PORT_SPEED_10:
1316 cmd->speed = SPEED_10;
1317 break;
1318 case PORT_SPEED_100:
1319 cmd->speed = SPEED_100;
1320 break;
1321 case PORT_SPEED_1000:
1322 cmd->speed = SPEED_1000;
1323 break;
1324 default:
1325 cmd->speed = -1;
1326 break;
1327 }
1328 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1329 cmd->port = PORT_MII;
1330 cmd->phy_address = 0;
1331 cmd->transceiver = XCVR_INTERNAL;
1332 cmd->autoneg = AUTONEG_DISABLE;
1333 cmd->maxtxpkt = 1;
1334 cmd->maxrxpkt = 1;
1335
1336 return 0;
1337 }
1338
1339 static int
1340 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1341 {
1342 struct mv643xx_eth_private *mp = netdev_priv(dev);
1343
1344 /*
1345 * The MAC does not support 1000baseT_Half.
1346 */
1347 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1348
1349 return phy_ethtool_sset(mp->phy, cmd);
1350 }
1351
1352 static int
1353 mv643xx_eth_set_settings_phyless(struct net_device *dev,
1354 struct ethtool_cmd *cmd)
1355 {
1356 return -EINVAL;
1357 }
1358
1359 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1360 struct ethtool_drvinfo *drvinfo)
1361 {
1362 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1363 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1364 strncpy(drvinfo->fw_version, "N/A", 32);
1365 strncpy(drvinfo->bus_info, "platform", 32);
1366 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1367 }
1368
1369 static int mv643xx_eth_nway_reset(struct net_device *dev)
1370 {
1371 struct mv643xx_eth_private *mp = netdev_priv(dev);
1372
1373 return genphy_restart_aneg(mp->phy);
1374 }
1375
1376 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1377 {
1378 return -EINVAL;
1379 }
1380
1381 static u32 mv643xx_eth_get_link(struct net_device *dev)
1382 {
1383 return !!netif_carrier_ok(dev);
1384 }
1385
1386 static void mv643xx_eth_get_strings(struct net_device *dev,
1387 uint32_t stringset, uint8_t *data)
1388 {
1389 int i;
1390
1391 if (stringset == ETH_SS_STATS) {
1392 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1393 memcpy(data + i * ETH_GSTRING_LEN,
1394 mv643xx_eth_stats[i].stat_string,
1395 ETH_GSTRING_LEN);
1396 }
1397 }
1398 }
1399
1400 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1401 struct ethtool_stats *stats,
1402 uint64_t *data)
1403 {
1404 struct mv643xx_eth_private *mp = netdev_priv(dev);
1405 int i;
1406
1407 mv643xx_eth_get_stats(dev);
1408 mib_counters_update(mp);
1409
1410 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1411 const struct mv643xx_eth_stats *stat;
1412 void *p;
1413
1414 stat = mv643xx_eth_stats + i;
1415
1416 if (stat->netdev_off >= 0)
1417 p = ((void *)mp->dev) + stat->netdev_off;
1418 else
1419 p = ((void *)mp) + stat->mp_off;
1420
1421 data[i] = (stat->sizeof_stat == 8) ?
1422 *(uint64_t *)p : *(uint32_t *)p;
1423 }
1424 }
1425
1426 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1427 {
1428 if (sset == ETH_SS_STATS)
1429 return ARRAY_SIZE(mv643xx_eth_stats);
1430
1431 return -EOPNOTSUPP;
1432 }
1433
1434 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1435 .get_settings = mv643xx_eth_get_settings,
1436 .set_settings = mv643xx_eth_set_settings,
1437 .get_drvinfo = mv643xx_eth_get_drvinfo,
1438 .nway_reset = mv643xx_eth_nway_reset,
1439 .get_link = mv643xx_eth_get_link,
1440 .set_sg = ethtool_op_set_sg,
1441 .get_strings = mv643xx_eth_get_strings,
1442 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1443 .get_sset_count = mv643xx_eth_get_sset_count,
1444 };
1445
1446 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1447 .get_settings = mv643xx_eth_get_settings_phyless,
1448 .set_settings = mv643xx_eth_set_settings_phyless,
1449 .get_drvinfo = mv643xx_eth_get_drvinfo,
1450 .nway_reset = mv643xx_eth_nway_reset_phyless,
1451 .get_link = mv643xx_eth_get_link,
1452 .set_sg = ethtool_op_set_sg,
1453 .get_strings = mv643xx_eth_get_strings,
1454 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1455 .get_sset_count = mv643xx_eth_get_sset_count,
1456 };
1457
1458
1459 /* address handling *********************************************************/
1460 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1461 {
1462 unsigned int mac_h;
1463 unsigned int mac_l;
1464
1465 mac_h = rdlp(mp, MAC_ADDR_HIGH);
1466 mac_l = rdlp(mp, MAC_ADDR_LOW);
1467
1468 addr[0] = (mac_h >> 24) & 0xff;
1469 addr[1] = (mac_h >> 16) & 0xff;
1470 addr[2] = (mac_h >> 8) & 0xff;
1471 addr[3] = mac_h & 0xff;
1472 addr[4] = (mac_l >> 8) & 0xff;
1473 addr[5] = mac_l & 0xff;
1474 }
1475
1476 static void init_mac_tables(struct mv643xx_eth_private *mp)
1477 {
1478 int i;
1479
1480 for (i = 0; i < 0x100; i += 4) {
1481 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1482 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1483 }
1484
1485 for (i = 0; i < 0x10; i += 4)
1486 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1487 }
1488
1489 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1490 int table, unsigned char entry)
1491 {
1492 unsigned int table_reg;
1493
1494 /* Set "accepts frame bit" at specified table entry */
1495 table_reg = rdl(mp, table + (entry & 0xfc));
1496 table_reg |= 0x01 << (8 * (entry & 3));
1497 wrl(mp, table + (entry & 0xfc), table_reg);
1498 }
1499
1500 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1501 {
1502 unsigned int mac_h;
1503 unsigned int mac_l;
1504 int table;
1505
1506 mac_l = (addr[4] << 8) | addr[5];
1507 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1508
1509 wrlp(mp, MAC_ADDR_LOW, mac_l);
1510 wrlp(mp, MAC_ADDR_HIGH, mac_h);
1511
1512 table = UNICAST_TABLE(mp->port_num);
1513 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1514 }
1515
1516 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1517 {
1518 struct mv643xx_eth_private *mp = netdev_priv(dev);
1519
1520 /* +2 is for the offset of the HW addr type */
1521 memcpy(dev->dev_addr, addr + 2, 6);
1522
1523 init_mac_tables(mp);
1524 uc_addr_set(mp, dev->dev_addr);
1525
1526 return 0;
1527 }
1528
1529 static int addr_crc(unsigned char *addr)
1530 {
1531 int crc = 0;
1532 int i;
1533
1534 for (i = 0; i < 6; i++) {
1535 int j;
1536
1537 crc = (crc ^ addr[i]) << 8;
1538 for (j = 7; j >= 0; j--) {
1539 if (crc & (0x100 << j))
1540 crc ^= 0x107 << j;
1541 }
1542 }
1543
1544 return crc;
1545 }
1546
1547 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1548 {
1549 struct mv643xx_eth_private *mp = netdev_priv(dev);
1550 u32 port_config;
1551 struct dev_addr_list *addr;
1552 int i;
1553
1554 port_config = rdlp(mp, PORT_CONFIG);
1555 if (dev->flags & IFF_PROMISC)
1556 port_config |= UNICAST_PROMISCUOUS_MODE;
1557 else
1558 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1559 wrlp(mp, PORT_CONFIG, port_config);
1560
1561 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1562 int port_num = mp->port_num;
1563 u32 accept = 0x01010101;
1564
1565 for (i = 0; i < 0x100; i += 4) {
1566 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1567 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1568 }
1569 return;
1570 }
1571
1572 for (i = 0; i < 0x100; i += 4) {
1573 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1574 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1575 }
1576
1577 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1578 u8 *a = addr->da_addr;
1579 int table;
1580
1581 if (addr->da_addrlen != 6)
1582 continue;
1583
1584 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1585 table = SPECIAL_MCAST_TABLE(mp->port_num);
1586 set_filter_table_entry(mp, table, a[5]);
1587 } else {
1588 int crc = addr_crc(a);
1589
1590 table = OTHER_MCAST_TABLE(mp->port_num);
1591 set_filter_table_entry(mp, table, crc);
1592 }
1593 }
1594 }
1595
1596
1597 /* rx/tx queue initialisation ***********************************************/
1598 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1599 {
1600 struct rx_queue *rxq = mp->rxq + index;
1601 struct rx_desc *rx_desc;
1602 int size;
1603 int i;
1604
1605 rxq->index = index;
1606
1607 rxq->rx_ring_size = mp->default_rx_ring_size;
1608
1609 rxq->rx_desc_count = 0;
1610 rxq->rx_curr_desc = 0;
1611 rxq->rx_used_desc = 0;
1612
1613 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1614
1615 if (index == 0 && size <= mp->rx_desc_sram_size) {
1616 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1617 mp->rx_desc_sram_size);
1618 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1619 } else {
1620 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1621 &rxq->rx_desc_dma,
1622 GFP_KERNEL);
1623 }
1624
1625 if (rxq->rx_desc_area == NULL) {
1626 dev_printk(KERN_ERR, &mp->dev->dev,
1627 "can't allocate rx ring (%d bytes)\n", size);
1628 goto out;
1629 }
1630 memset(rxq->rx_desc_area, 0, size);
1631
1632 rxq->rx_desc_area_size = size;
1633 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1634 GFP_KERNEL);
1635 if (rxq->rx_skb == NULL) {
1636 dev_printk(KERN_ERR, &mp->dev->dev,
1637 "can't allocate rx skb ring\n");
1638 goto out_free;
1639 }
1640
1641 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1642 for (i = 0; i < rxq->rx_ring_size; i++) {
1643 int nexti;
1644
1645 nexti = i + 1;
1646 if (nexti == rxq->rx_ring_size)
1647 nexti = 0;
1648
1649 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1650 nexti * sizeof(struct rx_desc);
1651 }
1652
1653 return 0;
1654
1655
1656 out_free:
1657 if (index == 0 && size <= mp->rx_desc_sram_size)
1658 iounmap(rxq->rx_desc_area);
1659 else
1660 dma_free_coherent(NULL, size,
1661 rxq->rx_desc_area,
1662 rxq->rx_desc_dma);
1663
1664 out:
1665 return -ENOMEM;
1666 }
1667
1668 static void rxq_deinit(struct rx_queue *rxq)
1669 {
1670 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1671 int i;
1672
1673 rxq_disable(rxq);
1674
1675 for (i = 0; i < rxq->rx_ring_size; i++) {
1676 if (rxq->rx_skb[i]) {
1677 dev_kfree_skb(rxq->rx_skb[i]);
1678 rxq->rx_desc_count--;
1679 }
1680 }
1681
1682 if (rxq->rx_desc_count) {
1683 dev_printk(KERN_ERR, &mp->dev->dev,
1684 "error freeing rx ring -- %d skbs stuck\n",
1685 rxq->rx_desc_count);
1686 }
1687
1688 if (rxq->index == 0 &&
1689 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1690 iounmap(rxq->rx_desc_area);
1691 else
1692 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1693 rxq->rx_desc_area, rxq->rx_desc_dma);
1694
1695 kfree(rxq->rx_skb);
1696 }
1697
1698 static int txq_init(struct mv643xx_eth_private *mp, int index)
1699 {
1700 struct tx_queue *txq = mp->txq + index;
1701 struct tx_desc *tx_desc;
1702 int size;
1703 int i;
1704
1705 txq->index = index;
1706
1707 txq->tx_ring_size = mp->default_tx_ring_size;
1708
1709 txq->tx_desc_count = 0;
1710 txq->tx_curr_desc = 0;
1711 txq->tx_used_desc = 0;
1712
1713 size = txq->tx_ring_size * sizeof(struct tx_desc);
1714
1715 if (index == 0 && size <= mp->tx_desc_sram_size) {
1716 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1717 mp->tx_desc_sram_size);
1718 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1719 } else {
1720 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1721 &txq->tx_desc_dma,
1722 GFP_KERNEL);
1723 }
1724
1725 if (txq->tx_desc_area == NULL) {
1726 dev_printk(KERN_ERR, &mp->dev->dev,
1727 "can't allocate tx ring (%d bytes)\n", size);
1728 return -ENOMEM;
1729 }
1730 memset(txq->tx_desc_area, 0, size);
1731
1732 txq->tx_desc_area_size = size;
1733
1734 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1735 for (i = 0; i < txq->tx_ring_size; i++) {
1736 struct tx_desc *txd = tx_desc + i;
1737 int nexti;
1738
1739 nexti = i + 1;
1740 if (nexti == txq->tx_ring_size)
1741 nexti = 0;
1742
1743 txd->cmd_sts = 0;
1744 txd->next_desc_ptr = txq->tx_desc_dma +
1745 nexti * sizeof(struct tx_desc);
1746 }
1747
1748 skb_queue_head_init(&txq->tx_skb);
1749
1750 return 0;
1751 }
1752
1753 static void txq_deinit(struct tx_queue *txq)
1754 {
1755 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1756
1757 txq_disable(txq);
1758 txq_reclaim(txq, txq->tx_ring_size, 1);
1759
1760 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1761
1762 if (txq->index == 0 &&
1763 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1764 iounmap(txq->tx_desc_area);
1765 else
1766 dma_free_coherent(NULL, txq->tx_desc_area_size,
1767 txq->tx_desc_area, txq->tx_desc_dma);
1768 }
1769
1770
1771 /* netdev ops and related ***************************************************/
1772 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1773 {
1774 u32 int_cause;
1775 u32 int_cause_ext;
1776
1777 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1778 if (int_cause == 0)
1779 return 0;
1780
1781 int_cause_ext = 0;
1782 if (int_cause & INT_EXT)
1783 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1784
1785 int_cause &= INT_TX_END | INT_RX;
1786 if (int_cause) {
1787 wrlp(mp, INT_CAUSE, ~int_cause);
1788 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1789 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1790 mp->work_rx |= (int_cause & INT_RX) >> 2;
1791 }
1792
1793 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1794 if (int_cause_ext) {
1795 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1796 if (int_cause_ext & INT_EXT_LINK_PHY)
1797 mp->work_link = 1;
1798 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1799 }
1800
1801 return 1;
1802 }
1803
1804 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1805 {
1806 struct net_device *dev = (struct net_device *)dev_id;
1807 struct mv643xx_eth_private *mp = netdev_priv(dev);
1808
1809 if (unlikely(!mv643xx_eth_collect_events(mp)))
1810 return IRQ_NONE;
1811
1812 wrlp(mp, INT_MASK, 0);
1813 napi_schedule(&mp->napi);
1814
1815 return IRQ_HANDLED;
1816 }
1817
1818 static void handle_link_event(struct mv643xx_eth_private *mp)
1819 {
1820 struct net_device *dev = mp->dev;
1821 u32 port_status;
1822 int speed;
1823 int duplex;
1824 int fc;
1825
1826 port_status = rdlp(mp, PORT_STATUS);
1827 if (!(port_status & LINK_UP)) {
1828 if (netif_carrier_ok(dev)) {
1829 int i;
1830
1831 printk(KERN_INFO "%s: link down\n", dev->name);
1832
1833 netif_carrier_off(dev);
1834
1835 for (i = 0; i < mp->txq_count; i++) {
1836 struct tx_queue *txq = mp->txq + i;
1837
1838 txq_reclaim(txq, txq->tx_ring_size, 1);
1839 txq_reset_hw_ptr(txq);
1840 }
1841 }
1842 return;
1843 }
1844
1845 switch (port_status & PORT_SPEED_MASK) {
1846 case PORT_SPEED_10:
1847 speed = 10;
1848 break;
1849 case PORT_SPEED_100:
1850 speed = 100;
1851 break;
1852 case PORT_SPEED_1000:
1853 speed = 1000;
1854 break;
1855 default:
1856 speed = -1;
1857 break;
1858 }
1859 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1860 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1861
1862 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1863 "flow control %sabled\n", dev->name,
1864 speed, duplex ? "full" : "half",
1865 fc ? "en" : "dis");
1866
1867 if (!netif_carrier_ok(dev))
1868 netif_carrier_on(dev);
1869 }
1870
1871 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1872 {
1873 struct mv643xx_eth_private *mp;
1874 int work_done;
1875
1876 mp = container_of(napi, struct mv643xx_eth_private, napi);
1877
1878 mp->work_rx_refill |= mp->work_rx_oom;
1879 mp->work_rx_oom = 0;
1880
1881 work_done = 0;
1882 while (work_done < budget) {
1883 u8 queue_mask;
1884 int queue;
1885 int work_tbd;
1886
1887 if (mp->work_link) {
1888 mp->work_link = 0;
1889 handle_link_event(mp);
1890 continue;
1891 }
1892
1893 queue_mask = mp->work_tx | mp->work_tx_end |
1894 mp->work_rx | mp->work_rx_refill;
1895 if (!queue_mask) {
1896 if (mv643xx_eth_collect_events(mp))
1897 continue;
1898 break;
1899 }
1900
1901 queue = fls(queue_mask) - 1;
1902 queue_mask = 1 << queue;
1903
1904 work_tbd = budget - work_done;
1905 if (work_tbd > 16)
1906 work_tbd = 16;
1907
1908 if (mp->work_tx_end & queue_mask) {
1909 txq_kick(mp->txq + queue);
1910 } else if (mp->work_tx & queue_mask) {
1911 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1912 txq_maybe_wake(mp->txq + queue);
1913 } else if (mp->work_rx & queue_mask) {
1914 work_done += rxq_process(mp->rxq + queue, work_tbd);
1915 } else if (mp->work_rx_refill & queue_mask) {
1916 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1917 } else {
1918 BUG();
1919 }
1920 }
1921
1922 if (work_done < budget) {
1923 if (mp->work_rx_oom)
1924 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1925 napi_complete(napi);
1926 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
1927 }
1928
1929 return work_done;
1930 }
1931
1932 static inline void oom_timer_wrapper(unsigned long data)
1933 {
1934 struct mv643xx_eth_private *mp = (void *)data;
1935
1936 napi_schedule(&mp->napi);
1937 }
1938
1939 static void phy_reset(struct mv643xx_eth_private *mp)
1940 {
1941 int data;
1942
1943 data = phy_read(mp->phy, MII_BMCR);
1944 if (data < 0)
1945 return;
1946
1947 data |= BMCR_RESET;
1948 if (phy_write(mp->phy, MII_BMCR, data) < 0)
1949 return;
1950
1951 do {
1952 data = phy_read(mp->phy, MII_BMCR);
1953 } while (data >= 0 && data & BMCR_RESET);
1954 }
1955
1956 static void port_start(struct mv643xx_eth_private *mp)
1957 {
1958 u32 pscr;
1959 int i;
1960
1961 /*
1962 * Perform PHY reset, if there is a PHY.
1963 */
1964 if (mp->phy != NULL) {
1965 struct ethtool_cmd cmd;
1966
1967 mv643xx_eth_get_settings(mp->dev, &cmd);
1968 phy_reset(mp);
1969 mv643xx_eth_set_settings(mp->dev, &cmd);
1970 }
1971
1972 /*
1973 * Configure basic link parameters.
1974 */
1975 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1976
1977 pscr |= SERIAL_PORT_ENABLE;
1978 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1979
1980 pscr |= DO_NOT_FORCE_LINK_FAIL;
1981 if (mp->phy == NULL)
1982 pscr |= FORCE_LINK_PASS;
1983 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1984
1985 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
1986
1987 /*
1988 * Configure TX path and queues.
1989 */
1990 tx_set_rate(mp, 1000000000, 16777216);
1991 for (i = 0; i < mp->txq_count; i++) {
1992 struct tx_queue *txq = mp->txq + i;
1993
1994 txq_reset_hw_ptr(txq);
1995 txq_set_rate(txq, 1000000000, 16777216);
1996 txq_set_fixed_prio_mode(txq);
1997 }
1998
1999 /*
2000 * Add configured unicast address to address filter table.
2001 */
2002 uc_addr_set(mp, mp->dev->dev_addr);
2003
2004 /*
2005 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2006 * frames to RX queue #0, and include the pseudo-header when
2007 * calculating receive checksums.
2008 */
2009 wrlp(mp, PORT_CONFIG, 0x02000000);
2010
2011 /*
2012 * Treat BPDUs as normal multicasts, and disable partition mode.
2013 */
2014 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2015
2016 /*
2017 * Enable the receive queues.
2018 */
2019 for (i = 0; i < mp->rxq_count; i++) {
2020 struct rx_queue *rxq = mp->rxq + i;
2021 u32 addr;
2022
2023 addr = (u32)rxq->rx_desc_dma;
2024 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2025 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2026
2027 rxq_enable(rxq);
2028 }
2029 }
2030
2031 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2032 {
2033 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2034 u32 val;
2035
2036 val = rdlp(mp, SDMA_CONFIG);
2037 if (mp->shared->extended_rx_coal_limit) {
2038 if (coal > 0xffff)
2039 coal = 0xffff;
2040 val &= ~0x023fff80;
2041 val |= (coal & 0x8000) << 10;
2042 val |= (coal & 0x7fff) << 7;
2043 } else {
2044 if (coal > 0x3fff)
2045 coal = 0x3fff;
2046 val &= ~0x003fff00;
2047 val |= (coal & 0x3fff) << 8;
2048 }
2049 wrlp(mp, SDMA_CONFIG, val);
2050 }
2051
2052 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2053 {
2054 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2055
2056 if (coal > 0x3fff)
2057 coal = 0x3fff;
2058 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, (coal & 0x3fff) << 4);
2059 }
2060
2061 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2062 {
2063 int skb_size;
2064
2065 /*
2066 * Reserve 2+14 bytes for an ethernet header (the hardware
2067 * automatically prepends 2 bytes of dummy data to each
2068 * received packet), 16 bytes for up to four VLAN tags, and
2069 * 4 bytes for the trailing FCS -- 36 bytes total.
2070 */
2071 skb_size = mp->dev->mtu + 36;
2072
2073 /*
2074 * Make sure that the skb size is a multiple of 8 bytes, as
2075 * the lower three bits of the receive descriptor's buffer
2076 * size field are ignored by the hardware.
2077 */
2078 mp->skb_size = (skb_size + 7) & ~7;
2079 }
2080
2081 static int mv643xx_eth_open(struct net_device *dev)
2082 {
2083 struct mv643xx_eth_private *mp = netdev_priv(dev);
2084 int err;
2085 int i;
2086
2087 wrlp(mp, INT_CAUSE, 0);
2088 wrlp(mp, INT_CAUSE_EXT, 0);
2089 rdlp(mp, INT_CAUSE_EXT);
2090
2091 err = request_irq(dev->irq, mv643xx_eth_irq,
2092 IRQF_SHARED, dev->name, dev);
2093 if (err) {
2094 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2095 return -EAGAIN;
2096 }
2097
2098 init_mac_tables(mp);
2099
2100 mv643xx_eth_recalc_skb_size(mp);
2101
2102 napi_enable(&mp->napi);
2103
2104 skb_queue_head_init(&mp->rx_recycle);
2105
2106 for (i = 0; i < mp->rxq_count; i++) {
2107 err = rxq_init(mp, i);
2108 if (err) {
2109 while (--i >= 0)
2110 rxq_deinit(mp->rxq + i);
2111 goto out;
2112 }
2113
2114 rxq_refill(mp->rxq + i, INT_MAX);
2115 }
2116
2117 if (mp->work_rx_oom) {
2118 mp->rx_oom.expires = jiffies + (HZ / 10);
2119 add_timer(&mp->rx_oom);
2120 }
2121
2122 for (i = 0; i < mp->txq_count; i++) {
2123 err = txq_init(mp, i);
2124 if (err) {
2125 while (--i >= 0)
2126 txq_deinit(mp->txq + i);
2127 goto out_free;
2128 }
2129 }
2130
2131 netif_carrier_off(dev);
2132
2133 port_start(mp);
2134
2135 set_rx_coal(mp, 0);
2136 set_tx_coal(mp, 0);
2137
2138 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2139 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2140
2141 return 0;
2142
2143
2144 out_free:
2145 for (i = 0; i < mp->rxq_count; i++)
2146 rxq_deinit(mp->rxq + i);
2147 out:
2148 free_irq(dev->irq, dev);
2149
2150 return err;
2151 }
2152
2153 static void port_reset(struct mv643xx_eth_private *mp)
2154 {
2155 unsigned int data;
2156 int i;
2157
2158 for (i = 0; i < mp->rxq_count; i++)
2159 rxq_disable(mp->rxq + i);
2160 for (i = 0; i < mp->txq_count; i++)
2161 txq_disable(mp->txq + i);
2162
2163 while (1) {
2164 u32 ps = rdlp(mp, PORT_STATUS);
2165
2166 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2167 break;
2168 udelay(10);
2169 }
2170
2171 /* Reset the Enable bit in the Configuration Register */
2172 data = rdlp(mp, PORT_SERIAL_CONTROL);
2173 data &= ~(SERIAL_PORT_ENABLE |
2174 DO_NOT_FORCE_LINK_FAIL |
2175 FORCE_LINK_PASS);
2176 wrlp(mp, PORT_SERIAL_CONTROL, data);
2177 }
2178
2179 static int mv643xx_eth_stop(struct net_device *dev)
2180 {
2181 struct mv643xx_eth_private *mp = netdev_priv(dev);
2182 int i;
2183
2184 wrlp(mp, INT_MASK, 0x00000000);
2185 rdlp(mp, INT_MASK);
2186
2187 del_timer_sync(&mp->mib_counters_timer);
2188
2189 napi_disable(&mp->napi);
2190
2191 del_timer_sync(&mp->rx_oom);
2192
2193 netif_carrier_off(dev);
2194
2195 free_irq(dev->irq, dev);
2196
2197 port_reset(mp);
2198 mv643xx_eth_get_stats(dev);
2199 mib_counters_update(mp);
2200
2201 skb_queue_purge(&mp->rx_recycle);
2202
2203 for (i = 0; i < mp->rxq_count; i++)
2204 rxq_deinit(mp->rxq + i);
2205 for (i = 0; i < mp->txq_count; i++)
2206 txq_deinit(mp->txq + i);
2207
2208 return 0;
2209 }
2210
2211 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2212 {
2213 struct mv643xx_eth_private *mp = netdev_priv(dev);
2214
2215 if (mp->phy != NULL)
2216 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2217
2218 return -EOPNOTSUPP;
2219 }
2220
2221 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2222 {
2223 struct mv643xx_eth_private *mp = netdev_priv(dev);
2224
2225 if (new_mtu < 64 || new_mtu > 9500)
2226 return -EINVAL;
2227
2228 dev->mtu = new_mtu;
2229 mv643xx_eth_recalc_skb_size(mp);
2230 tx_set_rate(mp, 1000000000, 16777216);
2231
2232 if (!netif_running(dev))
2233 return 0;
2234
2235 /*
2236 * Stop and then re-open the interface. This will allocate RX
2237 * skbs of the new MTU.
2238 * There is a possible danger that the open will not succeed,
2239 * due to memory being full.
2240 */
2241 mv643xx_eth_stop(dev);
2242 if (mv643xx_eth_open(dev)) {
2243 dev_printk(KERN_ERR, &dev->dev,
2244 "fatal error on re-opening device after "
2245 "MTU change\n");
2246 }
2247
2248 return 0;
2249 }
2250
2251 static void tx_timeout_task(struct work_struct *ugly)
2252 {
2253 struct mv643xx_eth_private *mp;
2254
2255 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2256 if (netif_running(mp->dev)) {
2257 netif_tx_stop_all_queues(mp->dev);
2258 port_reset(mp);
2259 port_start(mp);
2260 netif_tx_wake_all_queues(mp->dev);
2261 }
2262 }
2263
2264 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2265 {
2266 struct mv643xx_eth_private *mp = netdev_priv(dev);
2267
2268 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2269
2270 schedule_work(&mp->tx_timeout_task);
2271 }
2272
2273 #ifdef CONFIG_NET_POLL_CONTROLLER
2274 static void mv643xx_eth_netpoll(struct net_device *dev)
2275 {
2276 struct mv643xx_eth_private *mp = netdev_priv(dev);
2277
2278 wrlp(mp, INT_MASK, 0x00000000);
2279 rdlp(mp, INT_MASK);
2280
2281 mv643xx_eth_irq(dev->irq, dev);
2282
2283 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2284 }
2285 #endif
2286
2287
2288 /* platform glue ************************************************************/
2289 static void
2290 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2291 struct mbus_dram_target_info *dram)
2292 {
2293 void __iomem *base = msp->base;
2294 u32 win_enable;
2295 u32 win_protect;
2296 int i;
2297
2298 for (i = 0; i < 6; i++) {
2299 writel(0, base + WINDOW_BASE(i));
2300 writel(0, base + WINDOW_SIZE(i));
2301 if (i < 4)
2302 writel(0, base + WINDOW_REMAP_HIGH(i));
2303 }
2304
2305 win_enable = 0x3f;
2306 win_protect = 0;
2307
2308 for (i = 0; i < dram->num_cs; i++) {
2309 struct mbus_dram_window *cs = dram->cs + i;
2310
2311 writel((cs->base & 0xffff0000) |
2312 (cs->mbus_attr << 8) |
2313 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2314 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2315
2316 win_enable &= ~(1 << i);
2317 win_protect |= 3 << (2 * i);
2318 }
2319
2320 writel(win_enable, base + WINDOW_BAR_ENABLE);
2321 msp->win_protect = win_protect;
2322 }
2323
2324 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2325 {
2326 /*
2327 * Check whether we have a 14-bit coal limit field in bits
2328 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2329 * SDMA config register.
2330 */
2331 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2332 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2333 msp->extended_rx_coal_limit = 1;
2334 else
2335 msp->extended_rx_coal_limit = 0;
2336
2337 /*
2338 * Check whether the MAC supports TX rate control, and if
2339 * yes, whether its associated registers are in the old or
2340 * the new place.
2341 */
2342 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2343 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2344 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2345 } else {
2346 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2347 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2348 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2349 else
2350 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2351 }
2352 }
2353
2354 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2355 {
2356 static int mv643xx_eth_version_printed;
2357 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2358 struct mv643xx_eth_shared_private *msp;
2359 struct resource *res;
2360 int ret;
2361
2362 if (!mv643xx_eth_version_printed++)
2363 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2364 "driver version %s\n", mv643xx_eth_driver_version);
2365
2366 ret = -EINVAL;
2367 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2368 if (res == NULL)
2369 goto out;
2370
2371 ret = -ENOMEM;
2372 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2373 if (msp == NULL)
2374 goto out;
2375 memset(msp, 0, sizeof(*msp));
2376
2377 msp->base = ioremap(res->start, res->end - res->start + 1);
2378 if (msp->base == NULL)
2379 goto out_free;
2380
2381 /*
2382 * Set up and register SMI bus.
2383 */
2384 if (pd == NULL || pd->shared_smi == NULL) {
2385 msp->smi_bus = mdiobus_alloc();
2386 if (msp->smi_bus == NULL)
2387 goto out_unmap;
2388
2389 msp->smi_bus->priv = msp;
2390 msp->smi_bus->name = "mv643xx_eth smi";
2391 msp->smi_bus->read = smi_bus_read;
2392 msp->smi_bus->write = smi_bus_write,
2393 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2394 msp->smi_bus->parent = &pdev->dev;
2395 msp->smi_bus->phy_mask = 0xffffffff;
2396 if (mdiobus_register(msp->smi_bus) < 0)
2397 goto out_free_mii_bus;
2398 msp->smi = msp;
2399 } else {
2400 msp->smi = platform_get_drvdata(pd->shared_smi);
2401 }
2402
2403 msp->err_interrupt = NO_IRQ;
2404 init_waitqueue_head(&msp->smi_busy_wait);
2405
2406 /*
2407 * Check whether the error interrupt is hooked up.
2408 */
2409 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2410 if (res != NULL) {
2411 int err;
2412
2413 err = request_irq(res->start, mv643xx_eth_err_irq,
2414 IRQF_SHARED, "mv643xx_eth", msp);
2415 if (!err) {
2416 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2417 msp->err_interrupt = res->start;
2418 }
2419 }
2420
2421 /*
2422 * (Re-)program MBUS remapping windows if we are asked to.
2423 */
2424 if (pd != NULL && pd->dram != NULL)
2425 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2426
2427 /*
2428 * Detect hardware parameters.
2429 */
2430 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2431 infer_hw_params(msp);
2432
2433 platform_set_drvdata(pdev, msp);
2434
2435 return 0;
2436
2437 out_free_mii_bus:
2438 mdiobus_free(msp->smi_bus);
2439 out_unmap:
2440 iounmap(msp->base);
2441 out_free:
2442 kfree(msp);
2443 out:
2444 return ret;
2445 }
2446
2447 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2448 {
2449 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2450 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2451
2452 if (pd == NULL || pd->shared_smi == NULL) {
2453 mdiobus_free(msp->smi_bus);
2454 mdiobus_unregister(msp->smi_bus);
2455 }
2456 if (msp->err_interrupt != NO_IRQ)
2457 free_irq(msp->err_interrupt, msp);
2458 iounmap(msp->base);
2459 kfree(msp);
2460
2461 return 0;
2462 }
2463
2464 static struct platform_driver mv643xx_eth_shared_driver = {
2465 .probe = mv643xx_eth_shared_probe,
2466 .remove = mv643xx_eth_shared_remove,
2467 .driver = {
2468 .name = MV643XX_ETH_SHARED_NAME,
2469 .owner = THIS_MODULE,
2470 },
2471 };
2472
2473 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2474 {
2475 int addr_shift = 5 * mp->port_num;
2476 u32 data;
2477
2478 data = rdl(mp, PHY_ADDR);
2479 data &= ~(0x1f << addr_shift);
2480 data |= (phy_addr & 0x1f) << addr_shift;
2481 wrl(mp, PHY_ADDR, data);
2482 }
2483
2484 static int phy_addr_get(struct mv643xx_eth_private *mp)
2485 {
2486 unsigned int data;
2487
2488 data = rdl(mp, PHY_ADDR);
2489
2490 return (data >> (5 * mp->port_num)) & 0x1f;
2491 }
2492
2493 static void set_params(struct mv643xx_eth_private *mp,
2494 struct mv643xx_eth_platform_data *pd)
2495 {
2496 struct net_device *dev = mp->dev;
2497
2498 if (is_valid_ether_addr(pd->mac_addr))
2499 memcpy(dev->dev_addr, pd->mac_addr, 6);
2500 else
2501 uc_addr_get(mp, dev->dev_addr);
2502
2503 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2504 if (pd->rx_queue_size)
2505 mp->default_rx_ring_size = pd->rx_queue_size;
2506 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2507 mp->rx_desc_sram_size = pd->rx_sram_size;
2508
2509 mp->rxq_count = pd->rx_queue_count ? : 1;
2510
2511 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2512 if (pd->tx_queue_size)
2513 mp->default_tx_ring_size = pd->tx_queue_size;
2514 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2515 mp->tx_desc_sram_size = pd->tx_sram_size;
2516
2517 mp->txq_count = pd->tx_queue_count ? : 1;
2518 }
2519
2520 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2521 int phy_addr)
2522 {
2523 struct mii_bus *bus = mp->shared->smi->smi_bus;
2524 struct phy_device *phydev;
2525 int start;
2526 int num;
2527 int i;
2528
2529 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2530 start = phy_addr_get(mp) & 0x1f;
2531 num = 32;
2532 } else {
2533 start = phy_addr & 0x1f;
2534 num = 1;
2535 }
2536
2537 phydev = NULL;
2538 for (i = 0; i < num; i++) {
2539 int addr = (start + i) & 0x1f;
2540
2541 if (bus->phy_map[addr] == NULL)
2542 mdiobus_scan(bus, addr);
2543
2544 if (phydev == NULL) {
2545 phydev = bus->phy_map[addr];
2546 if (phydev != NULL)
2547 phy_addr_set(mp, addr);
2548 }
2549 }
2550
2551 return phydev;
2552 }
2553
2554 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2555 {
2556 struct phy_device *phy = mp->phy;
2557
2558 phy_reset(mp);
2559
2560 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2561
2562 if (speed == 0) {
2563 phy->autoneg = AUTONEG_ENABLE;
2564 phy->speed = 0;
2565 phy->duplex = 0;
2566 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2567 } else {
2568 phy->autoneg = AUTONEG_DISABLE;
2569 phy->advertising = 0;
2570 phy->speed = speed;
2571 phy->duplex = duplex;
2572 }
2573 phy_start_aneg(phy);
2574 }
2575
2576 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2577 {
2578 u32 pscr;
2579
2580 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2581 if (pscr & SERIAL_PORT_ENABLE) {
2582 pscr &= ~SERIAL_PORT_ENABLE;
2583 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2584 }
2585
2586 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2587 if (mp->phy == NULL) {
2588 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2589 if (speed == SPEED_1000)
2590 pscr |= SET_GMII_SPEED_TO_1000;
2591 else if (speed == SPEED_100)
2592 pscr |= SET_MII_SPEED_TO_100;
2593
2594 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2595
2596 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2597 if (duplex == DUPLEX_FULL)
2598 pscr |= SET_FULL_DUPLEX_MODE;
2599 }
2600
2601 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2602 }
2603
2604 static int mv643xx_eth_probe(struct platform_device *pdev)
2605 {
2606 struct mv643xx_eth_platform_data *pd;
2607 struct mv643xx_eth_private *mp;
2608 struct net_device *dev;
2609 struct resource *res;
2610 int err;
2611
2612 pd = pdev->dev.platform_data;
2613 if (pd == NULL) {
2614 dev_printk(KERN_ERR, &pdev->dev,
2615 "no mv643xx_eth_platform_data\n");
2616 return -ENODEV;
2617 }
2618
2619 if (pd->shared == NULL) {
2620 dev_printk(KERN_ERR, &pdev->dev,
2621 "no mv643xx_eth_platform_data->shared\n");
2622 return -ENODEV;
2623 }
2624
2625 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2626 if (!dev)
2627 return -ENOMEM;
2628
2629 mp = netdev_priv(dev);
2630 platform_set_drvdata(pdev, mp);
2631
2632 mp->shared = platform_get_drvdata(pd->shared);
2633 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2634 mp->port_num = pd->port_number;
2635
2636 mp->dev = dev;
2637
2638 set_params(mp, pd);
2639 dev->real_num_tx_queues = mp->txq_count;
2640
2641 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2642 mp->phy = phy_scan(mp, pd->phy_addr);
2643
2644 if (mp->phy != NULL) {
2645 phy_init(mp, pd->speed, pd->duplex);
2646 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2647 } else {
2648 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2649 }
2650
2651 init_pscr(mp, pd->speed, pd->duplex);
2652
2653
2654 mib_counters_clear(mp);
2655
2656 init_timer(&mp->mib_counters_timer);
2657 mp->mib_counters_timer.data = (unsigned long)mp;
2658 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2659 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2660 add_timer(&mp->mib_counters_timer);
2661
2662 spin_lock_init(&mp->mib_counters_lock);
2663
2664 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2665
2666 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2667
2668 init_timer(&mp->rx_oom);
2669 mp->rx_oom.data = (unsigned long)mp;
2670 mp->rx_oom.function = oom_timer_wrapper;
2671
2672
2673 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2674 BUG_ON(!res);
2675 dev->irq = res->start;
2676
2677 dev->get_stats = mv643xx_eth_get_stats;
2678 dev->hard_start_xmit = mv643xx_eth_xmit;
2679 dev->open = mv643xx_eth_open;
2680 dev->stop = mv643xx_eth_stop;
2681 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2682 dev->set_mac_address = mv643xx_eth_set_mac_address;
2683 dev->do_ioctl = mv643xx_eth_ioctl;
2684 dev->change_mtu = mv643xx_eth_change_mtu;
2685 dev->tx_timeout = mv643xx_eth_tx_timeout;
2686 #ifdef CONFIG_NET_POLL_CONTROLLER
2687 dev->poll_controller = mv643xx_eth_netpoll;
2688 #endif
2689 dev->watchdog_timeo = 2 * HZ;
2690 dev->base_addr = 0;
2691
2692 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2693 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2694
2695 SET_NETDEV_DEV(dev, &pdev->dev);
2696
2697 if (mp->shared->win_protect)
2698 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2699
2700 err = register_netdev(dev);
2701 if (err)
2702 goto out;
2703
2704 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2705 mp->port_num, dev->dev_addr);
2706
2707 if (mp->tx_desc_sram_size > 0)
2708 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2709
2710 return 0;
2711
2712 out:
2713 free_netdev(dev);
2714
2715 return err;
2716 }
2717
2718 static int mv643xx_eth_remove(struct platform_device *pdev)
2719 {
2720 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2721
2722 unregister_netdev(mp->dev);
2723 if (mp->phy != NULL)
2724 phy_detach(mp->phy);
2725 flush_scheduled_work();
2726 free_netdev(mp->dev);
2727
2728 platform_set_drvdata(pdev, NULL);
2729
2730 return 0;
2731 }
2732
2733 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2734 {
2735 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2736
2737 /* Mask all interrupts on ethernet port */
2738 wrlp(mp, INT_MASK, 0);
2739 rdlp(mp, INT_MASK);
2740
2741 if (netif_running(mp->dev))
2742 port_reset(mp);
2743 }
2744
2745 static struct platform_driver mv643xx_eth_driver = {
2746 .probe = mv643xx_eth_probe,
2747 .remove = mv643xx_eth_remove,
2748 .shutdown = mv643xx_eth_shutdown,
2749 .driver = {
2750 .name = MV643XX_ETH_NAME,
2751 .owner = THIS_MODULE,
2752 },
2753 };
2754
2755 static int __init mv643xx_eth_init_module(void)
2756 {
2757 int rc;
2758
2759 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2760 if (!rc) {
2761 rc = platform_driver_register(&mv643xx_eth_driver);
2762 if (rc)
2763 platform_driver_unregister(&mv643xx_eth_shared_driver);
2764 }
2765
2766 return rc;
2767 }
2768 module_init(mv643xx_eth_init_module);
2769
2770 static void __exit mv643xx_eth_cleanup_module(void)
2771 {
2772 platform_driver_unregister(&mv643xx_eth_driver);
2773 platform_driver_unregister(&mv643xx_eth_shared_driver);
2774 }
2775 module_exit(mv643xx_eth_cleanup_module);
2776
2777 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2778 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2779 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2780 MODULE_LICENSE("GPL");
2781 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2782 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
WandBoard kernel