2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
20 static char *dev_info
= "ath9k";
22 MODULE_AUTHOR("Atheros Communications");
23 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25 MODULE_LICENSE("Dual BSD/GPL");
27 static int modparam_nohwcrypt
;
28 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption");
31 /* We use the hw_value as an index into our private channel structure */
33 #define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
39 #define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
46 /* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
50 static struct ieee80211_channel ath9k_2ghz_chantable
[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
67 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
71 static struct ieee80211_channel ath9k_5ghz_chantable
[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
102 static void ath_cache_conf_rate(struct ath_softc
*sc
,
103 struct ieee80211_conf
*conf
)
105 switch (conf
->channel
->band
) {
106 case IEEE80211_BAND_2GHZ
:
107 if (conf_is_ht20(conf
))
109 sc
->hw_rate_table
[ATH9K_MODE_11NG_HT20
];
110 else if (conf_is_ht40_minus(conf
))
112 sc
->hw_rate_table
[ATH9K_MODE_11NG_HT40MINUS
];
113 else if (conf_is_ht40_plus(conf
))
115 sc
->hw_rate_table
[ATH9K_MODE_11NG_HT40PLUS
];
118 sc
->hw_rate_table
[ATH9K_MODE_11G
];
120 case IEEE80211_BAND_5GHZ
:
121 if (conf_is_ht20(conf
))
123 sc
->hw_rate_table
[ATH9K_MODE_11NA_HT20
];
124 else if (conf_is_ht40_minus(conf
))
126 sc
->hw_rate_table
[ATH9K_MODE_11NA_HT40MINUS
];
127 else if (conf_is_ht40_plus(conf
))
129 sc
->hw_rate_table
[ATH9K_MODE_11NA_HT40PLUS
];
132 sc
->hw_rate_table
[ATH9K_MODE_11A
];
140 static void ath_update_txpow(struct ath_softc
*sc
)
142 struct ath_hw
*ah
= sc
->sc_ah
;
145 if (sc
->curtxpow
!= sc
->config
.txpowlimit
) {
146 ath9k_hw_set_txpowerlimit(ah
, sc
->config
.txpowlimit
);
147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah
, ATH9K_CAP_TXPOW
, 1, &txpow
);
149 sc
->curtxpow
= txpow
;
153 static u8
parse_mpdudensity(u8 mpdudensity
)
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
166 switch (mpdudensity
) {
172 /* Our lower layer calculations limit our precision to
188 static void ath_setup_rates(struct ath_softc
*sc
, enum ieee80211_band band
)
190 const struct ath_rate_table
*rate_table
= NULL
;
191 struct ieee80211_supported_band
*sband
;
192 struct ieee80211_rate
*rate
;
196 case IEEE80211_BAND_2GHZ
:
197 rate_table
= sc
->hw_rate_table
[ATH9K_MODE_11G
];
199 case IEEE80211_BAND_5GHZ
:
200 rate_table
= sc
->hw_rate_table
[ATH9K_MODE_11A
];
206 if (rate_table
== NULL
)
209 sband
= &sc
->sbands
[band
];
210 rate
= sc
->rates
[band
];
212 if (rate_table
->rate_cnt
> ATH_RATE_MAX
)
213 maxrates
= ATH_RATE_MAX
;
215 maxrates
= rate_table
->rate_cnt
;
217 for (i
= 0; i
< maxrates
; i
++) {
218 rate
[i
].bitrate
= rate_table
->info
[i
].ratekbps
/ 100;
219 rate
[i
].hw_value
= rate_table
->info
[i
].ratecode
;
220 if (rate_table
->info
[i
].short_preamble
) {
221 rate
[i
].hw_value_short
= rate_table
->info
[i
].ratecode
|
222 rate_table
->info
[i
].short_preamble
;
223 rate
[i
].flags
= IEEE80211_RATE_SHORT_PREAMBLE
;
227 DPRINTF(sc
, ATH_DBG_CONFIG
, "Rate: %2dMbps, ratecode: %2d\n",
228 rate
[i
].bitrate
/ 10, rate
[i
].hw_value
);
232 static struct ath9k_channel
*ath_get_curchannel(struct ath_softc
*sc
,
233 struct ieee80211_hw
*hw
)
235 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
236 struct ath9k_channel
*channel
;
239 chan_idx
= curchan
->hw_value
;
240 channel
= &sc
->sc_ah
->channels
[chan_idx
];
241 ath9k_update_ichannel(sc
, hw
, channel
);
246 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending
248 * DMA, then restart stuff.
250 int ath_set_channel(struct ath_softc
*sc
, struct ieee80211_hw
*hw
,
251 struct ath9k_channel
*hchan
)
253 struct ath_hw
*ah
= sc
->sc_ah
;
254 bool fastcc
= true, stopped
;
255 struct ieee80211_channel
*channel
= hw
->conf
.channel
;
258 if (sc
->sc_flags
& SC_OP_INVALID
)
264 * This is only performed if the channel settings have
267 * To switch channels clear any pending DMA operations;
268 * wait long enough for the RX fifo to drain, reset the
269 * hardware at the new frequency, and then re-enable
270 * the relevant bits of the h/w.
272 ath9k_hw_set_interrupts(ah
, 0);
273 ath_drain_all_txq(sc
, false);
274 stopped
= ath_stoprecv(sc
);
276 /* XXX: do not flush receive queue here. We don't want
277 * to flush data frames already in queue because of
278 * changing channel. */
280 if (!stopped
|| (sc
->sc_flags
& SC_OP_FULL_RESET
))
283 DPRINTF(sc
, ATH_DBG_CONFIG
,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
285 sc
->sc_ah
->curchan
->channel
,
286 channel
->center_freq
, sc
->tx_chan_width
);
288 spin_lock_bh(&sc
->sc_resetlock
);
290 r
= ath9k_hw_reset(ah
, hchan
, fastcc
);
292 DPRINTF(sc
, ATH_DBG_FATAL
,
293 "Unable to reset channel (%u Mhz) "
295 channel
->center_freq
, r
);
296 spin_unlock_bh(&sc
->sc_resetlock
);
299 spin_unlock_bh(&sc
->sc_resetlock
);
301 sc
->sc_flags
&= ~SC_OP_FULL_RESET
;
303 if (ath_startrecv(sc
) != 0) {
304 DPRINTF(sc
, ATH_DBG_FATAL
,
305 "Unable to restart recv logic\n");
310 ath_cache_conf_rate(sc
, &hw
->conf
);
311 ath_update_txpow(sc
);
312 ath9k_hw_set_interrupts(ah
, sc
->imask
);
315 ath9k_ps_restore(sc
);
320 * This routine performs the periodic noise floor calibration function
321 * that is used to adjust and optimize the chip performance. This
322 * takes environmental changes (location, temperature) into account.
323 * When the task is complete, it reschedules itself depending on the
324 * appropriate interval that was calculated.
326 static void ath_ani_calibrate(unsigned long data
)
328 struct ath_softc
*sc
= (struct ath_softc
*)data
;
329 struct ath_hw
*ah
= sc
->sc_ah
;
330 bool longcal
= false;
331 bool shortcal
= false;
332 bool aniflag
= false;
333 unsigned int timestamp
= jiffies_to_msecs(jiffies
);
334 u32 cal_interval
, short_cal_interval
;
336 short_cal_interval
= (ah
->opmode
== NL80211_IFTYPE_AP
) ?
337 ATH_AP_SHORT_CALINTERVAL
: ATH_STA_SHORT_CALINTERVAL
;
340 * don't calibrate when we're scanning.
341 * we are most likely not on our home channel.
343 spin_lock(&sc
->ani_lock
);
344 if (sc
->sc_flags
& SC_OP_SCANNING
)
347 /* Only calibrate if awake */
348 if (sc
->sc_ah
->power_mode
!= ATH9K_PM_AWAKE
)
353 /* Long calibration runs independently of short calibration. */
354 if ((timestamp
- sc
->ani
.longcal_timer
) >= ATH_LONG_CALINTERVAL
) {
356 DPRINTF(sc
, ATH_DBG_ANI
, "longcal @%lu\n", jiffies
);
357 sc
->ani
.longcal_timer
= timestamp
;
360 /* Short calibration applies only while caldone is false */
361 if (!sc
->ani
.caldone
) {
362 if ((timestamp
- sc
->ani
.shortcal_timer
) >= short_cal_interval
) {
364 DPRINTF(sc
, ATH_DBG_ANI
, "shortcal @%lu\n", jiffies
);
365 sc
->ani
.shortcal_timer
= timestamp
;
366 sc
->ani
.resetcal_timer
= timestamp
;
369 if ((timestamp
- sc
->ani
.resetcal_timer
) >=
370 ATH_RESTART_CALINTERVAL
) {
371 sc
->ani
.caldone
= ath9k_hw_reset_calvalid(ah
);
373 sc
->ani
.resetcal_timer
= timestamp
;
377 /* Verify whether we must check ANI */
378 if ((timestamp
- sc
->ani
.checkani_timer
) >= ATH_ANI_POLLINTERVAL
) {
380 sc
->ani
.checkani_timer
= timestamp
;
383 /* Skip all processing if there's nothing to do. */
384 if (longcal
|| shortcal
|| aniflag
) {
385 /* Call ANI routine if necessary */
387 ath9k_hw_ani_monitor(ah
, &sc
->nodestats
, ah
->curchan
);
389 /* Perform calibration if necessary */
390 if (longcal
|| shortcal
) {
391 sc
->ani
.caldone
= ath9k_hw_calibrate(ah
, ah
->curchan
,
392 sc
->rx_chainmask
, longcal
);
395 sc
->ani
.noise_floor
= ath9k_hw_getchan_noise(ah
,
398 DPRINTF(sc
, ATH_DBG_ANI
," calibrate chan %u/%x nf: %d\n",
399 ah
->curchan
->channel
, ah
->curchan
->channelFlags
,
400 sc
->ani
.noise_floor
);
404 ath9k_ps_restore(sc
);
407 spin_unlock(&sc
->ani_lock
);
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
413 cal_interval
= ATH_LONG_CALINTERVAL
;
414 if (sc
->sc_ah
->config
.enable_ani
)
415 cal_interval
= min(cal_interval
, (u32
)ATH_ANI_POLLINTERVAL
);
416 if (!sc
->ani
.caldone
)
417 cal_interval
= min(cal_interval
, (u32
)short_cal_interval
);
419 mod_timer(&sc
->ani
.timer
, jiffies
+ msecs_to_jiffies(cal_interval
));
422 static void ath_start_ani(struct ath_softc
*sc
)
424 unsigned long timestamp
= jiffies_to_msecs(jiffies
);
426 sc
->ani
.longcal_timer
= timestamp
;
427 sc
->ani
.shortcal_timer
= timestamp
;
428 sc
->ani
.checkani_timer
= timestamp
;
430 mod_timer(&sc
->ani
.timer
,
431 jiffies
+ msecs_to_jiffies(ATH_ANI_POLLINTERVAL
));
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
440 void ath_update_chainmask(struct ath_softc
*sc
, int is_ht
)
443 (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BT_COEX
)) {
444 sc
->tx_chainmask
= sc
->sc_ah
->caps
.tx_chainmask
;
445 sc
->rx_chainmask
= sc
->sc_ah
->caps
.rx_chainmask
;
447 sc
->tx_chainmask
= 1;
448 sc
->rx_chainmask
= 1;
451 DPRINTF(sc
, ATH_DBG_CONFIG
, "tx chmask: %d, rx chmask: %d\n",
452 sc
->tx_chainmask
, sc
->rx_chainmask
);
455 static void ath_node_attach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
459 an
= (struct ath_node
*)sta
->drv_priv
;
461 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
462 ath_tx_node_init(sc
, an
);
463 an
->maxampdu
= 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR
+
464 sta
->ht_cap
.ampdu_factor
);
465 an
->mpdudensity
= parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
466 an
->last_rssi
= ATH_RSSI_DUMMY_MARKER
;
470 static void ath_node_detach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
)
472 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
474 if (sc
->sc_flags
& SC_OP_TXAGGR
)
475 ath_tx_node_cleanup(sc
, an
);
478 static void ath9k_tasklet(unsigned long data
)
480 struct ath_softc
*sc
= (struct ath_softc
*)data
;
481 u32 status
= sc
->intrstatus
;
485 if (status
& ATH9K_INT_FATAL
) {
486 ath_reset(sc
, false);
487 ath9k_ps_restore(sc
);
491 if (status
& (ATH9K_INT_RX
| ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
)) {
492 spin_lock_bh(&sc
->rx
.rxflushlock
);
493 ath_rx_tasklet(sc
, 0);
494 spin_unlock_bh(&sc
->rx
.rxflushlock
);
497 if (status
& ATH9K_INT_TX
)
500 if ((status
& ATH9K_INT_TSFOOR
) && sc
->ps_enabled
) {
502 * TSF sync does not look correct; remain awake to sync with
505 DPRINTF(sc
, ATH_DBG_PS
, "TSFOOR - Sync with next Beacon\n");
506 sc
->sc_flags
|= SC_OP_WAIT_FOR_BEACON
| SC_OP_BEACON_SYNC
;
509 /* re-enable hardware interrupt */
510 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
511 ath9k_ps_restore(sc
);
514 irqreturn_t
ath_isr(int irq
, void *dev
)
516 #define SCHED_INTR ( \
526 struct ath_softc
*sc
= dev
;
527 struct ath_hw
*ah
= sc
->sc_ah
;
528 enum ath9k_int status
;
532 * The hardware is not ready/present, don't
533 * touch anything. Note this can happen early
534 * on if the IRQ is shared.
536 if (sc
->sc_flags
& SC_OP_INVALID
)
540 /* shared irq, not for us */
542 if (!ath9k_hw_intrpend(ah
))
546 * Figure out the reason(s) for the interrupt. Note
547 * that the hal returns a pseudo-ISR that may include
548 * bits we haven't explicitly enabled so we mask the
549 * value to insure we only process bits we requested.
551 ath9k_hw_getisr(ah
, &status
); /* NB: clears ISR too */
552 status
&= sc
->imask
; /* discard unasked-for bits */
555 * If there are no status bits set, then this interrupt was not
556 * for me (should have been caught above).
561 /* Cache the status */
562 sc
->intrstatus
= status
;
564 if (status
& SCHED_INTR
)
568 * If a FATAL or RXORN interrupt is received, we have to reset the
571 if (status
& (ATH9K_INT_FATAL
| ATH9K_INT_RXORN
))
574 if (status
& ATH9K_INT_SWBA
)
575 tasklet_schedule(&sc
->bcon_tasklet
);
577 if (status
& ATH9K_INT_TXURN
)
578 ath9k_hw_updatetxtriglevel(ah
, true);
580 if (status
& ATH9K_INT_MIB
) {
582 * Disable interrupts until we service the MIB
583 * interrupt; otherwise it will continue to
586 ath9k_hw_set_interrupts(ah
, 0);
588 * Let the hal handle the event. We assume
589 * it will clear whatever condition caused
592 ath9k_hw_procmibevent(ah
, &sc
->nodestats
);
593 ath9k_hw_set_interrupts(ah
, sc
->imask
);
596 if (!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
597 if (status
& ATH9K_INT_TIM_TIMER
) {
598 /* Clear RxAbort bit so that we can
600 ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
);
601 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
602 sc
->sc_flags
|= SC_OP_WAIT_FOR_BEACON
;
607 ath_debug_stat_interrupt(sc
, status
);
610 /* turn off every interrupt except SWBA */
611 ath9k_hw_set_interrupts(ah
, (sc
->imask
& ATH9K_INT_SWBA
));
612 tasklet_schedule(&sc
->intr_tq
);
620 static u32
ath_get_extchanmode(struct ath_softc
*sc
,
621 struct ieee80211_channel
*chan
,
622 enum nl80211_channel_type channel_type
)
626 switch (chan
->band
) {
627 case IEEE80211_BAND_2GHZ
:
628 switch(channel_type
) {
629 case NL80211_CHAN_NO_HT
:
630 case NL80211_CHAN_HT20
:
631 chanmode
= CHANNEL_G_HT20
;
633 case NL80211_CHAN_HT40PLUS
:
634 chanmode
= CHANNEL_G_HT40PLUS
;
636 case NL80211_CHAN_HT40MINUS
:
637 chanmode
= CHANNEL_G_HT40MINUS
;
641 case IEEE80211_BAND_5GHZ
:
642 switch(channel_type
) {
643 case NL80211_CHAN_NO_HT
:
644 case NL80211_CHAN_HT20
:
645 chanmode
= CHANNEL_A_HT20
;
647 case NL80211_CHAN_HT40PLUS
:
648 chanmode
= CHANNEL_A_HT40PLUS
;
650 case NL80211_CHAN_HT40MINUS
:
651 chanmode
= CHANNEL_A_HT40MINUS
;
662 static int ath_setkey_tkip(struct ath_softc
*sc
, u16 keyix
, const u8
*key
,
663 struct ath9k_keyval
*hk
, const u8
*addr
,
669 key_txmic
= key
+ NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY
;
670 key_rxmic
= key
+ NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY
;
674 * Group key installation - only two key cache entries are used
675 * regardless of splitmic capability since group key is only
676 * used either for TX or RX.
679 memcpy(hk
->kv_mic
, key_txmic
, sizeof(hk
->kv_mic
));
680 memcpy(hk
->kv_txmic
, key_txmic
, sizeof(hk
->kv_mic
));
682 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
683 memcpy(hk
->kv_txmic
, key_rxmic
, sizeof(hk
->kv_mic
));
685 return ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
, hk
, addr
);
688 /* TX and RX keys share the same key cache entry. */
689 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
690 memcpy(hk
->kv_txmic
, key_txmic
, sizeof(hk
->kv_txmic
));
691 return ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
, hk
, addr
);
694 /* Separate key cache entries for TX and RX */
696 /* TX key goes at first index, RX key at +32. */
697 memcpy(hk
->kv_mic
, key_txmic
, sizeof(hk
->kv_mic
));
698 if (!ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
, hk
, NULL
)) {
699 /* TX MIC entry failed. No need to proceed further */
700 DPRINTF(sc
, ATH_DBG_FATAL
,
701 "Setting TX MIC Key Failed\n");
705 memcpy(hk
->kv_mic
, key_rxmic
, sizeof(hk
->kv_mic
));
706 /* XXX delete tx key on failure? */
707 return ath9k_hw_set_keycache_entry(sc
->sc_ah
, keyix
+ 32, hk
, addr
);
710 static int ath_reserve_key_cache_slot_tkip(struct ath_softc
*sc
)
714 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
/ 2; i
++) {
715 if (test_bit(i
, sc
->keymap
) ||
716 test_bit(i
+ 64, sc
->keymap
))
717 continue; /* At least one part of TKIP key allocated */
719 (test_bit(i
+ 32, sc
->keymap
) ||
720 test_bit(i
+ 64 + 32, sc
->keymap
)))
721 continue; /* At least one part of TKIP key allocated */
723 /* Found a free slot for a TKIP key */
729 static int ath_reserve_key_cache_slot(struct ath_softc
*sc
)
733 /* First, try to find slots that would not be available for TKIP. */
735 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
/ 4; i
++) {
736 if (!test_bit(i
, sc
->keymap
) &&
737 (test_bit(i
+ 32, sc
->keymap
) ||
738 test_bit(i
+ 64, sc
->keymap
) ||
739 test_bit(i
+ 64 + 32, sc
->keymap
)))
741 if (!test_bit(i
+ 32, sc
->keymap
) &&
742 (test_bit(i
, sc
->keymap
) ||
743 test_bit(i
+ 64, sc
->keymap
) ||
744 test_bit(i
+ 64 + 32, sc
->keymap
)))
746 if (!test_bit(i
+ 64, sc
->keymap
) &&
747 (test_bit(i
, sc
->keymap
) ||
748 test_bit(i
+ 32, sc
->keymap
) ||
749 test_bit(i
+ 64 + 32, sc
->keymap
)))
751 if (!test_bit(i
+ 64 + 32, sc
->keymap
) &&
752 (test_bit(i
, sc
->keymap
) ||
753 test_bit(i
+ 32, sc
->keymap
) ||
754 test_bit(i
+ 64, sc
->keymap
)))
758 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
/ 2; i
++) {
759 if (!test_bit(i
, sc
->keymap
) &&
760 test_bit(i
+ 64, sc
->keymap
))
762 if (test_bit(i
, sc
->keymap
) &&
763 !test_bit(i
+ 64, sc
->keymap
))
768 /* No partially used TKIP slots, pick any available slot */
769 for (i
= IEEE80211_WEP_NKID
; i
< sc
->keymax
; i
++) {
770 /* Do not allow slots that could be needed for TKIP group keys
771 * to be used. This limitation could be removed if we know that
772 * TKIP will not be used. */
773 if (i
>= 64 && i
< 64 + IEEE80211_WEP_NKID
)
776 if (i
>= 32 && i
< 32 + IEEE80211_WEP_NKID
)
778 if (i
>= 64 + 32 && i
< 64 + 32 + IEEE80211_WEP_NKID
)
782 if (!test_bit(i
, sc
->keymap
))
783 return i
; /* Found a free slot for a key */
786 /* No free slot found */
790 static int ath_key_config(struct ath_softc
*sc
,
791 struct ieee80211_vif
*vif
,
792 struct ieee80211_sta
*sta
,
793 struct ieee80211_key_conf
*key
)
795 struct ath9k_keyval hk
;
796 const u8
*mac
= NULL
;
800 memset(&hk
, 0, sizeof(hk
));
804 hk
.kv_type
= ATH9K_CIPHER_WEP
;
807 hk
.kv_type
= ATH9K_CIPHER_TKIP
;
810 hk
.kv_type
= ATH9K_CIPHER_AES_CCM
;
816 hk
.kv_len
= key
->keylen
;
817 memcpy(hk
.kv_val
, key
->key
, key
->keylen
);
819 if (!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
)) {
820 /* For now, use the default keys for broadcast keys. This may
821 * need to change with virtual interfaces. */
823 } else if (key
->keyidx
) {
828 if (vif
->type
!= NL80211_IFTYPE_AP
) {
829 /* Only keyidx 0 should be used with unicast key, but
830 * allow this for client mode for now. */
839 if (key
->alg
== ALG_TKIP
)
840 idx
= ath_reserve_key_cache_slot_tkip(sc
);
842 idx
= ath_reserve_key_cache_slot(sc
);
844 return -ENOSPC
; /* no free key cache entries */
847 if (key
->alg
== ALG_TKIP
)
848 ret
= ath_setkey_tkip(sc
, idx
, key
->key
, &hk
, mac
,
849 vif
->type
== NL80211_IFTYPE_AP
);
851 ret
= ath9k_hw_set_keycache_entry(sc
->sc_ah
, idx
, &hk
, mac
);
856 set_bit(idx
, sc
->keymap
);
857 if (key
->alg
== ALG_TKIP
) {
858 set_bit(idx
+ 64, sc
->keymap
);
860 set_bit(idx
+ 32, sc
->keymap
);
861 set_bit(idx
+ 64 + 32, sc
->keymap
);
868 static void ath_key_delete(struct ath_softc
*sc
, struct ieee80211_key_conf
*key
)
870 ath9k_hw_keyreset(sc
->sc_ah
, key
->hw_key_idx
);
871 if (key
->hw_key_idx
< IEEE80211_WEP_NKID
)
874 clear_bit(key
->hw_key_idx
, sc
->keymap
);
875 if (key
->alg
!= ALG_TKIP
)
878 clear_bit(key
->hw_key_idx
+ 64, sc
->keymap
);
880 clear_bit(key
->hw_key_idx
+ 32, sc
->keymap
);
881 clear_bit(key
->hw_key_idx
+ 64 + 32, sc
->keymap
);
885 static void setup_ht_cap(struct ath_softc
*sc
,
886 struct ieee80211_sta_ht_cap
*ht_info
)
888 u8 tx_streams
, rx_streams
;
890 ht_info
->ht_supported
= true;
891 ht_info
->cap
= IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
892 IEEE80211_HT_CAP_SM_PS
|
893 IEEE80211_HT_CAP_SGI_40
|
894 IEEE80211_HT_CAP_DSSSCCK40
;
896 ht_info
->ampdu_factor
= IEEE80211_HT_MAX_AMPDU_64K
;
897 ht_info
->ampdu_density
= IEEE80211_HT_MPDU_DENSITY_8
;
899 /* set up supported mcs set */
900 memset(&ht_info
->mcs
, 0, sizeof(ht_info
->mcs
));
901 tx_streams
= !(sc
->tx_chainmask
& (sc
->tx_chainmask
- 1)) ? 1 : 2;
902 rx_streams
= !(sc
->rx_chainmask
& (sc
->rx_chainmask
- 1)) ? 1 : 2;
904 if (tx_streams
!= rx_streams
) {
905 DPRINTF(sc
, ATH_DBG_CONFIG
, "TX streams %d, RX streams: %d\n",
906 tx_streams
, rx_streams
);
907 ht_info
->mcs
.tx_params
|= IEEE80211_HT_MCS_TX_RX_DIFF
;
908 ht_info
->mcs
.tx_params
|= ((tx_streams
- 1) <<
909 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
912 ht_info
->mcs
.rx_mask
[0] = 0xff;
914 ht_info
->mcs
.rx_mask
[1] = 0xff;
916 ht_info
->mcs
.tx_params
|= IEEE80211_HT_MCS_TX_DEFINED
;
919 static void ath9k_bss_assoc_info(struct ath_softc
*sc
,
920 struct ieee80211_vif
*vif
,
921 struct ieee80211_bss_conf
*bss_conf
)
924 if (bss_conf
->assoc
) {
925 DPRINTF(sc
, ATH_DBG_CONFIG
, "Bss Info ASSOC %d, bssid: %pM\n",
926 bss_conf
->aid
, sc
->curbssid
);
928 /* New association, store aid */
929 sc
->curaid
= bss_conf
->aid
;
930 ath9k_hw_write_associd(sc
);
933 * Request a re-configuration of Beacon related timers
934 * on the receipt of the first Beacon frame (i.e.,
935 * after time sync with the AP).
937 sc
->sc_flags
|= SC_OP_BEACON_SYNC
;
939 /* Configure the beacon */
940 ath_beacon_config(sc
, vif
);
942 /* Reset rssi stats */
943 sc
->nodestats
.ns_avgbrssi
= ATH_RSSI_DUMMY_MARKER
;
944 sc
->nodestats
.ns_avgrssi
= ATH_RSSI_DUMMY_MARKER
;
945 sc
->nodestats
.ns_avgtxrssi
= ATH_RSSI_DUMMY_MARKER
;
946 sc
->nodestats
.ns_avgtxrate
= ATH_RATE_DUMMY_MARKER
;
950 DPRINTF(sc
, ATH_DBG_CONFIG
, "Bss Info DISASSOC\n");
953 del_timer_sync(&sc
->ani
.timer
);
957 /********************************/
959 /********************************/
961 static void ath_led_blink_work(struct work_struct
*work
)
963 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
964 ath_led_blink_work
.work
);
966 if (!(sc
->sc_flags
& SC_OP_LED_ASSOCIATED
))
969 if ((sc
->led_on_duration
== ATH_LED_ON_DURATION_IDLE
) ||
970 (sc
->led_off_duration
== ATH_LED_OFF_DURATION_IDLE
))
971 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 0);
973 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
,
974 (sc
->sc_flags
& SC_OP_LED_ON
) ? 1 : 0);
976 queue_delayed_work(sc
->hw
->workqueue
, &sc
->ath_led_blink_work
,
977 (sc
->sc_flags
& SC_OP_LED_ON
) ?
978 msecs_to_jiffies(sc
->led_off_duration
) :
979 msecs_to_jiffies(sc
->led_on_duration
));
981 sc
->led_on_duration
= sc
->led_on_cnt
?
982 max((ATH_LED_ON_DURATION_IDLE
- sc
->led_on_cnt
), 25) :
983 ATH_LED_ON_DURATION_IDLE
;
984 sc
->led_off_duration
= sc
->led_off_cnt
?
985 max((ATH_LED_OFF_DURATION_IDLE
- sc
->led_off_cnt
), 10) :
986 ATH_LED_OFF_DURATION_IDLE
;
987 sc
->led_on_cnt
= sc
->led_off_cnt
= 0;
988 if (sc
->sc_flags
& SC_OP_LED_ON
)
989 sc
->sc_flags
&= ~SC_OP_LED_ON
;
991 sc
->sc_flags
|= SC_OP_LED_ON
;
994 static void ath_led_brightness(struct led_classdev
*led_cdev
,
995 enum led_brightness brightness
)
997 struct ath_led
*led
= container_of(led_cdev
, struct ath_led
, led_cdev
);
998 struct ath_softc
*sc
= led
->sc
;
1000 switch (brightness
) {
1002 if (led
->led_type
== ATH_LED_ASSOC
||
1003 led
->led_type
== ATH_LED_RADIO
) {
1004 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
,
1005 (led
->led_type
== ATH_LED_RADIO
));
1006 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
1007 if (led
->led_type
== ATH_LED_RADIO
)
1008 sc
->sc_flags
&= ~SC_OP_LED_ON
;
1014 if (led
->led_type
== ATH_LED_ASSOC
) {
1015 sc
->sc_flags
|= SC_OP_LED_ASSOCIATED
;
1016 queue_delayed_work(sc
->hw
->workqueue
,
1017 &sc
->ath_led_blink_work
, 0);
1018 } else if (led
->led_type
== ATH_LED_RADIO
) {
1019 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 0);
1020 sc
->sc_flags
|= SC_OP_LED_ON
;
1030 static int ath_register_led(struct ath_softc
*sc
, struct ath_led
*led
,
1036 led
->led_cdev
.name
= led
->name
;
1037 led
->led_cdev
.default_trigger
= trigger
;
1038 led
->led_cdev
.brightness_set
= ath_led_brightness
;
1040 ret
= led_classdev_register(wiphy_dev(sc
->hw
->wiphy
), &led
->led_cdev
);
1042 DPRINTF(sc
, ATH_DBG_FATAL
,
1043 "Failed to register led:%s", led
->name
);
1045 led
->registered
= 1;
1049 static void ath_unregister_led(struct ath_led
*led
)
1051 if (led
->registered
) {
1052 led_classdev_unregister(&led
->led_cdev
);
1053 led
->registered
= 0;
1057 static void ath_deinit_leds(struct ath_softc
*sc
)
1059 cancel_delayed_work_sync(&sc
->ath_led_blink_work
);
1060 ath_unregister_led(&sc
->assoc_led
);
1061 sc
->sc_flags
&= ~SC_OP_LED_ASSOCIATED
;
1062 ath_unregister_led(&sc
->tx_led
);
1063 ath_unregister_led(&sc
->rx_led
);
1064 ath_unregister_led(&sc
->radio_led
);
1065 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
1068 static void ath_init_leds(struct ath_softc
*sc
)
1073 /* Configure gpio 1 for output */
1074 ath9k_hw_cfg_output(sc
->sc_ah
, ATH_LED_PIN
,
1075 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1076 /* LED off, active low */
1077 ath9k_hw_set_gpio(sc
->sc_ah
, ATH_LED_PIN
, 1);
1079 INIT_DELAYED_WORK(&sc
->ath_led_blink_work
, ath_led_blink_work
);
1081 trigger
= ieee80211_get_radio_led_name(sc
->hw
);
1082 snprintf(sc
->radio_led
.name
, sizeof(sc
->radio_led
.name
),
1083 "ath9k-%s::radio", wiphy_name(sc
->hw
->wiphy
));
1084 ret
= ath_register_led(sc
, &sc
->radio_led
, trigger
);
1085 sc
->radio_led
.led_type
= ATH_LED_RADIO
;
1089 trigger
= ieee80211_get_assoc_led_name(sc
->hw
);
1090 snprintf(sc
->assoc_led
.name
, sizeof(sc
->assoc_led
.name
),
1091 "ath9k-%s::assoc", wiphy_name(sc
->hw
->wiphy
));
1092 ret
= ath_register_led(sc
, &sc
->assoc_led
, trigger
);
1093 sc
->assoc_led
.led_type
= ATH_LED_ASSOC
;
1097 trigger
= ieee80211_get_tx_led_name(sc
->hw
);
1098 snprintf(sc
->tx_led
.name
, sizeof(sc
->tx_led
.name
),
1099 "ath9k-%s::tx", wiphy_name(sc
->hw
->wiphy
));
1100 ret
= ath_register_led(sc
, &sc
->tx_led
, trigger
);
1101 sc
->tx_led
.led_type
= ATH_LED_TX
;
1105 trigger
= ieee80211_get_rx_led_name(sc
->hw
);
1106 snprintf(sc
->rx_led
.name
, sizeof(sc
->rx_led
.name
),
1107 "ath9k-%s::rx", wiphy_name(sc
->hw
->wiphy
));
1108 ret
= ath_register_led(sc
, &sc
->rx_led
, trigger
);
1109 sc
->rx_led
.led_type
= ATH_LED_RX
;
1116 ath_deinit_leds(sc
);
1119 void ath_radio_enable(struct ath_softc
*sc
)
1121 struct ath_hw
*ah
= sc
->sc_ah
;
1122 struct ieee80211_channel
*channel
= sc
->hw
->conf
.channel
;
1125 ath9k_ps_wakeup(sc
);
1126 ath9k_hw_configpcipowersave(ah
, 0);
1129 ah
->curchan
= ath_get_curchannel(sc
, sc
->hw
);
1131 spin_lock_bh(&sc
->sc_resetlock
);
1132 r
= ath9k_hw_reset(ah
, ah
->curchan
, false);
1134 DPRINTF(sc
, ATH_DBG_FATAL
,
1135 "Unable to reset channel %u (%uMhz) ",
1136 "reset status %d\n",
1137 channel
->center_freq
, r
);
1139 spin_unlock_bh(&sc
->sc_resetlock
);
1141 ath_update_txpow(sc
);
1142 if (ath_startrecv(sc
) != 0) {
1143 DPRINTF(sc
, ATH_DBG_FATAL
,
1144 "Unable to restart recv logic\n");
1148 if (sc
->sc_flags
& SC_OP_BEACONS
)
1149 ath_beacon_config(sc
, NULL
); /* restart beacons */
1151 /* Re-Enable interrupts */
1152 ath9k_hw_set_interrupts(ah
, sc
->imask
);
1155 ath9k_hw_cfg_output(ah
, ATH_LED_PIN
,
1156 AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1157 ath9k_hw_set_gpio(ah
, ATH_LED_PIN
, 0);
1159 ieee80211_wake_queues(sc
->hw
);
1160 ath9k_ps_restore(sc
);
1163 void ath_radio_disable(struct ath_softc
*sc
)
1165 struct ath_hw
*ah
= sc
->sc_ah
;
1166 struct ieee80211_channel
*channel
= sc
->hw
->conf
.channel
;
1169 ath9k_ps_wakeup(sc
);
1170 ieee80211_stop_queues(sc
->hw
);
1173 ath9k_hw_set_gpio(ah
, ATH_LED_PIN
, 1);
1174 ath9k_hw_cfg_gpio_input(ah
, ATH_LED_PIN
);
1176 /* Disable interrupts */
1177 ath9k_hw_set_interrupts(ah
, 0);
1179 ath_drain_all_txq(sc
, false); /* clear pending tx frames */
1180 ath_stoprecv(sc
); /* turn off frame recv */
1181 ath_flushrecv(sc
); /* flush recv queue */
1184 ah
->curchan
= ath_get_curchannel(sc
, sc
->hw
);
1186 spin_lock_bh(&sc
->sc_resetlock
);
1187 r
= ath9k_hw_reset(ah
, ah
->curchan
, false);
1189 DPRINTF(sc
, ATH_DBG_FATAL
,
1190 "Unable to reset channel %u (%uMhz) "
1191 "reset status %d\n",
1192 channel
->center_freq
, r
);
1194 spin_unlock_bh(&sc
->sc_resetlock
);
1196 ath9k_hw_phy_disable(ah
);
1197 ath9k_hw_configpcipowersave(ah
, 1);
1198 ath9k_ps_restore(sc
);
1199 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1202 /*******************/
1204 /*******************/
1206 static bool ath_is_rfkill_set(struct ath_softc
*sc
)
1208 struct ath_hw
*ah
= sc
->sc_ah
;
1210 return ath9k_hw_gpio_get(ah
, ah
->rfkill_gpio
) ==
1211 ah
->rfkill_polarity
;
1214 static void ath9k_rfkill_poll_state(struct ieee80211_hw
*hw
)
1216 struct ath_wiphy
*aphy
= hw
->priv
;
1217 struct ath_softc
*sc
= aphy
->sc
;
1218 bool blocked
= !!ath_is_rfkill_set(sc
);
1220 wiphy_rfkill_set_hw_state(hw
->wiphy
, blocked
);
1223 ath_radio_disable(sc
);
1225 ath_radio_enable(sc
);
1228 static void ath_start_rfkill_poll(struct ath_softc
*sc
)
1230 struct ath_hw
*ah
= sc
->sc_ah
;
1232 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1233 wiphy_rfkill_start_polling(sc
->hw
->wiphy
);
1236 void ath_cleanup(struct ath_softc
*sc
)
1239 free_irq(sc
->irq
, sc
);
1240 ath_bus_cleanup(sc
);
1241 kfree(sc
->sec_wiphy
);
1242 ieee80211_free_hw(sc
->hw
);
1245 void ath_detach(struct ath_softc
*sc
)
1247 struct ieee80211_hw
*hw
= sc
->hw
;
1250 ath9k_ps_wakeup(sc
);
1252 DPRINTF(sc
, ATH_DBG_CONFIG
, "Detach ATH hw\n");
1254 ath_deinit_leds(sc
);
1255 cancel_work_sync(&sc
->chan_work
);
1256 cancel_delayed_work_sync(&sc
->wiphy_work
);
1257 cancel_delayed_work_sync(&sc
->tx_complete_work
);
1259 for (i
= 0; i
< sc
->num_sec_wiphy
; i
++) {
1260 struct ath_wiphy
*aphy
= sc
->sec_wiphy
[i
];
1263 sc
->sec_wiphy
[i
] = NULL
;
1264 ieee80211_unregister_hw(aphy
->hw
);
1265 ieee80211_free_hw(aphy
->hw
);
1267 ieee80211_unregister_hw(hw
);
1271 tasklet_kill(&sc
->intr_tq
);
1272 tasklet_kill(&sc
->bcon_tasklet
);
1274 if (!(sc
->sc_flags
& SC_OP_INVALID
))
1275 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_AWAKE
);
1277 /* cleanup tx queues */
1278 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1279 if (ATH_TXQ_SETUP(sc
, i
))
1280 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1282 ath9k_hw_detach(sc
->sc_ah
);
1283 ath9k_exit_debug(sc
);
1286 static int ath9k_reg_notifier(struct wiphy
*wiphy
,
1287 struct regulatory_request
*request
)
1289 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
1290 struct ath_wiphy
*aphy
= hw
->priv
;
1291 struct ath_softc
*sc
= aphy
->sc
;
1292 struct ath_regulatory
*reg
= &sc
->sc_ah
->regulatory
;
1294 return ath_reg_notifier_apply(wiphy
, request
, reg
);
1297 static int ath_init(u16 devid
, struct ath_softc
*sc
)
1299 struct ath_hw
*ah
= NULL
;
1304 /* XXX: hardware will not be ready until ath_open() being called */
1305 sc
->sc_flags
|= SC_OP_INVALID
;
1307 if (ath9k_init_debug(sc
) < 0)
1308 printk(KERN_ERR
"Unable to create debugfs files\n");
1310 spin_lock_init(&sc
->wiphy_lock
);
1311 spin_lock_init(&sc
->sc_resetlock
);
1312 spin_lock_init(&sc
->sc_serial_rw
);
1313 spin_lock_init(&sc
->ani_lock
);
1314 spin_lock_init(&sc
->sc_pm_lock
);
1315 mutex_init(&sc
->mutex
);
1316 tasklet_init(&sc
->intr_tq
, ath9k_tasklet
, (unsigned long)sc
);
1317 tasklet_init(&sc
->bcon_tasklet
, ath_beacon_tasklet
,
1321 * Cache line size is used to size and align various
1322 * structures used to communicate with the hardware.
1324 ath_read_cachesize(sc
, &csz
);
1325 /* XXX assert csz is non-zero */
1326 sc
->cachelsz
= csz
<< 2; /* convert to bytes */
1328 ah
= ath9k_hw_attach(devid
, sc
, &status
);
1330 DPRINTF(sc
, ATH_DBG_FATAL
,
1331 "Unable to attach hardware; HAL status %d\n", status
);
1337 /* Get the hardware key cache size. */
1338 sc
->keymax
= ah
->caps
.keycache_size
;
1339 if (sc
->keymax
> ATH_KEYMAX
) {
1340 DPRINTF(sc
, ATH_DBG_ANY
,
1341 "Warning, using only %u entries in %u key cache\n",
1342 ATH_KEYMAX
, sc
->keymax
);
1343 sc
->keymax
= ATH_KEYMAX
;
1347 * Reset the key cache since some parts do not
1348 * reset the contents on initial power up.
1350 for (i
= 0; i
< sc
->keymax
; i
++)
1351 ath9k_hw_keyreset(ah
, (u16
) i
);
1356 /* default to MONITOR mode */
1357 sc
->sc_ah
->opmode
= NL80211_IFTYPE_MONITOR
;
1359 /* Setup rate tables */
1361 ath_rate_attach(sc
);
1362 ath_setup_rates(sc
, IEEE80211_BAND_2GHZ
);
1363 ath_setup_rates(sc
, IEEE80211_BAND_5GHZ
);
1366 * Allocate hardware transmit queues: one queue for
1367 * beacon frames and one data queue for each QoS
1368 * priority. Note that the hal handles reseting
1369 * these queues at the needed time.
1371 sc
->beacon
.beaconq
= ath_beaconq_setup(ah
);
1372 if (sc
->beacon
.beaconq
== -1) {
1373 DPRINTF(sc
, ATH_DBG_FATAL
,
1374 "Unable to setup a beacon xmit queue\n");
1378 sc
->beacon
.cabq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_CAB
, 0);
1379 if (sc
->beacon
.cabq
== NULL
) {
1380 DPRINTF(sc
, ATH_DBG_FATAL
,
1381 "Unable to setup CAB xmit queue\n");
1386 sc
->config
.cabqReadytime
= ATH_CABQ_READY_TIME
;
1387 ath_cabq_update(sc
);
1389 for (i
= 0; i
< ARRAY_SIZE(sc
->tx
.hwq_map
); i
++)
1390 sc
->tx
.hwq_map
[i
] = -1;
1392 /* Setup data queues */
1393 /* NB: ensure BK queue is the lowest priority h/w queue */
1394 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BK
)) {
1395 DPRINTF(sc
, ATH_DBG_FATAL
,
1396 "Unable to setup xmit queue for BK traffic\n");
1401 if (!ath_tx_setup(sc
, ATH9K_WME_AC_BE
)) {
1402 DPRINTF(sc
, ATH_DBG_FATAL
,
1403 "Unable to setup xmit queue for BE traffic\n");
1407 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VI
)) {
1408 DPRINTF(sc
, ATH_DBG_FATAL
,
1409 "Unable to setup xmit queue for VI traffic\n");
1413 if (!ath_tx_setup(sc
, ATH9K_WME_AC_VO
)) {
1414 DPRINTF(sc
, ATH_DBG_FATAL
,
1415 "Unable to setup xmit queue for VO traffic\n");
1420 /* Initializes the noise floor to a reasonable default value.
1421 * Later on this will be updated during ANI processing. */
1423 sc
->ani
.noise_floor
= ATH_DEFAULT_NOISE_FLOOR
;
1424 setup_timer(&sc
->ani
.timer
, ath_ani_calibrate
, (unsigned long)sc
);
1426 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1427 ATH9K_CIPHER_TKIP
, NULL
)) {
1429 * Whether we should enable h/w TKIP MIC.
1430 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1431 * report WMM capable, so it's always safe to turn on
1432 * TKIP MIC in this case.
1434 ath9k_hw_setcapability(sc
->sc_ah
, ATH9K_CAP_TKIP_MIC
,
1439 * Check whether the separate key cache entries
1440 * are required to handle both tx+rx MIC keys.
1441 * With split mic keys the number of stations is limited
1442 * to 27 otherwise 59.
1444 if (ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1445 ATH9K_CIPHER_TKIP
, NULL
)
1446 && ath9k_hw_getcapability(ah
, ATH9K_CAP_CIPHER
,
1447 ATH9K_CIPHER_MIC
, NULL
)
1448 && ath9k_hw_getcapability(ah
, ATH9K_CAP_TKIP_SPLIT
,
1452 /* turn on mcast key search if possible */
1453 if (!ath9k_hw_getcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 0, NULL
))
1454 (void)ath9k_hw_setcapability(ah
, ATH9K_CAP_MCAST_KEYSRCH
, 1,
1457 sc
->config
.txpowlimit
= ATH_TXPOWER_MAX
;
1459 /* 11n Capabilities */
1460 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1461 sc
->sc_flags
|= SC_OP_TXAGGR
;
1462 sc
->sc_flags
|= SC_OP_RXAGGR
;
1465 sc
->tx_chainmask
= ah
->caps
.tx_chainmask
;
1466 sc
->rx_chainmask
= ah
->caps
.rx_chainmask
;
1468 ath9k_hw_setcapability(ah
, ATH9K_CAP_DIVERSITY
, 1, true, NULL
);
1469 sc
->rx
.defant
= ath9k_hw_getdefantenna(ah
);
1471 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
1472 memcpy(sc
->bssidmask
, ath_bcast_mac
, ETH_ALEN
);
1474 sc
->beacon
.slottime
= ATH9K_SLOT_TIME_9
; /* default to short slot time */
1476 /* initialize beacon slots */
1477 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++) {
1478 sc
->beacon
.bslot
[i
] = NULL
;
1479 sc
->beacon
.bslot_aphy
[i
] = NULL
;
1482 /* setup channels and rates */
1484 sc
->sbands
[IEEE80211_BAND_2GHZ
].channels
= ath9k_2ghz_chantable
;
1485 sc
->sbands
[IEEE80211_BAND_2GHZ
].bitrates
=
1486 sc
->rates
[IEEE80211_BAND_2GHZ
];
1487 sc
->sbands
[IEEE80211_BAND_2GHZ
].band
= IEEE80211_BAND_2GHZ
;
1488 sc
->sbands
[IEEE80211_BAND_2GHZ
].n_channels
=
1489 ARRAY_SIZE(ath9k_2ghz_chantable
);
1491 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
)) {
1492 sc
->sbands
[IEEE80211_BAND_5GHZ
].channels
= ath9k_5ghz_chantable
;
1493 sc
->sbands
[IEEE80211_BAND_5GHZ
].bitrates
=
1494 sc
->rates
[IEEE80211_BAND_5GHZ
];
1495 sc
->sbands
[IEEE80211_BAND_5GHZ
].band
= IEEE80211_BAND_5GHZ
;
1496 sc
->sbands
[IEEE80211_BAND_5GHZ
].n_channels
=
1497 ARRAY_SIZE(ath9k_5ghz_chantable
);
1500 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BT_COEX
)
1501 ath9k_hw_btcoex_enable(sc
->sc_ah
);
1505 /* cleanup tx queues */
1506 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1507 if (ATH_TXQ_SETUP(sc
, i
))
1508 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1511 ath9k_hw_detach(ah
);
1512 ath9k_exit_debug(sc
);
1517 void ath_set_hw_capab(struct ath_softc
*sc
, struct ieee80211_hw
*hw
)
1519 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
1520 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1521 IEEE80211_HW_SIGNAL_DBM
|
1522 IEEE80211_HW_AMPDU_AGGREGATION
|
1523 IEEE80211_HW_SUPPORTS_PS
|
1524 IEEE80211_HW_PS_NULLFUNC_STACK
|
1525 IEEE80211_HW_SPECTRUM_MGMT
;
1527 if (AR_SREV_9160_10_OR_LATER(sc
->sc_ah
) || modparam_nohwcrypt
)
1528 hw
->flags
|= IEEE80211_HW_MFP_CAPABLE
;
1530 hw
->wiphy
->interface_modes
=
1531 BIT(NL80211_IFTYPE_AP
) |
1532 BIT(NL80211_IFTYPE_STATION
) |
1533 BIT(NL80211_IFTYPE_ADHOC
) |
1534 BIT(NL80211_IFTYPE_MESH_POINT
);
1538 hw
->channel_change_time
= 5000;
1539 hw
->max_listen_interval
= 10;
1540 /* Hardware supports 10 but we use 4 */
1541 hw
->max_rate_tries
= 4;
1542 hw
->sta_data_size
= sizeof(struct ath_node
);
1543 hw
->vif_data_size
= sizeof(struct ath_vif
);
1545 hw
->rate_control_algorithm
= "ath9k_rate_control";
1547 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
1548 &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1549 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
))
1550 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
1551 &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1554 int ath_attach(u16 devid
, struct ath_softc
*sc
)
1556 struct ieee80211_hw
*hw
= sc
->hw
;
1558 struct ath_regulatory
*reg
;
1560 DPRINTF(sc
, ATH_DBG_CONFIG
, "Attach ATH hw\n");
1562 error
= ath_init(devid
, sc
);
1566 /* get mac address from hardware and set in mac80211 */
1568 SET_IEEE80211_PERM_ADDR(hw
, sc
->sc_ah
->macaddr
);
1570 ath_set_hw_capab(sc
, hw
);
1572 error
= ath_regd_init(&sc
->sc_ah
->regulatory
, sc
->hw
->wiphy
,
1573 ath9k_reg_notifier
);
1577 reg
= &sc
->sc_ah
->regulatory
;
1579 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1580 setup_ht_cap(sc
, &sc
->sbands
[IEEE80211_BAND_2GHZ
].ht_cap
);
1581 if (test_bit(ATH9K_MODE_11A
, sc
->sc_ah
->caps
.wireless_modes
))
1582 setup_ht_cap(sc
, &sc
->sbands
[IEEE80211_BAND_5GHZ
].ht_cap
);
1585 /* initialize tx/rx engine */
1586 error
= ath_tx_init(sc
, ATH_TXBUF
);
1590 error
= ath_rx_init(sc
, ATH_RXBUF
);
1594 INIT_WORK(&sc
->chan_work
, ath9k_wiphy_chan_work
);
1595 INIT_DELAYED_WORK(&sc
->wiphy_work
, ath9k_wiphy_work
);
1596 sc
->wiphy_scheduler_int
= msecs_to_jiffies(500);
1598 error
= ieee80211_register_hw(hw
);
1600 if (!ath_is_world_regd(reg
)) {
1601 error
= regulatory_hint(hw
->wiphy
, reg
->alpha2
);
1606 /* Initialize LED control */
1609 ath_start_rfkill_poll(sc
);
1614 /* cleanup tx queues */
1615 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1616 if (ATH_TXQ_SETUP(sc
, i
))
1617 ath_tx_cleanupq(sc
, &sc
->tx
.txq
[i
]);
1619 ath9k_hw_detach(sc
->sc_ah
);
1620 ath9k_exit_debug(sc
);
1625 int ath_reset(struct ath_softc
*sc
, bool retry_tx
)
1627 struct ath_hw
*ah
= sc
->sc_ah
;
1628 struct ieee80211_hw
*hw
= sc
->hw
;
1631 ath9k_hw_set_interrupts(ah
, 0);
1632 ath_drain_all_txq(sc
, retry_tx
);
1636 spin_lock_bh(&sc
->sc_resetlock
);
1637 r
= ath9k_hw_reset(ah
, sc
->sc_ah
->curchan
, false);
1639 DPRINTF(sc
, ATH_DBG_FATAL
,
1640 "Unable to reset hardware; reset status %d\n", r
);
1641 spin_unlock_bh(&sc
->sc_resetlock
);
1643 if (ath_startrecv(sc
) != 0)
1644 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to start recv logic\n");
1647 * We may be doing a reset in response to a request
1648 * that changes the channel so update any state that
1649 * might change as a result.
1651 ath_cache_conf_rate(sc
, &hw
->conf
);
1653 ath_update_txpow(sc
);
1655 if (sc
->sc_flags
& SC_OP_BEACONS
)
1656 ath_beacon_config(sc
, NULL
); /* restart beacons */
1658 ath9k_hw_set_interrupts(ah
, sc
->imask
);
1662 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1663 if (ATH_TXQ_SETUP(sc
, i
)) {
1664 spin_lock_bh(&sc
->tx
.txq
[i
].axq_lock
);
1665 ath_txq_schedule(sc
, &sc
->tx
.txq
[i
]);
1666 spin_unlock_bh(&sc
->tx
.txq
[i
].axq_lock
);
1675 * This function will allocate both the DMA descriptor structure, and the
1676 * buffers it contains. These are used to contain the descriptors used
1679 int ath_descdma_setup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
1680 struct list_head
*head
, const char *name
,
1681 int nbuf
, int ndesc
)
1683 #define DS2PHYS(_dd, _ds) \
1684 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1685 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1686 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1688 struct ath_desc
*ds
;
1690 int i
, bsize
, error
;
1692 DPRINTF(sc
, ATH_DBG_CONFIG
, "%s DMA: %u buffers %u desc/buf\n",
1695 INIT_LIST_HEAD(head
);
1696 /* ath_desc must be a multiple of DWORDs */
1697 if ((sizeof(struct ath_desc
) % 4) != 0) {
1698 DPRINTF(sc
, ATH_DBG_FATAL
, "ath_desc not DWORD aligned\n");
1699 ASSERT((sizeof(struct ath_desc
) % 4) == 0);
1704 dd
->dd_desc_len
= sizeof(struct ath_desc
) * nbuf
* ndesc
;
1707 * Need additional DMA memory because we can't use
1708 * descriptors that cross the 4K page boundary. Assume
1709 * one skipped descriptor per 4K page.
1711 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
1713 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd
->dd_desc_len
);
1716 while (ndesc_skipped
) {
1717 dma_len
= ndesc_skipped
* sizeof(struct ath_desc
);
1718 dd
->dd_desc_len
+= dma_len
;
1720 ndesc_skipped
= ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len
);
1724 /* allocate descriptors */
1725 dd
->dd_desc
= dma_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
1726 &dd
->dd_desc_paddr
, GFP_KERNEL
);
1727 if (dd
->dd_desc
== NULL
) {
1732 DPRINTF(sc
, ATH_DBG_CONFIG
, "%s DMA map: %p (%u) -> %llx (%u)\n",
1733 name
, ds
, (u32
) dd
->dd_desc_len
,
1734 ito64(dd
->dd_desc_paddr
), /*XXX*/(u32
) dd
->dd_desc_len
);
1736 /* allocate buffers */
1737 bsize
= sizeof(struct ath_buf
) * nbuf
;
1738 bf
= kzalloc(bsize
, GFP_KERNEL
);
1745 for (i
= 0; i
< nbuf
; i
++, bf
++, ds
+= ndesc
) {
1747 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
1749 if (!(sc
->sc_ah
->caps
.hw_caps
&
1750 ATH9K_HW_CAP_4KB_SPLITTRANS
)) {
1752 * Skip descriptor addresses which can cause 4KB
1753 * boundary crossing (addr + length) with a 32 dword
1756 while (ATH_DESC_4KB_BOUND_CHECK(bf
->bf_daddr
)) {
1757 ASSERT((caddr_t
) bf
->bf_desc
<
1758 ((caddr_t
) dd
->dd_desc
+
1763 bf
->bf_daddr
= DS2PHYS(dd
, ds
);
1766 list_add_tail(&bf
->list
, head
);
1770 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
1773 memset(dd
, 0, sizeof(*dd
));
1775 #undef ATH_DESC_4KB_BOUND_CHECK
1776 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1780 void ath_descdma_cleanup(struct ath_softc
*sc
,
1781 struct ath_descdma
*dd
,
1782 struct list_head
*head
)
1784 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
1787 INIT_LIST_HEAD(head
);
1788 kfree(dd
->dd_bufptr
);
1789 memset(dd
, 0, sizeof(*dd
));
1792 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
)
1798 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VO
];
1801 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_VI
];
1804 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
1807 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BK
];
1810 qnum
= sc
->tx
.hwq_map
[ATH9K_WME_AC_BE
];
1817 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
)
1822 case ATH9K_WME_AC_VO
:
1825 case ATH9K_WME_AC_VI
:
1828 case ATH9K_WME_AC_BE
:
1831 case ATH9K_WME_AC_BK
:
1842 /* XXX: Remove me once we don't depend on ath9k_channel for all
1843 * this redundant data */
1844 void ath9k_update_ichannel(struct ath_softc
*sc
, struct ieee80211_hw
*hw
,
1845 struct ath9k_channel
*ichan
)
1847 struct ieee80211_channel
*chan
= hw
->conf
.channel
;
1848 struct ieee80211_conf
*conf
= &hw
->conf
;
1850 ichan
->channel
= chan
->center_freq
;
1853 if (chan
->band
== IEEE80211_BAND_2GHZ
) {
1854 ichan
->chanmode
= CHANNEL_G
;
1855 ichan
->channelFlags
= CHANNEL_2GHZ
| CHANNEL_OFDM
;
1857 ichan
->chanmode
= CHANNEL_A
;
1858 ichan
->channelFlags
= CHANNEL_5GHZ
| CHANNEL_OFDM
;
1861 sc
->tx_chan_width
= ATH9K_HT_MACMODE_20
;
1863 if (conf_is_ht(conf
)) {
1864 if (conf_is_ht40(conf
))
1865 sc
->tx_chan_width
= ATH9K_HT_MACMODE_2040
;
1867 ichan
->chanmode
= ath_get_extchanmode(sc
, chan
,
1868 conf
->channel_type
);
1872 /**********************/
1873 /* mac80211 callbacks */
1874 /**********************/
1876 static int ath9k_start(struct ieee80211_hw
*hw
)
1878 struct ath_wiphy
*aphy
= hw
->priv
;
1879 struct ath_softc
*sc
= aphy
->sc
;
1880 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
1881 struct ath9k_channel
*init_channel
;
1884 DPRINTF(sc
, ATH_DBG_CONFIG
, "Starting driver with "
1885 "initial channel: %d MHz\n", curchan
->center_freq
);
1887 mutex_lock(&sc
->mutex
);
1889 if (ath9k_wiphy_started(sc
)) {
1890 if (sc
->chan_idx
== curchan
->hw_value
) {
1892 * Already on the operational channel, the new wiphy
1893 * can be marked active.
1895 aphy
->state
= ATH_WIPHY_ACTIVE
;
1896 ieee80211_wake_queues(hw
);
1899 * Another wiphy is on another channel, start the new
1900 * wiphy in paused state.
1902 aphy
->state
= ATH_WIPHY_PAUSED
;
1903 ieee80211_stop_queues(hw
);
1905 mutex_unlock(&sc
->mutex
);
1908 aphy
->state
= ATH_WIPHY_ACTIVE
;
1910 /* setup initial channel */
1912 sc
->chan_idx
= curchan
->hw_value
;
1914 init_channel
= ath_get_curchannel(sc
, hw
);
1916 /* Reset SERDES registers */
1917 ath9k_hw_configpcipowersave(sc
->sc_ah
, 0);
1920 * The basic interface to setting the hardware in a good
1921 * state is ``reset''. On return the hardware is known to
1922 * be powered up and with interrupts disabled. This must
1923 * be followed by initialization of the appropriate bits
1924 * and then setup of the interrupt mask.
1926 spin_lock_bh(&sc
->sc_resetlock
);
1927 r
= ath9k_hw_reset(sc
->sc_ah
, init_channel
, false);
1929 DPRINTF(sc
, ATH_DBG_FATAL
,
1930 "Unable to reset hardware; reset status %d "
1931 "(freq %u MHz)\n", r
,
1932 curchan
->center_freq
);
1933 spin_unlock_bh(&sc
->sc_resetlock
);
1936 spin_unlock_bh(&sc
->sc_resetlock
);
1939 * This is needed only to setup initial state
1940 * but it's best done after a reset.
1942 ath_update_txpow(sc
);
1945 * Setup the hardware after reset:
1946 * The receive engine is set going.
1947 * Frame transmit is handled entirely
1948 * in the frame output path; there's nothing to do
1949 * here except setup the interrupt mask.
1951 if (ath_startrecv(sc
) != 0) {
1952 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to start recv logic\n");
1957 /* Setup our intr mask. */
1958 sc
->imask
= ATH9K_INT_RX
| ATH9K_INT_TX
1959 | ATH9K_INT_RXEOL
| ATH9K_INT_RXORN
1960 | ATH9K_INT_FATAL
| ATH9K_INT_GLOBAL
;
1962 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_GTT
)
1963 sc
->imask
|= ATH9K_INT_GTT
;
1965 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
)
1966 sc
->imask
|= ATH9K_INT_CST
;
1968 ath_cache_conf_rate(sc
, &hw
->conf
);
1970 sc
->sc_flags
&= ~SC_OP_INVALID
;
1972 /* Disable BMISS interrupt when we're not associated */
1973 sc
->imask
&= ~(ATH9K_INT_SWBA
| ATH9K_INT_BMISS
);
1974 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
1976 ieee80211_wake_queues(hw
);
1978 queue_delayed_work(sc
->hw
->workqueue
, &sc
->tx_complete_work
, 0);
1981 mutex_unlock(&sc
->mutex
);
1986 static int ath9k_tx(struct ieee80211_hw
*hw
,
1987 struct sk_buff
*skb
)
1989 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1990 struct ath_wiphy
*aphy
= hw
->priv
;
1991 struct ath_softc
*sc
= aphy
->sc
;
1992 struct ath_tx_control txctl
;
1993 int hdrlen
, padsize
;
1995 if (aphy
->state
!= ATH_WIPHY_ACTIVE
&& aphy
->state
!= ATH_WIPHY_SCAN
) {
1996 printk(KERN_DEBUG
"ath9k: %s: TX in unexpected wiphy state "
1997 "%d\n", wiphy_name(hw
->wiphy
), aphy
->state
);
2001 if (sc
->ps_enabled
) {
2002 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2004 * mac80211 does not set PM field for normal data frames, so we
2005 * need to update that based on the current PS mode.
2007 if (ieee80211_is_data(hdr
->frame_control
) &&
2008 !ieee80211_is_nullfunc(hdr
->frame_control
) &&
2009 !ieee80211_has_pm(hdr
->frame_control
)) {
2010 DPRINTF(sc
, ATH_DBG_PS
, "Add PM=1 for a TX frame "
2011 "while in PS mode\n");
2012 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_PM
);
2016 if (unlikely(sc
->sc_ah
->power_mode
!= ATH9K_PM_AWAKE
)) {
2018 * We are using PS-Poll and mac80211 can request TX while in
2019 * power save mode. Need to wake up hardware for the TX to be
2020 * completed and if needed, also for RX of buffered frames.
2022 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2023 ath9k_ps_wakeup(sc
);
2024 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
2025 if (ieee80211_is_pspoll(hdr
->frame_control
)) {
2026 DPRINTF(sc
, ATH_DBG_PS
, "Sending PS-Poll to pick a "
2027 "buffered frame\n");
2028 sc
->sc_flags
|= SC_OP_WAIT_FOR_PSPOLL_DATA
;
2030 DPRINTF(sc
, ATH_DBG_PS
, "Wake up to complete TX\n");
2031 sc
->sc_flags
|= SC_OP_WAIT_FOR_TX_ACK
;
2034 * The actual restore operation will happen only after
2035 * the sc_flags bit is cleared. We are just dropping
2036 * the ps_usecount here.
2038 ath9k_ps_restore(sc
);
2041 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
2044 * As a temporary workaround, assign seq# here; this will likely need
2045 * to be cleaned up to work better with Beacon transmission and virtual
2048 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2049 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2050 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2051 sc
->tx
.seq_no
+= 0x10;
2052 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2053 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
2056 /* Add the padding after the header if this is not already done */
2057 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2059 padsize
= hdrlen
% 4;
2060 if (skb_headroom(skb
) < padsize
)
2062 skb_push(skb
, padsize
);
2063 memmove(skb
->data
, skb
->data
+ padsize
, hdrlen
);
2066 /* Check if a tx queue is available */
2068 txctl
.txq
= ath_test_get_txq(sc
, skb
);
2072 DPRINTF(sc
, ATH_DBG_XMIT
, "transmitting packet, skb: %p\n", skb
);
2074 if (ath_tx_start(hw
, skb
, &txctl
) != 0) {
2075 DPRINTF(sc
, ATH_DBG_XMIT
, "TX failed\n");
2081 dev_kfree_skb_any(skb
);
2085 static void ath9k_stop(struct ieee80211_hw
*hw
)
2087 struct ath_wiphy
*aphy
= hw
->priv
;
2088 struct ath_softc
*sc
= aphy
->sc
;
2090 aphy
->state
= ATH_WIPHY_INACTIVE
;
2092 if (sc
->sc_flags
& SC_OP_INVALID
) {
2093 DPRINTF(sc
, ATH_DBG_ANY
, "Device not present\n");
2097 mutex_lock(&sc
->mutex
);
2099 if (ath9k_wiphy_started(sc
)) {
2100 mutex_unlock(&sc
->mutex
);
2101 return; /* another wiphy still in use */
2104 /* make sure h/w will not generate any interrupt
2105 * before setting the invalid flag. */
2106 ath9k_hw_set_interrupts(sc
->sc_ah
, 0);
2108 if (!(sc
->sc_flags
& SC_OP_INVALID
)) {
2109 ath_drain_all_txq(sc
, false);
2111 ath9k_hw_phy_disable(sc
->sc_ah
);
2113 sc
->rx
.rxlink
= NULL
;
2115 wiphy_rfkill_stop_polling(sc
->hw
->wiphy
);
2117 /* disable HAL and put h/w to sleep */
2118 ath9k_hw_disable(sc
->sc_ah
);
2119 ath9k_hw_configpcipowersave(sc
->sc_ah
, 1);
2121 sc
->sc_flags
|= SC_OP_INVALID
;
2123 mutex_unlock(&sc
->mutex
);
2125 DPRINTF(sc
, ATH_DBG_CONFIG
, "Driver halt\n");
2128 static int ath9k_add_interface(struct ieee80211_hw
*hw
,
2129 struct ieee80211_if_init_conf
*conf
)
2131 struct ath_wiphy
*aphy
= hw
->priv
;
2132 struct ath_softc
*sc
= aphy
->sc
;
2133 struct ath_vif
*avp
= (void *)conf
->vif
->drv_priv
;
2134 enum nl80211_iftype ic_opmode
= NL80211_IFTYPE_UNSPECIFIED
;
2137 mutex_lock(&sc
->mutex
);
2139 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
) &&
2145 switch (conf
->type
) {
2146 case NL80211_IFTYPE_STATION
:
2147 ic_opmode
= NL80211_IFTYPE_STATION
;
2149 case NL80211_IFTYPE_ADHOC
:
2150 case NL80211_IFTYPE_AP
:
2151 case NL80211_IFTYPE_MESH_POINT
:
2152 if (sc
->nbcnvifs
>= ATH_BCBUF
) {
2156 ic_opmode
= conf
->type
;
2159 DPRINTF(sc
, ATH_DBG_FATAL
,
2160 "Interface type %d not yet supported\n", conf
->type
);
2165 DPRINTF(sc
, ATH_DBG_CONFIG
, "Attach a VIF of type: %d\n", ic_opmode
);
2167 /* Set the VIF opmode */
2168 avp
->av_opmode
= ic_opmode
;
2173 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
2174 ath9k_set_bssid_mask(hw
);
2177 goto out
; /* skip global settings for secondary vif */
2179 if (ic_opmode
== NL80211_IFTYPE_AP
) {
2180 ath9k_hw_set_tsfadjust(sc
->sc_ah
, 1);
2181 sc
->sc_flags
|= SC_OP_TSF_RESET
;
2184 /* Set the device opmode */
2185 sc
->sc_ah
->opmode
= ic_opmode
;
2188 * Enable MIB interrupts when there are hardware phy counters.
2189 * Note we only do this (at the moment) for station mode.
2191 if ((conf
->type
== NL80211_IFTYPE_STATION
) ||
2192 (conf
->type
== NL80211_IFTYPE_ADHOC
) ||
2193 (conf
->type
== NL80211_IFTYPE_MESH_POINT
)) {
2194 if (ath9k_hw_phycounters(sc
->sc_ah
))
2195 sc
->imask
|= ATH9K_INT_MIB
;
2196 sc
->imask
|= ATH9K_INT_TSFOOR
;
2199 ath9k_hw_set_interrupts(sc
->sc_ah
, sc
->imask
);
2201 if (conf
->type
== NL80211_IFTYPE_AP
||
2202 conf
->type
== NL80211_IFTYPE_ADHOC
||
2203 conf
->type
== NL80211_IFTYPE_MONITOR
)
2207 mutex_unlock(&sc
->mutex
);
2211 static void ath9k_remove_interface(struct ieee80211_hw
*hw
,
2212 struct ieee80211_if_init_conf
*conf
)
2214 struct ath_wiphy
*aphy
= hw
->priv
;
2215 struct ath_softc
*sc
= aphy
->sc
;
2216 struct ath_vif
*avp
= (void *)conf
->vif
->drv_priv
;
2219 DPRINTF(sc
, ATH_DBG_CONFIG
, "Detach Interface\n");
2221 mutex_lock(&sc
->mutex
);
2224 del_timer_sync(&sc
->ani
.timer
);
2226 /* Reclaim beacon resources */
2227 if ((sc
->sc_ah
->opmode
== NL80211_IFTYPE_AP
) ||
2228 (sc
->sc_ah
->opmode
== NL80211_IFTYPE_ADHOC
) ||
2229 (sc
->sc_ah
->opmode
== NL80211_IFTYPE_MESH_POINT
)) {
2230 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2231 ath_beacon_return(sc
, avp
);
2234 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2236 for (i
= 0; i
< ARRAY_SIZE(sc
->beacon
.bslot
); i
++) {
2237 if (sc
->beacon
.bslot
[i
] == conf
->vif
) {
2238 printk(KERN_DEBUG
"%s: vif had allocated beacon "
2239 "slot\n", __func__
);
2240 sc
->beacon
.bslot
[i
] = NULL
;
2241 sc
->beacon
.bslot_aphy
[i
] = NULL
;
2247 mutex_unlock(&sc
->mutex
);
2250 static int ath9k_config(struct ieee80211_hw
*hw
, u32 changed
)
2252 struct ath_wiphy
*aphy
= hw
->priv
;
2253 struct ath_softc
*sc
= aphy
->sc
;
2254 struct ieee80211_conf
*conf
= &hw
->conf
;
2255 struct ath_hw
*ah
= sc
->sc_ah
;
2256 bool all_wiphys_idle
= false, disable_radio
= false;
2258 mutex_lock(&sc
->mutex
);
2260 /* Leave this as the first check */
2261 if (changed
& IEEE80211_CONF_CHANGE_IDLE
) {
2263 spin_lock_bh(&sc
->wiphy_lock
);
2264 all_wiphys_idle
= ath9k_all_wiphys_idle(sc
);
2265 spin_unlock_bh(&sc
->wiphy_lock
);
2267 if (conf
->flags
& IEEE80211_CONF_IDLE
){
2268 if (all_wiphys_idle
)
2269 disable_radio
= true;
2271 else if (all_wiphys_idle
) {
2272 ath_radio_enable(sc
);
2273 DPRINTF(sc
, ATH_DBG_CONFIG
,
2274 "not-idle: enabling radio\n");
2278 if (changed
& IEEE80211_CONF_CHANGE_PS
) {
2279 if (conf
->flags
& IEEE80211_CONF_PS
) {
2280 if (!(ah
->caps
.hw_caps
&
2281 ATH9K_HW_CAP_AUTOSLEEP
)) {
2282 if ((sc
->imask
& ATH9K_INT_TIM_TIMER
) == 0) {
2283 sc
->imask
|= ATH9K_INT_TIM_TIMER
;
2284 ath9k_hw_set_interrupts(sc
->sc_ah
,
2287 ath9k_hw_setrxabort(sc
->sc_ah
, 1);
2289 sc
->ps_enabled
= true;
2291 sc
->ps_enabled
= false;
2292 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_AWAKE
);
2293 if (!(ah
->caps
.hw_caps
&
2294 ATH9K_HW_CAP_AUTOSLEEP
)) {
2295 ath9k_hw_setrxabort(sc
->sc_ah
, 0);
2296 sc
->sc_flags
&= ~(SC_OP_WAIT_FOR_BEACON
|
2297 SC_OP_WAIT_FOR_CAB
|
2298 SC_OP_WAIT_FOR_PSPOLL_DATA
|
2299 SC_OP_WAIT_FOR_TX_ACK
);
2300 if (sc
->imask
& ATH9K_INT_TIM_TIMER
) {
2301 sc
->imask
&= ~ATH9K_INT_TIM_TIMER
;
2302 ath9k_hw_set_interrupts(sc
->sc_ah
,
2309 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2310 struct ieee80211_channel
*curchan
= hw
->conf
.channel
;
2311 int pos
= curchan
->hw_value
;
2313 aphy
->chan_idx
= pos
;
2314 aphy
->chan_is_ht
= conf_is_ht(conf
);
2316 if (aphy
->state
== ATH_WIPHY_SCAN
||
2317 aphy
->state
== ATH_WIPHY_ACTIVE
)
2318 ath9k_wiphy_pause_all_forced(sc
, aphy
);
2321 * Do not change operational channel based on a paused
2324 goto skip_chan_change
;
2327 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set channel: %d MHz\n",
2328 curchan
->center_freq
);
2330 /* XXX: remove me eventualy */
2331 ath9k_update_ichannel(sc
, hw
, &sc
->sc_ah
->channels
[pos
]);
2333 ath_update_chainmask(sc
, conf_is_ht(conf
));
2335 if (ath_set_channel(sc
, hw
, &sc
->sc_ah
->channels
[pos
]) < 0) {
2336 DPRINTF(sc
, ATH_DBG_FATAL
, "Unable to set channel\n");
2337 mutex_unlock(&sc
->mutex
);
2343 if (changed
& IEEE80211_CONF_CHANGE_POWER
)
2344 sc
->config
.txpowlimit
= 2 * conf
->power_level
;
2346 if (disable_radio
) {
2347 DPRINTF(sc
, ATH_DBG_CONFIG
, "idle: disabling radio\n");
2348 ath_radio_disable(sc
);
2351 mutex_unlock(&sc
->mutex
);
2356 #define SUPPORTED_FILTERS \
2357 (FIF_PROMISC_IN_BSS | \
2361 FIF_BCN_PRBRESP_PROMISC | \
2364 /* FIXME: sc->sc_full_reset ? */
2365 static void ath9k_configure_filter(struct ieee80211_hw
*hw
,
2366 unsigned int changed_flags
,
2367 unsigned int *total_flags
,
2369 struct dev_mc_list
*mclist
)
2371 struct ath_wiphy
*aphy
= hw
->priv
;
2372 struct ath_softc
*sc
= aphy
->sc
;
2375 changed_flags
&= SUPPORTED_FILTERS
;
2376 *total_flags
&= SUPPORTED_FILTERS
;
2378 sc
->rx
.rxfilter
= *total_flags
;
2379 ath9k_ps_wakeup(sc
);
2380 rfilt
= ath_calcrxfilter(sc
);
2381 ath9k_hw_setrxfilter(sc
->sc_ah
, rfilt
);
2382 ath9k_ps_restore(sc
);
2384 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set HW RX filter: 0x%x\n", sc
->rx
.rxfilter
);
2387 static void ath9k_sta_notify(struct ieee80211_hw
*hw
,
2388 struct ieee80211_vif
*vif
,
2389 enum sta_notify_cmd cmd
,
2390 struct ieee80211_sta
*sta
)
2392 struct ath_wiphy
*aphy
= hw
->priv
;
2393 struct ath_softc
*sc
= aphy
->sc
;
2396 case STA_NOTIFY_ADD
:
2397 ath_node_attach(sc
, sta
);
2399 case STA_NOTIFY_REMOVE
:
2400 ath_node_detach(sc
, sta
);
2407 static int ath9k_conf_tx(struct ieee80211_hw
*hw
, u16 queue
,
2408 const struct ieee80211_tx_queue_params
*params
)
2410 struct ath_wiphy
*aphy
= hw
->priv
;
2411 struct ath_softc
*sc
= aphy
->sc
;
2412 struct ath9k_tx_queue_info qi
;
2415 if (queue
>= WME_NUM_AC
)
2418 mutex_lock(&sc
->mutex
);
2420 memset(&qi
, 0, sizeof(struct ath9k_tx_queue_info
));
2422 qi
.tqi_aifs
= params
->aifs
;
2423 qi
.tqi_cwmin
= params
->cw_min
;
2424 qi
.tqi_cwmax
= params
->cw_max
;
2425 qi
.tqi_burstTime
= params
->txop
;
2426 qnum
= ath_get_hal_qnum(queue
, sc
);
2428 DPRINTF(sc
, ATH_DBG_CONFIG
,
2429 "Configure tx [queue/halq] [%d/%d], "
2430 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2431 queue
, qnum
, params
->aifs
, params
->cw_min
,
2432 params
->cw_max
, params
->txop
);
2434 ret
= ath_txq_update(sc
, qnum
, &qi
);
2436 DPRINTF(sc
, ATH_DBG_FATAL
, "TXQ Update failed\n");
2438 mutex_unlock(&sc
->mutex
);
2443 static int ath9k_set_key(struct ieee80211_hw
*hw
,
2444 enum set_key_cmd cmd
,
2445 struct ieee80211_vif
*vif
,
2446 struct ieee80211_sta
*sta
,
2447 struct ieee80211_key_conf
*key
)
2449 struct ath_wiphy
*aphy
= hw
->priv
;
2450 struct ath_softc
*sc
= aphy
->sc
;
2453 if (modparam_nohwcrypt
)
2456 mutex_lock(&sc
->mutex
);
2457 ath9k_ps_wakeup(sc
);
2458 DPRINTF(sc
, ATH_DBG_CONFIG
, "Set HW Key\n");
2462 ret
= ath_key_config(sc
, vif
, sta
, key
);
2464 key
->hw_key_idx
= ret
;
2465 /* push IV and Michael MIC generation to stack */
2466 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
2467 if (key
->alg
== ALG_TKIP
)
2468 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
2469 if (sc
->sc_ah
->sw_mgmt_crypto
&& key
->alg
== ALG_CCMP
)
2470 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT
;
2475 ath_key_delete(sc
, key
);
2481 ath9k_ps_restore(sc
);
2482 mutex_unlock(&sc
->mutex
);
2487 static void ath9k_bss_info_changed(struct ieee80211_hw
*hw
,
2488 struct ieee80211_vif
*vif
,
2489 struct ieee80211_bss_conf
*bss_conf
,
2492 struct ath_wiphy
*aphy
= hw
->priv
;
2493 struct ath_softc
*sc
= aphy
->sc
;
2494 struct ath_hw
*ah
= sc
->sc_ah
;
2495 struct ath_vif
*avp
= (void *)vif
->drv_priv
;
2499 mutex_lock(&sc
->mutex
);
2502 * TODO: Need to decide which hw opmode to use for
2503 * multi-interface cases
2504 * XXX: This belongs into add_interface!
2506 if (vif
->type
== NL80211_IFTYPE_AP
&&
2507 ah
->opmode
!= NL80211_IFTYPE_AP
) {
2508 ah
->opmode
= NL80211_IFTYPE_STATION
;
2509 ath9k_hw_setopmode(ah
);
2510 memcpy(sc
->curbssid
, sc
->sc_ah
->macaddr
, ETH_ALEN
);
2512 ath9k_hw_write_associd(sc
);
2513 /* Request full reset to get hw opmode changed properly */
2514 sc
->sc_flags
|= SC_OP_FULL_RESET
;
2517 if ((changed
& BSS_CHANGED_BSSID
) &&
2518 !is_zero_ether_addr(bss_conf
->bssid
)) {
2519 switch (vif
->type
) {
2520 case NL80211_IFTYPE_STATION
:
2521 case NL80211_IFTYPE_ADHOC
:
2522 case NL80211_IFTYPE_MESH_POINT
:
2524 memcpy(sc
->curbssid
, bss_conf
->bssid
, ETH_ALEN
);
2525 memcpy(avp
->bssid
, bss_conf
->bssid
, ETH_ALEN
);
2527 ath9k_hw_write_associd(sc
);
2529 /* Set aggregation protection mode parameters */
2530 sc
->config
.ath_aggr_prot
= 0;
2532 DPRINTF(sc
, ATH_DBG_CONFIG
,
2533 "RX filter 0x%x bssid %pM aid 0x%x\n",
2534 rfilt
, sc
->curbssid
, sc
->curaid
);
2536 /* need to reconfigure the beacon */
2537 sc
->sc_flags
&= ~SC_OP_BEACONS
;
2545 if ((vif
->type
== NL80211_IFTYPE_ADHOC
) ||
2546 (vif
->type
== NL80211_IFTYPE_AP
) ||
2547 (vif
->type
== NL80211_IFTYPE_MESH_POINT
)) {
2548 if ((changed
& BSS_CHANGED_BEACON
) ||
2549 (changed
& BSS_CHANGED_BEACON_ENABLED
&&
2550 bss_conf
->enable_beacon
)) {
2552 * Allocate and setup the beacon frame.
2554 * Stop any previous beacon DMA. This may be
2555 * necessary, for example, when an ibss merge
2556 * causes reconfiguration; we may be called
2557 * with beacon transmission active.
2559 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
2561 error
= ath_beacon_alloc(aphy
, vif
);
2563 ath_beacon_config(sc
, vif
);
2567 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2568 if ((avp
->av_opmode
!= NL80211_IFTYPE_STATION
)) {
2569 for (i
= 0; i
< IEEE80211_WEP_NKID
; i
++)
2570 if (ath9k_hw_keyisvalid(sc
->sc_ah
, (u16
)i
))
2571 ath9k_hw_keysetmac(sc
->sc_ah
,
2576 /* Only legacy IBSS for now */
2577 if (vif
->type
== NL80211_IFTYPE_ADHOC
)
2578 ath_update_chainmask(sc
, 0);
2580 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
2581 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed PREAMBLE %d\n",
2582 bss_conf
->use_short_preamble
);
2583 if (bss_conf
->use_short_preamble
)
2584 sc
->sc_flags
|= SC_OP_PREAMBLE_SHORT
;
2586 sc
->sc_flags
&= ~SC_OP_PREAMBLE_SHORT
;
2589 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
2590 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed CTS PROT %d\n",
2591 bss_conf
->use_cts_prot
);
2592 if (bss_conf
->use_cts_prot
&&
2593 hw
->conf
.channel
->band
!= IEEE80211_BAND_5GHZ
)
2594 sc
->sc_flags
|= SC_OP_PROTECT_ENABLE
;
2596 sc
->sc_flags
&= ~SC_OP_PROTECT_ENABLE
;
2599 if (changed
& BSS_CHANGED_ASSOC
) {
2600 DPRINTF(sc
, ATH_DBG_CONFIG
, "BSS Changed ASSOC %d\n",
2602 ath9k_bss_assoc_info(sc
, vif
, bss_conf
);
2606 * The HW TSF has to be reset when the beacon interval changes.
2607 * We set the flag here, and ath_beacon_config_ap() would take this
2608 * into account when it gets called through the subsequent
2609 * config_interface() call - with IFCC_BEACON in the changed field.
2612 if (changed
& BSS_CHANGED_BEACON_INT
) {
2613 sc
->sc_flags
|= SC_OP_TSF_RESET
;
2614 sc
->beacon_interval
= bss_conf
->beacon_int
;
2617 mutex_unlock(&sc
->mutex
);
2620 static u64
ath9k_get_tsf(struct ieee80211_hw
*hw
)
2623 struct ath_wiphy
*aphy
= hw
->priv
;
2624 struct ath_softc
*sc
= aphy
->sc
;
2626 mutex_lock(&sc
->mutex
);
2627 tsf
= ath9k_hw_gettsf64(sc
->sc_ah
);
2628 mutex_unlock(&sc
->mutex
);
2633 static void ath9k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
2635 struct ath_wiphy
*aphy
= hw
->priv
;
2636 struct ath_softc
*sc
= aphy
->sc
;
2638 mutex_lock(&sc
->mutex
);
2639 ath9k_hw_settsf64(sc
->sc_ah
, tsf
);
2640 mutex_unlock(&sc
->mutex
);
2643 static void ath9k_reset_tsf(struct ieee80211_hw
*hw
)
2645 struct ath_wiphy
*aphy
= hw
->priv
;
2646 struct ath_softc
*sc
= aphy
->sc
;
2648 mutex_lock(&sc
->mutex
);
2649 ath9k_hw_reset_tsf(sc
->sc_ah
);
2650 mutex_unlock(&sc
->mutex
);
2653 static int ath9k_ampdu_action(struct ieee80211_hw
*hw
,
2654 enum ieee80211_ampdu_mlme_action action
,
2655 struct ieee80211_sta
*sta
,
2658 struct ath_wiphy
*aphy
= hw
->priv
;
2659 struct ath_softc
*sc
= aphy
->sc
;
2663 case IEEE80211_AMPDU_RX_START
:
2664 if (!(sc
->sc_flags
& SC_OP_RXAGGR
))
2667 case IEEE80211_AMPDU_RX_STOP
:
2669 case IEEE80211_AMPDU_TX_START
:
2670 ath_tx_aggr_start(sc
, sta
, tid
, ssn
);
2671 ieee80211_start_tx_ba_cb_irqsafe(hw
, sta
->addr
, tid
);
2673 case IEEE80211_AMPDU_TX_STOP
:
2674 ath_tx_aggr_stop(sc
, sta
, tid
);
2675 ieee80211_stop_tx_ba_cb_irqsafe(hw
, sta
->addr
, tid
);
2677 case IEEE80211_AMPDU_TX_OPERATIONAL
:
2678 ath_tx_aggr_resume(sc
, sta
, tid
);
2681 DPRINTF(sc
, ATH_DBG_FATAL
, "Unknown AMPDU action\n");
2687 static void ath9k_sw_scan_start(struct ieee80211_hw
*hw
)
2689 struct ath_wiphy
*aphy
= hw
->priv
;
2690 struct ath_softc
*sc
= aphy
->sc
;
2692 if (ath9k_wiphy_scanning(sc
)) {
2693 printk(KERN_DEBUG
"ath9k: Two wiphys trying to scan at the "
2696 * Do not allow the concurrent scanning state for now. This
2697 * could be improved with scanning control moved into ath9k.
2702 aphy
->state
= ATH_WIPHY_SCAN
;
2703 ath9k_wiphy_pause_all_forced(sc
, aphy
);
2705 spin_lock_bh(&sc
->ani_lock
);
2706 sc
->sc_flags
|= SC_OP_SCANNING
;
2707 spin_unlock_bh(&sc
->ani_lock
);
2710 static void ath9k_sw_scan_complete(struct ieee80211_hw
*hw
)
2712 struct ath_wiphy
*aphy
= hw
->priv
;
2713 struct ath_softc
*sc
= aphy
->sc
;
2715 spin_lock_bh(&sc
->ani_lock
);
2716 aphy
->state
= ATH_WIPHY_ACTIVE
;
2717 sc
->sc_flags
&= ~SC_OP_SCANNING
;
2718 sc
->sc_flags
|= SC_OP_FULL_RESET
;
2719 spin_unlock_bh(&sc
->ani_lock
);
2722 struct ieee80211_ops ath9k_ops
= {
2724 .start
= ath9k_start
,
2726 .add_interface
= ath9k_add_interface
,
2727 .remove_interface
= ath9k_remove_interface
,
2728 .config
= ath9k_config
,
2729 .configure_filter
= ath9k_configure_filter
,
2730 .sta_notify
= ath9k_sta_notify
,
2731 .conf_tx
= ath9k_conf_tx
,
2732 .bss_info_changed
= ath9k_bss_info_changed
,
2733 .set_key
= ath9k_set_key
,
2734 .get_tsf
= ath9k_get_tsf
,
2735 .set_tsf
= ath9k_set_tsf
,
2736 .reset_tsf
= ath9k_reset_tsf
,
2737 .ampdu_action
= ath9k_ampdu_action
,
2738 .sw_scan_start
= ath9k_sw_scan_start
,
2739 .sw_scan_complete
= ath9k_sw_scan_complete
,
2740 .rfkill_poll
= ath9k_rfkill_poll_state
,
2746 } ath_mac_bb_names
[] = {
2747 { AR_SREV_VERSION_5416_PCI
, "5416" },
2748 { AR_SREV_VERSION_5416_PCIE
, "5418" },
2749 { AR_SREV_VERSION_9100
, "9100" },
2750 { AR_SREV_VERSION_9160
, "9160" },
2751 { AR_SREV_VERSION_9280
, "9280" },
2752 { AR_SREV_VERSION_9285
, "9285" },
2753 { AR_SREV_VERSION_9287
, "9287" }
2759 } ath_rf_names
[] = {
2761 { AR_RAD5133_SREV_MAJOR
, "5133" },
2762 { AR_RAD5122_SREV_MAJOR
, "5122" },
2763 { AR_RAD2133_SREV_MAJOR
, "2133" },
2764 { AR_RAD2122_SREV_MAJOR
, "2122" }
2768 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2771 ath_mac_bb_name(u32 mac_bb_version
)
2775 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
2776 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
2777 return ath_mac_bb_names
[i
].name
;
2785 * Return the RF name. "????" is returned if the RF is unknown.
2788 ath_rf_name(u16 rf_version
)
2792 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
2793 if (ath_rf_names
[i
].version
== rf_version
) {
2794 return ath_rf_names
[i
].name
;
2801 static int __init
ath9k_init(void)
2805 /* Register rate control algorithm */
2806 error
= ath_rate_control_register();
2809 "ath9k: Unable to register rate control "
2815 error
= ath9k_debug_create_root();
2818 "ath9k: Unable to create debugfs root: %d\n",
2820 goto err_rate_unregister
;
2823 error
= ath_pci_init();
2826 "ath9k: No PCI devices found, driver not installed.\n");
2828 goto err_remove_root
;
2831 error
= ath_ahb_init();
2843 ath9k_debug_remove_root();
2844 err_rate_unregister
:
2845 ath_rate_control_unregister();
2849 module_init(ath9k_init
);
2851 static void __exit
ath9k_exit(void)
2855 ath9k_debug_remove_root();
2856 ath_rate_control_unregister();
2857 printk(KERN_INFO
"%s: Driver unloaded\n", dev_info
);
2859 module_exit(ath9k_exit
);