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Blackfin: update AD7879 resources to match the new gpiolib driver support
[wandboard.git] / drivers / ata / ata_piix.c
blobc33806654e46d5bfb984866c7bdad185c4f90ffe
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <scsi/scsi_host.h>
94 #include <linux/libata.h>
95 #include <linux/dmi.h>
96
97 #define DRV_NAME "ata_piix"
98 #define DRV_VERSION "2.13"
99
100 enum {
101 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
102 ICH5_PMR = 0x90, /* port mapping register */
103 ICH5_PCS = 0x92, /* port control and status */
104 PIIX_SIDPR_BAR = 5,
105 PIIX_SIDPR_LEN = 16,
106 PIIX_SIDPR_IDX = 0,
107 PIIX_SIDPR_DATA = 4,
108
109 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
110 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
111
112 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
113 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
114
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117
118 /* constants for mapping table */
119 P0 = 0, /* port 0 */
120 P1 = 1, /* port 1 */
121 P2 = 2, /* port 2 */
122 P3 = 3, /* port 3 */
123 IDE = -1, /* IDE */
124 NA = -2, /* not avaliable */
125 RV = -3, /* reserved */
126
127 PIIX_AHCI_DEVICE = 6,
128
129 /* host->flags bits */
130 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
131 };
132
133 enum piix_controller_ids {
134 /* controller IDs */
135 piix_pata_mwdma, /* PIIX3 MWDMA only */
136 piix_pata_33, /* PIIX4 at 33Mhz */
137 ich_pata_33, /* ICH up to UDMA 33 only */
138 ich_pata_66, /* ICH up to 66 Mhz */
139 ich_pata_100, /* ICH up to UDMA 100 */
140 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
141 ich5_sata,
142 ich6_sata,
143 ich6m_sata,
144 ich8_sata,
145 ich8_2port_sata,
146 ich8m_apple_sata, /* locks up on second port enable */
147 tolapai_sata,
148 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
149 };
150
151 struct piix_map_db {
152 const u32 mask;
153 const u16 port_enable;
154 const int map[][4];
155 };
156
157 struct piix_host_priv {
158 const int *map;
159 u32 saved_iocfg;
160 void __iomem *sidpr;
161 };
162
163 static int piix_init_one(struct pci_dev *pdev,
164 const struct pci_device_id *ent);
165 static void piix_remove_one(struct pci_dev *pdev);
166 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
167 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
168 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
169 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
170 static int ich_pata_cable_detect(struct ata_port *ap);
171 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
172 static int piix_sidpr_scr_read(struct ata_link *link,
173 unsigned int reg, u32 *val);
174 static int piix_sidpr_scr_write(struct ata_link *link,
175 unsigned int reg, u32 val);
176 static bool piix_irq_check(struct ata_port *ap);
177 #ifdef CONFIG_PM
178 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
179 static int piix_pci_device_resume(struct pci_dev *pdev);
180 #endif
181
182 static unsigned int in_module_init = 1;
183
184 static const struct pci_device_id piix_pci_tbl[] = {
185 /* Intel PIIX3 for the 430HX etc */
186 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
187 /* VMware ICH4 */
188 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
189 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
190 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
191 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
192 /* Intel PIIX4 */
193 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
194 /* Intel PIIX4 */
195 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
196 /* Intel PIIX */
197 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
198 /* Intel ICH (i810, i815, i840) UDMA 66*/
199 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
200 /* Intel ICH0 : UDMA 33*/
201 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
202 /* Intel ICH2M */
203 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
205 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* Intel ICH3M */
207 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* Intel ICH3 (E7500/1) UDMA 100 */
209 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
211 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* Intel ICH5 */
214 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215 /* C-ICH (i810E2) */
216 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
217 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
218 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* ICH6 (and 6) (i915) UDMA 100 */
220 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 /* ICH7/7-R (i945, i975) UDMA 100*/
222 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
223 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
224 /* ICH8 Mobile PATA Controller */
225 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
226
227 /* SATA ports */
228
229 /* 82801EB (ICH5) */
230 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
231 /* 82801EB (ICH5) */
232 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
233 /* 6300ESB (ICH5 variant with broken PCS present bits) */
234 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
235 /* 6300ESB pretending RAID */
236 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
237 /* 82801FB/FW (ICH6/ICH6W) */
238 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
239 /* 82801FR/FRW (ICH6R/ICH6RW) */
240 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
241 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
242 * Attach iff the controller is in IDE mode. */
243 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
244 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
245 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
246 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
247 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
248 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
249 /* Enterprise Southbridge 2 (631xESB/632xESB) */
250 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
251 /* SATA Controller 1 IDE (ICH8) */
252 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
253 /* SATA Controller 2 IDE (ICH8) */
254 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
255 /* Mobile SATA Controller IDE (ICH8M), Apple */
256 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
257 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
258 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
259 /* Mobile SATA Controller IDE (ICH8M) */
260 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
261 /* SATA Controller IDE (ICH9) */
262 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
263 /* SATA Controller IDE (ICH9) */
264 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
265 /* SATA Controller IDE (ICH9) */
266 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
267 /* SATA Controller IDE (ICH9M) */
268 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
269 /* SATA Controller IDE (ICH9M) */
270 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
271 /* SATA Controller IDE (ICH9M) */
272 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
273 /* SATA Controller IDE (Tolapai) */
274 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
275 /* SATA Controller IDE (ICH10) */
276 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
277 /* SATA Controller IDE (ICH10) */
278 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
279 /* SATA Controller IDE (ICH10) */
280 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
281 /* SATA Controller IDE (ICH10) */
282 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
283 /* SATA Controller IDE (PCH) */
284 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
285 /* SATA Controller IDE (PCH) */
286 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
287 /* SATA Controller IDE (PCH) */
288 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
289 /* SATA Controller IDE (PCH) */
290 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
291 /* SATA Controller IDE (PCH) */
292 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
293 /* SATA Controller IDE (PCH) */
294 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
295 /* SATA Controller IDE (CPT) */
296 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
297 /* SATA Controller IDE (CPT) */
298 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
299 /* SATA Controller IDE (CPT) */
300 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
301 /* SATA Controller IDE (CPT) */
302 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
303 { } /* terminate list */
304 };
305
306 static struct pci_driver piix_pci_driver = {
307 .name = DRV_NAME,
308 .id_table = piix_pci_tbl,
309 .probe = piix_init_one,
310 .remove = piix_remove_one,
311 #ifdef CONFIG_PM
312 .suspend = piix_pci_device_suspend,
313 .resume = piix_pci_device_resume,
314 #endif
315 };
316
317 static struct scsi_host_template piix_sht = {
318 ATA_BMDMA_SHT(DRV_NAME),
319 };
320
321 static struct ata_port_operations piix_sata_ops = {
322 .inherits = &ata_bmdma32_port_ops,
323 .sff_irq_check = piix_irq_check,
324 };
325
326 static struct ata_port_operations piix_pata_ops = {
327 .inherits = &piix_sata_ops,
328 .cable_detect = ata_cable_40wire,
329 .set_piomode = piix_set_piomode,
330 .set_dmamode = piix_set_dmamode,
331 .prereset = piix_pata_prereset,
332 };
333
334 static struct ata_port_operations piix_vmw_ops = {
335 .inherits = &piix_pata_ops,
336 .bmdma_status = piix_vmw_bmdma_status,
337 };
338
339 static struct ata_port_operations ich_pata_ops = {
340 .inherits = &piix_pata_ops,
341 .cable_detect = ich_pata_cable_detect,
342 .set_dmamode = ich_set_dmamode,
343 };
344
345 static struct ata_port_operations piix_sidpr_sata_ops = {
346 .inherits = &piix_sata_ops,
347 .hardreset = sata_std_hardreset,
348 .scr_read = piix_sidpr_scr_read,
349 .scr_write = piix_sidpr_scr_write,
350 };
351
352 static const struct piix_map_db ich5_map_db = {
353 .mask = 0x7,
354 .port_enable = 0x3,
355 .map = {
356 /* PM PS SM SS MAP */
357 { P0, NA, P1, NA }, /* 000b */
358 { P1, NA, P0, NA }, /* 001b */
359 { RV, RV, RV, RV },
360 { RV, RV, RV, RV },
361 { P0, P1, IDE, IDE }, /* 100b */
362 { P1, P0, IDE, IDE }, /* 101b */
363 { IDE, IDE, P0, P1 }, /* 110b */
364 { IDE, IDE, P1, P0 }, /* 111b */
365 },
366 };
367
368 static const struct piix_map_db ich6_map_db = {
369 .mask = 0x3,
370 .port_enable = 0xf,
371 .map = {
372 /* PM PS SM SS MAP */
373 { P0, P2, P1, P3 }, /* 00b */
374 { IDE, IDE, P1, P3 }, /* 01b */
375 { P0, P2, IDE, IDE }, /* 10b */
376 { RV, RV, RV, RV },
377 },
378 };
379
380 static const struct piix_map_db ich6m_map_db = {
381 .mask = 0x3,
382 .port_enable = 0x5,
383
384 /* Map 01b isn't specified in the doc but some notebooks use
385 * it anyway. MAP 01b have been spotted on both ICH6M and
386 * ICH7M.
387 */
388 .map = {
389 /* PM PS SM SS MAP */
390 { P0, P2, NA, NA }, /* 00b */
391 { IDE, IDE, P1, P3 }, /* 01b */
392 { P0, P2, IDE, IDE }, /* 10b */
393 { RV, RV, RV, RV },
394 },
395 };
396
397 static const struct piix_map_db ich8_map_db = {
398 .mask = 0x3,
399 .port_enable = 0xf,
400 .map = {
401 /* PM PS SM SS MAP */
402 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
403 { RV, RV, RV, RV },
404 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
405 { RV, RV, RV, RV },
406 },
407 };
408
409 static const struct piix_map_db ich8_2port_map_db = {
410 .mask = 0x3,
411 .port_enable = 0x3,
412 .map = {
413 /* PM PS SM SS MAP */
414 { P0, NA, P1, NA }, /* 00b */
415 { RV, RV, RV, RV }, /* 01b */
416 { RV, RV, RV, RV }, /* 10b */
417 { RV, RV, RV, RV },
418 },
419 };
420
421 static const struct piix_map_db ich8m_apple_map_db = {
422 .mask = 0x3,
423 .port_enable = 0x1,
424 .map = {
425 /* PM PS SM SS MAP */
426 { P0, NA, NA, NA }, /* 00b */
427 { RV, RV, RV, RV },
428 { P0, P2, IDE, IDE }, /* 10b */
429 { RV, RV, RV, RV },
430 },
431 };
432
433 static const struct piix_map_db tolapai_map_db = {
434 .mask = 0x3,
435 .port_enable = 0x3,
436 .map = {
437 /* PM PS SM SS MAP */
438 { P0, NA, P1, NA }, /* 00b */
439 { RV, RV, RV, RV }, /* 01b */
440 { RV, RV, RV, RV }, /* 10b */
441 { RV, RV, RV, RV },
442 },
443 };
444
445 static const struct piix_map_db *piix_map_db_table[] = {
446 [ich5_sata] = &ich5_map_db,
447 [ich6_sata] = &ich6_map_db,
448 [ich6m_sata] = &ich6m_map_db,
449 [ich8_sata] = &ich8_map_db,
450 [ich8_2port_sata] = &ich8_2port_map_db,
451 [ich8m_apple_sata] = &ich8m_apple_map_db,
452 [tolapai_sata] = &tolapai_map_db,
453 };
454
455 static struct ata_port_info piix_port_info[] = {
456 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
457 {
458 .flags = PIIX_PATA_FLAGS,
459 .pio_mask = ATA_PIO4,
460 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
461 .port_ops = &piix_pata_ops,
462 },
463
464 [piix_pata_33] = /* PIIX4 at 33MHz */
465 {
466 .flags = PIIX_PATA_FLAGS,
467 .pio_mask = ATA_PIO4,
468 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
469 .udma_mask = ATA_UDMA2,
470 .port_ops = &piix_pata_ops,
471 },
472
473 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
474 {
475 .flags = PIIX_PATA_FLAGS,
476 .pio_mask = ATA_PIO4,
477 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
478 .udma_mask = ATA_UDMA2,
479 .port_ops = &ich_pata_ops,
480 },
481
482 [ich_pata_66] = /* ICH controllers up to 66MHz */
483 {
484 .flags = PIIX_PATA_FLAGS,
485 .pio_mask = ATA_PIO4,
486 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
487 .udma_mask = ATA_UDMA4,
488 .port_ops = &ich_pata_ops,
489 },
490
491 [ich_pata_100] =
492 {
493 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
494 .pio_mask = ATA_PIO4,
495 .mwdma_mask = ATA_MWDMA12_ONLY,
496 .udma_mask = ATA_UDMA5,
497 .port_ops = &ich_pata_ops,
498 },
499
500 [ich_pata_100_nomwdma1] =
501 {
502 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
503 .pio_mask = ATA_PIO4,
504 .mwdma_mask = ATA_MWDMA2_ONLY,
505 .udma_mask = ATA_UDMA5,
506 .port_ops = &ich_pata_ops,
507 },
508
509 [ich5_sata] =
510 {
511 .flags = PIIX_SATA_FLAGS,
512 .pio_mask = ATA_PIO4,
513 .mwdma_mask = ATA_MWDMA2,
514 .udma_mask = ATA_UDMA6,
515 .port_ops = &piix_sata_ops,
516 },
517
518 [ich6_sata] =
519 {
520 .flags = PIIX_SATA_FLAGS,
521 .pio_mask = ATA_PIO4,
522 .mwdma_mask = ATA_MWDMA2,
523 .udma_mask = ATA_UDMA6,
524 .port_ops = &piix_sata_ops,
525 },
526
527 [ich6m_sata] =
528 {
529 .flags = PIIX_SATA_FLAGS,
530 .pio_mask = ATA_PIO4,
531 .mwdma_mask = ATA_MWDMA2,
532 .udma_mask = ATA_UDMA6,
533 .port_ops = &piix_sata_ops,
534 },
535
536 [ich8_sata] =
537 {
538 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
539 .pio_mask = ATA_PIO4,
540 .mwdma_mask = ATA_MWDMA2,
541 .udma_mask = ATA_UDMA6,
542 .port_ops = &piix_sata_ops,
543 },
544
545 [ich8_2port_sata] =
546 {
547 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
548 .pio_mask = ATA_PIO4,
549 .mwdma_mask = ATA_MWDMA2,
550 .udma_mask = ATA_UDMA6,
551 .port_ops = &piix_sata_ops,
552 },
553
554 [tolapai_sata] =
555 {
556 .flags = PIIX_SATA_FLAGS,
557 .pio_mask = ATA_PIO4,
558 .mwdma_mask = ATA_MWDMA2,
559 .udma_mask = ATA_UDMA6,
560 .port_ops = &piix_sata_ops,
561 },
562
563 [ich8m_apple_sata] =
564 {
565 .flags = PIIX_SATA_FLAGS,
566 .pio_mask = ATA_PIO4,
567 .mwdma_mask = ATA_MWDMA2,
568 .udma_mask = ATA_UDMA6,
569 .port_ops = &piix_sata_ops,
570 },
571
572 [piix_pata_vmw] =
573 {
574 .flags = PIIX_PATA_FLAGS,
575 .pio_mask = ATA_PIO4,
576 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
577 .udma_mask = ATA_UDMA2,
578 .port_ops = &piix_vmw_ops,
579 },
580
581 };
582
583 static struct pci_bits piix_enable_bits[] = {
584 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
585 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
586 };
587
588 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
589 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
590 MODULE_LICENSE("GPL");
591 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
592 MODULE_VERSION(DRV_VERSION);
593
594 struct ich_laptop {
595 u16 device;
596 u16 subvendor;
597 u16 subdevice;
598 };
599
600 /*
601 * List of laptops that use short cables rather than 80 wire
602 */
603
604 static const struct ich_laptop ich_laptop[] = {
605 /* devid, subvendor, subdev */
606 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
607 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
608 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
609 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
610 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
611 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
612 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
613 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
614 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
615 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
616 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
617 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
618 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
619 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
620 /* end marker */
621 { 0, }
622 };
623
624 /**
625 * ich_pata_cable_detect - Probe host controller cable detect info
626 * @ap: Port for which cable detect info is desired
627 *
628 * Read 80c cable indicator from ATA PCI device's PCI config
629 * register. This register is normally set by firmware (BIOS).
630 *
631 * LOCKING:
632 * None (inherited from caller).
633 */
634
635 static int ich_pata_cable_detect(struct ata_port *ap)
636 {
637 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
638 struct piix_host_priv *hpriv = ap->host->private_data;
639 const struct ich_laptop *lap = &ich_laptop[0];
640 u8 mask;
641
642 /* Check for specials - Acer Aspire 5602WLMi */
643 while (lap->device) {
644 if (lap->device == pdev->device &&
645 lap->subvendor == pdev->subsystem_vendor &&
646 lap->subdevice == pdev->subsystem_device)
647 return ATA_CBL_PATA40_SHORT;
648
649 lap++;
650 }
651
652 /* check BIOS cable detect results */
653 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
654 if ((hpriv->saved_iocfg & mask) == 0)
655 return ATA_CBL_PATA40;
656 return ATA_CBL_PATA80;
657 }
658
659 /**
660 * piix_pata_prereset - prereset for PATA host controller
661 * @link: Target link
662 * @deadline: deadline jiffies for the operation
663 *
664 * LOCKING:
665 * None (inherited from caller).
666 */
667 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
668 {
669 struct ata_port *ap = link->ap;
670 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
671
672 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
673 return -ENOENT;
674 return ata_sff_prereset(link, deadline);
675 }
676
677 static DEFINE_SPINLOCK(piix_lock);
678
679 /**
680 * piix_set_piomode - Initialize host controller PATA PIO timings
681 * @ap: Port whose timings we are configuring
682 * @adev: um
683 *
684 * Set PIO mode for device, in host controller PCI config space.
685 *
686 * LOCKING:
687 * None (inherited from caller).
688 */
689
690 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
691 {
692 struct pci_dev *dev = to_pci_dev(ap->host->dev);
693 unsigned long flags;
694 unsigned int pio = adev->pio_mode - XFER_PIO_0;
695 unsigned int is_slave = (adev->devno != 0);
696 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
697 unsigned int slave_port = 0x44;
698 u16 master_data;
699 u8 slave_data;
700 u8 udma_enable;
701 int control = 0;
702
703 /*
704 * See Intel Document 298600-004 for the timing programing rules
705 * for ICH controllers.
706 */
707
708 static const /* ISP RTC */
709 u8 timings[][2] = { { 0, 0 },
710 { 0, 0 },
711 { 1, 0 },
712 { 2, 1 },
713 { 2, 3 }, };
714
715 if (pio >= 2)
716 control |= 1; /* TIME1 enable */
717 if (ata_pio_need_iordy(adev))
718 control |= 2; /* IE enable */
719
720 /* Intel specifies that the PPE functionality is for disk only */
721 if (adev->class == ATA_DEV_ATA)
722 control |= 4; /* PPE enable */
723
724 spin_lock_irqsave(&piix_lock, flags);
725
726 /* PIO configuration clears DTE unconditionally. It will be
727 * programmed in set_dmamode which is guaranteed to be called
728 * after set_piomode if any DMA mode is available.
729 */
730 pci_read_config_word(dev, master_port, &master_data);
731 if (is_slave) {
732 /* clear TIME1|IE1|PPE1|DTE1 */
733 master_data &= 0xff0f;
734 /* Enable SITRE (separate slave timing register) */
735 master_data |= 0x4000;
736 /* enable PPE1, IE1 and TIME1 as needed */
737 master_data |= (control << 4);
738 pci_read_config_byte(dev, slave_port, &slave_data);
739 slave_data &= (ap->port_no ? 0x0f : 0xf0);
740 /* Load the timing nibble for this slave */
741 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
742 << (ap->port_no ? 4 : 0);
743 } else {
744 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
745 master_data &= 0xccf0;
746 /* Enable PPE, IE and TIME as appropriate */
747 master_data |= control;
748 /* load ISP and RCT */
749 master_data |=
750 (timings[pio][0] << 12) |
751 (timings[pio][1] << 8);
752 }
753 pci_write_config_word(dev, master_port, master_data);
754 if (is_slave)
755 pci_write_config_byte(dev, slave_port, slave_data);
756
757 /* Ensure the UDMA bit is off - it will be turned back on if
758 UDMA is selected */
759
760 if (ap->udma_mask) {
761 pci_read_config_byte(dev, 0x48, &udma_enable);
762 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
763 pci_write_config_byte(dev, 0x48, udma_enable);
764 }
765
766 spin_unlock_irqrestore(&piix_lock, flags);
767 }
768
769 /**
770 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
771 * @ap: Port whose timings we are configuring
772 * @adev: Drive in question
773 * @isich: set if the chip is an ICH device
774 *
775 * Set UDMA mode for device, in host controller PCI config space.
776 *
777 * LOCKING:
778 * None (inherited from caller).
779 */
780
781 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
782 {
783 struct pci_dev *dev = to_pci_dev(ap->host->dev);
784 unsigned long flags;
785 u8 master_port = ap->port_no ? 0x42 : 0x40;
786 u16 master_data;
787 u8 speed = adev->dma_mode;
788 int devid = adev->devno + 2 * ap->port_no;
789 u8 udma_enable = 0;
790
791 static const /* ISP RTC */
792 u8 timings[][2] = { { 0, 0 },
793 { 0, 0 },
794 { 1, 0 },
795 { 2, 1 },
796 { 2, 3 }, };
797
798 spin_lock_irqsave(&piix_lock, flags);
799
800 pci_read_config_word(dev, master_port, &master_data);
801 if (ap->udma_mask)
802 pci_read_config_byte(dev, 0x48, &udma_enable);
803
804 if (speed >= XFER_UDMA_0) {
805 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
806 u16 udma_timing;
807 u16 ideconf;
808 int u_clock, u_speed;
809
810 /*
811 * UDMA is handled by a combination of clock switching and
812 * selection of dividers
813 *
814 * Handy rule: Odd modes are UDMATIMx 01, even are 02
815 * except UDMA0 which is 00
816 */
817 u_speed = min(2 - (udma & 1), udma);
818 if (udma == 5)
819 u_clock = 0x1000; /* 100Mhz */
820 else if (udma > 2)
821 u_clock = 1; /* 66Mhz */
822 else
823 u_clock = 0; /* 33Mhz */
824
825 udma_enable |= (1 << devid);
826
827 /* Load the CT/RP selection */
828 pci_read_config_word(dev, 0x4A, &udma_timing);
829 udma_timing &= ~(3 << (4 * devid));
830 udma_timing |= u_speed << (4 * devid);
831 pci_write_config_word(dev, 0x4A, udma_timing);
832
833 if (isich) {
834 /* Select a 33/66/100Mhz clock */
835 pci_read_config_word(dev, 0x54, &ideconf);
836 ideconf &= ~(0x1001 << devid);
837 ideconf |= u_clock << devid;
838 /* For ICH or later we should set bit 10 for better
839 performance (WR_PingPong_En) */
840 pci_write_config_word(dev, 0x54, ideconf);
841 }
842 } else {
843 /*
844 * MWDMA is driven by the PIO timings. We must also enable
845 * IORDY unconditionally along with TIME1. PPE has already
846 * been set when the PIO timing was set.
847 */
848 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
849 unsigned int control;
850 u8 slave_data;
851 const unsigned int needed_pio[3] = {
852 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
853 };
854 int pio = needed_pio[mwdma] - XFER_PIO_0;
855
856 control = 3; /* IORDY|TIME1 */
857
858 /* If the drive MWDMA is faster than it can do PIO then
859 we must force PIO into PIO0 */
860
861 if (adev->pio_mode < needed_pio[mwdma])
862 /* Enable DMA timing only */
863 control |= 8; /* PIO cycles in PIO0 */
864
865 if (adev->devno) { /* Slave */
866 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
867 master_data |= control << 4;
868 pci_read_config_byte(dev, 0x44, &slave_data);
869 slave_data &= (ap->port_no ? 0x0f : 0xf0);
870 /* Load the matching timing */
871 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
872 pci_write_config_byte(dev, 0x44, slave_data);
873 } else { /* Master */
874 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
875 and master timing bits */
876 master_data |= control;
877 master_data |=
878 (timings[pio][0] << 12) |
879 (timings[pio][1] << 8);
880 }
881
882 if (ap->udma_mask)
883 udma_enable &= ~(1 << devid);
884
885 pci_write_config_word(dev, master_port, master_data);
886 }
887 /* Don't scribble on 0x48 if the controller does not support UDMA */
888 if (ap->udma_mask)
889 pci_write_config_byte(dev, 0x48, udma_enable);
890
891 spin_unlock_irqrestore(&piix_lock, flags);
892 }
893
894 /**
895 * piix_set_dmamode - Initialize host controller PATA DMA timings
896 * @ap: Port whose timings we are configuring
897 * @adev: um
898 *
899 * Set MW/UDMA mode for device, in host controller PCI config space.
900 *
901 * LOCKING:
902 * None (inherited from caller).
903 */
904
905 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
906 {
907 do_pata_set_dmamode(ap, adev, 0);
908 }
909
910 /**
911 * ich_set_dmamode - Initialize host controller PATA DMA timings
912 * @ap: Port whose timings we are configuring
913 * @adev: um
914 *
915 * Set MW/UDMA mode for device, in host controller PCI config space.
916 *
917 * LOCKING:
918 * None (inherited from caller).
919 */
920
921 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
922 {
923 do_pata_set_dmamode(ap, adev, 1);
924 }
925
926 /*
927 * Serial ATA Index/Data Pair Superset Registers access
928 *
929 * Beginning from ICH8, there's a sane way to access SCRs using index
930 * and data register pair located at BAR5 which means that we have
931 * separate SCRs for master and slave. This is handled using libata
932 * slave_link facility.
933 */
934 static const int piix_sidx_map[] = {
935 [SCR_STATUS] = 0,
936 [SCR_ERROR] = 2,
937 [SCR_CONTROL] = 1,
938 };
939
940 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
941 {
942 struct ata_port *ap = link->ap;
943 struct piix_host_priv *hpriv = ap->host->private_data;
944
945 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
946 hpriv->sidpr + PIIX_SIDPR_IDX);
947 }
948
949 static int piix_sidpr_scr_read(struct ata_link *link,
950 unsigned int reg, u32 *val)
951 {
952 struct piix_host_priv *hpriv = link->ap->host->private_data;
953
954 if (reg >= ARRAY_SIZE(piix_sidx_map))
955 return -EINVAL;
956
957 piix_sidpr_sel(link, reg);
958 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
959 return 0;
960 }
961
962 static int piix_sidpr_scr_write(struct ata_link *link,
963 unsigned int reg, u32 val)
964 {
965 struct piix_host_priv *hpriv = link->ap->host->private_data;
966
967 if (reg >= ARRAY_SIZE(piix_sidx_map))
968 return -EINVAL;
969
970 piix_sidpr_sel(link, reg);
971 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
972 return 0;
973 }
974
975 static bool piix_irq_check(struct ata_port *ap)
976 {
977 if (unlikely(!ap->ioaddr.bmdma_addr))
978 return false;
979
980 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
981 }
982
983 #ifdef CONFIG_PM
984 static int piix_broken_suspend(void)
985 {
986 static const struct dmi_system_id sysids[] = {
987 {
988 .ident = "TECRA M3",
989 .matches = {
990 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
991 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
992 },
993 },
994 {
995 .ident = "TECRA M3",
996 .matches = {
997 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
998 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
999 },
1000 },
1001 {
1002 .ident = "TECRA M4",
1003 .matches = {
1004 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1005 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1006 },
1007 },
1008 {
1009 .ident = "TECRA M4",
1010 .matches = {
1011 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1012 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1013 },
1014 },
1015 {
1016 .ident = "TECRA M5",
1017 .matches = {
1018 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1019 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1020 },
1021 },
1022 {
1023 .ident = "TECRA M6",
1024 .matches = {
1025 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1026 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1027 },
1028 },
1029 {
1030 .ident = "TECRA M7",
1031 .matches = {
1032 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1033 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1034 },
1035 },
1036 {
1037 .ident = "TECRA A8",
1038 .matches = {
1039 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1040 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1041 },
1042 },
1043 {
1044 .ident = "Satellite R20",
1045 .matches = {
1046 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1047 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1048 },
1049 },
1050 {
1051 .ident = "Satellite R25",
1052 .matches = {
1053 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1054 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1055 },
1056 },
1057 {
1058 .ident = "Satellite U200",
1059 .matches = {
1060 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1061 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1062 },
1063 },
1064 {
1065 .ident = "Satellite U200",
1066 .matches = {
1067 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1068 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1069 },
1070 },
1071 {
1072 .ident = "Satellite Pro U200",
1073 .matches = {
1074 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1075 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1076 },
1077 },
1078 {
1079 .ident = "Satellite U205",
1080 .matches = {
1081 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1082 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1083 },
1084 },
1085 {
1086 .ident = "SATELLITE U205",
1087 .matches = {
1088 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1089 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1090 },
1091 },
1092 {
1093 .ident = "Portege M500",
1094 .matches = {
1095 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1096 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1097 },
1098 },
1099 {
1100 .ident = "VGN-BX297XP",
1101 .matches = {
1102 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1103 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1104 },
1105 },
1106
1107 { } /* terminate list */
1108 };
1109 static const char *oemstrs[] = {
1110 "Tecra M3,",
1111 };
1112 int i;
1113
1114 if (dmi_check_system(sysids))
1115 return 1;
1116
1117 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1118 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1119 return 1;
1120
1121 /* TECRA M4 sometimes forgets its identify and reports bogus
1122 * DMI information. As the bogus information is a bit
1123 * generic, match as many entries as possible. This manual
1124 * matching is necessary because dmi_system_id.matches is
1125 * limited to four entries.
1126 */
1127 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1128 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1129 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1130 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1131 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1132 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1133 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1134 return 1;
1135
1136 return 0;
1137 }
1138
1139 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1140 {
1141 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1142 unsigned long flags;
1143 int rc = 0;
1144
1145 rc = ata_host_suspend(host, mesg);
1146 if (rc)
1147 return rc;
1148
1149 /* Some braindamaged ACPI suspend implementations expect the
1150 * controller to be awake on entry; otherwise, it burns cpu
1151 * cycles and power trying to do something to the sleeping
1152 * beauty.
1153 */
1154 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1155 pci_save_state(pdev);
1156
1157 /* mark its power state as "unknown", since we don't
1158 * know if e.g. the BIOS will change its device state
1159 * when we suspend.
1160 */
1161 if (pdev->current_state == PCI_D0)
1162 pdev->current_state = PCI_UNKNOWN;
1163
1164 /* tell resume that it's waking up from broken suspend */
1165 spin_lock_irqsave(&host->lock, flags);
1166 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1167 spin_unlock_irqrestore(&host->lock, flags);
1168 } else
1169 ata_pci_device_do_suspend(pdev, mesg);
1170
1171 return 0;
1172 }
1173
1174 static int piix_pci_device_resume(struct pci_dev *pdev)
1175 {
1176 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1177 unsigned long flags;
1178 int rc;
1179
1180 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1181 spin_lock_irqsave(&host->lock, flags);
1182 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1183 spin_unlock_irqrestore(&host->lock, flags);
1184
1185 pci_set_power_state(pdev, PCI_D0);
1186 pci_restore_state(pdev);
1187
1188 /* PCI device wasn't disabled during suspend. Use
1189 * pci_reenable_device() to avoid affecting the enable
1190 * count.
1191 */
1192 rc = pci_reenable_device(pdev);
1193 if (rc)
1194 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1195 "device after resume (%d)\n", rc);
1196 } else
1197 rc = ata_pci_device_do_resume(pdev);
1198
1199 if (rc == 0)
1200 ata_host_resume(host);
1201
1202 return rc;
1203 }
1204 #endif
1205
1206 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1207 {
1208 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1209 }
1210
1211 #define AHCI_PCI_BAR 5
1212 #define AHCI_GLOBAL_CTL 0x04
1213 #define AHCI_ENABLE (1 << 31)
1214 static int piix_disable_ahci(struct pci_dev *pdev)
1215 {
1216 void __iomem *mmio;
1217 u32 tmp;
1218 int rc = 0;
1219
1220 /* BUG: pci_enable_device has not yet been called. This
1221 * works because this device is usually set up by BIOS.
1222 */
1223
1224 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1225 !pci_resource_len(pdev, AHCI_PCI_BAR))
1226 return 0;
1227
1228 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1229 if (!mmio)
1230 return -ENOMEM;
1231
1232 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1233 if (tmp & AHCI_ENABLE) {
1234 tmp &= ~AHCI_ENABLE;
1235 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1236
1237 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1238 if (tmp & AHCI_ENABLE)
1239 rc = -EIO;
1240 }
1241
1242 pci_iounmap(pdev, mmio);
1243 return rc;
1244 }
1245
1246 /**
1247 * piix_check_450nx_errata - Check for problem 450NX setup
1248 * @ata_dev: the PCI device to check
1249 *
1250 * Check for the present of 450NX errata #19 and errata #25. If
1251 * they are found return an error code so we can turn off DMA
1252 */
1253
1254 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1255 {
1256 struct pci_dev *pdev = NULL;
1257 u16 cfg;
1258 int no_piix_dma = 0;
1259
1260 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1261 /* Look for 450NX PXB. Check for problem configurations
1262 A PCI quirk checks bit 6 already */
1263 pci_read_config_word(pdev, 0x41, &cfg);
1264 /* Only on the original revision: IDE DMA can hang */
1265 if (pdev->revision == 0x00)
1266 no_piix_dma = 1;
1267 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1268 else if (cfg & (1<<14) && pdev->revision < 5)
1269 no_piix_dma = 2;
1270 }
1271 if (no_piix_dma)
1272 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1273 if (no_piix_dma == 2)
1274 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1275 return no_piix_dma;
1276 }
1277
1278 static void __devinit piix_init_pcs(struct ata_host *host,
1279 const struct piix_map_db *map_db)
1280 {
1281 struct pci_dev *pdev = to_pci_dev(host->dev);
1282 u16 pcs, new_pcs;
1283
1284 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1285
1286 new_pcs = pcs | map_db->port_enable;
1287
1288 if (new_pcs != pcs) {
1289 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1290 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1291 msleep(150);
1292 }
1293 }
1294
1295 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1296 struct ata_port_info *pinfo,
1297 const struct piix_map_db *map_db)
1298 {
1299 const int *map;
1300 int i, invalid_map = 0;
1301 u8 map_value;
1302
1303 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1304
1305 map = map_db->map[map_value & map_db->mask];
1306
1307 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1308 for (i = 0; i < 4; i++) {
1309 switch (map[i]) {
1310 case RV:
1311 invalid_map = 1;
1312 printk(" XX");
1313 break;
1314
1315 case NA:
1316 printk(" --");
1317 break;
1318
1319 case IDE:
1320 WARN_ON((i & 1) || map[i + 1] != IDE);
1321 pinfo[i / 2] = piix_port_info[ich_pata_100];
1322 i++;
1323 printk(" IDE IDE");
1324 break;
1325
1326 default:
1327 printk(" P%d", map[i]);
1328 if (i & 1)
1329 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1330 break;
1331 }
1332 }
1333 printk(" ]\n");
1334
1335 if (invalid_map)
1336 dev_printk(KERN_ERR, &pdev->dev,
1337 "invalid MAP value %u\n", map_value);
1338
1339 return map;
1340 }
1341
1342 static bool piix_no_sidpr(struct ata_host *host)
1343 {
1344 struct pci_dev *pdev = to_pci_dev(host->dev);
1345
1346 /*
1347 * Samsung DB-P70 only has three ATA ports exposed and
1348 * curiously the unconnected first port reports link online
1349 * while not responding to SRST protocol causing excessive
1350 * detection delay.
1351 *
1352 * Unfortunately, the system doesn't carry enough DMI
1353 * information to identify the machine but does have subsystem
1354 * vendor and device set. As it's unclear whether the
1355 * subsystem vendor/device is used only for this specific
1356 * board, the port can't be disabled solely with the
1357 * information; however, turning off SIDPR access works around
1358 * the problem. Turn it off.
1359 *
1360 * This problem is reported in bnc#441240.
1361 *
1362 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1363 */
1364 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1365 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1366 pdev->subsystem_device == 0xb049) {
1367 dev_printk(KERN_WARNING, host->dev,
1368 "Samsung DB-P70 detected, disabling SIDPR\n");
1369 return true;
1370 }
1371
1372 return false;
1373 }
1374
1375 static int __devinit piix_init_sidpr(struct ata_host *host)
1376 {
1377 struct pci_dev *pdev = to_pci_dev(host->dev);
1378 struct piix_host_priv *hpriv = host->private_data;
1379 struct ata_link *link0 = &host->ports[0]->link;
1380 u32 scontrol;
1381 int i, rc;
1382
1383 /* check for availability */
1384 for (i = 0; i < 4; i++)
1385 if (hpriv->map[i] == IDE)
1386 return 0;
1387
1388 /* is it blacklisted? */
1389 if (piix_no_sidpr(host))
1390 return 0;
1391
1392 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1393 return 0;
1394
1395 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1396 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1397 return 0;
1398
1399 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1400 return 0;
1401
1402 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1403
1404 /* SCR access via SIDPR doesn't work on some configurations.
1405 * Give it a test drive by inhibiting power save modes which
1406 * we'll do anyway.
1407 */
1408 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1409
1410 /* if IPM is already 3, SCR access is probably working. Don't
1411 * un-inhibit power save modes as BIOS might have inhibited
1412 * them for a reason.
1413 */
1414 if ((scontrol & 0xf00) != 0x300) {
1415 scontrol |= 0x300;
1416 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1417 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1418
1419 if ((scontrol & 0xf00) != 0x300) {
1420 dev_printk(KERN_INFO, host->dev, "SCR access via "
1421 "SIDPR is available but doesn't work\n");
1422 return 0;
1423 }
1424 }
1425
1426 /* okay, SCRs available, set ops and ask libata for slave_link */
1427 for (i = 0; i < 2; i++) {
1428 struct ata_port *ap = host->ports[i];
1429
1430 ap->ops = &piix_sidpr_sata_ops;
1431
1432 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1433 rc = ata_slave_link_init(ap);
1434 if (rc)
1435 return rc;
1436 }
1437 }
1438
1439 return 0;
1440 }
1441
1442 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1443 {
1444 static const struct dmi_system_id sysids[] = {
1445 {
1446 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1447 * isn't used to boot the system which
1448 * disables the channel.
1449 */
1450 .ident = "M570U",
1451 .matches = {
1452 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1453 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1454 },
1455 },
1456
1457 { } /* terminate list */
1458 };
1459 struct pci_dev *pdev = to_pci_dev(host->dev);
1460 struct piix_host_priv *hpriv = host->private_data;
1461
1462 if (!dmi_check_system(sysids))
1463 return;
1464
1465 /* The datasheet says that bit 18 is NOOP but certain systems
1466 * seem to use it to disable a channel. Clear the bit on the
1467 * affected systems.
1468 */
1469 if (hpriv->saved_iocfg & (1 << 18)) {
1470 dev_printk(KERN_INFO, &pdev->dev,
1471 "applying IOCFG bit18 quirk\n");
1472 pci_write_config_dword(pdev, PIIX_IOCFG,
1473 hpriv->saved_iocfg & ~(1 << 18));
1474 }
1475 }
1476
1477 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1478 {
1479 static const struct dmi_system_id broken_systems[] = {
1480 {
1481 .ident = "HP Compaq 2510p",
1482 .matches = {
1483 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1484 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1485 },
1486 /* PCI slot number of the controller */
1487 .driver_data = (void *)0x1FUL,
1488 },
1489 {
1490 .ident = "HP Compaq nc6000",
1491 .matches = {
1492 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1493 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1494 },
1495 /* PCI slot number of the controller */
1496 .driver_data = (void *)0x1FUL,
1497 },
1498
1499 { } /* terminate list */
1500 };
1501 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1502
1503 if (dmi) {
1504 unsigned long slot = (unsigned long)dmi->driver_data;
1505 /* apply the quirk only to on-board controllers */
1506 return slot == PCI_SLOT(pdev->devfn);
1507 }
1508
1509 return false;
1510 }
1511
1512 /**
1513 * piix_init_one - Register PIIX ATA PCI device with kernel services
1514 * @pdev: PCI device to register
1515 * @ent: Entry in piix_pci_tbl matching with @pdev
1516 *
1517 * Called from kernel PCI layer. We probe for combined mode (sigh),
1518 * and then hand over control to libata, for it to do the rest.
1519 *
1520 * LOCKING:
1521 * Inherited from PCI layer (may sleep).
1522 *
1523 * RETURNS:
1524 * Zero on success, or -ERRNO value.
1525 */
1526
1527 static int __devinit piix_init_one(struct pci_dev *pdev,
1528 const struct pci_device_id *ent)
1529 {
1530 static int printed_version;
1531 struct device *dev = &pdev->dev;
1532 struct ata_port_info port_info[2];
1533 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1534 unsigned long port_flags;
1535 struct ata_host *host;
1536 struct piix_host_priv *hpriv;
1537 int rc;
1538
1539 if (!printed_version++)
1540 dev_printk(KERN_DEBUG, &pdev->dev,
1541 "version " DRV_VERSION "\n");
1542
1543 /* no hotplugging support for later devices (FIXME) */
1544 if (!in_module_init && ent->driver_data >= ich5_sata)
1545 return -ENODEV;
1546
1547 if (piix_broken_system_poweroff(pdev)) {
1548 piix_port_info[ent->driver_data].flags |=
1549 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1550 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1551 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1552 "on poweroff and hibernation\n");
1553 }
1554
1555 port_info[0] = piix_port_info[ent->driver_data];
1556 port_info[1] = piix_port_info[ent->driver_data];
1557
1558 port_flags = port_info[0].flags;
1559
1560 /* enable device and prepare host */
1561 rc = pcim_enable_device(pdev);
1562 if (rc)
1563 return rc;
1564
1565 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1566 if (!hpriv)
1567 return -ENOMEM;
1568
1569 /* Save IOCFG, this will be used for cable detection, quirk
1570 * detection and restoration on detach. This is necessary
1571 * because some ACPI implementations mess up cable related
1572 * bits on _STM. Reported on kernel bz#11879.
1573 */
1574 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1575
1576 /* ICH6R may be driven by either ata_piix or ahci driver
1577 * regardless of BIOS configuration. Make sure AHCI mode is
1578 * off.
1579 */
1580 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1581 rc = piix_disable_ahci(pdev);
1582 if (rc)
1583 return rc;
1584 }
1585
1586 /* SATA map init can change port_info, do it before prepping host */
1587 if (port_flags & ATA_FLAG_SATA)
1588 hpriv->map = piix_init_sata_map(pdev, port_info,
1589 piix_map_db_table[ent->driver_data]);
1590
1591 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
1592 if (rc)
1593 return rc;
1594 host->private_data = hpriv;
1595
1596 /* initialize controller */
1597 if (port_flags & ATA_FLAG_SATA) {
1598 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1599 rc = piix_init_sidpr(host);
1600 if (rc)
1601 return rc;
1602 }
1603
1604 /* apply IOCFG bit18 quirk */
1605 piix_iocfg_bit18_quirk(host);
1606
1607 /* On ICH5, some BIOSen disable the interrupt using the
1608 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1609 * On ICH6, this bit has the same effect, but only when
1610 * MSI is disabled (and it is disabled, as we don't use
1611 * message-signalled interrupts currently).
1612 */
1613 if (port_flags & PIIX_FLAG_CHECKINTR)
1614 pci_intx(pdev, 1);
1615
1616 if (piix_check_450nx_errata(pdev)) {
1617 /* This writes into the master table but it does not
1618 really matter for this errata as we will apply it to
1619 all the PIIX devices on the board */
1620 host->ports[0]->mwdma_mask = 0;
1621 host->ports[0]->udma_mask = 0;
1622 host->ports[1]->mwdma_mask = 0;
1623 host->ports[1]->udma_mask = 0;
1624 }
1625 host->flags |= ATA_HOST_PARALLEL_SCAN;
1626
1627 pci_set_master(pdev);
1628 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
1629 }
1630
1631 static void piix_remove_one(struct pci_dev *pdev)
1632 {
1633 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1634 struct piix_host_priv *hpriv = host->private_data;
1635
1636 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1637
1638 ata_pci_remove_one(pdev);
1639 }
1640
1641 static int __init piix_init(void)
1642 {
1643 int rc;
1644
1645 DPRINTK("pci_register_driver\n");
1646 rc = pci_register_driver(&piix_pci_driver);
1647 if (rc)
1648 return rc;
1649
1650 in_module_init = 0;
1651
1652 DPRINTK("done\n");
1653 return 0;
1654 }
1655
1656 static void __exit piix_exit(void)
1657 {
1658 pci_unregister_driver(&piix_pci_driver);
1659 }
1660
1661 module_init(piix_init);
1662 module_exit(piix_exit);
WandBoard kernel