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Staging: rtl8192e: remove #if 0 sections
[wandboard.git] / drivers / staging / rtl8192e / r8192E_dm.c
blobe3d5aa3f8cb706d89b8262143e8feba4c7d3c33d
1 /*++
2 Copyright-c Realtek Semiconductor Corp. All rights reserved.
3
4 Module Name:
5 r8192U_dm.c
6
7 Abstract:
8 HW dynamic mechanism.
9
10 Major Change History:
11 When Who What
12 ---------- --------------- -------------------------------
13 2008-05-14 amy create version 0 porting from windows code.
14
15 --*/
16 #include "r8192E.h"
17 #include "r8192E_dm.h"
18 #include "r8192E_hw.h"
19 #include "r819xE_phy.h"
20 #include "r819xE_phyreg.h"
21 #include "r8190_rtl8256.h"
22 /*---------------------------Define Local Constant---------------------------*/
23 //
24 // Indicate different AP vendor for IOT issue.
25 //
26 #ifdef RTL8190P
27 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
28 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322};
29 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
30 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322};
31 #else
32 #ifdef RTL8192E
33 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
34 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322};
35 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
36 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322};
37 #else
38 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
39 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f};
40 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
41 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f};
42 #endif
43 #endif
44
45 #define RTK_UL_EDCA 0xa44f
46 #define RTK_DL_EDCA 0x5e4322
47 /*---------------------------Define Local Constant---------------------------*/
48
49
50 /*------------------------Define global variable-----------------------------*/
51 // Debug variable ?
52 dig_t dm_digtable;
53 // Store current shoftware write register content for MAC PHY.
54 u8 dm_shadow[16][256] = {{0}};
55 // For Dynamic Rx Path Selection by Signal Strength
56 DRxPathSel DM_RxPathSelTable;
57 /*------------------------Define global variable-----------------------------*/
58
59
60 /*------------------------Define local variable------------------------------*/
61 /*------------------------Define local variable------------------------------*/
62
63
64 /*--------------------Define export function prototype-----------------------*/
65 extern void init_hal_dm(struct net_device *dev);
66 extern void deinit_hal_dm(struct net_device *dev);
67
68 extern void hal_dm_watchdog(struct net_device *dev);
69
70
71 extern void init_rate_adaptive(struct net_device *dev);
72 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
73 extern void dm_txpower_trackingcallback(struct work_struct *work);
74 #else
75 extern void dm_txpower_trackingcallback(struct net_device *dev);
76 #endif
77
78 extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
79 extern void dm_restore_dynamic_mechanism_state(struct net_device *dev);
80 extern void dm_backup_dynamic_mechanism_state(struct net_device *dev);
81 extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
82 u32 dm_type,
83 u32 dm_value);
84 extern void DM_ChangeFsyncSetting(struct net_device *dev,
85 s32 DM_Type,
86 s32 DM_Value);
87 extern void dm_force_tx_fw_info(struct net_device *dev,
88 u32 force_type,
89 u32 force_value);
90 extern void dm_init_edca_turbo(struct net_device *dev);
91 extern void dm_rf_operation_test_callback(unsigned long data);
92 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
93 extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
94 #else
95 extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev);
96 #endif
97 extern void dm_fsync_timer_callback(unsigned long data);
98 extern void dm_check_fsync(struct net_device *dev);
99 extern void dm_shadow_init(struct net_device *dev);
100 extern void dm_initialize_txpower_tracking(struct net_device *dev);
101
102 #ifdef RTL8192E
103 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
104 extern void dm_gpio_change_rf_callback(struct work_struct *work);
105 #else
106 extern void dm_gpio_change_rf_callback(struct net_device *dev);
107 #endif
108 #endif
109
110
111
112 /*--------------------Define export function prototype-----------------------*/
113
114
115 /*---------------------Define local function prototype-----------------------*/
116 // DM --> Rate Adaptive
117 static void dm_check_rate_adaptive(struct net_device *dev);
118
119 // DM --> Bandwidth switch
120 static void dm_init_bandwidth_autoswitch(struct net_device *dev);
121 static void dm_bandwidth_autoswitch( struct net_device *dev);
122
123 // DM --> TX power control
124 //static void dm_initialize_txpower_tracking(struct net_device *dev);
125
126 static void dm_check_txpower_tracking(struct net_device *dev);
127
128
129
130 //static void dm_txpower_reset_recovery(struct net_device *dev);
131
132
133 // DM --> BB init gain restore
134 #ifndef RTL8192U
135 static void dm_bb_initialgain_restore(struct net_device *dev);
136
137
138 // DM --> BB init gain backup
139 static void dm_bb_initialgain_backup(struct net_device *dev);
140 #endif
141
142 // DM --> Dynamic Init Gain by RSSI
143 static void dm_dig_init(struct net_device *dev);
144 static void dm_ctrl_initgain_byrssi(struct net_device *dev);
145 static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
146 static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device *dev);
147 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
148 static void dm_initial_gain(struct net_device *dev);
149 static void dm_pd_th(struct net_device *dev);
150 static void dm_cs_ratio(struct net_device *dev);
151
152 static void dm_init_ctstoself(struct net_device *dev);
153 // DM --> EDCA turboe mode control
154 static void dm_check_edca_turbo(struct net_device *dev);
155
156 // DM --> HW RF control
157 static void dm_check_rfctrl_gpio(struct net_device *dev);
158
159 #ifndef RTL8190P
160 //static void dm_gpio_change_rf(struct net_device *dev);
161 #endif
162 // DM --> Check PBC
163 static void dm_check_pbc_gpio(struct net_device *dev);
164
165
166 // DM --> Check current RX RF path state
167 static void dm_check_rx_path_selection(struct net_device *dev);
168 static void dm_init_rxpath_selection(struct net_device *dev);
169 static void dm_rxpath_sel_byrssi(struct net_device *dev);
170
171
172 // DM --> Fsync for broadcom ap
173 static void dm_init_fsync(struct net_device *dev);
174 static void dm_deInit_fsync(struct net_device *dev);
175
176 //Added by vivi, 20080522
177 static void dm_check_txrateandretrycount(struct net_device *dev);
178
179 /*---------------------Define local function prototype-----------------------*/
180
181 /*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18
182 static void dm_init_dynamic_txpower(struct net_device *dev);
183 static void dm_dynamic_txpower(struct net_device *dev);
184
185
186 // DM --> For rate adaptive and DIG, we must send RSSI to firmware
187 static void dm_send_rssi_tofw(struct net_device *dev);
188 static void dm_ctstoself(struct net_device *dev);
189 /*---------------------------Define function prototype------------------------*/
190 //================================================================================
191 // HW Dynamic mechanism interface.
192 //================================================================================
193
194 //
195 // Description:
196 // Prepare SW resource for HW dynamic mechanism.
197 //
198 // Assumption:
199 // This function is only invoked at driver intialization once.
200 //
201 //
202 void init_hal_dm(struct net_device *dev)
203 {
204 struct r8192_priv *priv = ieee80211_priv(dev);
205
206 // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism.
207 priv->undecorated_smoothed_pwdb = -1;
208
209 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
210 dm_init_dynamic_txpower(dev);
211 init_rate_adaptive(dev);
212 //dm_initialize_txpower_tracking(dev);
213 dm_dig_init(dev);
214 dm_init_edca_turbo(dev);
215 dm_init_bandwidth_autoswitch(dev);
216 dm_init_fsync(dev);
217 dm_init_rxpath_selection(dev);
218 dm_init_ctstoself(dev);
219 #ifdef RTL8192E
220 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
221 INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
222 #else
223 INIT_WORK(&priv->gpio_change_rf_wq, (void(*)(void*)) dm_gpio_change_rf_callback,dev);
224 #endif
225 #endif
226
227 } // InitHalDm
228
229 void deinit_hal_dm(struct net_device *dev)
230 {
231
232 dm_deInit_fsync(dev);
233
234 }
235
236
237 #ifdef USB_RX_AGGREGATION_SUPPORT
238 void dm_CheckRxAggregation(struct net_device *dev) {
239 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
240 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
241 static unsigned long lastTxOkCnt = 0;
242 static unsigned long lastRxOkCnt = 0;
243 unsigned long curTxOkCnt = 0;
244 unsigned long curRxOkCnt = 0;
245
246 /*
247 if (pHalData->bForcedUsbRxAggr) {
248 if (pHalData->ForcedUsbRxAggrInfo == 0) {
249 if (pHalData->bCurrentRxAggrEnable) {
250 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
251 }
252 } else {
253 if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
254 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
255 }
256 }
257 return;
258 }
259
260 */
261 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
262 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
263
264 if((curTxOkCnt + curRxOkCnt) < 15000000) {
265 return;
266 }
267
268 if(curTxOkCnt > 4*curRxOkCnt) {
269 if (priv->bCurrentRxAggrEnable) {
270 write_nic_dword(dev, 0x1a8, 0);
271 priv->bCurrentRxAggrEnable = false;
272 }
273 }else{
274 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
275 u32 ulValue;
276 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
277 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
278 /*
279 * If usb rx firmware aggregation is enabled,
280 * when anyone of three threshold conditions above is reached,
281 * firmware will send aggregated packet to driver.
282 */
283 write_nic_dword(dev, 0x1a8, ulValue);
284 priv->bCurrentRxAggrEnable = true;
285 }
286 }
287
288 lastTxOkCnt = priv->stats.txbytesunicast;
289 lastRxOkCnt = priv->stats.rxbytesunicast;
290 } // dm_CheckEdcaTurbo
291 #endif
292
293
294
295 void hal_dm_watchdog(struct net_device *dev)
296 {
297 //struct r8192_priv *priv = ieee80211_priv(dev);
298
299 //static u8 previous_bssid[6] ={0};
300
301 /*Add by amy 2008/05/15 ,porting from windows code.*/
302 dm_check_rate_adaptive(dev);
303 dm_dynamic_txpower(dev);
304 dm_check_txrateandretrycount(dev);
305
306 dm_check_txpower_tracking(dev);
307
308 dm_ctrl_initgain_byrssi(dev);
309 dm_check_edca_turbo(dev);
310 dm_bandwidth_autoswitch(dev);
311
312 dm_check_rfctrl_gpio(dev);
313 dm_check_rx_path_selection(dev);
314 dm_check_fsync(dev);
315
316 // Add by amy 2008-05-15 porting from windows code.
317 dm_check_pbc_gpio(dev);
318 dm_send_rssi_tofw(dev);
319 dm_ctstoself(dev);
320
321 #ifdef USB_RX_AGGREGATION_SUPPORT
322 dm_CheckRxAggregation(dev);
323 #endif
324 } //HalDmWatchDog
325
326
327 /*
328 * Decide Rate Adaptive Set according to distance (signal strength)
329 * 01/11/2008 MHC Modify input arguments and RATR table level.
330 * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call
331 * the function after making sure RF_Type.
332 */
333 void init_rate_adaptive(struct net_device * dev)
334 {
335
336 struct r8192_priv *priv = ieee80211_priv(dev);
337 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
338
339 pra->ratr_state = DM_RATR_STA_MAX;
340 pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High;
341 pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5;
342 pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5;
343
344 pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5;
345 pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M;
346 pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M;
347
348 if(priv->CustomerID == RT_CID_819x_Netcore)
349 pra->ping_rssi_enable = 1;
350 else
351 pra->ping_rssi_enable = 0;
352 pra->ping_rssi_thresh_for_ra = 15;
353
354
355 if (priv->rf_type == RF_2T4R)
356 {
357 // 07/10/08 MH Modify for RA smooth scheme.
358 /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/
359 pra->upper_rssi_threshold_ratr = 0x8f0f0000;
360 pra->middle_rssi_threshold_ratr = 0x8f0ff000;
361 pra->low_rssi_threshold_ratr = 0x8f0ff001;
362 pra->low_rssi_threshold_ratr_40M = 0x8f0ff005;
363 pra->low_rssi_threshold_ratr_20M = 0x8f0ff001;
364 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
365 }
366 else if (priv->rf_type == RF_1T2R)
367 {
368 pra->upper_rssi_threshold_ratr = 0x000f0000;
369 pra->middle_rssi_threshold_ratr = 0x000ff000;
370 pra->low_rssi_threshold_ratr = 0x000ff001;
371 pra->low_rssi_threshold_ratr_40M = 0x000ff005;
372 pra->low_rssi_threshold_ratr_20M = 0x000ff001;
373 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
374 }
375
376 } // InitRateAdaptive
377
378
379 /*-----------------------------------------------------------------------------
380 * Function: dm_check_rate_adaptive()
381 *
382 * Overview:
383 *
384 * Input: NONE
385 *
386 * Output: NONE
387 *
388 * Return: NONE
389 *
390 * Revised History:
391 * When Who Remark
392 * 05/26/08 amy Create version 0 proting from windows code.
393 *
394 *---------------------------------------------------------------------------*/
395 static void dm_check_rate_adaptive(struct net_device * dev)
396 {
397 struct r8192_priv *priv = ieee80211_priv(dev);
398 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
399 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
400 u32 currentRATR, targetRATR = 0;
401 u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
402 bool bshort_gi_enabled = false;
403 static u8 ping_rssi_state=0;
404
405
406 if(!priv->up)
407 {
408 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
409 return;
410 }
411
412 if(pra->rate_adaptive_disabled)//this variable is set by ioctl.
413 return;
414
415 // TODO: Only 11n mode is implemented currently,
416 if( !(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
417 priv->ieee80211->mode == WIRELESS_MODE_N_5G))
418 return;
419
420 if( priv->ieee80211->state == IEEE80211_LINKED )
421 {
422 // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");
423
424 //
425 // Check whether Short GI is enabled
426 //
427 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
428 (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
429
430
431 pra->upper_rssi_threshold_ratr =
432 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
433
434 pra->middle_rssi_threshold_ratr =
435 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
436
437 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
438 {
439 pra->low_rssi_threshold_ratr =
440 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
441 }
442 else
443 {
444 pra->low_rssi_threshold_ratr =
445 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
446 }
447 //cosa add for test
448 pra->ping_rssi_ratr =
449 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
450
451 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
452 time to link with AP. We will not change upper/lower threshold. If
453 STA stay in high or low level, we must change two different threshold
454 to prevent jumping frequently. */
455 if (pra->ratr_state == DM_RATR_STA_HIGH)
456 {
457 HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra;
458 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
459 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
460 }
461 else if (pra->ratr_state == DM_RATR_STA_LOW)
462 {
463 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
464 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
465 (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
466 }
467 else
468 {
469 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
470 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
471 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
472 }
473
474 //DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);
475 if(priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA)
476 {
477 //DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);
478 pra->ratr_state = DM_RATR_STA_HIGH;
479 targetRATR = pra->upper_rssi_threshold_ratr;
480 }else if(priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA)
481 {
482 //DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);
483 pra->ratr_state = DM_RATR_STA_MIDDLE;
484 targetRATR = pra->middle_rssi_threshold_ratr;
485 }else
486 {
487 //DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);
488 pra->ratr_state = DM_RATR_STA_LOW;
489 targetRATR = pra->low_rssi_threshold_ratr;
490 }
491
492 //cosa add for test
493 if(pra->ping_rssi_enable)
494 {
495 //pHalData->UndecoratedSmoothedPWDB = 19;
496 if(priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5))
497 {
498 if( (priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
499 ping_rssi_state )
500 {
501 //DbgPrint("TestRSSI = %d, set RATR to 0x%x \n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);
502 pra->ratr_state = DM_RATR_STA_LOW;
503 targetRATR = pra->ping_rssi_ratr;
504 ping_rssi_state = 1;
505 }
506 //else
507 // DbgPrint("TestRSSI is between the range. \n");
508 }
509 else
510 {
511 //DbgPrint("TestRSSI Recover to 0x%x \n", targetRATR);
512 ping_rssi_state = 0;
513 }
514 }
515
516 // 2008.04.01
517 #if 1
518 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
519 if(priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
520 targetRATR &= 0xf00fffff;
521 #endif
522
523 //
524 // Check whether updating of RATR0 is required
525 //
526 currentRATR = read_nic_dword(dev, RATR0);
527 if( targetRATR != currentRATR )
528 {
529 u32 ratr_value;
530 ratr_value = targetRATR;
531 RT_TRACE(COMP_RATE,"currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
532 if(priv->rf_type == RF_1T2R)
533 {
534 ratr_value &= ~(RATE_ALL_OFDM_2SS);
535 }
536 write_nic_dword(dev, RATR0, ratr_value);
537 write_nic_byte(dev, UFWP, 1);
538
539 pra->last_ratr = targetRATR;
540 }
541
542 }
543 else
544 {
545 pra->ratr_state = DM_RATR_STA_MAX;
546 }
547
548 } // dm_CheckRateAdaptive
549
550
551 static void dm_init_bandwidth_autoswitch(struct net_device * dev)
552 {
553 struct r8192_priv *priv = ieee80211_priv(dev);
554
555 priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
556 priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
557 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
558 priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
559
560 } // dm_init_bandwidth_autoswitch
561
562
563 static void dm_bandwidth_autoswitch(struct net_device * dev)
564 {
565 struct r8192_priv *priv = ieee80211_priv(dev);
566
567 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||!priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable){
568 return;
569 }else{
570 if(priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false){//If send packets in 40 Mhz in 20/40
571 if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
572 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
573 }else{//in force send packets in 20 Mhz in 20/40
574 if(priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
575 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
576
577 }
578 }
579 } // dm_BandwidthAutoSwitch
580
581 //OFDM default at 0db, index=6.
582 #ifndef RTL8190P
583 static u32 OFDMSwingTable[OFDM_Table_Length] = {
584 0x7f8001fe, // 0, +6db
585 0x71c001c7, // 1, +5db
586 0x65400195, // 2, +4db
587 0x5a400169, // 3, +3db
588 0x50800142, // 4, +2db
589 0x47c0011f, // 5, +1db
590 0x40000100, // 6, +0db ===> default, upper for higher temprature, lower for low temprature
591 0x390000e4, // 7, -1db
592 0x32c000cb, // 8, -2db
593 0x2d4000b5, // 9, -3db
594 0x288000a2, // 10, -4db
595 0x24000090, // 11, -5db
596 0x20000080, // 12, -6db
597 0x1c800072, // 13, -7db
598 0x19800066, // 14, -8db
599 0x26c0005b, // 15, -9db
600 0x24400051, // 16, -10db
601 0x12000048, // 17, -11db
602 0x10000040 // 18, -12db
603 };
604 static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
605 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default
606 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db
607 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db
608 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db
609 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db
610 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db
611 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default
612 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db
613 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db
614 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db
615 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db
616 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db
617 };
618
619 static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = {
620 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default
621 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db
622 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db
623 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db
624 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db
625 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db
626 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default
627 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db
628 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db
629 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db
630 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
631 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
632 };
633 #endif
634 #define Pw_Track_Flag 0x11d
635 #define Tssi_Mea_Value 0x13c
636 #define Tssi_Report_Value1 0x134
637 #define Tssi_Report_Value2 0x13e
638 #define FW_Busy_Flag 0x13f
639 static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
640 {
641 struct r8192_priv *priv = ieee80211_priv(dev);
642 bool bHighpowerstate, viviflag = FALSE;
643 DCMD_TXCMD_T tx_cmd;
644 u8 powerlevelOFDM24G;
645 int i =0, j = 0, k = 0;
646 u8 RF_Type, tmp_report[5]={0, 0, 0, 0, 0};
647 u32 Value;
648 u8 Pwr_Flag;
649 u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0;
650 #ifdef RTL8192U
651 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
652 #endif
653 // bool rtStatus = true;
654 u32 delta=0;
655 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
656 // write_nic_byte(dev, 0x1ba, 0);
657 write_nic_byte(dev, Pw_Track_Flag, 0);
658 write_nic_byte(dev, FW_Busy_Flag, 0);
659 priv->ieee80211->bdynamic_txpower_enable = false;
660 bHighpowerstate = priv->bDynamicTxHighPower;
661
662 powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
663 RF_Type = priv->rf_type;
664 Value = (RF_Type<<8) | powerlevelOFDM24G;
665
666 RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
667
668 for(j = 0; j<=30; j++)
669 { //fill tx_cmd
670
671 tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING;
672 tx_cmd.Length = 4;
673 tx_cmd.Value = Value;
674 #ifdef RTL8192U
675 rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
676 if (rtStatus == RT_STATUS_FAILURE)
677 {
678 RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
679 }
680 #else
681 cmpk_message_handle_tx(dev, (u8*)&tx_cmd, DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
682 #endif
683 mdelay(1);
684 //DbgPrint("hi, vivi, strange\n");
685 for(i = 0;i <= 30; i++)
686 {
687 Pwr_Flag = read_nic_byte(dev, Pw_Track_Flag);
688
689 if (Pwr_Flag == 0)
690 {
691 mdelay(1);
692 continue;
693 }
694
695 Avg_TSSI_Meas = read_nic_word(dev, Tssi_Mea_Value);
696
697 if(Avg_TSSI_Meas == 0)
698 {
699 write_nic_byte(dev, Pw_Track_Flag, 0);
700 write_nic_byte(dev, FW_Busy_Flag, 0);
701 return;
702 }
703
704 for(k = 0;k < 5; k++)
705 {
706 if(k !=4)
707 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value1+k);
708 else
709 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value2);
710
711 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
712 }
713
714 //check if the report value is right
715 for(k = 0;k < 5; k++)
716 {
717 if(tmp_report[k] <= 20)
718 {
719 viviflag =TRUE;
720 break;
721 }
722 }
723 if(viviflag ==TRUE)
724 {
725 write_nic_byte(dev, Pw_Track_Flag, 0);
726 viviflag = FALSE;
727 RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n");
728 for(k = 0;k < 5; k++)
729 tmp_report[k] = 0;
730 break;
731 }
732
733 for(k = 0;k < 5; k++)
734 {
735 Avg_TSSI_Meas_from_driver += tmp_report[k];
736 }
737
738 Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
739 RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
740 TSSI_13dBm = priv->TSSI_13dBm;
741 RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
742
743 //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)
744 // For MacOS-compatible
745 if(Avg_TSSI_Meas_from_driver > TSSI_13dBm)
746 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
747 else
748 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
749
750 if(delta <= E_FOR_TX_POWER_TRACK)
751 {
752 priv->ieee80211->bdynamic_txpower_enable = TRUE;
753 write_nic_byte(dev, Pw_Track_Flag, 0);
754 write_nic_byte(dev, FW_Busy_Flag, 0);
755 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
756 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
757 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
758 #ifdef RTL8190P
759 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
760 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
761 #endif
762 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
763 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
764 return;
765 }
766 else
767 {
768 if(Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK)
769 {
770 if (RF_Type == RF_2T4R)
771 {
772
773 if((priv->rfa_txpowertrackingindex > 0) &&(priv->rfc_txpowertrackingindex > 0))
774 {
775 priv->rfa_txpowertrackingindex--;
776 if(priv->rfa_txpowertrackingindex_real > 4)
777 {
778 priv->rfa_txpowertrackingindex_real--;
779 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
780 }
781
782 priv->rfc_txpowertrackingindex--;
783 if(priv->rfc_txpowertrackingindex_real > 4)
784 {
785 priv->rfc_txpowertrackingindex_real--;
786 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
787 }
788 }
789 else
790 {
791 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
792 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
793 }
794 }
795 else
796 {
797 if(priv->rfc_txpowertrackingindex > 0)
798 {
799 priv->rfc_txpowertrackingindex--;
800 if(priv->rfc_txpowertrackingindex_real > 4)
801 {
802 priv->rfc_txpowertrackingindex_real--;
803 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
804 }
805 }
806 else
807 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
808 }
809 }
810 else
811 {
812 if (RF_Type == RF_2T4R)
813 {
814 if((priv->rfa_txpowertrackingindex < TxBBGainTableLength - 1) &&(priv->rfc_txpowertrackingindex < TxBBGainTableLength - 1))
815 {
816 priv->rfa_txpowertrackingindex++;
817 priv->rfa_txpowertrackingindex_real++;
818 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
819 priv->rfc_txpowertrackingindex++;
820 priv->rfc_txpowertrackingindex_real++;
821 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
822 }
823 else
824 {
825 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
826 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
827 }
828 }
829 else
830 {
831 if(priv->rfc_txpowertrackingindex < (TxBBGainTableLength - 1))
832 {
833 priv->rfc_txpowertrackingindex++;
834 priv->rfc_txpowertrackingindex_real++;
835 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
836 }
837 else
838 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
839 }
840 }
841 if (RF_Type == RF_2T4R)
842 priv->CCKPresentAttentuation_difference
843 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
844 else
845 priv->CCKPresentAttentuation_difference
846 = priv->rfc_txpowertrackingindex - priv->rfc_txpowertracking_default;
847
848 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
849 priv->CCKPresentAttentuation
850 = priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
851 else
852 priv->CCKPresentAttentuation
853 = priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
854
855 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
856 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
857 if(priv->CCKPresentAttentuation < 0)
858 priv->CCKPresentAttentuation = 0;
859
860 if(1)
861 {
862 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
863 {
864 priv->bcck_in_ch14 = TRUE;
865 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
866 }
867 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
868 {
869 priv->bcck_in_ch14 = FALSE;
870 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
871 }
872 else
873 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
874 }
875 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
876 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
877 #ifdef RTL8190P
878 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
879 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
880 #endif
881 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
882 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
883
884 if (priv->CCKPresentAttentuation_difference <= -12||priv->CCKPresentAttentuation_difference >= 24)
885 {
886 priv->ieee80211->bdynamic_txpower_enable = TRUE;
887 write_nic_byte(dev, Pw_Track_Flag, 0);
888 write_nic_byte(dev, FW_Busy_Flag, 0);
889 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
890 return;
891 }
892
893
894 }
895 write_nic_byte(dev, Pw_Track_Flag, 0);
896 Avg_TSSI_Meas_from_driver = 0;
897 for(k = 0;k < 5; k++)
898 tmp_report[k] = 0;
899 break;
900 }
901 write_nic_byte(dev, FW_Busy_Flag, 0);
902 }
903 priv->ieee80211->bdynamic_txpower_enable = TRUE;
904 write_nic_byte(dev, Pw_Track_Flag, 0);
905 }
906 #ifndef RTL8190P
907 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
908 {
909 #define ThermalMeterVal 9
910 struct r8192_priv *priv = ieee80211_priv(dev);
911 u32 tmpRegA, TempCCk;
912 u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
913 int i =0, CCKSwingNeedUpdate=0;
914
915 if(!priv->btxpower_trackingInit)
916 {
917 //Query OFDM default setting
918 tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
919 for(i=0; i<OFDM_Table_Length; i++) //find the index
920 {
921 if(tmpRegA == OFDMSwingTable[i])
922 {
923 priv->OFDM_index= (u8)i;
924 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
925 rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
926 }
927 }
928
929 //Query CCK default setting From 0xa22
930 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
931 for(i=0 ; i<CCK_Table_length ; i++)
932 {
933 if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0])
934 {
935 priv->CCK_index =(u8) i;
936 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
937 rCCK0_TxFilter1, TempCCk, priv->CCK_index);
938 break;
939 }
940 }
941 priv->btxpower_trackingInit = TRUE;
942 //pHalData->TXPowercount = 0;
943 return;
944 }
945
946 // read and filter out unreasonable value
947 tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7]
948 RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d \n", tmpRegA);
949 if(tmpRegA < 3 || tmpRegA > 13)
950 return;
951 if(tmpRegA >= 12) // if over 12, TP will be bad when high temprature
952 tmpRegA = 12;
953 RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d \n", tmpRegA);
954 priv->ThermalMeter[0] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
955 priv->ThermalMeter[1] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
956
957 //Get current RF-A temprature index
958 if(priv->ThermalMeter[0] >= (u8)tmpRegA) //lower temprature
959 {
960 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
961 tmpCCK40Mindex = tmpCCK20Mindex - 6;
962 if(tmpOFDMindex >= OFDM_Table_Length)
963 tmpOFDMindex = OFDM_Table_Length-1;
964 if(tmpCCK20Mindex >= CCK_Table_length)
965 tmpCCK20Mindex = CCK_Table_length-1;
966 if(tmpCCK40Mindex >= CCK_Table_length)
967 tmpCCK40Mindex = CCK_Table_length-1;
968 }
969 else
970 {
971 tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]);
972 if(tmpval >= 6) // higher temprature
973 tmpOFDMindex = tmpCCK20Mindex = 0; // max to +6dB
974 else
975 tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval;
976 tmpCCK40Mindex = 0;
977 }
978 //DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
979 //((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
980 //tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);
981 if(priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) //40M
982 tmpCCKindex = tmpCCK40Mindex;
983 else
984 tmpCCKindex = tmpCCK20Mindex;
985
986 //record for bandwidth swith
987 priv->Record_CCK_20Mindex = tmpCCK20Mindex;
988 priv->Record_CCK_40Mindex = tmpCCK40Mindex;
989 RT_TRACE(COMP_POWER_TRACKING, "Record_CCK_20Mindex / Record_CCK_40Mindex = %d / %d.\n",
990 priv->Record_CCK_20Mindex, priv->Record_CCK_40Mindex);
991
992 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
993 {
994 priv->bcck_in_ch14 = TRUE;
995 CCKSwingNeedUpdate = 1;
996 }
997 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
998 {
999 priv->bcck_in_ch14 = FALSE;
1000 CCKSwingNeedUpdate = 1;
1001 }
1002
1003 if(priv->CCK_index != tmpCCKindex)
1004 {
1005 priv->CCK_index = tmpCCKindex;
1006 CCKSwingNeedUpdate = 1;
1007 }
1008
1009 if(CCKSwingNeedUpdate)
1010 {
1011 //DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);
1012 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1013 }
1014 if(priv->OFDM_index != tmpOFDMindex)
1015 {
1016 priv->OFDM_index = tmpOFDMindex;
1017 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
1018 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
1019 priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
1020 }
1021 priv->txpower_count = 0;
1022 }
1023 #endif
1024 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1025 void dm_txpower_trackingcallback(struct work_struct *work)
1026 {
1027 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
1028 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq);
1029 struct net_device *dev = priv->ieee80211->dev;
1030 #else
1031 extern void dm_txpower_trackingcallback(struct net_device *dev)
1032 {
1033 #ifndef RTL8190P
1034 struct r8192_priv *priv = ieee80211_priv(dev);
1035 #endif
1036 #endif
1037
1038 #ifdef RTL8190P
1039 dm_TXPowerTrackingCallback_TSSI(dev);
1040 #else
1041 //if(priv->bDcut == TRUE)
1042 if(priv->IC_Cut >= IC_VersionCut_D)
1043 dm_TXPowerTrackingCallback_TSSI(dev);
1044 else
1045 dm_TXPowerTrackingCallback_ThermalMeter(dev);
1046 #endif
1047 }
1048
1049
1050 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
1051 {
1052
1053 struct r8192_priv *priv = ieee80211_priv(dev);
1054
1055 //Initial the Tx BB index and mapping value
1056 priv->txbbgain_table[0].txbb_iq_amplifygain = 12;
1057 priv->txbbgain_table[0].txbbgain_value=0x7f8001fe;
1058 priv->txbbgain_table[1].txbb_iq_amplifygain = 11;
1059 priv->txbbgain_table[1].txbbgain_value=0x788001e2;
1060 priv->txbbgain_table[2].txbb_iq_amplifygain = 10;
1061 priv->txbbgain_table[2].txbbgain_value=0x71c001c7;
1062 priv->txbbgain_table[3].txbb_iq_amplifygain = 9;
1063 priv->txbbgain_table[3].txbbgain_value=0x6b8001ae;
1064 priv->txbbgain_table[4].txbb_iq_amplifygain = 8;
1065 priv->txbbgain_table[4].txbbgain_value=0x65400195;
1066 priv->txbbgain_table[5].txbb_iq_amplifygain = 7;
1067 priv->txbbgain_table[5].txbbgain_value=0x5fc0017f;
1068 priv->txbbgain_table[6].txbb_iq_amplifygain = 6;
1069 priv->txbbgain_table[6].txbbgain_value=0x5a400169;
1070 priv->txbbgain_table[7].txbb_iq_amplifygain = 5;
1071 priv->txbbgain_table[7].txbbgain_value=0x55400155;
1072 priv->txbbgain_table[8].txbb_iq_amplifygain = 4;
1073 priv->txbbgain_table[8].txbbgain_value=0x50800142;
1074 priv->txbbgain_table[9].txbb_iq_amplifygain = 3;
1075 priv->txbbgain_table[9].txbbgain_value=0x4c000130;
1076 priv->txbbgain_table[10].txbb_iq_amplifygain = 2;
1077 priv->txbbgain_table[10].txbbgain_value=0x47c0011f;
1078 priv->txbbgain_table[11].txbb_iq_amplifygain = 1;
1079 priv->txbbgain_table[11].txbbgain_value=0x43c0010f;
1080 priv->txbbgain_table[12].txbb_iq_amplifygain = 0;
1081 priv->txbbgain_table[12].txbbgain_value=0x40000100;
1082 priv->txbbgain_table[13].txbb_iq_amplifygain = -1;
1083 priv->txbbgain_table[13].txbbgain_value=0x3c8000f2;
1084 priv->txbbgain_table[14].txbb_iq_amplifygain = -2;
1085 priv->txbbgain_table[14].txbbgain_value=0x390000e4;
1086 priv->txbbgain_table[15].txbb_iq_amplifygain = -3;
1087 priv->txbbgain_table[15].txbbgain_value=0x35c000d7;
1088 priv->txbbgain_table[16].txbb_iq_amplifygain = -4;
1089 priv->txbbgain_table[16].txbbgain_value=0x32c000cb;
1090 priv->txbbgain_table[17].txbb_iq_amplifygain = -5;
1091 priv->txbbgain_table[17].txbbgain_value=0x300000c0;
1092 priv->txbbgain_table[18].txbb_iq_amplifygain = -6;
1093 priv->txbbgain_table[18].txbbgain_value=0x2d4000b5;
1094 priv->txbbgain_table[19].txbb_iq_amplifygain = -7;
1095 priv->txbbgain_table[19].txbbgain_value=0x2ac000ab;
1096 priv->txbbgain_table[20].txbb_iq_amplifygain = -8;
1097 priv->txbbgain_table[20].txbbgain_value=0x288000a2;
1098 priv->txbbgain_table[21].txbb_iq_amplifygain = -9;
1099 priv->txbbgain_table[21].txbbgain_value=0x26000098;
1100 priv->txbbgain_table[22].txbb_iq_amplifygain = -10;
1101 priv->txbbgain_table[22].txbbgain_value=0x24000090;
1102 priv->txbbgain_table[23].txbb_iq_amplifygain = -11;
1103 priv->txbbgain_table[23].txbbgain_value=0x22000088;
1104 priv->txbbgain_table[24].txbb_iq_amplifygain = -12;
1105 priv->txbbgain_table[24].txbbgain_value=0x20000080;
1106 priv->txbbgain_table[25].txbb_iq_amplifygain = -13;
1107 priv->txbbgain_table[25].txbbgain_value=0x1a00006c;
1108 priv->txbbgain_table[26].txbb_iq_amplifygain = -14;
1109 priv->txbbgain_table[26].txbbgain_value=0x1c800072;
1110 priv->txbbgain_table[27].txbb_iq_amplifygain = -15;
1111 priv->txbbgain_table[27].txbbgain_value=0x18000060;
1112 priv->txbbgain_table[28].txbb_iq_amplifygain = -16;
1113 priv->txbbgain_table[28].txbbgain_value=0x19800066;
1114 priv->txbbgain_table[29].txbb_iq_amplifygain = -17;
1115 priv->txbbgain_table[29].txbbgain_value=0x15800056;
1116 priv->txbbgain_table[30].txbb_iq_amplifygain = -18;
1117 priv->txbbgain_table[30].txbbgain_value=0x26c0005b;
1118 priv->txbbgain_table[31].txbb_iq_amplifygain = -19;
1119 priv->txbbgain_table[31].txbbgain_value=0x14400051;
1120 priv->txbbgain_table[32].txbb_iq_amplifygain = -20;
1121 priv->txbbgain_table[32].txbbgain_value=0x24400051;
1122 priv->txbbgain_table[33].txbb_iq_amplifygain = -21;
1123 priv->txbbgain_table[33].txbbgain_value=0x1300004c;
1124 priv->txbbgain_table[34].txbb_iq_amplifygain = -22;
1125 priv->txbbgain_table[34].txbbgain_value=0x12000048;
1126 priv->txbbgain_table[35].txbb_iq_amplifygain = -23;
1127 priv->txbbgain_table[35].txbbgain_value=0x11000044;
1128 priv->txbbgain_table[36].txbb_iq_amplifygain = -24;
1129 priv->txbbgain_table[36].txbbgain_value=0x10000040;
1130
1131 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1132 //This Table is for CH1~CH13
1133 priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36;
1134 priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35;
1135 priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e;
1136 priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25;
1137 priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c;
1138 priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12;
1139 priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09;
1140 priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04;
1141
1142 priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33;
1143 priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32;
1144 priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b;
1145 priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23;
1146 priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a;
1147 priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11;
1148 priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08;
1149 priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04;
1150
1151 priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30;
1152 priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f;
1153 priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29;
1154 priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21;
1155 priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19;
1156 priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10;
1157 priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08;
1158 priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03;
1159
1160 priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d;
1161 priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d;
1162 priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27;
1163 priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f;
1164 priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18;
1165 priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f;
1166 priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08;
1167 priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03;
1168
1169 priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b;
1170 priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a;
1171 priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25;
1172 priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e;
1173 priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16;
1174 priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e;
1175 priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07;
1176 priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03;
1177
1178 priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28;
1179 priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28;
1180 priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22;
1181 priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c;
1182 priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15;
1183 priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d;
1184 priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07;
1185 priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03;
1186
1187 priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26;
1188 priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25;
1189 priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21;
1190 priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b;
1191 priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14;
1192 priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d;
1193 priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06;
1194 priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03;
1195
1196 priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24;
1197 priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23;
1198 priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f;
1199 priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19;
1200 priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13;
1201 priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c;
1202 priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06;
1203 priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03;
1204
1205 priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22;
1206 priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21;
1207 priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d;
1208 priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18;
1209 priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11;
1210 priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b;
1211 priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06;
1212 priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02;
1213
1214 priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20;
1215 priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20;
1216 priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b;
1217 priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16;
1218 priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11;
1219 priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08;
1220 priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05;
1221 priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02;
1222
1223 priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f;
1224 priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e;
1225 priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a;
1226 priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15;
1227 priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10;
1228 priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a;
1229 priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05;
1230 priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02;
1231
1232 priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d;
1233 priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c;
1234 priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18;
1235 priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14;
1236 priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f;
1237 priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a;
1238 priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05;
1239 priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02;
1240
1241 priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b;
1242 priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a;
1243 priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17;
1244 priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13;
1245 priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e;
1246 priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09;
1247 priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04;
1248 priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02;
1249
1250 priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a;
1251 priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19;
1252 priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16;
1253 priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12;
1254 priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d;
1255 priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09;
1256 priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04;
1257 priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02;
1258
1259 priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18;
1260 priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17;
1261 priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15;
1262 priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11;
1263 priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c;
1264 priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08;
1265 priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04;
1266 priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02;
1267
1268 priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17;
1269 priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16;
1270 priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13;
1271 priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10;
1272 priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c;
1273 priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08;
1274 priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04;
1275 priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02;
1276
1277 priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16;
1278 priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15;
1279 priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12;
1280 priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f;
1281 priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b;
1282 priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07;
1283 priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04;
1284 priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01;
1285
1286 priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14;
1287 priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14;
1288 priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11;
1289 priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e;
1290 priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b;
1291 priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07;
1292 priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03;
1293 priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02;
1294
1295 priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13;
1296 priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13;
1297 priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10;
1298 priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d;
1299 priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a;
1300 priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06;
1301 priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03;
1302 priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01;
1303
1304 priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12;
1305 priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12;
1306 priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f;
1307 priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c;
1308 priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09;
1309 priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06;
1310 priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03;
1311 priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01;
1312
1313 priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11;
1314 priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11;
1315 priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f;
1316 priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c;
1317 priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09;
1318 priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06;
1319 priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03;
1320 priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01;
1321
1322 priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10;
1323 priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10;
1324 priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e;
1325 priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b;
1326 priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08;
1327 priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05;
1328 priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03;
1329 priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01;
1330
1331 priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f;
1332 priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f;
1333 priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d;
1334 priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b;
1335 priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08;
1336 priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05;
1337 priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03;
1338 priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01;
1339
1340 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1341 //This Table is for CH14
1342 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36;
1343 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35;
1344 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e;
1345 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b;
1346 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00;
1347 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00;
1348 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00;
1349 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00;
1350
1351 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33;
1352 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32;
1353 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b;
1354 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19;
1355 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00;
1356 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00;
1357 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00;
1358 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00;
1359
1360 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30;
1361 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f;
1362 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29;
1363 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18;
1364 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00;
1365 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00;
1366 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00;
1367 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00;
1368
1369 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d;
1370 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d;
1371 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27;
1372 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17;
1373 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00;
1374 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00;
1375 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00;
1376 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00;
1377
1378 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b;
1379 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a;
1380 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25;
1381 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15;
1382 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00;
1383 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00;
1384 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00;
1385 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00;
1386
1387 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28;
1388 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28;
1389 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22;
1390 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14;
1391 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00;
1392 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00;
1393 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00;
1394 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00;
1395
1396 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26;
1397 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25;
1398 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21;
1399 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13;
1400 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00;
1401 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00;
1402 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00;
1403 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00;
1404
1405 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24;
1406 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23;
1407 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f;
1408 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12;
1409 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00;
1410 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00;
1411 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00;
1412 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00;
1413
1414 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22;
1415 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21;
1416 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d;
1417 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11;
1418 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00;
1419 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00;
1420 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00;
1421 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00;
1422
1423 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20;
1424 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20;
1425 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b;
1426 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10;
1427 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00;
1428 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00;
1429 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00;
1430 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00;
1431
1432 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f;
1433 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e;
1434 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a;
1435 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f;
1436 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00;
1437 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00;
1438 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00;
1439 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00;
1440
1441 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d;
1442 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c;
1443 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18;
1444 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e;
1445 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00;
1446 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00;
1447 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00;
1448 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00;
1449
1450 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b;
1451 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a;
1452 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17;
1453 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e;
1454 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00;
1455 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00;
1456 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00;
1457 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00;
1458
1459 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a;
1460 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19;
1461 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16;
1462 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d;
1463 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00;
1464 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00;
1465 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00;
1466 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00;
1467
1468 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18;
1469 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17;
1470 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15;
1471 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c;
1472 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00;
1473 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00;
1474 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00;
1475 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00;
1476
1477 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17;
1478 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16;
1479 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13;
1480 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b;
1481 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00;
1482 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00;
1483 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00;
1484 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00;
1485
1486 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16;
1487 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15;
1488 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12;
1489 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b;
1490 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00;
1491 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00;
1492 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00;
1493 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00;
1494
1495 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14;
1496 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14;
1497 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11;
1498 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a;
1499 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00;
1500 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00;
1501 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00;
1502 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00;
1503
1504 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13;
1505 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13;
1506 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10;
1507 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a;
1508 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00;
1509 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00;
1510 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00;
1511 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00;
1512
1513 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12;
1514 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12;
1515 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f;
1516 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09;
1517 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00;
1518 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00;
1519 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00;
1520 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00;
1521
1522 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11;
1523 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11;
1524 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f;
1525 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09;
1526 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00;
1527 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00;
1528 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00;
1529 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00;
1530
1531 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10;
1532 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10;
1533 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e;
1534 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08;
1535 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00;
1536 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00;
1537 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00;
1538 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00;
1539
1540 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f;
1541 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f;
1542 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d;
1543 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08;
1544 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00;
1545 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00;
1546 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00;
1547 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00;
1548
1549 priv->btxpower_tracking = TRUE;
1550 priv->txpower_count = 0;
1551 priv->btxpower_trackingInit = FALSE;
1552
1553 }
1554 #ifndef RTL8190P
1555 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1556 {
1557 struct r8192_priv *priv = ieee80211_priv(dev);
1558
1559 // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism
1560 // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1561 // 3-wire by driver cause RF goes into wrong state.
1562 if(priv->ieee80211->FwRWRF)
1563 priv->btxpower_tracking = TRUE;
1564 else
1565 priv->btxpower_tracking = FALSE;
1566 priv->txpower_count = 0;
1567 priv->btxpower_trackingInit = FALSE;
1568 }
1569 #endif
1570
1571 void dm_initialize_txpower_tracking(struct net_device *dev)
1572 {
1573 #ifndef RTL8190P
1574 struct r8192_priv *priv = ieee80211_priv(dev);
1575 #endif
1576 #ifdef RTL8190P
1577 dm_InitializeTXPowerTracking_TSSI(dev);
1578 #else
1579 //if(priv->bDcut == TRUE)
1580 if(priv->IC_Cut >= IC_VersionCut_D)
1581 dm_InitializeTXPowerTracking_TSSI(dev);
1582 else
1583 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1584 #endif
1585 } // dm_InitializeTXPowerTracking
1586
1587
1588 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1589 {
1590 struct r8192_priv *priv = ieee80211_priv(dev);
1591 static u32 tx_power_track_counter = 0;
1592 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
1593 if(read_nic_byte(dev, 0x11e) ==1)
1594 return;
1595 if(!priv->btxpower_tracking)
1596 return;
1597 tx_power_track_counter++;
1598
1599
1600 if(tx_power_track_counter > 90)
1601 {
1602 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1603 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1604 #else
1605 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1606 schedule_task(&priv->txpower_tracking_wq);
1607 #else
1608 queue_work(priv->priv_wq,&priv->txpower_tracking_wq);
1609 #endif
1610 #endif
1611 tx_power_track_counter =0;
1612 }
1613
1614 }
1615
1616 #ifndef RTL8190P
1617 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1618 {
1619 struct r8192_priv *priv = ieee80211_priv(dev);
1620 static u8 TM_Trigger=0;
1621
1622 //DbgPrint("dm_CheckTXPowerTracking() \n");
1623 if(!priv->btxpower_tracking)
1624 return;
1625 else
1626 {
1627 if(priv->txpower_count <= 2)
1628 {
1629 priv->txpower_count++;
1630 return;
1631 }
1632 }
1633
1634 if(!TM_Trigger)
1635 {
1636 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
1637 //actually write reg0x02 bit1=0, then bit1=1.
1638 //DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1639 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1640 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1641 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1642 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1643 TM_Trigger = 1;
1644 return;
1645 }
1646 else
1647 {
1648 //DbgPrint("Schedule TxPowerTrackingWorkItem\n");
1649 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1650 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1651 #else
1652 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1653 schedule_task(&priv->txpower_tracking_wq);
1654 #else
1655 queue_work(priv->priv_wq,&priv->txpower_tracking_wq);
1656 #endif
1657 #endif
1658 TM_Trigger = 0;
1659 }
1660 }
1661 #endif
1662
1663 static void dm_check_txpower_tracking(struct net_device *dev)
1664 {
1665 #ifndef RTL8190P
1666 struct r8192_priv *priv = ieee80211_priv(dev);
1667 //static u32 tx_power_track_counter = 0;
1668 #endif
1669 #ifdef RTL8190P
1670 dm_CheckTXPowerTracking_TSSI(dev);
1671 #else
1672 //if(priv->bDcut == TRUE)
1673 if(priv->IC_Cut >= IC_VersionCut_D)
1674 dm_CheckTXPowerTracking_TSSI(dev);
1675 else
1676 dm_CheckTXPowerTracking_ThermalMeter(dev);
1677 #endif
1678
1679 } // dm_CheckTXPowerTracking
1680
1681
1682 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
1683 {
1684 u32 TempVal;
1685 struct r8192_priv *priv = ieee80211_priv(dev);
1686 //Write 0xa22 0xa23
1687 TempVal = 0;
1688 if(!bInCH14){
1689 //Write 0xa22 0xa23
1690 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1691 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1692
1693 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1694 //Write 0xa24 ~ 0xa27
1695 TempVal = 0;
1696 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1697 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1698 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1699 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1700 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1701 //Write 0xa28 0xa29
1702 TempVal = 0;
1703 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1704 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1705
1706 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1707 }
1708 else
1709 {
1710 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1711 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1712
1713 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1714 //Write 0xa24 ~ 0xa27
1715 TempVal = 0;
1716 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1717 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1718 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1719 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1720 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1721 //Write 0xa28 0xa29
1722 TempVal = 0;
1723 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1724 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1725
1726 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1727 }
1728
1729
1730 }
1731 #ifndef RTL8190P
1732 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14)
1733 {
1734 u32 TempVal;
1735 struct r8192_priv *priv = ieee80211_priv(dev);
1736
1737 TempVal = 0;
1738 if(!bInCH14)
1739 {
1740 //Write 0xa22 0xa23
1741 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1742 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ;
1743 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1744 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1745 rCCK0_TxFilter1, TempVal);
1746 //Write 0xa24 ~ 0xa27
1747 TempVal = 0;
1748 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1749 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1750 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+
1751 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1752 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1753 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1754 rCCK0_TxFilter2, TempVal);
1755 //Write 0xa28 0xa29
1756 TempVal = 0;
1757 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1758 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ;
1759
1760 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1761 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1762 rCCK0_DebugPort, TempVal);
1763 }
1764 else
1765 {
1766 // priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug.
1767 //Write 0xa22 0xa23
1768 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
1769 (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ;
1770
1771 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1772 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1773 rCCK0_TxFilter1, TempVal);
1774 //Write 0xa24 ~ 0xa27
1775 TempVal = 0;
1776 TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] +
1777 (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1778 (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+
1779 (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1780 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1781 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1782 rCCK0_TxFilter2, TempVal);
1783 //Write 0xa28 0xa29
1784 TempVal = 0;
1785 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
1786 (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ;
1787
1788 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1789 RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n",
1790 rCCK0_DebugPort, TempVal);
1791 }
1792 }
1793 #endif
1794
1795
1796 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1797 { // dm_CCKTxPowerAdjust
1798 #ifndef RTL8190P
1799 struct r8192_priv *priv = ieee80211_priv(dev);
1800 #endif
1801 #ifdef RTL8190P
1802 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1803 #else
1804 //if(priv->bDcut == TRUE)
1805 if(priv->IC_Cut >= IC_VersionCut_D)
1806 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1807 else
1808 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1809 #endif
1810 }
1811
1812
1813 #ifndef RTL8192U
1814 static void dm_txpower_reset_recovery(
1815 struct net_device *dev
1816 )
1817 {
1818 struct r8192_priv *priv = ieee80211_priv(dev);
1819
1820 RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1821 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1822 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1823 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex);
1824 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1825 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->CCKPresentAttentuation);
1826 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1827
1828 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1829 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1830 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);
1831 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1832
1833 } // dm_TXPowerResetRecovery
1834
1835 void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1836 {
1837 struct r8192_priv *priv = ieee80211_priv(dev);
1838 u32 reg_ratr = priv->rate_adaptive.last_ratr;
1839
1840 if(!priv->up)
1841 {
1842 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1843 return;
1844 }
1845
1846 //
1847 // Restore previous state for rate adaptive
1848 //
1849 if(priv->rate_adaptive.rate_adaptive_disabled)
1850 return;
1851 // TODO: Only 11n mode is implemented currently,
1852 if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||
1853 priv->ieee80211->mode==WIRELESS_MODE_N_5G))
1854 return;
1855 {
1856 /* 2007/11/15 MH Copy from 8190PCI. */
1857 u32 ratr_value;
1858 ratr_value = reg_ratr;
1859 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
1860 {
1861 ratr_value &=~ (RATE_ALL_OFDM_2SS);
1862 //DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);
1863 }
1864 //DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);
1865 //cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);
1866 write_nic_dword(dev, RATR0, ratr_value);
1867 write_nic_byte(dev, UFWP, 1);
1868 }
1869 //Resore TX Power Tracking Index
1870 if(priv->btxpower_trackingInit && priv->btxpower_tracking){
1871 dm_txpower_reset_recovery(dev);
1872 }
1873
1874 //
1875 //Restore BB Initial Gain
1876 //
1877 dm_bb_initialgain_restore(dev);
1878
1879 } // DM_RestoreDynamicMechanismState
1880
1881 static void dm_bb_initialgain_restore(struct net_device *dev)
1882 {
1883 struct r8192_priv *priv = ieee80211_priv(dev);
1884 u32 bit_mask = 0x7f; //Bit0~ Bit6
1885
1886 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1887 return;
1888
1889 //Disable Initial Gain
1890 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1891 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1892 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1893 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1894 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1895 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1896 bit_mask = bMaskByte2;
1897 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1898
1899 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1900 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1901 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1902 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1903 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1904 //Enable Initial Gain
1905 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
1906 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1907
1908 } // dm_BBInitialGainRestore
1909
1910
1911 void dm_backup_dynamic_mechanism_state(struct net_device *dev)
1912 {
1913 struct r8192_priv *priv = ieee80211_priv(dev);
1914
1915 // Fsync to avoid reset
1916 priv->bswitch_fsync = false;
1917 priv->bfsync_processing = false;
1918 //Backup BB InitialGain
1919 dm_bb_initialgain_backup(dev);
1920
1921 } // DM_BackupDynamicMechanismState
1922
1923
1924 static void dm_bb_initialgain_backup(struct net_device *dev)
1925 {
1926 struct r8192_priv *priv = ieee80211_priv(dev);
1927 u32 bit_mask = bMaskByte0; //Bit0~ Bit6
1928
1929 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1930 return;
1931
1932 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1933 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1934 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1935 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1936 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1937 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1938 bit_mask = bMaskByte2;
1939 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1940
1941 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1942 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1943 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1944 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1945 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1946
1947 } // dm_BBInitialGainBakcup
1948
1949 #endif
1950 /*-----------------------------------------------------------------------------
1951 * Function: dm_change_dynamic_initgain_thresh()
1952 *
1953 * Overview:
1954 *
1955 * Input: NONE
1956 *
1957 * Output: NONE
1958 *
1959 * Return: NONE
1960 *
1961 * Revised History:
1962 * When Who Remark
1963 * 05/29/2008 amy Create Version 0 porting from windows code.
1964 *
1965 *---------------------------------------------------------------------------*/
1966 void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value)
1967 {
1968 if (dm_type == DIG_TYPE_THRESH_HIGH)
1969 {
1970 dm_digtable.rssi_high_thresh = dm_value;
1971 }
1972 else if (dm_type == DIG_TYPE_THRESH_LOW)
1973 {
1974 dm_digtable.rssi_low_thresh = dm_value;
1975 }
1976 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
1977 {
1978 dm_digtable.rssi_high_power_highthresh = dm_value;
1979 }
1980 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
1981 {
1982 dm_digtable.rssi_high_power_highthresh = dm_value;
1983 }
1984 else if (dm_type == DIG_TYPE_ENABLE)
1985 {
1986 dm_digtable.dig_state = DM_STA_DIG_MAX;
1987 dm_digtable.dig_enable_flag = true;
1988 }
1989 else if (dm_type == DIG_TYPE_DISABLE)
1990 {
1991 dm_digtable.dig_state = DM_STA_DIG_MAX;
1992 dm_digtable.dig_enable_flag = false;
1993 }
1994 else if (dm_type == DIG_TYPE_DBG_MODE)
1995 {
1996 if(dm_value >= DM_DBG_MAX)
1997 dm_value = DM_DBG_OFF;
1998 dm_digtable.dbg_mode = (u8)dm_value;
1999 }
2000 else if (dm_type == DIG_TYPE_RSSI)
2001 {
2002 if(dm_value > 100)
2003 dm_value = 30;
2004 dm_digtable.rssi_val = (long)dm_value;
2005 }
2006 else if (dm_type == DIG_TYPE_ALGORITHM)
2007 {
2008 if (dm_value >= DIG_ALGO_MAX)
2009 dm_value = DIG_ALGO_BY_FALSE_ALARM;
2010 if(dm_digtable.dig_algorithm != (u8)dm_value)
2011 dm_digtable.dig_algorithm_switch = 1;
2012 dm_digtable.dig_algorithm = (u8)dm_value;
2013 }
2014 else if (dm_type == DIG_TYPE_BACKOFF)
2015 {
2016 if(dm_value > 30)
2017 dm_value = 30;
2018 dm_digtable.backoff_val = (u8)dm_value;
2019 }
2020 else if(dm_type == DIG_TYPE_RX_GAIN_MIN)
2021 {
2022 if(dm_value == 0)
2023 dm_value = 0x1;
2024 dm_digtable.rx_gain_range_min = (u8)dm_value;
2025 }
2026 else if(dm_type == DIG_TYPE_RX_GAIN_MAX)
2027 {
2028 if(dm_value > 0x50)
2029 dm_value = 0x50;
2030 dm_digtable.rx_gain_range_max = (u8)dm_value;
2031 }
2032 } /* DM_ChangeDynamicInitGainThresh */
2033
2034
2035 /*-----------------------------------------------------------------------------
2036 * Function: dm_dig_init()
2037 *
2038 * Overview: Set DIG scheme init value.
2039 *
2040 * Input: NONE
2041 *
2042 * Output: NONE
2043 *
2044 * Return: NONE
2045 *
2046 * Revised History:
2047 * When Who Remark
2048 * 05/15/2008 amy Create Version 0 porting from windows code.
2049 *
2050 *---------------------------------------------------------------------------*/
2051 static void dm_dig_init(struct net_device *dev)
2052 {
2053 struct r8192_priv *priv = ieee80211_priv(dev);
2054 /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
2055 dm_digtable.dig_enable_flag = true;
2056 dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
2057 dm_digtable.dbg_mode = DM_DBG_OFF; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig
2058 dm_digtable.dig_algorithm_switch = 0;
2059
2060 /* 2007/10/04 MH Define init gain threshol. */
2061 dm_digtable.dig_state = DM_STA_DIG_MAX;
2062 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
2063 dm_digtable.initialgain_lowerbound_state = false;
2064
2065 dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW;
2066 dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH;
2067
2068 dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
2069 dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
2070
2071 dm_digtable.rssi_val = 50; //for new dig debug rssi value
2072 dm_digtable.backoff_val = DM_DIG_BACKOFF;
2073 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
2074 if(priv->CustomerID == RT_CID_819x_Netcore)
2075 dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore;
2076 else
2077 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
2078
2079 } /* dm_dig_init */
2080
2081
2082 /*-----------------------------------------------------------------------------
2083 * Function: dm_ctrl_initgain_byrssi()
2084 *
2085 * Overview: Driver must monitor RSSI and notify firmware to change initial
2086 * gain according to different threshold. BB team provide the
2087 * suggested solution.
2088 *
2089 * Input: struct net_device *dev
2090 *
2091 * Output: NONE
2092 *
2093 * Return: NONE
2094 *
2095 * Revised History:
2096 * When Who Remark
2097 * 05/27/2008 amy Create Version 0 porting from windows code.
2098 *---------------------------------------------------------------------------*/
2099 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
2100 {
2101
2102 if (dm_digtable.dig_enable_flag == false)
2103 return;
2104
2105 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2106 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
2107 else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
2108 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
2109 else
2110 return;
2111 }
2112
2113
2114 static void dm_ctrl_initgain_byrssi_by_driverrssi(
2115 struct net_device *dev)
2116 {
2117 struct r8192_priv *priv = ieee80211_priv(dev);
2118 u8 i;
2119 static u8 fw_dig=0;
2120
2121 if (dm_digtable.dig_enable_flag == false)
2122 return;
2123
2124 //DbgPrint("Dig by Sw Rssi \n");
2125 if(dm_digtable.dig_algorithm_switch) // if swithed algorithm, we have to disable FW Dig.
2126 fw_dig = 0;
2127 if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled
2128 {// FW DIG Off
2129 for(i=0; i<3; i++)
2130 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2131 fw_dig++;
2132 dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off.
2133 }
2134
2135 if(priv->ieee80211->state == IEEE80211_LINKED)
2136 dm_digtable.cur_connect_state = DIG_CONNECT;
2137 else
2138 dm_digtable.cur_connect_state = DIG_DISCONNECT;
2139
2140 //DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n",
2141 //DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);
2142
2143 if(dm_digtable.dbg_mode == DM_DBG_OFF)
2144 dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
2145 //DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val);
2146 dm_initial_gain(dev);
2147 dm_pd_th(dev);
2148 dm_cs_ratio(dev);
2149 if(dm_digtable.dig_algorithm_switch)
2150 dm_digtable.dig_algorithm_switch = 0;
2151 dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
2152
2153 } /* dm_CtrlInitGainByRssi */
2154
2155 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
2156 struct net_device *dev)
2157 {
2158 struct r8192_priv *priv = ieee80211_priv(dev);
2159 static u32 reset_cnt = 0;
2160 u8 i;
2161
2162 if (dm_digtable.dig_enable_flag == false)
2163 return;
2164
2165 if(dm_digtable.dig_algorithm_switch)
2166 {
2167 dm_digtable.dig_state = DM_STA_DIG_MAX;
2168 // Fw DIG On.
2169 for(i=0; i<3; i++)
2170 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2171 dm_digtable.dig_algorithm_switch = 0;
2172 }
2173
2174 if (priv->ieee80211->state != IEEE80211_LINKED)
2175 return;
2176
2177 // For smooth, we can not change DIG state.
2178 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
2179 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
2180 {
2181 return;
2182 }
2183 //DbgPrint("Dig by Fw False Alarm\n");
2184 //if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)
2185 /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
2186 pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
2187 DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
2188 /* 1. When RSSI decrease, We have to judge if it is smaller than a treshold
2189 and then execute below step. */
2190 if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh))
2191 {
2192 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
2193 will be reset to init value. We must prevent the condition. */
2194 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
2195 (priv->reset_count == reset_cnt))
2196 {
2197 return;
2198 }
2199 else
2200 {
2201 reset_cnt = priv->reset_count;
2202 }
2203
2204 // If DIG is off, DIG high power state must reset.
2205 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
2206 dm_digtable.dig_state = DM_STA_DIG_OFF;
2207
2208 // 1.1 DIG Off.
2209 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2210
2211 // 1.2 Set initial gain.
2212 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
2213 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2214 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
2215 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
2216
2217 // 1.3 Lower PD_TH for OFDM.
2218 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2219 {
2220 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2221 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2222 #ifdef RTL8190P
2223 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2224 #else
2225 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2226 #endif
2227 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2228 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2229 */
2230 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2231
2232
2233 //else
2234 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2235 }
2236 else
2237 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2238
2239 // 1.4 Lower CS ratio for CCK.
2240 write_nic_byte(dev, 0xa0a, 0x08);
2241
2242 // 1.5 Higher EDCCA.
2243 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
2244 return;
2245
2246 }
2247
2248 /* 2. When RSSI increase, We have to judge if it is larger than a treshold
2249 and then execute below step. */
2250 if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) )
2251 {
2252 u8 reset_flag = 0;
2253
2254 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
2255 (priv->reset_count == reset_cnt))
2256 {
2257 dm_ctrl_initgain_byrssi_highpwr(dev);
2258 return;
2259 }
2260 else
2261 {
2262 if (priv->reset_count != reset_cnt)
2263 reset_flag = 1;
2264
2265 reset_cnt = priv->reset_count;
2266 }
2267
2268 dm_digtable.dig_state = DM_STA_DIG_ON;
2269 //DbgPrint("DIG ON\n\r");
2270
2271 // 2.1 Set initial gain.
2272 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
2273 if (reset_flag == 1)
2274 {
2275 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
2276 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2277 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
2278 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
2279 }
2280 else
2281 {
2282 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
2283 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2284 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
2285 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
2286 }
2287
2288 // 2.2 Higher PD_TH for OFDM.
2289 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2290 {
2291 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2292 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2293 #ifdef RTL8190P
2294 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2295 #else
2296 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2297 #endif
2298 /*
2299 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2300 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2301 */
2302 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2303
2304 //else
2305 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
2306 }
2307 else
2308 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2309
2310 // 2.3 Higher CS ratio for CCK.
2311 write_nic_byte(dev, 0xa0a, 0xcd);
2312
2313 // 2.4 Lower EDCCA.
2314 /* 2008/01/11 MH 90/92 series are the same. */
2315 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
2316
2317 // 2.5 DIG On.
2318 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2319
2320 }
2321
2322 dm_ctrl_initgain_byrssi_highpwr(dev);
2323
2324 } /* dm_CtrlInitGainByRssi */
2325
2326
2327 /*-----------------------------------------------------------------------------
2328 * Function: dm_ctrl_initgain_byrssi_highpwr()
2329 *
2330 * Overview:
2331 *
2332 * Input: NONE
2333 *
2334 * Output: NONE
2335 *
2336 * Return: NONE
2337 *
2338 * Revised History:
2339 * When Who Remark
2340 * 05/28/2008 amy Create Version 0 porting from windows code.
2341 *
2342 *---------------------------------------------------------------------------*/
2343 static void dm_ctrl_initgain_byrssi_highpwr(
2344 struct net_device * dev)
2345 {
2346 struct r8192_priv *priv = ieee80211_priv(dev);
2347 static u32 reset_cnt_highpwr = 0;
2348
2349 // For smooth, we can not change high power DIG state in the range.
2350 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
2351 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
2352 {
2353 return;
2354 }
2355
2356 /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
2357 it is larger than a treshold and then execute below step. */
2358 // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
2359 if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh)
2360 {
2361 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
2362 (priv->reset_count == reset_cnt_highpwr))
2363 return;
2364 else
2365 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
2366
2367 // 3.1 Higher PD_TH for OFDM for high power state.
2368 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2369 {
2370 #ifdef RTL8190P
2371 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2372 #else
2373 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2374 #endif
2375
2376 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2377 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2378 */
2379
2380 }
2381 else
2382 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2383 }
2384 else
2385 {
2386 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF&&
2387 (priv->reset_count == reset_cnt_highpwr))
2388 return;
2389 else
2390 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
2391
2392 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
2393 priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh)
2394 {
2395 // 3.2 Recover PD_TH for OFDM for normal power region.
2396 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2397 {
2398 #ifdef RTL8190P
2399 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2400 #else
2401 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2402 #endif
2403 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2404 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2405 */
2406
2407 }
2408 else
2409 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2410 }
2411 }
2412
2413 reset_cnt_highpwr = priv->reset_count;
2414
2415 } /* dm_CtrlInitGainByRssiHighPwr */
2416
2417
2418 static void dm_initial_gain(
2419 struct net_device * dev)
2420 {
2421 struct r8192_priv *priv = ieee80211_priv(dev);
2422 u8 initial_gain=0;
2423 static u8 initialized=0, force_write=0;
2424 static u32 reset_cnt=0;
2425
2426 if(dm_digtable.dig_algorithm_switch)
2427 {
2428 initialized = 0;
2429 reset_cnt = 0;
2430 }
2431
2432 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2433 {
2434 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2435 {
2436 if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max)
2437 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max;
2438 else if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
2439 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
2440 else
2441 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
2442 }
2443 else //current state is disconnected
2444 {
2445 if(dm_digtable.cur_ig_value == 0)
2446 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2447 else
2448 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
2449 }
2450 }
2451 else // disconnected -> connected or connected -> disconnected
2452 {
2453 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2454 dm_digtable.pre_ig_value = 0;
2455 }
2456 //DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);
2457
2458 // if silent reset happened, we should rewrite the values back
2459 if(priv->reset_count != reset_cnt)
2460 {
2461 force_write = 1;
2462 reset_cnt = priv->reset_count;
2463 }
2464
2465 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))
2466 force_write = 1;
2467
2468 {
2469 if((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
2470 || !initialized || force_write)
2471 {
2472 initial_gain = (u8)dm_digtable.cur_ig_value;
2473 //DbgPrint("Write initial gain = 0x%x\n", initial_gain);
2474 // Set initial gain.
2475 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
2476 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
2477 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
2478 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
2479 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
2480 initialized = 1;
2481 force_write = 0;
2482 }
2483 }
2484 }
2485
2486 static void dm_pd_th(
2487 struct net_device * dev)
2488 {
2489 struct r8192_priv *priv = ieee80211_priv(dev);
2490 static u8 initialized=0, force_write=0;
2491 static u32 reset_cnt = 0;
2492
2493 if(dm_digtable.dig_algorithm_switch)
2494 {
2495 initialized = 0;
2496 reset_cnt = 0;
2497 }
2498
2499 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2500 {
2501 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2502 {
2503 if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
2504 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
2505 else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2506 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2507 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
2508 (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
2509 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
2510 else
2511 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
2512 }
2513 else
2514 {
2515 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2516 }
2517 }
2518 else // disconnected -> connected or connected -> disconnected
2519 {
2520 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2521 }
2522
2523 // if silent reset happened, we should rewrite the values back
2524 if(priv->reset_count != reset_cnt)
2525 {
2526 force_write = 1;
2527 reset_cnt = priv->reset_count;
2528 }
2529
2530 {
2531 if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
2532 (initialized<=3) || force_write)
2533 {
2534 //DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);
2535 if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER)
2536 {
2537 // Lower PD_TH for OFDM.
2538 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2539 {
2540 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2541 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2542 #ifdef RTL8190P
2543 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2544 #else
2545 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2546 #endif
2547 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2548 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2549 */
2550 }
2551 else
2552 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2553 }
2554 else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)
2555 {
2556 // Higher PD_TH for OFDM.
2557 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2558 {
2559 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2560 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2561 #ifdef RTL8190P
2562 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2563 #else
2564 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2565 #endif
2566 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2567 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2568 */
2569 }
2570 else
2571 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2572 }
2573 else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)
2574 {
2575 // Higher PD_TH for OFDM for high power state.
2576 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2577 {
2578 #ifdef RTL8190P
2579 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2580 #else
2581 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2582 #endif
2583 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2584 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2585 */
2586 }
2587 else
2588 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2589 }
2590 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2591 if(initialized <= 3)
2592 initialized++;
2593 force_write = 0;
2594 }
2595 }
2596 }
2597
2598 static void dm_cs_ratio(
2599 struct net_device * dev)
2600 {
2601 struct r8192_priv *priv = ieee80211_priv(dev);
2602 static u8 initialized=0,force_write=0;
2603 static u32 reset_cnt = 0;
2604
2605 if(dm_digtable.dig_algorithm_switch)
2606 {
2607 initialized = 0;
2608 reset_cnt = 0;
2609 }
2610
2611 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2612 {
2613 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2614 {
2615 if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2616 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2617 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) )
2618 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2619 else
2620 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2621 }
2622 else
2623 {
2624 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2625 }
2626 }
2627 else // disconnected -> connected or connected -> disconnected
2628 {
2629 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2630 }
2631
2632 // if silent reset happened, we should rewrite the values back
2633 if(priv->reset_count != reset_cnt)
2634 {
2635 force_write = 1;
2636 reset_cnt = priv->reset_count;
2637 }
2638
2639
2640 {
2641 if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2642 !initialized || force_write)
2643 {
2644 //DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);
2645 if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
2646 {
2647 // Lower CS ratio for CCK.
2648 write_nic_byte(dev, 0xa0a, 0x08);
2649 }
2650 else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
2651 {
2652 // Higher CS ratio for CCK.
2653 write_nic_byte(dev, 0xa0a, 0xcd);
2654 }
2655 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2656 initialized = 1;
2657 force_write = 0;
2658 }
2659 }
2660 }
2661
2662 void dm_init_edca_turbo(struct net_device *dev)
2663 {
2664 struct r8192_priv *priv = ieee80211_priv(dev);
2665
2666 priv->bcurrent_turbo_EDCA = false;
2667 priv->ieee80211->bis_any_nonbepkts = false;
2668 priv->bis_cur_rdlstate = false;
2669 } // dm_init_edca_turbo
2670
2671 #if 1
2672 static void dm_check_edca_turbo(
2673 struct net_device * dev)
2674 {
2675 struct r8192_priv *priv = ieee80211_priv(dev);
2676 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2677 //PSTA_QOS pStaQos = pMgntInfo->pStaQos;
2678
2679 // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
2680 static unsigned long lastTxOkCnt = 0;
2681 static unsigned long lastRxOkCnt = 0;
2682 unsigned long curTxOkCnt = 0;
2683 unsigned long curRxOkCnt = 0;
2684
2685 //
2686 // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2687 // should follow the settings from QAP. By Bruce, 2007-12-07.
2688 //
2689 #if 1
2690 if(priv->ieee80211->state != IEEE80211_LINKED)
2691 goto dm_CheckEdcaTurbo_EXIT;
2692 #endif
2693 // We do not turn on EDCA turbo mode for some AP that has IOT issue
2694 if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2695 goto dm_CheckEdcaTurbo_EXIT;
2696
2697 // printk("========>%s():bis_any_nonbepkts is %d\n",__FUNCTION__,priv->bis_any_nonbepkts);
2698 // Check the status for current condition.
2699 if(!priv->ieee80211->bis_any_nonbepkts)
2700 {
2701 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2702 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2703 // For RT-AP, we needs to turn it on when Rx>Tx
2704 if(curRxOkCnt > 4*curTxOkCnt)
2705 {
2706 //printk("%s():curRxOkCnt > 4*curTxOkCnt\n");
2707 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2708 {
2709 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2710 priv->bis_cur_rdlstate = true;
2711 }
2712 }
2713 else
2714 {
2715
2716 //printk("%s():curRxOkCnt < 4*curTxOkCnt\n");
2717 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2718 {
2719 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2720 priv->bis_cur_rdlstate = false;
2721 }
2722
2723 }
2724
2725 priv->bcurrent_turbo_EDCA = true;
2726 }
2727 else
2728 {
2729 //
2730 // Turn Off EDCA turbo here.
2731 // Restore original EDCA according to the declaration of AP.
2732 //
2733 if(priv->bcurrent_turbo_EDCA)
2734 {
2735
2736 {
2737 u8 u1bAIFS;
2738 u32 u4bAcParam;
2739 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2740 u8 mode = priv->ieee80211->mode;
2741
2742 // For Each time updating EDCA parameter, reset EDCA turbo mode status.
2743 dm_init_edca_turbo(dev);
2744 u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
2745 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
2746 (((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)|
2747 (((u32)(qos_parameters->cw_min[0]))<< AC_PARAM_ECW_MIN_OFFSET)|
2748 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
2749 printk("===>u4bAcParam:%x, ", u4bAcParam);
2750 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
2751 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
2752
2753 // Check ACM bit.
2754 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2755 {
2756 // TODO: Modified this part and try to set acm control in only 1 IO processing!!
2757
2758 PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
2759 u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl );
2760 if( pAciAifsn->f.ACM )
2761 { // ACM bit is 1.
2762 AcmCtrl |= AcmHw_BeqEn;
2763 }
2764 else
2765 { // ACM bit is 0.
2766 AcmCtrl &= (~AcmHw_BeqEn);
2767 }
2768
2769 RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ;
2770 write_nic_byte(dev, AcmHwCtrl, AcmCtrl );
2771 }
2772 }
2773 priv->bcurrent_turbo_EDCA = false;
2774 }
2775 }
2776
2777
2778 dm_CheckEdcaTurbo_EXIT:
2779 // Set variables for next time.
2780 priv->ieee80211->bis_any_nonbepkts = false;
2781 lastTxOkCnt = priv->stats.txbytesunicast;
2782 lastRxOkCnt = priv->stats.rxbytesunicast;
2783 } // dm_CheckEdcaTurbo
2784 #endif
2785
2786 static void dm_init_ctstoself(struct net_device * dev)
2787 {
2788 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2789
2790 priv->ieee80211->bCTSToSelfEnable = TRUE;
2791 priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal;
2792 }
2793
2794 static void dm_ctstoself(struct net_device *dev)
2795 {
2796 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2797 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2798 static unsigned long lastTxOkCnt = 0;
2799 static unsigned long lastRxOkCnt = 0;
2800 unsigned long curTxOkCnt = 0;
2801 unsigned long curRxOkCnt = 0;
2802
2803 if(priv->ieee80211->bCTSToSelfEnable != TRUE)
2804 {
2805 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2806 return;
2807 }
2808 /*
2809 1. Uplink
2810 2. Linksys350/Linksys300N
2811 3. <50 disable, >55 enable
2812 */
2813
2814 if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
2815 {
2816 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2817 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2818 if(curRxOkCnt > 4*curTxOkCnt) //downlink, disable CTS to self
2819 {
2820 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2821 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");
2822 }
2823 else //uplink
2824 {
2825 #if 1
2826 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2827 #else
2828 if(priv->undecorated_smoothed_pwdb < priv->ieee80211->CTSToSelfTH) // disable CTS to self
2829 {
2830 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2831 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled\n");
2832 }
2833 else if(priv->undecorated_smoothed_pwdb >= (priv->ieee80211->CTSToSelfTH+5)) // enable CTS to self
2834 {
2835 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2836 //DbgPrint("dm_CTSToSelf() ==> CTS to self enabled\n");
2837 }
2838 #endif
2839 }
2840
2841 lastTxOkCnt = priv->stats.txbytesunicast;
2842 lastRxOkCnt = priv->stats.rxbytesunicast;
2843 }
2844 }
2845
2846
2847
2848 /*-----------------------------------------------------------------------------
2849 * Function: dm_check_rfctrl_gpio()
2850 *
2851 * Overview: Copy 8187B template for 9xseries.
2852 *
2853 * Input: NONE
2854 *
2855 * Output: NONE
2856 *
2857 * Return: NONE
2858 *
2859 * Revised History:
2860 * When Who Remark
2861 * 05/28/2008 amy Create Version 0 porting from windows code.
2862 *
2863 *---------------------------------------------------------------------------*/
2864 #if 1
2865 static void dm_check_rfctrl_gpio(struct net_device * dev)
2866 {
2867 #ifdef RTL8192E
2868 struct r8192_priv *priv = ieee80211_priv(dev);
2869 #endif
2870
2871 // Walk around for DTM test, we will not enable HW - radio on/off because r/w
2872 // page 1 register before Lextra bus is enabled cause system fails when resuming
2873 // from S4. 20080218, Emily
2874
2875 // Stop to execute workitem to prevent S3/S4 bug.
2876 #ifdef RTL8190P
2877 return;
2878 #endif
2879 #ifdef RTL8192U
2880 return;
2881 #endif
2882 #ifdef RTL8192E
2883 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
2884 queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
2885 #else
2886 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
2887 schedule_task(&priv->gpio_change_rf_wq);
2888 #else
2889 queue_work(priv->priv_wq,&priv->gpio_change_rf_wq);
2890 #endif
2891 #endif
2892 #endif
2893
2894 } /* dm_CheckRfCtrlGPIO */
2895
2896 #endif
2897 /*-----------------------------------------------------------------------------
2898 * Function: dm_check_pbc_gpio()
2899 *
2900 * Overview: Check if PBC button is pressed.
2901 *
2902 * Input: NONE
2903 *
2904 * Output: NONE
2905 *
2906 * Return: NONE
2907 *
2908 * Revised History:
2909 * When Who Remark
2910 * 05/28/2008 amy Create Version 0 porting from windows code.
2911 *
2912 *---------------------------------------------------------------------------*/
2913 static void dm_check_pbc_gpio(struct net_device *dev)
2914 {
2915 #ifdef RTL8192U
2916 struct r8192_priv *priv = ieee80211_priv(dev);
2917 u8 tmp1byte;
2918
2919
2920 tmp1byte = read_nic_byte(dev,GPI);
2921 if(tmp1byte == 0xff)
2922 return;
2923
2924 if (tmp1byte&BIT6 || tmp1byte&BIT0)
2925 {
2926 // Here we only set bPbcPressed to TRUE
2927 // After trigger PBC, the variable will be set to FALSE
2928 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
2929 priv->bpbc_pressed = true;
2930 }
2931 #endif
2932
2933 }
2934
2935 #ifdef RTL8192E
2936
2937 /*-----------------------------------------------------------------------------
2938 * Function: dm_GPIOChangeRF
2939 * Overview: PCI will not support workitem call back HW radio on-off control.
2940 *
2941 * Input: NONE
2942 *
2943 * Output: NONE
2944 *
2945 * Return: NONE
2946 *
2947 * Revised History:
2948 * When Who Remark
2949 * 02/21/2008 MHC Create Version 0.
2950 *
2951 *---------------------------------------------------------------------------*/
2952 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
2953 void dm_gpio_change_rf_callback(struct work_struct *work)
2954 {
2955 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
2956 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,gpio_change_rf_wq);
2957 struct net_device *dev = priv->ieee80211->dev;
2958 #else
2959 extern void dm_gpio_change_rf_callback(struct net_device *dev)
2960 {
2961 struct r8192_priv *priv = ieee80211_priv(dev);
2962 #endif
2963 u8 tmp1byte;
2964 RT_RF_POWER_STATE eRfPowerStateToSet;
2965 bool bActuallySet = false;
2966
2967 bActuallySet=false;
2968
2969 if(!priv->up)
2970 {
2971 RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n");
2972 }
2973 else
2974 {
2975 // 0x108 GPIO input register is read only
2976 //set 0x108 B1= 1: RF-ON; 0: RF-OFF.
2977 tmp1byte = read_nic_byte(dev,GPI);
2978
2979 eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;
2980
2981 if( (priv->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn))
2982 {
2983 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio ON\n");
2984
2985 priv->bHwRadioOff = false;
2986 bActuallySet = true;
2987 }
2988 else if ( (priv->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff))
2989 {
2990 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio OFF\n");
2991 priv->bHwRadioOff = true;
2992 bActuallySet = true;
2993 }
2994
2995 if(bActuallySet)
2996 {
2997 priv->bHwRfOffAction = 1;
2998 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
2999 //DrvIFIndicateCurrentPhyStatus(pAdapter);
3000
3001 }
3002 else
3003 {
3004 msleep(2000);
3005 }
3006
3007 }
3008
3009 } /* dm_GPIOChangeRF */
3010
3011 #endif
3012 /*-----------------------------------------------------------------------------
3013 * Function: DM_RFPathCheckWorkItemCallBack()
3014 *
3015 * Overview: Check if Current RF RX path is enabled
3016 *
3017 * Input: NONE
3018 *
3019 * Output: NONE
3020 *
3021 * Return: NONE
3022 *
3023 * Revised History:
3024 * When Who Remark
3025 * 01/30/2008 MHC Create Version 0.
3026 *
3027 *---------------------------------------------------------------------------*/
3028 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
3029 void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
3030 {
3031 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3032 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq);
3033 struct net_device *dev =priv->ieee80211->dev;
3034 #else
3035 extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev)
3036 {
3037 struct r8192_priv *priv = ieee80211_priv(dev);
3038 #endif
3039 //bool bactually_set = false;
3040 u8 rfpath = 0, i;
3041
3042
3043 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
3044 always be the same. We only read 0xc04 now. */
3045 rfpath = read_nic_byte(dev, 0xc04);
3046
3047 // Check Bit 0-3, it means if RF A-D is enabled.
3048 for (i = 0; i < RF90_PATH_MAX; i++)
3049 {
3050 if (rfpath & (0x01<<i))
3051 priv->brfpath_rxenable[i] = 1;
3052 else
3053 priv->brfpath_rxenable[i] = 0;
3054 }
3055 if(!DM_RxPathSelTable.Enable)
3056 return;
3057
3058 dm_rxpath_sel_byrssi(dev);
3059 } /* DM_RFPathCheckWorkItemCallBack */
3060
3061 static void dm_init_rxpath_selection(struct net_device * dev)
3062 {
3063 u8 i;
3064 struct r8192_priv *priv = ieee80211_priv(dev);
3065 DM_RxPathSelTable.Enable = 1; //default enabled
3066 DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;
3067 DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;
3068 if(priv->CustomerID == RT_CID_819x_Netcore)
3069 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
3070 else
3071 DM_RxPathSelTable.cck_method = CCK_Rx_Version_1;
3072 DM_RxPathSelTable.DbgMode = DM_DBG_OFF;
3073 DM_RxPathSelTable.disabledRF = 0;
3074 for(i=0; i<4; i++)
3075 {
3076 DM_RxPathSelTable.rf_rssi[i] = 50;
3077 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
3078 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
3079 }
3080 }
3081
3082 static void dm_rxpath_sel_byrssi(struct net_device * dev)
3083 {
3084 struct r8192_priv *priv = ieee80211_priv(dev);
3085 u8 i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0;
3086 u8 tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0;
3087 u8 cck_default_Rx=0x2; //RF-C
3088 u8 cck_optional_Rx=0x3;//RF-D
3089 long tmp_cck_max_pwdb=0, tmp_cck_min_pwdb=0, tmp_cck_sec_pwdb=0;
3090 u8 cck_rx_ver2_max_index=0, cck_rx_ver2_min_index=0, cck_rx_ver2_sec_index=0;
3091 u8 cur_rf_rssi;
3092 long cur_cck_pwdb;
3093 static u8 disabled_rf_cnt=0, cck_Rx_Path_initialized=0;
3094 u8 update_cck_rx_path;
3095
3096 if(priv->rf_type != RF_2T4R)
3097 return;
3098
3099 if(!cck_Rx_Path_initialized)
3100 {
3101 DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);
3102 cck_Rx_Path_initialized = 1;
3103 }
3104
3105 DM_RxPathSelTable.disabledRF = 0xf;
3106 DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04));
3107
3108 if(priv->ieee80211->mode == WIRELESS_MODE_B)
3109 {
3110 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; //pure B mode, fixed cck version2
3111 //DbgPrint("Pure B mode, use cck rx version2 \n");
3112 }
3113
3114 //decide max/sec/min rssi index
3115 for (i=0; i<RF90_PATH_MAX; i++)
3116 {
3117 if(!DM_RxPathSelTable.DbgMode)
3118 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
3119
3120 if(priv->brfpath_rxenable[i])
3121 {
3122 rf_num++;
3123 cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
3124
3125 if(rf_num == 1) // find first enabled rf path and the rssi values
3126 { //initialize, set all rssi index to the same one
3127 max_rssi_index = min_rssi_index = sec_rssi_index = i;
3128 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
3129 }
3130 else if(rf_num == 2)
3131 { // we pick up the max index first, and let sec and min to be the same one
3132 if(cur_rf_rssi >= tmp_max_rssi)
3133 {
3134 tmp_max_rssi = cur_rf_rssi;
3135 max_rssi_index = i;
3136 }
3137 else
3138 {
3139 tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
3140 sec_rssi_index = min_rssi_index = i;
3141 }
3142 }
3143 else
3144 {
3145 if(cur_rf_rssi > tmp_max_rssi)
3146 {
3147 tmp_sec_rssi = tmp_max_rssi;
3148 sec_rssi_index = max_rssi_index;
3149 tmp_max_rssi = cur_rf_rssi;
3150 max_rssi_index = i;
3151 }
3152 else if(cur_rf_rssi == tmp_max_rssi)
3153 { // let sec and min point to the different index
3154 tmp_sec_rssi = cur_rf_rssi;
3155 sec_rssi_index = i;
3156 }
3157 else if((cur_rf_rssi < tmp_max_rssi) &&(cur_rf_rssi > tmp_sec_rssi))
3158 {
3159 tmp_sec_rssi = cur_rf_rssi;
3160 sec_rssi_index = i;
3161 }
3162 else if(cur_rf_rssi == tmp_sec_rssi)
3163 {
3164 if(tmp_sec_rssi == tmp_min_rssi)
3165 { // let sec and min point to the different index
3166 tmp_sec_rssi = cur_rf_rssi;
3167 sec_rssi_index = i;
3168 }
3169 else
3170 {
3171 // This case we don't need to set any index
3172 }
3173 }
3174 else if((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi))
3175 {
3176 // This case we don't need to set any index
3177 }
3178 else if(cur_rf_rssi == tmp_min_rssi)
3179 {
3180 if(tmp_sec_rssi == tmp_min_rssi)
3181 { // let sec and min point to the different index
3182 tmp_min_rssi = cur_rf_rssi;
3183 min_rssi_index = i;
3184 }
3185 else
3186 {
3187 // This case we don't need to set any index
3188 }
3189 }
3190 else if(cur_rf_rssi < tmp_min_rssi)
3191 {
3192 tmp_min_rssi = cur_rf_rssi;
3193 min_rssi_index = i;
3194 }
3195 }
3196 }
3197 }
3198
3199 rf_num = 0;
3200 // decide max/sec/min cck pwdb index
3201 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
3202 {
3203 for (i=0; i<RF90_PATH_MAX; i++)
3204 {
3205 if(priv->brfpath_rxenable[i])
3206 {
3207 rf_num++;
3208 cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i];
3209
3210 if(rf_num == 1) // find first enabled rf path and the rssi values
3211 { //initialize, set all rssi index to the same one
3212 cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
3213 tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
3214 }
3215 else if(rf_num == 2)
3216 { // we pick up the max index first, and let sec and min to be the same one
3217 if(cur_cck_pwdb >= tmp_cck_max_pwdb)
3218 {
3219 tmp_cck_max_pwdb = cur_cck_pwdb;
3220 cck_rx_ver2_max_index = i;
3221 }
3222 else
3223 {
3224 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
3225 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
3226 }
3227 }
3228 else
3229 {
3230 if(cur_cck_pwdb > tmp_cck_max_pwdb)
3231 {
3232 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
3233 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
3234 tmp_cck_max_pwdb = cur_cck_pwdb;
3235 cck_rx_ver2_max_index = i;
3236 }
3237 else if(cur_cck_pwdb == tmp_cck_max_pwdb)
3238 { // let sec and min point to the different index
3239 tmp_cck_sec_pwdb = cur_cck_pwdb;
3240 cck_rx_ver2_sec_index = i;
3241 }
3242 else if((cur_cck_pwdb < tmp_cck_max_pwdb) &&(cur_cck_pwdb > tmp_cck_sec_pwdb))
3243 {
3244 tmp_cck_sec_pwdb = cur_cck_pwdb;
3245 cck_rx_ver2_sec_index = i;
3246 }
3247 else if(cur_cck_pwdb == tmp_cck_sec_pwdb)
3248 {
3249 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
3250 { // let sec and min point to the different index
3251 tmp_cck_sec_pwdb = cur_cck_pwdb;
3252 cck_rx_ver2_sec_index = i;
3253 }
3254 else
3255 {
3256 // This case we don't need to set any index
3257 }
3258 }
3259 else if((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb))
3260 {
3261 // This case we don't need to set any index
3262 }
3263 else if(cur_cck_pwdb == tmp_cck_min_pwdb)
3264 {
3265 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
3266 { // let sec and min point to the different index
3267 tmp_cck_min_pwdb = cur_cck_pwdb;
3268 cck_rx_ver2_min_index = i;
3269 }
3270 else
3271 {
3272 // This case we don't need to set any index
3273 }
3274 }
3275 else if(cur_cck_pwdb < tmp_cck_min_pwdb)
3276 {
3277 tmp_cck_min_pwdb = cur_cck_pwdb;
3278 cck_rx_ver2_min_index = i;
3279 }
3280 }
3281
3282 }
3283 }
3284 }
3285
3286
3287 // Set CCK Rx path
3288 // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
3289 update_cck_rx_path = 0;
3290 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
3291 {
3292 cck_default_Rx = cck_rx_ver2_max_index;
3293 cck_optional_Rx = cck_rx_ver2_sec_index;
3294 if(tmp_cck_max_pwdb != -64)
3295 update_cck_rx_path = 1;
3296 }
3297
3298 if(tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2)
3299 {
3300 if((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH)
3301 {
3302 //record the enabled rssi threshold
3303 DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
3304 //disable the BB Rx path, OFDM
3305 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0]
3306 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0]
3307 disabled_rf_cnt++;
3308 }
3309 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1)
3310 {
3311 cck_default_Rx = max_rssi_index;
3312 cck_optional_Rx = sec_rssi_index;
3313 if(tmp_max_rssi)
3314 update_cck_rx_path = 1;
3315 }
3316 }
3317
3318 if(update_cck_rx_path)
3319 {
3320 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
3321 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);
3322 }
3323
3324 if(DM_RxPathSelTable.disabledRF)
3325 {
3326 for(i=0; i<4; i++)
3327 {
3328 if((DM_RxPathSelTable.disabledRF>>i) & 0x1) //disabled rf
3329 {
3330 if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i])
3331 {
3332 //enable the BB Rx path
3333 //DbgPrint("RF-%d is enabled. \n", 0x1<<i);
3334 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0]
3335 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0]
3336 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
3337 disabled_rf_cnt--;
3338 }
3339 }
3340 }
3341 }
3342 }
3343
3344 /*-----------------------------------------------------------------------------
3345 * Function: dm_check_rx_path_selection()
3346 *
3347 * Overview: Call a workitem to check current RXRF path and Rx Path selection by RSSI.
3348 *
3349 * Input: NONE
3350 *
3351 * Output: NONE
3352 *
3353 * Return: NONE
3354 *
3355 * Revised History:
3356 * When Who Remark
3357 * 05/28/2008 amy Create Version 0 porting from windows code.
3358 *
3359 *---------------------------------------------------------------------------*/
3360 static void dm_check_rx_path_selection(struct net_device *dev)
3361 {
3362 struct r8192_priv *priv = ieee80211_priv(dev);
3363 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3364 queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0);
3365 #else
3366 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3367 schedule_task(&priv->rfpath_check_wq);
3368 #else
3369 queue_work(priv->priv_wq,&priv->rfpath_check_wq);
3370 #endif
3371 #endif
3372 } /* dm_CheckRxRFPath */
3373
3374
3375 static void dm_init_fsync (struct net_device *dev)
3376 {
3377 struct r8192_priv *priv = ieee80211_priv(dev);
3378
3379 priv->ieee80211->fsync_time_interval = 500;
3380 priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
3381 priv->ieee80211->fsync_rssi_threshold = 30;
3382 #ifdef RTL8190P
3383 priv->ieee80211->bfsync_enable = true;
3384 #else
3385 priv->ieee80211->bfsync_enable = false;
3386 #endif
3387 priv->ieee80211->fsync_multiple_timeinterval = 3;
3388 priv->ieee80211->fsync_firstdiff_ratethreshold= 100;
3389 priv->ieee80211->fsync_seconddiff_ratethreshold= 200;
3390 priv->ieee80211->fsync_state = Default_Fsync;
3391 priv->framesyncMonitor = 1; // current default 0xc38 monitor on
3392
3393 init_timer(&priv->fsync_timer);
3394 priv->fsync_timer.data = (unsigned long)dev;
3395 priv->fsync_timer.function = dm_fsync_timer_callback;
3396 }
3397
3398
3399 static void dm_deInit_fsync(struct net_device *dev)
3400 {
3401 struct r8192_priv *priv = ieee80211_priv(dev);
3402 del_timer_sync(&priv->fsync_timer);
3403 }
3404
3405 void dm_fsync_timer_callback(unsigned long data)
3406 {
3407 struct net_device *dev = (struct net_device *)data;
3408 struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
3409 u32 rate_index, rate_count = 0, rate_count_diff=0;
3410 bool bSwitchFromCountDiff = false;
3411 bool bDoubleTimeInterval = false;
3412
3413 if( priv->ieee80211->state == IEEE80211_LINKED &&
3414 priv->ieee80211->bfsync_enable &&
3415 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
3416 {
3417 // Count rate 54, MCS [7], [12, 13, 14, 15]
3418 u32 rate_bitmap;
3419 for(rate_index = 0; rate_index <= 27; rate_index++)
3420 {
3421 rate_bitmap = 1 << rate_index;
3422 if(priv->ieee80211->fsync_rate_bitmap & rate_bitmap)
3423 rate_count+= priv->stats.received_rate_histogram[1][rate_index];
3424 }
3425
3426 if(rate_count < priv->rate_record)
3427 rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
3428 else
3429 rate_count_diff = rate_count - priv->rate_record;
3430 if(rate_count_diff < priv->rateCountDiffRecord)
3431 {
3432
3433 u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
3434 // Contiune count
3435 if(DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
3436 priv->ContiuneDiffCount++;
3437 else
3438 priv->ContiuneDiffCount = 0;
3439
3440 // Contiune count over
3441 if(priv->ContiuneDiffCount >=2)
3442 {
3443 bSwitchFromCountDiff = true;
3444 priv->ContiuneDiffCount = 0;
3445 }
3446 }
3447 else
3448 {
3449 // Stop contiune count
3450 priv->ContiuneDiffCount = 0;
3451 }
3452
3453 //If Count diff <= FsyncRateCountThreshold
3454 if(rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold)
3455 {
3456 bSwitchFromCountDiff = true;
3457 priv->ContiuneDiffCount = 0;
3458 }
3459 priv->rate_record = rate_count;
3460 priv->rateCountDiffRecord = rate_count_diff;
3461 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
3462 // if we never receive those mcs rate and rssi > 30 % then switch fsyn
3463 if(priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff)
3464 {
3465 bDoubleTimeInterval = true;
3466 priv->bswitch_fsync = !priv->bswitch_fsync;
3467 if(priv->bswitch_fsync)
3468 {
3469 #ifdef RTL8190P
3470 write_nic_byte(dev,0xC36, 0x00);
3471 #else
3472 write_nic_byte(dev,0xC36, 0x1c);
3473 #endif
3474 write_nic_byte(dev, 0xC3e, 0x90);
3475 }
3476 else
3477 {
3478 #ifdef RTL8190P
3479 write_nic_byte(dev, 0xC36, 0x40);
3480 #else
3481 write_nic_byte(dev, 0xC36, 0x5c);
3482 #endif
3483 write_nic_byte(dev, 0xC3e, 0x96);
3484 }
3485 }
3486 else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)
3487 {
3488 if(priv->bswitch_fsync)
3489 {
3490 priv->bswitch_fsync = false;
3491 #ifdef RTL8190P
3492 write_nic_byte(dev, 0xC36, 0x40);
3493 #else
3494 write_nic_byte(dev, 0xC36, 0x5c);
3495 #endif
3496 write_nic_byte(dev, 0xC3e, 0x96);
3497 }
3498 }
3499 if(bDoubleTimeInterval){
3500 if(timer_pending(&priv->fsync_timer))
3501 del_timer_sync(&priv->fsync_timer);
3502 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
3503 add_timer(&priv->fsync_timer);
3504 }
3505 else{
3506 if(timer_pending(&priv->fsync_timer))
3507 del_timer_sync(&priv->fsync_timer);
3508 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
3509 add_timer(&priv->fsync_timer);
3510 }
3511 }
3512 else
3513 {
3514 // Let Register return to default value;
3515 if(priv->bswitch_fsync)
3516 {
3517 priv->bswitch_fsync = false;
3518 #ifdef RTL8190P
3519 write_nic_byte(dev, 0xC36, 0x40);
3520 #else
3521 write_nic_byte(dev, 0xC36, 0x5c);
3522 #endif
3523 write_nic_byte(dev, 0xC3e, 0x96);
3524 }
3525 priv->ContiuneDiffCount = 0;
3526 #ifdef RTL8190P
3527 write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd);
3528 #else
3529 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3530 #endif
3531 }
3532 RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
3533 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
3534 }
3535
3536 static void dm_StartHWFsync(struct net_device *dev)
3537 {
3538 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
3539 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
3540 write_nic_byte(dev, 0xc3b, 0x41);
3541 }
3542
3543 static void dm_EndSWFsync(struct net_device *dev)
3544 {
3545 struct r8192_priv *priv = ieee80211_priv(dev);
3546
3547 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
3548 del_timer_sync(&(priv->fsync_timer));
3549
3550 // Let Register return to default value;
3551 if(priv->bswitch_fsync)
3552 {
3553 priv->bswitch_fsync = false;
3554
3555 #ifdef RTL8190P
3556 write_nic_byte(dev, 0xC36, 0x40);
3557 #else
3558 write_nic_byte(dev, 0xC36, 0x5c);
3559 #endif
3560
3561 write_nic_byte(dev, 0xC3e, 0x96);
3562 }
3563
3564 priv->ContiuneDiffCount = 0;
3565 #ifndef RTL8190P
3566 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3567 #endif
3568
3569 }
3570
3571 static void dm_StartSWFsync(struct net_device *dev)
3572 {
3573 struct r8192_priv *priv = ieee80211_priv(dev);
3574 u32 rateIndex;
3575 u32 rateBitmap;
3576
3577 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
3578 // Initial rate record to zero, start to record.
3579 priv->rate_record = 0;
3580 // Initial contiune diff count to zero, start to record.
3581 priv->ContiuneDiffCount = 0;
3582 priv->rateCountDiffRecord = 0;
3583 priv->bswitch_fsync = false;
3584
3585 if(priv->ieee80211->mode == WIRELESS_MODE_N_24G)
3586 {
3587 priv->ieee80211->fsync_firstdiff_ratethreshold= 600;
3588 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
3589 }
3590 else
3591 {
3592 priv->ieee80211->fsync_firstdiff_ratethreshold= 200;
3593 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
3594 }
3595 for(rateIndex = 0; rateIndex <= 27; rateIndex++)
3596 {
3597 rateBitmap = 1 << rateIndex;
3598 if(priv->ieee80211->fsync_rate_bitmap & rateBitmap)
3599 priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
3600 }
3601 if(timer_pending(&priv->fsync_timer))
3602 del_timer_sync(&priv->fsync_timer);
3603 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
3604 add_timer(&priv->fsync_timer);
3605
3606 #ifndef RTL8190P
3607 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
3608 #endif
3609
3610 }
3611
3612 static void dm_EndHWFsync(struct net_device *dev)
3613 {
3614 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
3615 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3616 write_nic_byte(dev, 0xc3b, 0x49);
3617
3618 }
3619
3620 void dm_check_fsync(struct net_device *dev)
3621 {
3622 #define RegC38_Default 0
3623 #define RegC38_NonFsync_Other_AP 1
3624 #define RegC38_Fsync_AP_BCM 2
3625 struct r8192_priv *priv = ieee80211_priv(dev);
3626 //u32 framesyncC34;
3627 static u8 reg_c38_State=RegC38_Default;
3628 static u32 reset_cnt=0;
3629
3630 RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
3631 RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
3632
3633 if( priv->ieee80211->state == IEEE80211_LINKED &&
3634 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
3635 {
3636 if(priv->ieee80211->bfsync_enable == 0)
3637 {
3638 switch(priv->ieee80211->fsync_state)
3639 {
3640 case Default_Fsync:
3641 dm_StartHWFsync(dev);
3642 priv->ieee80211->fsync_state = HW_Fsync;
3643 break;
3644 case SW_Fsync:
3645 dm_EndSWFsync(dev);
3646 dm_StartHWFsync(dev);
3647 priv->ieee80211->fsync_state = HW_Fsync;
3648 break;
3649 case HW_Fsync:
3650 default:
3651 break;
3652 }
3653 }
3654 else
3655 {
3656 switch(priv->ieee80211->fsync_state)
3657 {
3658 case Default_Fsync:
3659 dm_StartSWFsync(dev);
3660 priv->ieee80211->fsync_state = SW_Fsync;
3661 break;
3662 case HW_Fsync:
3663 dm_EndHWFsync(dev);
3664 dm_StartSWFsync(dev);
3665 priv->ieee80211->fsync_state = SW_Fsync;
3666 break;
3667 case SW_Fsync:
3668 default:
3669 break;
3670
3671 }
3672 }
3673 if(priv->framesyncMonitor)
3674 {
3675 if(reg_c38_State != RegC38_Fsync_AP_BCM)
3676 { //For broadcom AP we write different default value
3677 #ifdef RTL8190P
3678 write_nic_byte(dev, rOFDM0_RxDetector3, 0x15);
3679 #else
3680 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
3681 #endif
3682
3683 reg_c38_State = RegC38_Fsync_AP_BCM;
3684 }
3685 }
3686 }
3687 else
3688 {
3689 switch(priv->ieee80211->fsync_state)
3690 {
3691 case HW_Fsync:
3692 dm_EndHWFsync(dev);
3693 priv->ieee80211->fsync_state = Default_Fsync;
3694 break;
3695 case SW_Fsync:
3696 dm_EndSWFsync(dev);
3697 priv->ieee80211->fsync_state = Default_Fsync;
3698 break;
3699 case Default_Fsync:
3700 default:
3701 break;
3702 }
3703
3704 if(priv->framesyncMonitor)
3705 {
3706 if(priv->ieee80211->state == IEEE80211_LINKED)
3707 {
3708 if(priv->undecorated_smoothed_pwdb <= RegC38_TH)
3709 {
3710 if(reg_c38_State != RegC38_NonFsync_Other_AP)
3711 {
3712 #ifdef RTL8190P
3713 write_nic_byte(dev, rOFDM0_RxDetector3, 0x10);
3714 #else
3715 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
3716 #endif
3717
3718 reg_c38_State = RegC38_NonFsync_Other_AP;
3719 #if 0//cosa
3720 if (Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
3721 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x10);
3722 else
3723 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x90);
3724 #endif
3725 }
3726 }
3727 else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5))
3728 {
3729 if(reg_c38_State)
3730 {
3731 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3732 reg_c38_State = RegC38_Default;
3733 //DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync);
3734 }
3735 }
3736 }
3737 else
3738 {
3739 if(reg_c38_State)
3740 {
3741 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3742 reg_c38_State = RegC38_Default;
3743 //DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync);
3744 }
3745 }
3746 }
3747 }
3748 if(priv->framesyncMonitor)
3749 {
3750 if(priv->reset_count != reset_cnt)
3751 { //After silent reset, the reg_c38_State will be returned to default value
3752 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3753 reg_c38_State = RegC38_Default;
3754 reset_cnt = priv->reset_count;
3755 //DbgPrint("reg_c38_State = 0 for silent reset. \n");
3756 }
3757 }
3758 else
3759 {
3760 if(reg_c38_State)
3761 {
3762 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3763 reg_c38_State = RegC38_Default;
3764 //DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync);
3765 }
3766 }
3767 }
3768
3769
3770 /*-----------------------------------------------------------------------------
3771 * Function: dm_shadow_init()
3772 *
3773 * Overview: Store all NIC MAC/BB register content.
3774 *
3775 * Input: NONE
3776 *
3777 * Output: NONE
3778 *
3779 * Return: NONE
3780 *
3781 * Revised History:
3782 * When Who Remark
3783 * 05/29/2008 amy Create Version 0 porting from windows code.
3784 *
3785 *---------------------------------------------------------------------------*/
3786 void dm_shadow_init(struct net_device *dev)
3787 {
3788 u8 page;
3789 u16 offset;
3790
3791 for (page = 0; page < 5; page++)
3792 for (offset = 0; offset < 256; offset++)
3793 {
3794 dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
3795 //DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);
3796 }
3797
3798 for (page = 8; page < 11; page++)
3799 for (offset = 0; offset < 256; offset++)
3800 dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
3801
3802 for (page = 12; page < 15; page++)
3803 for (offset = 0; offset < 256; offset++)
3804 dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
3805
3806 } /* dm_shadow_init */
3807
3808 /*---------------------------Define function prototype------------------------*/
3809 /*-----------------------------------------------------------------------------
3810 * Function: DM_DynamicTxPower()
3811 *
3812 * Overview: Detect Signal strength to control TX Registry
3813 Tx Power Control For Near/Far Range
3814 *
3815 * Input: NONE
3816 *
3817 * Output: NONE
3818 *
3819 * Return: NONE
3820 *
3821 * Revised History:
3822 * When Who Remark
3823 * 03/06/2008 Jacken Create Version 0.
3824 *
3825 *---------------------------------------------------------------------------*/
3826 static void dm_init_dynamic_txpower(struct net_device *dev)
3827 {
3828 struct r8192_priv *priv = ieee80211_priv(dev);
3829
3830 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
3831 priv->ieee80211->bdynamic_txpower_enable = true; //Default to enable Tx Power Control
3832 priv->bLastDTPFlag_High = false;
3833 priv->bLastDTPFlag_Low = false;
3834 priv->bDynamicTxHighPower = false;
3835 priv->bDynamicTxLowPower = false;
3836 }
3837
3838 static void dm_dynamic_txpower(struct net_device *dev)
3839 {
3840 struct r8192_priv *priv = ieee80211_priv(dev);
3841 unsigned int txhipower_threshhold=0;
3842 unsigned int txlowpower_threshold=0;
3843 if(priv->ieee80211->bdynamic_txpower_enable != true)
3844 {
3845 priv->bDynamicTxHighPower = false;
3846 priv->bDynamicTxLowPower = false;
3847 return;
3848 }
3849 //printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist);
3850 if((priv->ieee80211->current_network.atheros_cap_exist ) && (priv->ieee80211->mode == IEEE_G)){
3851 txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;
3852 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
3853 }
3854 else
3855 {
3856 txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
3857 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
3858 }
3859
3860 // printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__FUNCTION__,txhipower_threshhold,txlowpower_threshold);
3861
3862 RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb);
3863
3864 if(priv->ieee80211->state == IEEE80211_LINKED)
3865 {
3866 if(priv->undecorated_smoothed_pwdb >= txhipower_threshhold)
3867 {
3868 priv->bDynamicTxHighPower = true;
3869 priv->bDynamicTxLowPower = false;
3870 }
3871 else
3872 {
3873 // high power state check
3874 if(priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true)
3875 {
3876 priv->bDynamicTxHighPower = false;
3877 }
3878 // low power state check
3879 if(priv->undecorated_smoothed_pwdb < 35)
3880 {
3881 priv->bDynamicTxLowPower = true;
3882 }
3883 else if(priv->undecorated_smoothed_pwdb >= 40)
3884 {
3885 priv->bDynamicTxLowPower = false;
3886 }
3887 }
3888 }
3889 else
3890 {
3891 //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;
3892 priv->bDynamicTxHighPower = false;
3893 priv->bDynamicTxLowPower = false;
3894 }
3895
3896 if( (priv->bDynamicTxHighPower != priv->bLastDTPFlag_High ) ||
3897 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) )
3898 {
3899 RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel);
3900
3901
3902 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
3903
3904 }
3905 priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
3906 priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
3907
3908 } /* dm_dynamic_txpower */
3909
3910 //added by vivi, for read tx rate and retrycount
3911 static void dm_check_txrateandretrycount(struct net_device * dev)
3912 {
3913 struct r8192_priv *priv = ieee80211_priv(dev);
3914 struct ieee80211_device* ieee = priv->ieee80211;
3915 //for 11n tx rate
3916 // priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
3917 ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
3918 //printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
3919 //for initial tx rate
3920 // priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
3921 ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);
3922 //for tx tx retry count
3923 // priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
3924 ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
3925 }
3926
3927 static void dm_send_rssi_tofw(struct net_device *dev)
3928 {
3929 DCMD_TXCMD_T tx_cmd;
3930 struct r8192_priv *priv = ieee80211_priv(dev);
3931
3932 // If we test chariot, we should stop the TX command ?
3933 // Because 92E will always silent reset when we send tx command. We use register
3934 // 0x1e0(byte) to botify driver.
3935 write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
3936 return;
3937 #if 1
3938 tx_cmd.Op = TXCMD_SET_RX_RSSI;
3939 tx_cmd.Length = 4;
3940 tx_cmd.Value = priv->undecorated_smoothed_pwdb;
3941
3942 cmpk_message_handle_tx(dev, (u8*)&tx_cmd,
3943 DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
3944 #endif
3945 }
3946
3947 /*---------------------------Define function prototype------------------------*/
3948
WandBoard kernel