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Merge branch 'upstream'
[wandboard.git] / drivers / scsi / sata_sil24.c
blob05ce84286aea34bac3957571e39bc04729838958
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
14 *
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
22 * later version.
23 *
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
28 *
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/dma-mapping.h>
38 #include <scsi/scsi_host.h>
39 #include "scsi.h"
40 #include <linux/libata.h>
41 #include <asm/io.h>
42
43 #define DRV_NAME "sata_sil24"
44 #define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */
45
46 /*
47 * Port request block (PRB) 32 bytes
48 */
49 struct sil24_prb {
50 u16 ctrl;
51 u16 prot;
52 u32 rx_cnt;
53 u8 fis[6 * 4];
54 };
55
56 /*
57 * Scatter gather entry (SGE) 16 bytes
58 */
59 struct sil24_sge {
60 u64 addr;
61 u32 cnt;
62 u32 flags;
63 };
64
65 /*
66 * Port multiplier
67 */
68 struct sil24_port_multiplier {
69 u32 diag;
70 u32 sactive;
71 };
72
73 enum {
74 /*
75 * Global controller registers (128 bytes @ BAR0)
76 */
77 /* 32 bit regs */
78 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
79 HOST_CTRL = 0x40,
80 HOST_IRQ_STAT = 0x44,
81 HOST_PHY_CFG = 0x48,
82 HOST_BIST_CTRL = 0x50,
83 HOST_BIST_PTRN = 0x54,
84 HOST_BIST_STAT = 0x58,
85 HOST_MEM_BIST_STAT = 0x5c,
86 HOST_FLASH_CMD = 0x70,
87 /* 8 bit regs */
88 HOST_FLASH_DATA = 0x74,
89 HOST_TRANSITION_DETECT = 0x75,
90 HOST_GPIO_CTRL = 0x76,
91 HOST_I2C_ADDR = 0x78, /* 32 bit */
92 HOST_I2C_DATA = 0x7c,
93 HOST_I2C_XFER_CNT = 0x7e,
94 HOST_I2C_CTRL = 0x7f,
95
96 /* HOST_SLOT_STAT bits */
97 HOST_SSTAT_ATTN = (1 << 31),
98
99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
104 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
105
106 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
107 /* 32 bit regs */
108 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
109 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
110 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
111 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
112 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
113 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
114 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
115 PORT_CMD_ERR = 0x1024, /* command error number */
116 PORT_FIS_CFG = 0x1028,
117 PORT_FIFO_THRES = 0x102c,
118 /* 16 bit regs */
119 PORT_DECODE_ERR_CNT = 0x1040,
120 PORT_DECODE_ERR_THRESH = 0x1042,
121 PORT_CRC_ERR_CNT = 0x1044,
122 PORT_CRC_ERR_THRESH = 0x1046,
123 PORT_HSHK_ERR_CNT = 0x1048,
124 PORT_HSHK_ERR_THRESH = 0x104a,
125 /* 32 bit regs */
126 PORT_PHY_CFG = 0x1050,
127 PORT_SLOT_STAT = 0x1800,
128 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
129 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
130 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
131 PORT_SCONTROL = 0x1f00,
132 PORT_SSTATUS = 0x1f04,
133 PORT_SERROR = 0x1f08,
134 PORT_SACTIVE = 0x1f0c,
135
136 /* PORT_CTRL_STAT bits */
137 PORT_CS_PORT_RST = (1 << 0), /* port reset */
138 PORT_CS_DEV_RST = (1 << 1), /* device reset */
139 PORT_CS_INIT = (1 << 2), /* port initialize */
140 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
141 PORT_CS_RESUME = (1 << 6), /* port resume */
142 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
143 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
144 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
145
146 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
147 /* bits[11:0] are masked */
148 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
149 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
150 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
151 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
152 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
153 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
154 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
155 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
156
157 /* bits[27:16] are unmasked (raw) */
158 PORT_IRQ_RAW_SHIFT = 16,
159 PORT_IRQ_MASKED_MASK = 0x7ff,
160 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
161
162 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
163 PORT_IRQ_STEER_SHIFT = 30,
164 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
165
166 /* PORT_CMD_ERR constants */
167 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
168 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
169 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
170 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
171 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
172 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
173 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
174 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
175 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
176 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
177 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
178 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
179 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
180 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
181 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
182 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
183 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
184 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
185 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
186 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
187 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
188 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
189
190 /*
191 * Other constants
192 */
193 SGE_TRM = (1 << 31), /* Last SGE in chain */
194 PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */
195
196 /* board id */
197 BID_SIL3124 = 0,
198 BID_SIL3132 = 1,
199 BID_SIL3131 = 2,
200
201 IRQ_STAT_4PORTS = 0xf,
202 };
203
204 struct sil24_cmd_block {
205 struct sil24_prb prb;
206 struct sil24_sge sge[LIBATA_MAX_PRD];
207 };
208
209 /*
210 * ap->private_data
211 *
212 * The preview driver always returned 0 for status. We emulate it
213 * here from the previous interrupt.
214 */
215 struct sil24_port_priv {
216 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
217 dma_addr_t cmd_block_dma; /* DMA base addr for them */
218 struct ata_taskfile tf; /* Cached taskfile registers */
219 };
220
221 /* ap->host_set->private_data */
222 struct sil24_host_priv {
223 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
224 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
225 };
226
227 static u8 sil24_check_status(struct ata_port *ap);
228 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
229 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
230 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
231 static void sil24_phy_reset(struct ata_port *ap);
232 static void sil24_qc_prep(struct ata_queued_cmd *qc);
233 static int sil24_qc_issue(struct ata_queued_cmd *qc);
234 static void sil24_irq_clear(struct ata_port *ap);
235 static void sil24_eng_timeout(struct ata_port *ap);
236 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
237 static int sil24_port_start(struct ata_port *ap);
238 static void sil24_port_stop(struct ata_port *ap);
239 static void sil24_host_stop(struct ata_host_set *host_set);
240 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
241
242 static struct pci_device_id sil24_pci_tbl[] = {
243 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
244 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
245 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
246 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
247 { } /* terminate list */
248 };
249
250 static struct pci_driver sil24_pci_driver = {
251 .name = DRV_NAME,
252 .id_table = sil24_pci_tbl,
253 .probe = sil24_init_one,
254 .remove = ata_pci_remove_one, /* safe? */
255 };
256
257 static Scsi_Host_Template sil24_sht = {
258 .module = THIS_MODULE,
259 .name = DRV_NAME,
260 .ioctl = ata_scsi_ioctl,
261 .queuecommand = ata_scsi_queuecmd,
262 .eh_strategy_handler = ata_scsi_error,
263 .can_queue = ATA_DEF_QUEUE,
264 .this_id = ATA_SHT_THIS_ID,
265 .sg_tablesize = LIBATA_MAX_PRD,
266 .max_sectors = ATA_MAX_SECTORS,
267 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
268 .emulated = ATA_SHT_EMULATED,
269 .use_clustering = ATA_SHT_USE_CLUSTERING,
270 .proc_name = DRV_NAME,
271 .dma_boundary = ATA_DMA_BOUNDARY,
272 .slave_configure = ata_scsi_slave_config,
273 .bios_param = ata_std_bios_param,
274 .ordered_flush = 1, /* NCQ not supported yet */
275 };
276
277 static const struct ata_port_operations sil24_ops = {
278 .port_disable = ata_port_disable,
279
280 .check_status = sil24_check_status,
281 .check_altstatus = sil24_check_status,
282 .dev_select = ata_noop_dev_select,
283
284 .tf_read = sil24_tf_read,
285
286 .phy_reset = sil24_phy_reset,
287
288 .qc_prep = sil24_qc_prep,
289 .qc_issue = sil24_qc_issue,
290
291 .eng_timeout = sil24_eng_timeout,
292
293 .irq_handler = sil24_interrupt,
294 .irq_clear = sil24_irq_clear,
295
296 .scr_read = sil24_scr_read,
297 .scr_write = sil24_scr_write,
298
299 .port_start = sil24_port_start,
300 .port_stop = sil24_port_stop,
301 .host_stop = sil24_host_stop,
302 };
303
304 /*
305 * Use bits 30-31 of host_flags to encode available port numbers.
306 * Current maxium is 4.
307 */
308 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
309 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
310
311 static struct ata_port_info sil24_port_info[] = {
312 /* sil_3124 */
313 {
314 .sht = &sil24_sht,
315 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
316 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
317 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
318 .pio_mask = 0x1f, /* pio0-4 */
319 .mwdma_mask = 0x07, /* mwdma0-2 */
320 .udma_mask = 0x3f, /* udma0-5 */
321 .port_ops = &sil24_ops,
322 },
323 /* sil_3132 */
324 {
325 .sht = &sil24_sht,
326 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
327 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
328 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
329 .pio_mask = 0x1f, /* pio0-4 */
330 .mwdma_mask = 0x07, /* mwdma0-2 */
331 .udma_mask = 0x3f, /* udma0-5 */
332 .port_ops = &sil24_ops,
333 },
334 /* sil_3131/sil_3531 */
335 {
336 .sht = &sil24_sht,
337 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
338 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
339 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
340 .pio_mask = 0x1f, /* pio0-4 */
341 .mwdma_mask = 0x07, /* mwdma0-2 */
342 .udma_mask = 0x3f, /* udma0-5 */
343 .port_ops = &sil24_ops,
344 },
345 };
346
347 static inline void sil24_update_tf(struct ata_port *ap)
348 {
349 struct sil24_port_priv *pp = ap->private_data;
350 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
351 struct sil24_prb __iomem *prb = port;
352 u8 fis[6 * 4];
353
354 memcpy_fromio(fis, prb->fis, 6 * 4);
355 ata_tf_from_fis(fis, &pp->tf);
356 }
357
358 static u8 sil24_check_status(struct ata_port *ap)
359 {
360 struct sil24_port_priv *pp = ap->private_data;
361 return pp->tf.command;
362 }
363
364 static int sil24_scr_map[] = {
365 [SCR_CONTROL] = 0,
366 [SCR_STATUS] = 1,
367 [SCR_ERROR] = 2,
368 [SCR_ACTIVE] = 3,
369 };
370
371 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
372 {
373 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
374 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
375 void __iomem *addr;
376 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
377 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
378 }
379 return 0xffffffffU;
380 }
381
382 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
383 {
384 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
385 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
386 void __iomem *addr;
387 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
388 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
389 }
390 }
391
392 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
393 {
394 struct sil24_port_priv *pp = ap->private_data;
395 *tf = pp->tf;
396 }
397
398 static void sil24_phy_reset(struct ata_port *ap)
399 {
400 __sata_phy_reset(ap);
401 /*
402 * No ATAPI yet. Just unconditionally indicate ATA device.
403 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
404 * and libata core will ignore the device.
405 */
406 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
407 ap->device[0].class = ATA_DEV_ATA;
408 }
409
410 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
411 struct sil24_cmd_block *cb)
412 {
413 struct sil24_sge *sge = cb->sge;
414 struct scatterlist *sg;
415 unsigned int idx = 0;
416
417 ata_for_each_sg(sg, qc) {
418 sge->addr = cpu_to_le64(sg_dma_address(sg));
419 sge->cnt = cpu_to_le32(sg_dma_len(sg));
420 if (ata_sg_is_last(sg, qc))
421 sge->flags = cpu_to_le32(SGE_TRM);
422 else
423 sge->flags = 0;
424
425 sge++;
426 idx++;
427 }
428 }
429
430 static void sil24_qc_prep(struct ata_queued_cmd *qc)
431 {
432 struct ata_port *ap = qc->ap;
433 struct sil24_port_priv *pp = ap->private_data;
434 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
435 struct sil24_prb *prb = &cb->prb;
436
437 switch (qc->tf.protocol) {
438 case ATA_PROT_PIO:
439 case ATA_PROT_DMA:
440 case ATA_PROT_NODATA:
441 break;
442 default:
443 /* ATAPI isn't supported yet */
444 BUG();
445 }
446
447 ata_tf_to_fis(&qc->tf, prb->fis, 0);
448
449 if (qc->flags & ATA_QCFLAG_DMAMAP)
450 sil24_fill_sg(qc, cb);
451 }
452
453 static int sil24_qc_issue(struct ata_queued_cmd *qc)
454 {
455 struct ata_port *ap = qc->ap;
456 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
457 struct sil24_port_priv *pp = ap->private_data;
458 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
459
460 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
461 return 0;
462 }
463
464 static void sil24_irq_clear(struct ata_port *ap)
465 {
466 /* unused */
467 }
468
469 static int __sil24_reset_controller(void __iomem *port)
470 {
471 int cnt;
472 u32 tmp;
473
474 /* Reset controller state. Is this correct? */
475 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
476 readl(port + PORT_CTRL_STAT); /* sync */
477
478 /* Max ~100ms */
479 for (cnt = 0; cnt < 1000; cnt++) {
480 udelay(100);
481 tmp = readl(port + PORT_CTRL_STAT);
482 if (!(tmp & PORT_CS_DEV_RST))
483 break;
484 }
485
486 if (tmp & PORT_CS_DEV_RST)
487 return -1;
488 return 0;
489 }
490
491 static void sil24_reset_controller(struct ata_port *ap)
492 {
493 printk(KERN_NOTICE DRV_NAME
494 " ata%u: resetting controller...\n", ap->id);
495 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
496 printk(KERN_ERR DRV_NAME
497 " ata%u: failed to reset controller\n", ap->id);
498 }
499
500 static void sil24_eng_timeout(struct ata_port *ap)
501 {
502 struct ata_queued_cmd *qc;
503
504 qc = ata_qc_from_tag(ap, ap->active_tag);
505 if (!qc) {
506 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
507 ap->id);
508 return;
509 }
510
511 /*
512 * hack alert! We cannot use the supplied completion
513 * function from inside the ->eh_strategy_handler() thread.
514 * libata is the only user of ->eh_strategy_handler() in
515 * any kernel, so the default scsi_done() assumes it is
516 * not being called from the SCSI EH.
517 */
518 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
519 qc->scsidone = scsi_finish_command;
520 ata_qc_complete(qc, AC_ERR_OTHER);
521
522 sil24_reset_controller(ap);
523 }
524
525 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
526 {
527 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
528 struct sil24_port_priv *pp = ap->private_data;
529 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
530 u32 irq_stat, cmd_err, sstatus, serror;
531 unsigned int err_mask;
532
533 irq_stat = readl(port + PORT_IRQ_STAT);
534 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
535
536 if (!(irq_stat & PORT_IRQ_ERROR)) {
537 /* ignore non-completion, non-error irqs for now */
538 printk(KERN_WARNING DRV_NAME
539 "ata%u: non-error exception irq (irq_stat %x)\n",
540 ap->id, irq_stat);
541 return;
542 }
543
544 cmd_err = readl(port + PORT_CMD_ERR);
545 sstatus = readl(port + PORT_SSTATUS);
546 serror = readl(port + PORT_SERROR);
547 if (serror)
548 writel(serror, port + PORT_SERROR);
549
550 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
551 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
552 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
553
554 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
555 /*
556 * Device is reporting error, tf registers are valid.
557 */
558 sil24_update_tf(ap);
559 err_mask = ac_err_mask(pp->tf.command);
560 } else {
561 /*
562 * Other errors. libata currently doesn't have any
563 * mechanism to report these errors. Just turn on
564 * ATA_ERR.
565 */
566 err_mask = AC_ERR_OTHER;
567 }
568
569 if (qc)
570 ata_qc_complete(qc, err_mask);
571
572 sil24_reset_controller(ap);
573 }
574
575 static inline void sil24_host_intr(struct ata_port *ap)
576 {
577 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
578 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
579 u32 slot_stat;
580
581 slot_stat = readl(port + PORT_SLOT_STAT);
582 if (!(slot_stat & HOST_SSTAT_ATTN)) {
583 struct sil24_port_priv *pp = ap->private_data;
584 /*
585 * !HOST_SSAT_ATTN guarantees successful completion,
586 * so reading back tf registers is unnecessary for
587 * most commands. TODO: read tf registers for
588 * commands which require these values on successful
589 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
590 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
591 */
592 sil24_update_tf(ap);
593
594 if (qc)
595 ata_qc_complete(qc, ac_err_mask(pp->tf.command));
596 } else
597 sil24_error_intr(ap, slot_stat);
598 }
599
600 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
601 {
602 struct ata_host_set *host_set = dev_instance;
603 struct sil24_host_priv *hpriv = host_set->private_data;
604 unsigned handled = 0;
605 u32 status;
606 int i;
607
608 status = readl(hpriv->host_base + HOST_IRQ_STAT);
609
610 if (status == 0xffffffff) {
611 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
612 "PCI fault or device removal?\n");
613 goto out;
614 }
615
616 if (!(status & IRQ_STAT_4PORTS))
617 goto out;
618
619 spin_lock(&host_set->lock);
620
621 for (i = 0; i < host_set->n_ports; i++)
622 if (status & (1 << i)) {
623 struct ata_port *ap = host_set->ports[i];
624 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
625 sil24_host_intr(host_set->ports[i]);
626 handled++;
627 } else
628 printk(KERN_ERR DRV_NAME
629 ": interrupt from disabled port %d\n", i);
630 }
631
632 spin_unlock(&host_set->lock);
633 out:
634 return IRQ_RETVAL(handled);
635 }
636
637 static int sil24_port_start(struct ata_port *ap)
638 {
639 struct device *dev = ap->host_set->dev;
640 struct sil24_port_priv *pp;
641 struct sil24_cmd_block *cb;
642 size_t cb_size = sizeof(*cb);
643 dma_addr_t cb_dma;
644
645 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
646 if (!pp)
647 return -ENOMEM;
648 memset(pp, 0, sizeof(*pp));
649
650 pp->tf.command = ATA_DRDY;
651
652 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
653 if (!cb) {
654 kfree(pp);
655 return -ENOMEM;
656 }
657 memset(cb, 0, cb_size);
658
659 pp->cmd_block = cb;
660 pp->cmd_block_dma = cb_dma;
661
662 ap->private_data = pp;
663
664 return 0;
665 }
666
667 static void sil24_port_stop(struct ata_port *ap)
668 {
669 struct device *dev = ap->host_set->dev;
670 struct sil24_port_priv *pp = ap->private_data;
671 size_t cb_size = sizeof(*pp->cmd_block);
672
673 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
674 kfree(pp);
675 }
676
677 static void sil24_host_stop(struct ata_host_set *host_set)
678 {
679 struct sil24_host_priv *hpriv = host_set->private_data;
680
681 iounmap(hpriv->host_base);
682 iounmap(hpriv->port_base);
683 kfree(hpriv);
684 }
685
686 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
687 {
688 static int printed_version = 0;
689 unsigned int board_id = (unsigned int)ent->driver_data;
690 struct ata_port_info *pinfo = &sil24_port_info[board_id];
691 struct ata_probe_ent *probe_ent = NULL;
692 struct sil24_host_priv *hpriv = NULL;
693 void __iomem *host_base = NULL;
694 void __iomem *port_base = NULL;
695 int i, rc;
696
697 if (!printed_version++)
698 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
699
700 rc = pci_enable_device(pdev);
701 if (rc)
702 return rc;
703
704 rc = pci_request_regions(pdev, DRV_NAME);
705 if (rc)
706 goto out_disable;
707
708 rc = -ENOMEM;
709 /* ioremap mmio registers */
710 host_base = ioremap(pci_resource_start(pdev, 0),
711 pci_resource_len(pdev, 0));
712 if (!host_base)
713 goto out_free;
714 port_base = ioremap(pci_resource_start(pdev, 2),
715 pci_resource_len(pdev, 2));
716 if (!port_base)
717 goto out_free;
718
719 /* allocate & init probe_ent and hpriv */
720 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
721 if (!probe_ent)
722 goto out_free;
723
724 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
725 if (!hpriv)
726 goto out_free;
727
728 memset(probe_ent, 0, sizeof(*probe_ent));
729 probe_ent->dev = pci_dev_to_dev(pdev);
730 INIT_LIST_HEAD(&probe_ent->node);
731
732 probe_ent->sht = pinfo->sht;
733 probe_ent->host_flags = pinfo->host_flags;
734 probe_ent->pio_mask = pinfo->pio_mask;
735 probe_ent->udma_mask = pinfo->udma_mask;
736 probe_ent->port_ops = pinfo->port_ops;
737 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
738
739 probe_ent->irq = pdev->irq;
740 probe_ent->irq_flags = SA_SHIRQ;
741 probe_ent->mmio_base = port_base;
742 probe_ent->private_data = hpriv;
743
744 memset(hpriv, 0, sizeof(*hpriv));
745 hpriv->host_base = host_base;
746 hpriv->port_base = port_base;
747
748 /*
749 * Configure the device
750 */
751 /*
752 * FIXME: This device is certainly 64-bit capable. We just
753 * don't know how to use it. After fixing 32bit activation in
754 * this function, enable 64bit masks here.
755 */
756 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
757 if (rc) {
758 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
759 pci_name(pdev));
760 goto out_free;
761 }
762 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
763 if (rc) {
764 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
765 pci_name(pdev));
766 goto out_free;
767 }
768
769 /* GPIO off */
770 writel(0, host_base + HOST_FLASH_CMD);
771
772 /* Mask interrupts during initialization */
773 writel(0, host_base + HOST_CTRL);
774
775 for (i = 0; i < probe_ent->n_ports; i++) {
776 void __iomem *port = port_base + i * PORT_REGS_SIZE;
777 unsigned long portu = (unsigned long)port;
778 u32 tmp;
779 int cnt;
780
781 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
782 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
783
784 ata_std_ports(&probe_ent->port[i]);
785
786 /* Initial PHY setting */
787 writel(0x20c, port + PORT_PHY_CFG);
788
789 /* Clear port RST */
790 tmp = readl(port + PORT_CTRL_STAT);
791 if (tmp & PORT_CS_PORT_RST) {
792 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
793 readl(port + PORT_CTRL_STAT); /* sync */
794 for (cnt = 0; cnt < 10; cnt++) {
795 msleep(10);
796 tmp = readl(port + PORT_CTRL_STAT);
797 if (!(tmp & PORT_CS_PORT_RST))
798 break;
799 }
800 if (tmp & PORT_CS_PORT_RST)
801 printk(KERN_ERR DRV_NAME
802 "(%s): failed to clear port RST\n",
803 pci_name(pdev));
804 }
805
806 /* Zero error counters. */
807 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
808 writel(0x8000, port + PORT_CRC_ERR_THRESH);
809 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
810 writel(0x0000, port + PORT_DECODE_ERR_CNT);
811 writel(0x0000, port + PORT_CRC_ERR_CNT);
812 writel(0x0000, port + PORT_HSHK_ERR_CNT);
813
814 /* FIXME: 32bit activation? */
815 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
816 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
817
818 /* Configure interrupts */
819 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
820 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
821 port + PORT_IRQ_ENABLE_SET);
822
823 /* Clear interrupts */
824 writel(0x0fff0fff, port + PORT_IRQ_STAT);
825 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
826
827 /* Clear port multiplier enable and resume bits */
828 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
829
830 /* Reset itself */
831 if (__sil24_reset_controller(port))
832 printk(KERN_ERR DRV_NAME
833 "(%s): failed to reset controller\n",
834 pci_name(pdev));
835 }
836
837 /* Turn on interrupts */
838 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
839
840 pci_set_master(pdev);
841
842 /* FIXME: check ata_device_add return value */
843 ata_device_add(probe_ent);
844
845 kfree(probe_ent);
846 return 0;
847
848 out_free:
849 if (host_base)
850 iounmap(host_base);
851 if (port_base)
852 iounmap(port_base);
853 kfree(probe_ent);
854 kfree(hpriv);
855 pci_release_regions(pdev);
856 out_disable:
857 pci_disable_device(pdev);
858 return rc;
859 }
860
861 static int __init sil24_init(void)
862 {
863 return pci_module_init(&sil24_pci_driver);
864 }
865
866 static void __exit sil24_exit(void)
867 {
868 pci_unregister_driver(&sil24_pci_driver);
869 }
870
871 MODULE_AUTHOR("Tejun Heo");
872 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
873 MODULE_LICENSE("GPL");
874 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
875
876 module_init(sil24_init);
877 module_exit(sil24_exit);
WandBoard kernel