2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <asm/pci-direct.h>
26 #include <asm/amd_iommu_types.h>
27 #include <asm/amd_iommu.h>
28 #include <asm/iommu.h>
31 * definitions for the ACPI scanning code
33 #define PCI_BUS(x) (((x) >> 8) & 0xff)
34 #define IVRS_HEADER_LENGTH 48
36 #define ACPI_IVHD_TYPE 0x10
37 #define ACPI_IVMD_TYPE_ALL 0x20
38 #define ACPI_IVMD_TYPE 0x21
39 #define ACPI_IVMD_TYPE_RANGE 0x22
41 #define IVHD_DEV_ALL 0x01
42 #define IVHD_DEV_SELECT 0x02
43 #define IVHD_DEV_SELECT_RANGE_START 0x03
44 #define IVHD_DEV_RANGE_END 0x04
45 #define IVHD_DEV_ALIAS 0x42
46 #define IVHD_DEV_ALIAS_RANGE 0x43
47 #define IVHD_DEV_EXT_SELECT 0x46
48 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
50 #define IVHD_FLAG_HT_TUN_EN 0x00
51 #define IVHD_FLAG_PASSPW_EN 0x01
52 #define IVHD_FLAG_RESPASSPW_EN 0x02
53 #define IVHD_FLAG_ISOC_EN 0x03
55 #define IVMD_FLAG_EXCL_RANGE 0x08
56 #define IVMD_FLAG_UNITY_MAP 0x01
58 #define ACPI_DEVFLAG_INITPASS 0x01
59 #define ACPI_DEVFLAG_EXTINT 0x02
60 #define ACPI_DEVFLAG_NMI 0x04
61 #define ACPI_DEVFLAG_SYSMGT1 0x10
62 #define ACPI_DEVFLAG_SYSMGT2 0x20
63 #define ACPI_DEVFLAG_LINT0 0x40
64 #define ACPI_DEVFLAG_LINT1 0x80
65 #define ACPI_DEVFLAG_ATSDIS 0x10000000
68 * ACPI table definitions
70 * These data structures are laid over the table to parse the important values
75 * structure describing one IOMMU in the ACPI table. Typically followed by one
76 * or more ivhd_entrys.
88 } __attribute__((packed
));
91 * A device entry describing which devices a specific IOMMU translates and
92 * which requestor ids they use.
99 } __attribute__((packed
));
102 * An AMD IOMMU memory definition structure. It defines things like exclusion
103 * ranges for devices and regions that should be unity mapped.
114 } __attribute__((packed
));
116 static int __initdata amd_iommu_detected
;
118 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
120 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
122 unsigned amd_iommu_aperture_order
= 26; /* size of aperture in power of 2 */
123 int amd_iommu_isolate
; /* if 1, device isolation is enabled */
125 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
129 * Pointer to the device table which is shared by all AMD IOMMUs
130 * it is indexed by the PCI device id or the HT unit id and contains
131 * information about the domain the device belongs to as well as the
132 * page table root pointer.
134 struct dev_table_entry
*amd_iommu_dev_table
;
137 * The alias table is a driver specific data structure which contains the
138 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
139 * More than one device can share the same requestor id.
141 u16
*amd_iommu_alias_table
;
144 * The rlookup table is used to find the IOMMU which is responsible
145 * for a specific device. It is also indexed by the PCI device id.
147 struct amd_iommu
**amd_iommu_rlookup_table
;
150 * The pd table (protection domain table) is used to find the protection domain
151 * data structure a device belongs to. Indexed with the PCI device id too.
153 struct protection_domain
**amd_iommu_pd_table
;
156 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
157 * to know which ones are already in use.
159 unsigned long *amd_iommu_pd_alloc_bitmap
;
161 static u32 dev_table_size
; /* size of the device table */
162 static u32 alias_table_size
; /* size of the alias table */
163 static u32 rlookup_table_size
; /* size if the rlookup table */
165 static inline void update_last_devid(u16 devid
)
167 if (devid
> amd_iommu_last_bdf
)
168 amd_iommu_last_bdf
= devid
;
171 static inline unsigned long tbl_size(int entry_size
)
173 unsigned shift
= PAGE_SHIFT
+
174 get_order(amd_iommu_last_bdf
* entry_size
);
179 /****************************************************************************
181 * AMD IOMMU MMIO register space handling functions
183 * These functions are used to program the IOMMU device registers in
184 * MMIO space required for that driver.
186 ****************************************************************************/
189 * This function set the exclusion range in the IOMMU. DMA accesses to the
190 * exclusion range are passed through untranslated
192 static void __init
iommu_set_exclusion_range(struct amd_iommu
*iommu
)
194 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
195 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
198 if (!iommu
->exclusion_start
)
201 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
202 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
203 &entry
, sizeof(entry
));
206 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
207 &entry
, sizeof(entry
));
210 /* Programs the physical address of the device table into the IOMMU hardware */
211 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
215 BUG_ON(iommu
->mmio_base
== NULL
);
217 entry
= virt_to_phys(amd_iommu_dev_table
);
218 entry
|= (dev_table_size
>> 12) - 1;
219 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
220 &entry
, sizeof(entry
));
223 /* Generic functions to enable/disable certain features of the IOMMU. */
224 static void __init
iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
228 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
230 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
233 static void __init
iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
237 ctrl
= (u64
)readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
239 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
242 /* Function to enable the hardware */
243 void __init
iommu_enable(struct amd_iommu
*iommu
)
245 printk(KERN_INFO
"AMD IOMMU: Enabling IOMMU at ");
246 print_devid(iommu
->devid
, 0);
247 printk(" cap 0x%hx\n", iommu
->cap_ptr
);
249 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
253 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
254 * the system has one.
256 static u8
* __init
iommu_map_mmio_space(u64 address
)
260 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu"))
263 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
267 release_mem_region(address
, MMIO_REGION_LENGTH
);
272 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
274 if (iommu
->mmio_base
)
275 iounmap(iommu
->mmio_base
);
276 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
279 /****************************************************************************
281 * The functions below belong to the first pass of AMD IOMMU ACPI table
282 * parsing. In this pass we try to find out the highest device id this
283 * code has to handle. Upon this information the size of the shared data
284 * structures is determined later.
286 ****************************************************************************/
289 * This function reads the last device id the IOMMU has to handle from the PCI
290 * capability header for this IOMMU
292 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
296 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
297 update_last_devid(calc_devid(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
303 * After reading the highest device id from the IOMMU PCI capability header
304 * this function looks if there is a higher device id defined in the ACPI table
306 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
308 u8
*p
= (void *)h
, *end
= (void *)h
;
309 struct ivhd_entry
*dev
;
314 find_last_devid_on_pci(PCI_BUS(h
->devid
),
320 dev
= (struct ivhd_entry
*)p
;
322 case IVHD_DEV_SELECT
:
323 case IVHD_DEV_RANGE_END
:
325 case IVHD_DEV_EXT_SELECT
:
326 /* all the above subfield types refer to device ids */
327 update_last_devid(dev
->devid
);
332 p
+= 0x04 << (*p
>> 6);
341 * Iterate over all IVHD entries in the ACPI table and find the highest device
342 * id which we need to handle. This is the first of three functions which parse
343 * the ACPI table. So we check the checksum here.
345 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
348 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
349 struct ivhd_header
*h
;
352 * Validate checksum here so we don't need to do it when
353 * we actually parse the table
355 for (i
= 0; i
< table
->length
; ++i
)
358 /* ACPI table corrupt */
361 p
+= IVRS_HEADER_LENGTH
;
363 end
+= table
->length
;
365 h
= (struct ivhd_header
*)p
;
368 find_last_devid_from_ivhd(h
);
380 /****************************************************************************
382 * The following functions belong the the code path which parses the ACPI table
383 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
384 * data structures, initialize the device/alias/rlookup table and also
385 * basically initialize the hardware.
387 ****************************************************************************/
390 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
391 * write commands to that buffer later and the IOMMU will execute them
394 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
396 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
397 get_order(CMD_BUFFER_SIZE
));
403 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
;
405 entry
= (u64
)virt_to_phys(cmd_buf
);
406 entry
|= MMIO_CMD_SIZE_512
;
407 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
408 &entry
, sizeof(entry
));
410 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
415 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
417 free_pages((unsigned long)iommu
->cmd_buf
, get_order(CMD_BUFFER_SIZE
));
420 /* sets a specific bit in the device table entry. */
421 static void set_dev_entry_bit(u16 devid
, u8 bit
)
423 int i
= (bit
>> 5) & 0x07;
424 int _bit
= bit
& 0x1f;
426 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
429 /* Writes the specific IOMMU for a device into the rlookup table */
430 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
432 amd_iommu_rlookup_table
[devid
] = iommu
;
436 * This function takes the device specific flags read from the ACPI
437 * table and sets up the device table entry with that information
439 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
440 u16 devid
, u32 flags
, u32 ext_flags
)
442 if (flags
& ACPI_DEVFLAG_INITPASS
)
443 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
444 if (flags
& ACPI_DEVFLAG_EXTINT
)
445 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
446 if (flags
& ACPI_DEVFLAG_NMI
)
447 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
448 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
449 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
450 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
451 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
452 if (flags
& ACPI_DEVFLAG_LINT0
)
453 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
454 if (flags
& ACPI_DEVFLAG_LINT1
)
455 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
457 set_iommu_for_device(iommu
, devid
);
461 * Reads the device exclusion range from ACPI and initialize IOMMU with
464 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
466 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
468 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
473 * We only can configure exclusion ranges per IOMMU, not
474 * per device. But we can enable the exclusion range per
475 * device. This is done here
477 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
478 iommu
->exclusion_start
= m
->range_start
;
479 iommu
->exclusion_length
= m
->range_length
;
484 * This function reads some important data from the IOMMU PCI space and
485 * initializes the driver data structure with it. It reads the hardware
486 * capabilities and the first/last device entries
488 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
490 int bus
= PCI_BUS(iommu
->devid
);
491 int dev
= PCI_SLOT(iommu
->devid
);
492 int fn
= PCI_FUNC(iommu
->devid
);
493 int cap_ptr
= iommu
->cap_ptr
;
496 iommu
->cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_CAP_HDR_OFFSET
);
498 range
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
499 iommu
->first_device
= calc_devid(MMIO_GET_BUS(range
),
501 iommu
->last_device
= calc_devid(MMIO_GET_BUS(range
),
506 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
507 * initializes the hardware and our data structures with it.
509 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
510 struct ivhd_header
*h
)
513 u8
*end
= p
, flags
= 0;
514 u16 dev_i
, devid
= 0, devid_start
= 0, devid_to
= 0;
517 struct ivhd_entry
*e
;
520 * First set the recommended feature enable bits from ACPI
521 * into the IOMMU control registers
523 h
->flags
& IVHD_FLAG_HT_TUN_EN
?
524 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
525 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
527 h
->flags
& IVHD_FLAG_PASSPW_EN
?
528 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
529 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
531 h
->flags
& IVHD_FLAG_RESPASSPW_EN
?
532 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
533 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
535 h
->flags
& IVHD_FLAG_ISOC_EN
?
536 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
537 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
540 * make IOMMU memory accesses cache coherent
542 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
545 * Done. Now parse the device entries
547 p
+= sizeof(struct ivhd_header
);
551 e
= (struct ivhd_entry
*)p
;
554 for (dev_i
= iommu
->first_device
;
555 dev_i
<= iommu
->last_device
; ++dev_i
)
556 set_dev_entry_from_acpi(iommu
, dev_i
,
559 case IVHD_DEV_SELECT
:
561 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
563 case IVHD_DEV_SELECT_RANGE_START
:
564 devid_start
= e
->devid
;
571 devid_to
= e
->ext
>> 8;
572 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
573 amd_iommu_alias_table
[devid
] = devid_to
;
575 case IVHD_DEV_ALIAS_RANGE
:
576 devid_start
= e
->devid
;
578 devid_to
= e
->ext
>> 8;
582 case IVHD_DEV_EXT_SELECT
:
584 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
587 case IVHD_DEV_EXT_SELECT_RANGE
:
588 devid_start
= e
->devid
;
593 case IVHD_DEV_RANGE_END
:
595 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
597 amd_iommu_alias_table
[dev_i
] = devid_to
;
598 set_dev_entry_from_acpi(iommu
,
599 amd_iommu_alias_table
[dev_i
],
607 p
+= 0x04 << (e
->type
>> 6);
611 /* Initializes the device->iommu mapping for the driver */
612 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
616 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
617 set_iommu_for_device(iommu
, i
);
622 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
624 free_command_buffer(iommu
);
625 iommu_unmap_mmio_space(iommu
);
628 static void __init
free_iommu_all(void)
630 struct amd_iommu
*iommu
, *next
;
632 list_for_each_entry_safe(iommu
, next
, &amd_iommu_list
, list
) {
633 list_del(&iommu
->list
);
634 free_iommu_one(iommu
);
640 * This function clues the initialization function for one IOMMU
641 * together and also allocates the command buffer and programs the
642 * hardware. It does NOT enable the IOMMU. This is done afterwards.
644 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
646 spin_lock_init(&iommu
->lock
);
647 list_add_tail(&iommu
->list
, &amd_iommu_list
);
650 * Copy data from ACPI table entry to the iommu struct
652 iommu
->devid
= h
->devid
;
653 iommu
->cap_ptr
= h
->cap_ptr
;
654 iommu
->mmio_phys
= h
->mmio_phys
;
655 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
656 if (!iommu
->mmio_base
)
659 iommu_set_device_table(iommu
);
660 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
664 init_iommu_from_pci(iommu
);
665 init_iommu_from_acpi(iommu
, h
);
666 init_iommu_devices(iommu
);
672 * Iterates over all IOMMU entries in the ACPI table, allocates the
673 * IOMMU structure and initializes it with init_iommu_one()
675 static int __init
init_iommu_all(struct acpi_table_header
*table
)
677 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
678 struct ivhd_header
*h
;
679 struct amd_iommu
*iommu
;
682 end
+= table
->length
;
683 p
+= IVRS_HEADER_LENGTH
;
686 h
= (struct ivhd_header
*)p
;
689 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
692 ret
= init_iommu_one(iommu
, h
);
707 /****************************************************************************
709 * The next functions belong to the third pass of parsing the ACPI
710 * table. In this last pass the memory mapping requirements are
711 * gathered (like exclusion and unity mapping reanges).
713 ****************************************************************************/
715 static void __init
free_unity_maps(void)
717 struct unity_map_entry
*entry
, *next
;
719 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
720 list_del(&entry
->list
);
725 /* called when we find an exclusion range definition in ACPI */
726 static int __init
init_exclusion_range(struct ivmd_header
*m
)
732 set_device_exclusion_range(m
->devid
, m
);
734 case ACPI_IVMD_TYPE_ALL
:
735 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
736 set_device_exclusion_range(i
, m
);
738 case ACPI_IVMD_TYPE_RANGE
:
739 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
740 set_device_exclusion_range(i
, m
);
749 /* called for unity map ACPI definition */
750 static int __init
init_unity_map_range(struct ivmd_header
*m
)
752 struct unity_map_entry
*e
= 0;
754 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
761 e
->devid_start
= e
->devid_end
= m
->devid
;
763 case ACPI_IVMD_TYPE_ALL
:
765 e
->devid_end
= amd_iommu_last_bdf
;
767 case ACPI_IVMD_TYPE_RANGE
:
768 e
->devid_start
= m
->devid
;
769 e
->devid_end
= m
->aux
;
772 e
->address_start
= PAGE_ALIGN(m
->range_start
);
773 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
774 e
->prot
= m
->flags
>> 1;
776 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
781 /* iterates over all memory definitions we find in the ACPI table */
782 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
784 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
785 struct ivmd_header
*m
;
787 end
+= table
->length
;
788 p
+= IVRS_HEADER_LENGTH
;
791 m
= (struct ivmd_header
*)p
;
792 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
793 init_exclusion_range(m
);
794 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
795 init_unity_map_range(m
);
804 * Init the device table to not allow DMA access for devices and
805 * suppress all page faults
807 static void init_device_table(void)
811 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
812 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
813 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
814 set_dev_entry_bit(devid
, DEV_ENTRY_NO_PAGE_FAULT
);
819 * This function finally enables all IOMMUs found in the system after
820 * they have been initialized
822 static void __init
enable_iommus(void)
824 struct amd_iommu
*iommu
;
826 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
827 iommu_set_exclusion_range(iommu
);
833 * Suspend/Resume support
834 * disable suspend until real resume implemented
837 static int amd_iommu_resume(struct sys_device
*dev
)
842 static int amd_iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
847 static struct sysdev_class amd_iommu_sysdev_class
= {
849 .suspend
= amd_iommu_suspend
,
850 .resume
= amd_iommu_resume
,
853 static struct sys_device device_amd_iommu
= {
855 .cls
= &amd_iommu_sysdev_class
,
859 * This is the core init function for AMD IOMMU hardware in the system.
860 * This function is called from the generic x86 DMA layer initialization
863 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
866 * 1 pass) Find the highest PCI device id the driver has to handle.
867 * Upon this information the size of the data structures is
868 * determined that needs to be allocated.
870 * 2 pass) Initialize the data structures just allocated with the
871 * information in the ACPI table about available AMD IOMMUs
872 * in the system. It also maps the PCI devices in the
873 * system to specific IOMMUs
875 * 3 pass) After the basic data structures are allocated and
876 * initialized we update them with information about memory
877 * remapping requirements parsed out of the ACPI table in
880 * After that the hardware is initialized and ready to go. In the last
881 * step we do some Linux specific things like registering the driver in
882 * the dma_ops interface and initializing the suspend/resume support
883 * functions. Finally it prints some information about AMD IOMMUs and
884 * the driver state and enables the hardware.
886 int __init
amd_iommu_init(void)
892 printk(KERN_INFO
"AMD IOMMU disabled by kernel command line\n");
896 if (!amd_iommu_detected
)
900 * First parse ACPI tables to find the largest Bus/Dev/Func
901 * we need to handle. Upon this information the shared data
902 * structures for the IOMMUs in the system will be allocated
904 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
907 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
908 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
909 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
913 /* Device table - directly used by all IOMMUs */
914 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
915 get_order(dev_table_size
));
916 if (amd_iommu_dev_table
== NULL
)
920 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
921 * IOMMU see for that device
923 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
924 get_order(alias_table_size
));
925 if (amd_iommu_alias_table
== NULL
)
928 /* IOMMU rlookup table - find the IOMMU for a specific device */
929 amd_iommu_rlookup_table
= (void *)__get_free_pages(GFP_KERNEL
,
930 get_order(rlookup_table_size
));
931 if (amd_iommu_rlookup_table
== NULL
)
935 * Protection Domain table - maps devices to protection domains
936 * This table has the same size as the rlookup_table
938 amd_iommu_pd_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
939 get_order(rlookup_table_size
));
940 if (amd_iommu_pd_table
== NULL
)
943 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
944 GFP_KERNEL
| __GFP_ZERO
,
945 get_order(MAX_DOMAIN_ID
/8));
946 if (amd_iommu_pd_alloc_bitmap
== NULL
)
949 /* init the device table */
953 * let all alias entries point to itself
955 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
956 amd_iommu_alias_table
[i
] = i
;
959 * never allocate domain 0 because its used as the non-allocated and
960 * error value placeholder
962 amd_iommu_pd_alloc_bitmap
[0] = 1;
965 * now the data structures are allocated and basically initialized
966 * start the real acpi table scan
969 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
972 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
975 ret
= sysdev_class_register(&amd_iommu_sysdev_class
);
979 ret
= sysdev_register(&device_amd_iommu
);
983 ret
= amd_iommu_init_dma_ops();
989 printk(KERN_INFO
"AMD IOMMU: aperture size is %d MB\n",
990 (1 << (amd_iommu_aperture_order
-20)));
992 printk(KERN_INFO
"AMD IOMMU: device isolation ");
993 if (amd_iommu_isolate
)
996 printk("disabled\n");
1002 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
, 1);
1004 free_pages((unsigned long)amd_iommu_pd_table
,
1005 get_order(rlookup_table_size
));
1007 free_pages((unsigned long)amd_iommu_rlookup_table
,
1008 get_order(rlookup_table_size
));
1010 free_pages((unsigned long)amd_iommu_alias_table
,
1011 get_order(alias_table_size
));
1013 free_pages((unsigned long)amd_iommu_dev_table
,
1014 get_order(dev_table_size
));
1023 /****************************************************************************
1025 * Early detect code. This code runs at IOMMU detection time in the DMA
1026 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1029 ****************************************************************************/
1030 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
1035 void __init
amd_iommu_detect(void)
1037 if (swiotlb
|| no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
1040 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
1042 amd_iommu_detected
= 1;
1043 #ifdef CONFIG_GART_IOMMU
1044 gart_iommu_aperture_disabled
= 1;
1045 gart_iommu_aperture
= 0;
1050 /****************************************************************************
1052 * Parsing functions for the AMD IOMMU specific kernel command line
1055 ****************************************************************************/
1057 static int __init
parse_amd_iommu_options(char *str
)
1059 for (; *str
; ++str
) {
1060 if (strcmp(str
, "isolate") == 0)
1061 amd_iommu_isolate
= 1;
1067 static int __init
parse_amd_iommu_size_options(char *str
)
1069 unsigned order
= PAGE_SHIFT
+ get_order(memparse(str
, &str
));
1071 if ((order
> 24) && (order
< 31))
1072 amd_iommu_aperture_order
= order
;
1077 __setup("amd_iommu=", parse_amd_iommu_options
);
1078 __setup("amd_iommu_size=", parse_amd_iommu_size_options
);