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Remove all inclusions of <linux/config.h>
[wandboard.git] / sound / oss / maestro3.c
blob5ef6e617911b708a2205ab193872e27bcbbb03da
1 /*****************************************************************************
2 *
3 * ESS Maestro3/Allegro driver for Linux 2.4.x
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * (c) Copyright 2000 Zach Brown <zab@zabbo.net>
20 *
21 * I need to thank many people for helping make this driver happen.
22 * As always, Eric Brombaugh was a hacking machine and killed many bugs
23 * that I was too dumb to notice. Howard Kim at ESS provided reference boards
24 * and as much docs as he could. Todd and Mick at Dell tested snapshots on
25 * an army of laptops. msw and deviant at Red Hat also humoured me by hanging
26 * their laptops every few hours in the name of science.
27 *
28 * Shouts go out to Mike "DJ XPCom" Ang.
29 *
30 * History
31 * v1.23 - Jun 5 2002 - Michael Olson <olson@cs.odu.edu>
32 * added a module option to allow selection of GPIO pin number
33 * for external amp
34 * v1.22 - Feb 28 2001 - Zach Brown <zab@zabbo.net>
35 * allocate mem at insmod/setup, rather than open
36 * limit pci dma addresses to 28bit, thanks guys.
37 * v1.21 - Feb 04 2001 - Zach Brown <zab@zabbo.net>
38 * fix up really dumb notifier -> suspend oops
39 * v1.20 - Jan 30 2001 - Zach Brown <zab@zabbo.net>
40 * get rid of pm callback and use pci_dev suspend/resume instead
41 * m3_probe cleanups, including pm oops think-o
42 * v1.10 - Jan 6 2001 - Zach Brown <zab@zabbo.net>
43 * revert to lame remap_page_range mmap() just to make it work
44 * record mmap fixed.
45 * fix up incredibly broken open/release resource management
46 * duh. fix record format setting.
47 * add SMP locking and cleanup formatting here and there
48 * v1.00 - Dec 16 2000 - Zach Brown <zab@zabbo.net>
49 * port to sexy 2.4 interfaces
50 * properly align instance allocations so recording works
51 * clean up function namespace a little :/
52 * update PCI IDs based on mail from ESS
53 * arbitrarily bump version number to show its 2.4 now,
54 * 2.2 will stay 0., oss_audio port gets 2.
55 * v0.03 - Nov 05 2000 - Zach Brown <zab@zabbo.net>
56 * disable recording but allow dsp to be opened read
57 * pull out most silly compat defines
58 * v0.02 - Nov 04 2000 - Zach Brown <zab@zabbo.net>
59 * changed clocking setup for m3, slowdown fixed.
60 * codec reset is hopefully reliable now
61 * rudimentary apm/power management makes suspend/resume work
62 * v0.01 - Oct 31 2000 - Zach Brown <zab@zabbo.net>
63 * first release
64 * v0.00 - Sep 09 2000 - Zach Brown <zab@zabbo.net>
65 * first pass derivation from maestro.c
66 *
67 * TODO
68 * in/out allocated contiguously so fullduplex mmap will work?
69 * no beep on init (mute)
70 * resetup msrc data memory if freq changes?
71 *
72 * --
73 *
74 * Allow me to ramble a bit about the m3 architecture. The core of the
75 * chip is the 'assp', the custom ESS dsp that runs the show. It has
76 * a small amount of code and data ram. ESS drops binary dsp code images
77 * on our heads, but we don't get to see specs on the dsp.
78 *
79 * The constant piece of code on the dsp is the 'kernel'. It also has a
80 * chunk of the dsp memory that is statically set aside for its control
81 * info. This is the KDATA defines in maestro3.h. Part of its core
82 * data is a list of code addresses that point to the pieces of DSP code
83 * that it should walk through in its loop. These other pieces of code
84 * do the real work. The kernel presumably jumps into each of them in turn.
85 * These code images tend to have their own data area, and one can have
86 * multiple data areas representing different states for each of the 'client
87 * instance' code portions. There is generally a list in the kernel data
88 * that points to the data instances for a given piece of code.
89 *
90 * We've only been given the binary image for the 'minisrc', mini sample
91 * rate converter. This is rather annoying because it limits the work
92 * we can do on the dsp, but it also greatly simplifies the job of managing
93 * dsp data memory for the code and data for our playing streams :). We
94 * statically allocate the minisrc code into a region we 'know' to be free
95 * based on the map of the binary kernel image we're loading. We also
96 * statically allocate the data areas for the maximum number of pcm streams
97 * we can be dealing with. This max is set by the length of the static list
98 * in the kernel data that records the number of minisrc data regions we
99 * can have. Thats right, all software dsp mixing with static code list
100 * limits. Rock.
101 *
102 * How sound goes in and out is still a relative mystery. It appears
103 * that the dsp has the ability to get input and output through various
104 * 'connections'. To do IO from or to a connection, you put the address
105 * of the minisrc client area in the static kernel data lists for that
106 * input or output. so for pcm -> dsp -> mixer, we put the minisrc data
107 * instance in the DMA list and also in the list for the mixer. I guess
108 * it Just Knows which is in/out, and we give some dma control info that
109 * helps. There are all sorts of cool inputs/outputs that it seems we can't
110 * use without dsp code images that know how to use them.
111 *
112 * So at init time we preload all the memory allocation stuff and set some
113 * system wide parameters. When we really get a sound to play we build
114 * up its minisrc header (stream parameters, buffer addresses, input/output
115 * settings). Then we throw its header on the various lists. We also
116 * tickle some KDATA settings that ask the assp to raise clock interrupts
117 * and do some amount of software mixing before handing data to the ac97.
118 *
119 * Sorry for the vague details. Feel free to ask Eric or myself if you
120 * happen to be trying to use this driver elsewhere. Please accept my
121 * apologies for the quality of the OSS support code, its passed through
122 * too many hands now and desperately wants to be rethought.
123 */
124
125 /*****************************************************************************/
126
127 #include <linux/module.h>
128 #include <linux/kernel.h>
129 #include <linux/string.h>
130 #include <linux/ctype.h>
131 #include <linux/ioport.h>
132 #include <linux/sched.h>
133 #include <linux/delay.h>
134 #include <linux/sound.h>
135 #include <linux/slab.h>
136 #include <linux/soundcard.h>
137 #include <linux/pci.h>
138 #include <linux/vmalloc.h>
139 #include <linux/init.h>
140 #include <linux/interrupt.h>
141 #include <linux/poll.h>
142 #include <linux/reboot.h>
143 #include <linux/spinlock.h>
144 #include <linux/ac97_codec.h>
145 #include <linux/wait.h>
146 #include <linux/mutex.h>
147
148
149 #include <asm/io.h>
150 #include <asm/dma.h>
151 #include <asm/uaccess.h>
152
153 #include "maestro3.h"
154
155 #define M_DEBUG 1
156
157 #define DRIVER_VERSION "1.23"
158 #define M3_MODULE_NAME "maestro3"
159 #define PFX M3_MODULE_NAME ": "
160
161 #define M3_STATE_MAGIC 0x734d724d
162 #define M3_CARD_MAGIC 0x646e6f50
163
164 #define ESS_FMT_STEREO 0x01
165 #define ESS_FMT_16BIT 0x02
166 #define ESS_FMT_MASK 0x03
167 #define ESS_DAC_SHIFT 0
168 #define ESS_ADC_SHIFT 4
169
170 #define DAC_RUNNING 1
171 #define ADC_RUNNING 2
172
173 #define SND_DEV_DSP16 5
174
175 #ifdef M_DEBUG
176 static int debug;
177 #define DPMOD 1 /* per module load */
178 #define DPSTR 2 /* per 'stream' */
179 #define DPSYS 3 /* per syscall */
180 #define DPCRAP 4 /* stuff the user shouldn't see unless they're really debuggin */
181 #define DPINT 5 /* per interrupt, LOTS */
182 #define DPRINTK(DP, args...) {if (debug >= (DP)) printk(KERN_DEBUG PFX args);}
183 #else
184 #define DPRINTK(x)
185 #endif
186
187 struct m3_list {
188 int curlen;
189 u16 mem_addr;
190 int max;
191 };
192
193 static int external_amp = 1;
194 static int gpio_pin = -1;
195
196 struct m3_state {
197 unsigned int magic;
198 struct m3_card *card;
199 unsigned char fmt, enable;
200
201 int index;
202
203 /* this locks around the oss state in the driver */
204 /* no, this lock is removed - only use card->lock */
205 /* otherwise: against what are you protecting on SMP
206 when irqhandler uses s->lock
207 and m3_assp_read uses card->lock ?
208 */
209 struct mutex open_mutex;
210 wait_queue_head_t open_wait;
211 mode_t open_mode;
212
213 int dev_audio;
214
215 struct assp_instance {
216 u16 code, data;
217 } dac_inst, adc_inst;
218
219 /* should be in dmabuf */
220 unsigned int rateadc, ratedac;
221
222 struct dmabuf {
223 void *rawbuf;
224 unsigned buforder;
225 unsigned numfrag;
226 unsigned fragshift;
227 unsigned hwptr, swptr;
228 unsigned total_bytes;
229 int count;
230 unsigned error; /* over/underrun */
231 wait_queue_head_t wait;
232 /* redundant, but makes calculations easier */
233 unsigned fragsize;
234 unsigned dmasize;
235 unsigned fragsamples;
236 /* OSS stuff */
237 unsigned mapped:1;
238 unsigned ready:1;
239 unsigned endcleared:1;
240 unsigned ossfragshift;
241 int ossmaxfrags;
242 unsigned subdivision;
243 /* new in m3 */
244 int mixer_index, dma_index, msrc_index, adc1_index;
245 int in_lists;
246 /* 2.4.. */
247 dma_addr_t handle;
248
249 } dma_dac, dma_adc;
250 };
251
252 struct m3_card {
253 unsigned int magic;
254
255 struct m3_card *next;
256
257 struct ac97_codec *ac97;
258 spinlock_t ac97_lock;
259
260 int card_type;
261
262 #define NR_DSPS 1
263 #define MAX_DSPS NR_DSPS
264 struct m3_state channels[MAX_DSPS];
265
266 /* this locks around the physical registers on the card */
267 spinlock_t lock;
268
269 /* hardware resources */
270 struct pci_dev *pcidev;
271 u32 iobase;
272 u32 irq;
273
274 int dacs_active;
275
276 int timer_users;
277
278 struct m3_list msrc_list,
279 mixer_list,
280 adc1_list,
281 dma_list;
282
283 /* for storing reset state..*/
284 u8 reset_state;
285
286 u16 *suspend_mem;
287 int in_suspend;
288 wait_queue_head_t suspend_queue;
289 };
290
291 /*
292 * an arbitrary volume we set the internal
293 * volume settings to so that the ac97 volume
294 * range is a little less insane. 0x7fff is
295 * max.
296 */
297 #define ARB_VOLUME ( 0x6800 )
298
299 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
300
301 enum {
302 ESS_ALLEGRO,
303 ESS_MAESTRO3,
304 /*
305 * a maestro3 with 'hardware strapping', only
306 * found inside ESS?
307 */
308 ESS_MAESTRO3HW,
309 };
310
311 static char *card_names[] = {
312 [ESS_ALLEGRO] = "Allegro",
313 [ESS_MAESTRO3] = "Maestro3(i)",
314 [ESS_MAESTRO3HW] = "Maestro3(i)hw"
315 };
316
317 #ifndef PCI_VENDOR_ESS
318 #define PCI_VENDOR_ESS 0x125D
319 #endif
320
321 #define M3_DEVICE(DEV, TYPE) \
322 { \
323 .vendor = PCI_VENDOR_ESS, \
324 .device = DEV, \
325 .subvendor = PCI_ANY_ID, \
326 .subdevice = PCI_ANY_ID, \
327 .class = PCI_CLASS_MULTIMEDIA_AUDIO << 8, \
328 .class_mask = 0xffff << 8, \
329 .driver_data = TYPE, \
330 }
331
332 static struct pci_device_id m3_id_table[] = {
333 M3_DEVICE(0x1988, ESS_ALLEGRO),
334 M3_DEVICE(0x1998, ESS_MAESTRO3),
335 M3_DEVICE(0x199a, ESS_MAESTRO3HW),
336 {0,}
337 };
338
339 MODULE_DEVICE_TABLE (pci, m3_id_table);
340
341 /*
342 * reports seem to indicate that the m3 is limited
343 * to 28bit bus addresses. aaaargggh...
344 */
345 #define M3_PCI_DMA_MASK 0x0fffffff
346
347 static unsigned
348 ld2(unsigned int x)
349 {
350 unsigned r = 0;
351
352 if (x >= 0x10000) {
353 x >>= 16;
354 r += 16;
355 }
356 if (x >= 0x100) {
357 x >>= 8;
358 r += 8;
359 }
360 if (x >= 0x10) {
361 x >>= 4;
362 r += 4;
363 }
364 if (x >= 4) {
365 x >>= 2;
366 r += 2;
367 }
368 if (x >= 2)
369 r++;
370 return r;
371 }
372
373 static struct m3_card *devs;
374
375 /*
376 * I'm not very good at laying out functions in a file :)
377 */
378 static int m3_notifier(struct notifier_block *nb, unsigned long event, void *buf);
379 static int m3_suspend(struct pci_dev *pci_dev, pm_message_t state);
380 static void check_suspend(struct m3_card *card);
381
382 static struct notifier_block m3_reboot_nb = {
383 .notifier_call = m3_notifier,
384 };
385
386 static void m3_outw(struct m3_card *card,
387 u16 value, unsigned long reg)
388 {
389 check_suspend(card);
390 outw(value, card->iobase + reg);
391 }
392
393 static u16 m3_inw(struct m3_card *card, unsigned long reg)
394 {
395 check_suspend(card);
396 return inw(card->iobase + reg);
397 }
398 static void m3_outb(struct m3_card *card,
399 u8 value, unsigned long reg)
400 {
401 check_suspend(card);
402 outb(value, card->iobase + reg);
403 }
404 static u8 m3_inb(struct m3_card *card, unsigned long reg)
405 {
406 check_suspend(card);
407 return inb(card->iobase + reg);
408 }
409
410 /*
411 * access 16bit words to the code or data regions of the dsp's memory.
412 * index addresses 16bit words.
413 */
414 static u16 __m3_assp_read(struct m3_card *card, u16 region, u16 index)
415 {
416 m3_outw(card, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
417 m3_outw(card, index, DSP_PORT_MEMORY_INDEX);
418 return m3_inw(card, DSP_PORT_MEMORY_DATA);
419 }
420 static u16 m3_assp_read(struct m3_card *card, u16 region, u16 index)
421 {
422 unsigned long flags;
423 u16 ret;
424
425 spin_lock_irqsave(&(card->lock), flags);
426 ret = __m3_assp_read(card, region, index);
427 spin_unlock_irqrestore(&(card->lock), flags);
428
429 return ret;
430 }
431
432 static void __m3_assp_write(struct m3_card *card,
433 u16 region, u16 index, u16 data)
434 {
435 m3_outw(card, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
436 m3_outw(card, index, DSP_PORT_MEMORY_INDEX);
437 m3_outw(card, data, DSP_PORT_MEMORY_DATA);
438 }
439 static void m3_assp_write(struct m3_card *card,
440 u16 region, u16 index, u16 data)
441 {
442 unsigned long flags;
443
444 spin_lock_irqsave(&(card->lock), flags);
445 __m3_assp_write(card, region, index, data);
446 spin_unlock_irqrestore(&(card->lock), flags);
447 }
448
449 static void m3_assp_halt(struct m3_card *card)
450 {
451 card->reset_state = m3_inb(card, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
452 mdelay(10);
453 m3_outb(card, card->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
454 }
455
456 static void m3_assp_continue(struct m3_card *card)
457 {
458 m3_outb(card, card->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
459 }
460
461 /*
462 * This makes me sad. the maestro3 has lists
463 * internally that must be packed.. 0 terminates,
464 * apparently, or maybe all unused entries have
465 * to be 0, the lists have static lengths set
466 * by the binary code images.
467 */
468
469 static int m3_add_list(struct m3_card *card,
470 struct m3_list *list, u16 val)
471 {
472 DPRINTK(DPSTR, "adding val 0x%x to list 0x%p at pos %d\n",
473 val, list, list->curlen);
474
475 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
476 list->mem_addr + list->curlen,
477 val);
478
479 return list->curlen++;
480
481 }
482
483 static void m3_remove_list(struct m3_card *card,
484 struct m3_list *list, int index)
485 {
486 u16 val;
487 int lastindex = list->curlen - 1;
488
489 DPRINTK(DPSTR, "removing ind %d from list 0x%p\n",
490 index, list);
491
492 if(index != lastindex) {
493 val = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
494 list->mem_addr + lastindex);
495 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
496 list->mem_addr + index,
497 val);
498 }
499
500 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
501 list->mem_addr + lastindex,
502 0);
503
504 list->curlen--;
505 }
506
507 static void set_fmt(struct m3_state *s, unsigned char mask, unsigned char data)
508 {
509 int tmp;
510
511 s->fmt = (s->fmt & mask) | data;
512
513 tmp = (s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK;
514
515 /* write to 'mono' word */
516 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
517 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 1,
518 (tmp & ESS_FMT_STEREO) ? 0 : 1);
519 /* write to '8bit' word */
520 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
521 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 2,
522 (tmp & ESS_FMT_16BIT) ? 0 : 1);
523
524 tmp = (s->fmt >> ESS_ADC_SHIFT) & ESS_FMT_MASK;
525
526 /* write to 'mono' word */
527 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
528 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 1,
529 (tmp & ESS_FMT_STEREO) ? 0 : 1);
530 /* write to '8bit' word */
531 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
532 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 2,
533 (tmp & ESS_FMT_16BIT) ? 0 : 1);
534 }
535
536 static void set_dac_rate(struct m3_state *s, unsigned int rate)
537 {
538 u32 freq;
539
540 if (rate > 48000)
541 rate = 48000;
542 if (rate < 8000)
543 rate = 8000;
544
545 s->ratedac = rate;
546
547 freq = ((rate << 15) + 24000 ) / 48000;
548 if(freq)
549 freq--;
550
551 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
552 s->dac_inst.data + CDATA_FREQUENCY,
553 freq);
554 }
555
556 static void set_adc_rate(struct m3_state *s, unsigned int rate)
557 {
558 u32 freq;
559
560 if (rate > 48000)
561 rate = 48000;
562 if (rate < 8000)
563 rate = 8000;
564
565 s->rateadc = rate;
566
567 freq = ((rate << 15) + 24000 ) / 48000;
568 if(freq)
569 freq--;
570
571 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
572 s->adc_inst.data + CDATA_FREQUENCY,
573 freq);
574 }
575
576 static void inc_timer_users(struct m3_card *card)
577 {
578 unsigned long flags;
579
580 spin_lock_irqsave(&card->lock, flags);
581
582 card->timer_users++;
583 DPRINTK(DPSYS, "inc timer users now %d\n",
584 card->timer_users);
585 if(card->timer_users != 1)
586 goto out;
587
588 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
589 KDATA_TIMER_COUNT_RELOAD,
590 240 ) ;
591
592 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
593 KDATA_TIMER_COUNT_CURRENT,
594 240 ) ;
595
596 m3_outw(card,
597 m3_inw(card, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
598 HOST_INT_CTRL);
599 out:
600 spin_unlock_irqrestore(&card->lock, flags);
601 }
602
603 static void dec_timer_users(struct m3_card *card)
604 {
605 unsigned long flags;
606
607 spin_lock_irqsave(&card->lock, flags);
608
609 card->timer_users--;
610 DPRINTK(DPSYS, "dec timer users now %d\n",
611 card->timer_users);
612 if(card->timer_users > 0 )
613 goto out;
614
615 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
616 KDATA_TIMER_COUNT_RELOAD,
617 0 ) ;
618
619 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
620 KDATA_TIMER_COUNT_CURRENT,
621 0 ) ;
622
623 m3_outw(card, m3_inw(card, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
624 HOST_INT_CTRL);
625 out:
626 spin_unlock_irqrestore(&card->lock, flags);
627 }
628
629 /*
630 * {start,stop}_{adc,dac} should be called
631 * while holding the 'state' lock and they
632 * will try to grab the 'card' lock..
633 */
634 static void stop_adc(struct m3_state *s)
635 {
636 if (! (s->enable & ADC_RUNNING))
637 return;
638
639 s->enable &= ~ADC_RUNNING;
640 dec_timer_users(s->card);
641
642 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
643 s->adc_inst.data + CDATA_INSTANCE_READY, 0);
644
645 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
646 KDATA_ADC1_REQUEST, 0);
647 }
648
649 static void stop_dac(struct m3_state *s)
650 {
651 if (! (s->enable & DAC_RUNNING))
652 return;
653
654 DPRINTK(DPSYS, "stop_dac()\n");
655
656 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
657 s->dac_inst.data + CDATA_INSTANCE_READY, 0);
658
659 s->enable &= ~DAC_RUNNING;
660 s->card->dacs_active--;
661 dec_timer_users(s->card);
662
663 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
664 KDATA_MIXER_TASK_NUMBER,
665 s->card->dacs_active ) ;
666 }
667
668 static void start_dac(struct m3_state *s)
669 {
670 if( (!s->dma_dac.mapped && s->dma_dac.count < 1) ||
671 !s->dma_dac.ready ||
672 (s->enable & DAC_RUNNING))
673 return;
674
675 DPRINTK(DPSYS, "start_dac()\n");
676
677 s->enable |= DAC_RUNNING;
678 s->card->dacs_active++;
679 inc_timer_users(s->card);
680
681 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
682 s->dac_inst.data + CDATA_INSTANCE_READY, 1);
683
684 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
685 KDATA_MIXER_TASK_NUMBER,
686 s->card->dacs_active ) ;
687 }
688
689 static void start_adc(struct m3_state *s)
690 {
691 if ((! s->dma_adc.mapped &&
692 s->dma_adc.count >= (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
693 || !s->dma_adc.ready
694 || (s->enable & ADC_RUNNING) )
695 return;
696
697 DPRINTK(DPSYS, "start_adc()\n");
698
699 s->enable |= ADC_RUNNING;
700 inc_timer_users(s->card);
701
702 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
703 KDATA_ADC1_REQUEST, 1);
704
705 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
706 s->adc_inst.data + CDATA_INSTANCE_READY, 1);
707 }
708
709 static struct play_vals {
710 u16 addr, val;
711 } pv[] = {
712 {CDATA_LEFT_VOLUME, ARB_VOLUME},
713 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
714 {SRC3_DIRECTION_OFFSET, 0} ,
715 /* +1, +2 are stereo/16 bit */
716 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
717 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
718 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
719 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
720 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
721 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
722 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
723 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
724 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
725 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
726 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
727 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
728 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
729 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
730 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
731 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
732 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
733 };
734
735
736 /* the mode passed should be already shifted and masked */
737 static void m3_play_setup(struct m3_state *s, int mode, u32 rate, void *buffer, int size)
738 {
739 int dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
740 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
741 int dsp_in_buffer = s->dac_inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
742 int dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
743 struct dmabuf *db = &s->dma_dac;
744 int i;
745
746 DPRINTK(DPSTR, "mode=%d rate=%d buf=%p len=%d.\n",
747 mode, rate, buffer, size);
748
749 #define LO(x) ((x) & 0xffff)
750 #define HI(x) LO((x) >> 16)
751
752 /* host dma buffer pointers */
753
754 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
755 s->dac_inst.data + CDATA_HOST_SRC_ADDRL,
756 LO(virt_to_bus(buffer)));
757
758 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
759 s->dac_inst.data + CDATA_HOST_SRC_ADDRH,
760 HI(virt_to_bus(buffer)));
761
762 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
763 s->dac_inst.data + CDATA_HOST_SRC_END_PLUS_1L,
764 LO(virt_to_bus(buffer) + size));
765
766 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
767 s->dac_inst.data + CDATA_HOST_SRC_END_PLUS_1H,
768 HI(virt_to_bus(buffer) + size));
769
770 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
771 s->dac_inst.data + CDATA_HOST_SRC_CURRENTL,
772 LO(virt_to_bus(buffer)));
773
774 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
775 s->dac_inst.data + CDATA_HOST_SRC_CURRENTH,
776 HI(virt_to_bus(buffer)));
777 #undef LO
778 #undef HI
779
780 /* dsp buffers */
781
782 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
783 s->dac_inst.data + CDATA_IN_BUF_BEGIN,
784 dsp_in_buffer);
785
786 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
787 s->dac_inst.data + CDATA_IN_BUF_END_PLUS_1,
788 dsp_in_buffer + (dsp_in_size / 2));
789
790 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
791 s->dac_inst.data + CDATA_IN_BUF_HEAD,
792 dsp_in_buffer);
793
794 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
795 s->dac_inst.data + CDATA_IN_BUF_TAIL,
796 dsp_in_buffer);
797
798 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
799 s->dac_inst.data + CDATA_OUT_BUF_BEGIN,
800 dsp_out_buffer);
801
802 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
803 s->dac_inst.data + CDATA_OUT_BUF_END_PLUS_1,
804 dsp_out_buffer + (dsp_out_size / 2));
805
806 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
807 s->dac_inst.data + CDATA_OUT_BUF_HEAD,
808 dsp_out_buffer);
809
810 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
811 s->dac_inst.data + CDATA_OUT_BUF_TAIL,
812 dsp_out_buffer);
813
814 /*
815 * some per client initializers
816 */
817
818 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
819 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 12,
820 s->dac_inst.data + 40 + 8);
821
822 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
823 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 19,
824 s->dac_inst.code + MINISRC_COEF_LOC);
825
826 /* enable or disable low pass filter? */
827 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
828 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 22,
829 s->ratedac > 45000 ? 0xff : 0 );
830
831 /* tell it which way dma is going? */
832 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
833 s->dac_inst.data + CDATA_DMA_CONTROL,
834 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
835
836 /*
837 * set an armload of static initializers
838 */
839 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++)
840 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
841 s->dac_inst.data + pv[i].addr, pv[i].val);
842
843 /*
844 * put us in the lists if we're not already there
845 */
846
847 if(db->in_lists == 0) {
848
849 db->msrc_index = m3_add_list(s->card, &s->card->msrc_list,
850 s->dac_inst.data >> DP_SHIFT_COUNT);
851
852 db->dma_index = m3_add_list(s->card, &s->card->dma_list,
853 s->dac_inst.data >> DP_SHIFT_COUNT);
854
855 db->mixer_index = m3_add_list(s->card, &s->card->mixer_list,
856 s->dac_inst.data >> DP_SHIFT_COUNT);
857
858 db->in_lists = 1;
859 }
860
861 set_dac_rate(s,rate);
862 start_dac(s);
863 }
864
865 /*
866 * Native record driver
867 */
868 static struct rec_vals {
869 u16 addr, val;
870 } rv[] = {
871 {CDATA_LEFT_VOLUME, ARB_VOLUME},
872 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
873 {SRC3_DIRECTION_OFFSET, 1} ,
874 /* +1, +2 are stereo/16 bit */
875 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
876 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
877 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
878 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
879 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
880 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
881 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
882 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
883 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
884 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
885 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
886 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
887 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
888 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
889 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
890 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
891 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
892 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
893 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
894 };
895
896 /* again, passed mode is alrady shifted/masked */
897 static void m3_rec_setup(struct m3_state *s, int mode, u32 rate, void *buffer, int size)
898 {
899 int dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
900 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
901 int dsp_in_buffer = s->adc_inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
902 int dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
903 struct dmabuf *db = &s->dma_adc;
904 int i;
905
906 DPRINTK(DPSTR, "rec_setup mode=%d rate=%d buf=%p len=%d.\n",
907 mode, rate, buffer, size);
908
909 #define LO(x) ((x) & 0xffff)
910 #define HI(x) LO((x) >> 16)
911
912 /* host dma buffer pointers */
913
914 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
915 s->adc_inst.data + CDATA_HOST_SRC_ADDRL,
916 LO(virt_to_bus(buffer)));
917
918 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
919 s->adc_inst.data + CDATA_HOST_SRC_ADDRH,
920 HI(virt_to_bus(buffer)));
921
922 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
923 s->adc_inst.data + CDATA_HOST_SRC_END_PLUS_1L,
924 LO(virt_to_bus(buffer) + size));
925
926 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
927 s->adc_inst.data + CDATA_HOST_SRC_END_PLUS_1H,
928 HI(virt_to_bus(buffer) + size));
929
930 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
931 s->adc_inst.data + CDATA_HOST_SRC_CURRENTL,
932 LO(virt_to_bus(buffer)));
933
934 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
935 s->adc_inst.data + CDATA_HOST_SRC_CURRENTH,
936 HI(virt_to_bus(buffer)));
937 #undef LO
938 #undef HI
939
940 /* dsp buffers */
941
942 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
943 s->adc_inst.data + CDATA_IN_BUF_BEGIN,
944 dsp_in_buffer);
945
946 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
947 s->adc_inst.data + CDATA_IN_BUF_END_PLUS_1,
948 dsp_in_buffer + (dsp_in_size / 2));
949
950 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
951 s->adc_inst.data + CDATA_IN_BUF_HEAD,
952 dsp_in_buffer);
953
954 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
955 s->adc_inst.data + CDATA_IN_BUF_TAIL,
956 dsp_in_buffer);
957
958 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
959 s->adc_inst.data + CDATA_OUT_BUF_BEGIN,
960 dsp_out_buffer);
961
962 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
963 s->adc_inst.data + CDATA_OUT_BUF_END_PLUS_1,
964 dsp_out_buffer + (dsp_out_size / 2));
965
966 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
967 s->adc_inst.data + CDATA_OUT_BUF_HEAD,
968 dsp_out_buffer);
969
970 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
971 s->adc_inst.data + CDATA_OUT_BUF_TAIL,
972 dsp_out_buffer);
973
974 /*
975 * some per client initializers
976 */
977
978 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
979 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 12,
980 s->adc_inst.data + 40 + 8);
981
982 /* tell it which way dma is going? */
983 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
984 s->adc_inst.data + CDATA_DMA_CONTROL,
985 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
986 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
987
988 /*
989 * set an armload of static initializers
990 */
991 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++)
992 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
993 s->adc_inst.data + rv[i].addr, rv[i].val);
994
995 /*
996 * put us in the lists if we're not already there
997 */
998
999 if(db->in_lists == 0) {
1000
1001 db->adc1_index = m3_add_list(s->card, &s->card->adc1_list,
1002 s->adc_inst.data >> DP_SHIFT_COUNT);
1003
1004 db->dma_index = m3_add_list(s->card, &s->card->dma_list,
1005 s->adc_inst.data >> DP_SHIFT_COUNT);
1006
1007 db->msrc_index = m3_add_list(s->card, &s->card->msrc_list,
1008 s->adc_inst.data >> DP_SHIFT_COUNT);
1009
1010 db->in_lists = 1;
1011 }
1012
1013 set_adc_rate(s,rate);
1014 start_adc(s);
1015 }
1016 /* --------------------------------------------------------------------- */
1017
1018 static void set_dmaa(struct m3_state *s, unsigned int addr, unsigned int count)
1019 {
1020 DPRINTK(DPINT,"set_dmaa??\n");
1021 }
1022
1023 static void set_dmac(struct m3_state *s, unsigned int addr, unsigned int count)
1024 {
1025 DPRINTK(DPINT,"set_dmac??\n");
1026 }
1027
1028 static u32 get_dma_pos(struct m3_card *card,
1029 int instance_addr)
1030 {
1031 u16 hi = 0, lo = 0;
1032 int retry = 10;
1033
1034 /*
1035 * try and get a valid answer
1036 */
1037 while(retry--) {
1038 hi = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1039 instance_addr + CDATA_HOST_SRC_CURRENTH);
1040
1041 lo = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1042 instance_addr + CDATA_HOST_SRC_CURRENTL);
1043
1044 if(hi == m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1045 instance_addr + CDATA_HOST_SRC_CURRENTH))
1046 break;
1047 }
1048 return lo | (hi<<16);
1049 }
1050
1051 static u32 get_dmaa(struct m3_state *s)
1052 {
1053 u32 offset;
1054
1055 offset = get_dma_pos(s->card, s->dac_inst.data) -
1056 virt_to_bus(s->dma_dac.rawbuf);
1057
1058 DPRINTK(DPINT,"get_dmaa: 0x%08x\n",offset);
1059
1060 return offset;
1061 }
1062
1063 static u32 get_dmac(struct m3_state *s)
1064 {
1065 u32 offset;
1066
1067 offset = get_dma_pos(s->card, s->adc_inst.data) -
1068 virt_to_bus(s->dma_adc.rawbuf);
1069
1070 DPRINTK(DPINT,"get_dmac: 0x%08x\n",offset);
1071
1072 return offset;
1073
1074 }
1075
1076 static int
1077 prog_dmabuf(struct m3_state *s, unsigned rec)
1078 {
1079 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1080 unsigned rate = rec ? s->rateadc : s->ratedac;
1081 unsigned bytepersec;
1082 unsigned bufs;
1083 unsigned char fmt;
1084 unsigned long flags;
1085
1086 spin_lock_irqsave(&s->card->lock, flags);
1087
1088 fmt = s->fmt;
1089 if (rec) {
1090 stop_adc(s);
1091 fmt >>= ESS_ADC_SHIFT;
1092 } else {
1093 stop_dac(s);
1094 fmt >>= ESS_DAC_SHIFT;
1095 }
1096 fmt &= ESS_FMT_MASK;
1097
1098 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1099
1100 bytepersec = rate << sample_shift[fmt];
1101 bufs = PAGE_SIZE << db->buforder;
1102 if (db->ossfragshift) {
1103 if ((1000 << db->ossfragshift) < bytepersec)
1104 db->fragshift = ld2(bytepersec/1000);
1105 else
1106 db->fragshift = db->ossfragshift;
1107 } else {
1108 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1109 if (db->fragshift < 3)
1110 db->fragshift = 3;
1111 }
1112 db->numfrag = bufs >> db->fragshift;
1113 while (db->numfrag < 4 && db->fragshift > 3) {
1114 db->fragshift--;
1115 db->numfrag = bufs >> db->fragshift;
1116 }
1117 db->fragsize = 1 << db->fragshift;
1118 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1119 db->numfrag = db->ossmaxfrags;
1120 db->fragsamples = db->fragsize >> sample_shift[fmt];
1121 db->dmasize = db->numfrag << db->fragshift;
1122
1123 DPRINTK(DPSTR,"prog_dmabuf: numfrag: %d fragsize: %d dmasize: %d\n",db->numfrag,db->fragsize,db->dmasize);
1124
1125 memset(db->rawbuf, (fmt & ESS_FMT_16BIT) ? 0 : 0x80, db->dmasize);
1126
1127 if (rec)
1128 m3_rec_setup(s, fmt, s->rateadc, db->rawbuf, db->dmasize);
1129 else
1130 m3_play_setup(s, fmt, s->ratedac, db->rawbuf, db->dmasize);
1131
1132 db->ready = 1;
1133
1134 spin_unlock_irqrestore(&s->card->lock, flags);
1135
1136 return 0;
1137 }
1138
1139 static void clear_advance(struct m3_state *s)
1140 {
1141 unsigned char c = ((s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_16BIT) ? 0 : 0x80;
1142
1143 unsigned char *buf = s->dma_dac.rawbuf;
1144 unsigned bsize = s->dma_dac.dmasize;
1145 unsigned bptr = s->dma_dac.swptr;
1146 unsigned len = s->dma_dac.fragsize;
1147
1148 if (bptr + len > bsize) {
1149 unsigned x = bsize - bptr;
1150 memset(buf + bptr, c, x);
1151 /* account for wrapping? */
1152 bptr = 0;
1153 len -= x;
1154 }
1155 memset(buf + bptr, c, len);
1156 }
1157
1158 /* call with spinlock held! */
1159 static void m3_update_ptr(struct m3_state *s)
1160 {
1161 unsigned hwptr;
1162 int diff;
1163
1164 /* update ADC pointer */
1165 if (s->dma_adc.ready) {
1166 hwptr = get_dmac(s) % s->dma_adc.dmasize;
1167 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1168 s->dma_adc.hwptr = hwptr;
1169 s->dma_adc.total_bytes += diff;
1170 s->dma_adc.count += diff;
1171 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1172 wake_up(&s->dma_adc.wait);
1173 if (!s->dma_adc.mapped) {
1174 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1175 stop_adc(s);
1176 /* brute force everyone back in sync, sigh */
1177 s->dma_adc.count = 0;
1178 s->dma_adc.swptr = 0;
1179 s->dma_adc.hwptr = 0;
1180 s->dma_adc.error++;
1181 }
1182 }
1183 }
1184 /* update DAC pointer */
1185 if (s->dma_dac.ready) {
1186 hwptr = get_dmaa(s) % s->dma_dac.dmasize;
1187 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1188
1189 DPRINTK(DPINT,"updating dac: hwptr: %6d diff: %6d count: %6d\n",
1190 hwptr,diff,s->dma_dac.count);
1191
1192 s->dma_dac.hwptr = hwptr;
1193 s->dma_dac.total_bytes += diff;
1194
1195 if (s->dma_dac.mapped) {
1196
1197 s->dma_dac.count += diff;
1198 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize) {
1199 wake_up(&s->dma_dac.wait);
1200 }
1201 } else {
1202
1203 s->dma_dac.count -= diff;
1204
1205 if (s->dma_dac.count <= 0) {
1206 DPRINTK(DPCRAP,"underflow! diff: %d (0x%x) count: %d (0x%x) hw: %d (0x%x) sw: %d (0x%x)\n",
1207 diff, diff,
1208 s->dma_dac.count,
1209 s->dma_dac.count,
1210 hwptr, hwptr,
1211 s->dma_dac.swptr,
1212 s->dma_dac.swptr);
1213 stop_dac(s);
1214 /* brute force everyone back in sync, sigh */
1215 s->dma_dac.count = 0;
1216 s->dma_dac.swptr = hwptr;
1217 s->dma_dac.error++;
1218 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1219 clear_advance(s);
1220 s->dma_dac.endcleared = 1;
1221 }
1222 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize) {
1223 wake_up(&s->dma_dac.wait);
1224 DPRINTK(DPINT,"waking up DAC count: %d sw: %d hw: %d\n",
1225 s->dma_dac.count, s->dma_dac.swptr, hwptr);
1226 }
1227 }
1228 }
1229 }
1230
1231 static irqreturn_t m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1232 {
1233 struct m3_card *c = (struct m3_card *)dev_id;
1234 struct m3_state *s = &c->channels[0];
1235 u8 status;
1236
1237 status = inb(c->iobase+0x1A);
1238
1239 if(status == 0xff)
1240 return IRQ_NONE;
1241
1242 /* presumably acking the ints? */
1243 outw(status, c->iobase+0x1A);
1244
1245 if(c->in_suspend)
1246 return IRQ_HANDLED;
1247
1248 /*
1249 * ack an assp int if its running
1250 * and has an int pending
1251 */
1252 if( status & ASSP_INT_PENDING) {
1253 u8 ctl = inb(c->iobase + ASSP_CONTROL_B);
1254 if( !(ctl & STOP_ASSP_CLOCK)) {
1255 ctl = inb(c->iobase + ASSP_HOST_INT_STATUS );
1256 if(ctl & DSP2HOST_REQ_TIMER) {
1257 outb( DSP2HOST_REQ_TIMER, c->iobase + ASSP_HOST_INT_STATUS);
1258 /* update adc/dac info if it was a timer int */
1259 spin_lock(&c->lock);
1260 m3_update_ptr(s);
1261 spin_unlock(&c->lock);
1262 }
1263 }
1264 }
1265
1266 /* XXX is this needed? */
1267 if(status & 0x40)
1268 outb(0x40, c->iobase+0x1A);
1269 return IRQ_HANDLED;
1270 }
1271
1272
1273 /* --------------------------------------------------------------------- */
1274
1275 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value in %s\n";
1276
1277 #define VALIDATE_MAGIC(FOO,MAG) \
1278 ({ \
1279 if (!(FOO) || (FOO)->magic != MAG) { \
1280 printk(invalid_magic,__FUNCTION__); \
1281 return -ENXIO; \
1282 } \
1283 })
1284
1285 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,M3_STATE_MAGIC)
1286 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,M3_CARD_MAGIC)
1287
1288 /* --------------------------------------------------------------------- */
1289
1290 static int drain_dac(struct m3_state *s, int nonblock)
1291 {
1292 DECLARE_WAITQUEUE(wait,current);
1293 unsigned long flags;
1294 int count;
1295 signed long tmo;
1296
1297 if (s->dma_dac.mapped || !s->dma_dac.ready)
1298 return 0;
1299 set_current_state(TASK_INTERRUPTIBLE);
1300 add_wait_queue(&s->dma_dac.wait, &wait);
1301 for (;;) {
1302 spin_lock_irqsave(&s->card->lock, flags);
1303 count = s->dma_dac.count;
1304 spin_unlock_irqrestore(&s->card->lock, flags);
1305 if (count <= 0)
1306 break;
1307 if (signal_pending(current))
1308 break;
1309 if (nonblock) {
1310 remove_wait_queue(&s->dma_dac.wait, &wait);
1311 set_current_state(TASK_RUNNING);
1312 return -EBUSY;
1313 }
1314 tmo = (count * HZ) / s->ratedac;
1315 tmo >>= sample_shift[(s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK];
1316 /* XXX this is just broken. someone is waking us up alot, or schedule_timeout is broken.
1317 or something. who cares. - zach */
1318 if (!schedule_timeout(tmo ? tmo : 1) && tmo)
1319 DPRINTK(DPCRAP,"dma timed out?? %ld\n",jiffies);
1320 }
1321 remove_wait_queue(&s->dma_dac.wait, &wait);
1322 set_current_state(TASK_RUNNING);
1323 if (signal_pending(current))
1324 return -ERESTARTSYS;
1325 return 0;
1326 }
1327
1328 static ssize_t m3_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1329 {
1330 struct m3_state *s = (struct m3_state *)file->private_data;
1331 ssize_t ret;
1332 unsigned long flags;
1333 unsigned swptr;
1334 int cnt;
1335
1336 VALIDATE_STATE(s);
1337 if (s->dma_adc.mapped)
1338 return -ENXIO;
1339 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1340 return ret;
1341 if (!access_ok(VERIFY_WRITE, buffer, count))
1342 return -EFAULT;
1343 ret = 0;
1344
1345 spin_lock_irqsave(&s->card->lock, flags);
1346
1347 while (count > 0) {
1348 int timed_out;
1349
1350 swptr = s->dma_adc.swptr;
1351 cnt = s->dma_adc.dmasize-swptr;
1352 if (s->dma_adc.count < cnt)
1353 cnt = s->dma_adc.count;
1354
1355 if (cnt > count)
1356 cnt = count;
1357
1358 if (cnt <= 0) {
1359 start_adc(s);
1360 if (file->f_flags & O_NONBLOCK)
1361 {
1362 ret = ret ? ret : -EAGAIN;
1363 goto out;
1364 }
1365
1366 spin_unlock_irqrestore(&s->card->lock, flags);
1367 timed_out = interruptible_sleep_on_timeout(&s->dma_adc.wait, HZ) == 0;
1368 spin_lock_irqsave(&s->card->lock, flags);
1369
1370 if(timed_out) {
1371 printk("read: chip lockup? dmasz %u fragsz %u count %u hwptr %u swptr %u\n",
1372 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1373 s->dma_adc.hwptr, s->dma_adc.swptr);
1374 stop_adc(s);
1375 set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
1376 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1377 }
1378 if (signal_pending(current))
1379 {
1380 ret = ret ? ret : -ERESTARTSYS;
1381 goto out;
1382 }
1383 continue;
1384 }
1385
1386 spin_unlock_irqrestore(&s->card->lock, flags);
1387 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1388 ret = ret ? ret : -EFAULT;
1389 return ret;
1390 }
1391 spin_lock_irqsave(&s->card->lock, flags);
1392
1393 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1394 s->dma_adc.swptr = swptr;
1395 s->dma_adc.count -= cnt;
1396 count -= cnt;
1397 buffer += cnt;
1398 ret += cnt;
1399 start_adc(s);
1400 }
1401
1402 out:
1403 spin_unlock_irqrestore(&s->card->lock, flags);
1404 return ret;
1405 }
1406
1407 static ssize_t m3_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1408 {
1409 struct m3_state *s = (struct m3_state *)file->private_data;
1410 ssize_t ret;
1411 unsigned long flags;
1412 unsigned swptr;
1413 int cnt;
1414
1415 VALIDATE_STATE(s);
1416 if (s->dma_dac.mapped)
1417 return -ENXIO;
1418 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1419 return ret;
1420 if (!access_ok(VERIFY_READ, buffer, count))
1421 return -EFAULT;
1422 ret = 0;
1423
1424 spin_lock_irqsave(&s->card->lock, flags);
1425
1426 while (count > 0) {
1427 int timed_out;
1428
1429 if (s->dma_dac.count < 0) {
1430 s->dma_dac.count = 0;
1431 s->dma_dac.swptr = s->dma_dac.hwptr;
1432 }
1433 swptr = s->dma_dac.swptr;
1434
1435 cnt = s->dma_dac.dmasize-swptr;
1436
1437 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1438 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1439
1440
1441 if (cnt > count)
1442 cnt = count;
1443
1444 if (cnt <= 0) {
1445 start_dac(s);
1446 if (file->f_flags & O_NONBLOCK) {
1447 if(!ret) ret = -EAGAIN;
1448 goto out;
1449 }
1450 spin_unlock_irqrestore(&s->card->lock, flags);
1451 timed_out = interruptible_sleep_on_timeout(&s->dma_dac.wait, HZ) == 0;
1452 spin_lock_irqsave(&s->card->lock, flags);
1453 if(timed_out) {
1454 DPRINTK(DPCRAP,"write: chip lockup? dmasz %u fragsz %u count %u hwptr %u swptr %u\n",
1455 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
1456 s->dma_dac.hwptr, s->dma_dac.swptr);
1457 stop_dac(s);
1458 set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
1459 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
1460 }
1461 if (signal_pending(current)) {
1462 if (!ret) ret = -ERESTARTSYS;
1463 goto out;
1464 }
1465 continue;
1466 }
1467 spin_unlock_irqrestore(&s->card->lock, flags);
1468 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1469 if (!ret) ret = -EFAULT;
1470 return ret;
1471 }
1472 spin_lock_irqsave(&s->card->lock, flags);
1473
1474 DPRINTK(DPSYS,"wrote %6d bytes at sw: %6d cnt: %6d while hw: %6d\n",
1475 cnt, swptr, s->dma_dac.count, s->dma_dac.hwptr);
1476
1477 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1478
1479 s->dma_dac.swptr = swptr;
1480 s->dma_dac.count += cnt;
1481 s->dma_dac.endcleared = 0;
1482 count -= cnt;
1483 buffer += cnt;
1484 ret += cnt;
1485 start_dac(s);
1486 }
1487 out:
1488 spin_unlock_irqrestore(&s->card->lock, flags);
1489 return ret;
1490 }
1491
1492 static unsigned int m3_poll(struct file *file, struct poll_table_struct *wait)
1493 {
1494 struct m3_state *s = (struct m3_state *)file->private_data;
1495 unsigned long flags;
1496 unsigned int mask = 0;
1497
1498 VALIDATE_STATE(s);
1499 if (file->f_mode & FMODE_WRITE)
1500 poll_wait(file, &s->dma_dac.wait, wait);
1501 if (file->f_mode & FMODE_READ)
1502 poll_wait(file, &s->dma_adc.wait, wait);
1503
1504 spin_lock_irqsave(&s->card->lock, flags);
1505 m3_update_ptr(s);
1506
1507 if (file->f_mode & FMODE_READ) {
1508 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1509 mask |= POLLIN | POLLRDNORM;
1510 }
1511 if (file->f_mode & FMODE_WRITE) {
1512 if (s->dma_dac.mapped) {
1513 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1514 mask |= POLLOUT | POLLWRNORM;
1515 } else {
1516 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
1517 mask |= POLLOUT | POLLWRNORM;
1518 }
1519 }
1520
1521 spin_unlock_irqrestore(&s->card->lock, flags);
1522 return mask;
1523 }
1524
1525 static int m3_mmap(struct file *file, struct vm_area_struct *vma)
1526 {
1527 struct m3_state *s = (struct m3_state *)file->private_data;
1528 unsigned long max_size, size, start, offset;
1529 struct dmabuf *db;
1530 int ret = -EINVAL;
1531
1532 VALIDATE_STATE(s);
1533 if (vma->vm_flags & VM_WRITE) {
1534 if ((ret = prog_dmabuf(s, 0)) != 0)
1535 return ret;
1536 db = &s->dma_dac;
1537 } else
1538 if (vma->vm_flags & VM_READ) {
1539 if ((ret = prog_dmabuf(s, 1)) != 0)
1540 return ret;
1541 db = &s->dma_adc;
1542 } else
1543 return -EINVAL;
1544
1545 max_size = db->dmasize;
1546
1547 start = vma->vm_start;
1548 offset = (vma->vm_pgoff << PAGE_SHIFT);
1549 size = vma->vm_end - vma->vm_start;
1550
1551 if(size > max_size)
1552 goto out;
1553 if(offset > max_size - size)
1554 goto out;
1555
1556 /*
1557 * this will be ->nopage() once I can
1558 * ask Jeff what the hell I'm doing wrong.
1559 */
1560 ret = -EAGAIN;
1561 if (remap_pfn_range(vma, vma->vm_start,
1562 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1563 size, vma->vm_page_prot))
1564 goto out;
1565
1566 db->mapped = 1;
1567 ret = 0;
1568
1569 out:
1570 return ret;
1571 }
1572
1573 /*
1574 * this function is a disaster..
1575 */
1576 #define get_user_ret(x, ptr, ret) ({ if(get_user(x, ptr)) return ret; })
1577 static int m3_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1578 {
1579 struct m3_state *s = (struct m3_state *)file->private_data;
1580 struct m3_card *card=s->card;
1581 unsigned long flags;
1582 audio_buf_info abinfo;
1583 count_info cinfo;
1584 int val, mapped, ret;
1585 unsigned char fmtm, fmtd;
1586 void __user *argp = (void __user *)arg;
1587 int __user *p = argp;
1588
1589 VALIDATE_STATE(s);
1590
1591 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1592 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1593
1594 DPRINTK(DPSYS,"m3_ioctl: cmd %d\n", cmd);
1595
1596 switch (cmd) {
1597 case OSS_GETVERSION:
1598 return put_user(SOUND_VERSION, p);
1599
1600 case SNDCTL_DSP_SYNC:
1601 if (file->f_mode & FMODE_WRITE)
1602 return drain_dac(s, file->f_flags & O_NONBLOCK);
1603 return 0;
1604
1605 case SNDCTL_DSP_SETDUPLEX:
1606 /* XXX fix */
1607 return 0;
1608
1609 case SNDCTL_DSP_GETCAPS:
1610 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1611
1612 case SNDCTL_DSP_RESET:
1613 spin_lock_irqsave(&card->lock, flags);
1614 if (file->f_mode & FMODE_WRITE) {
1615 stop_dac(s);
1616 synchronize_irq(s->card->pcidev->irq);
1617 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1618 }
1619 if (file->f_mode & FMODE_READ) {
1620 stop_adc(s);
1621 synchronize_irq(s->card->pcidev->irq);
1622 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1623 }
1624 spin_unlock_irqrestore(&card->lock, flags);
1625 return 0;
1626
1627 case SNDCTL_DSP_SPEED:
1628 get_user_ret(val, p, -EFAULT);
1629 spin_lock_irqsave(&card->lock, flags);
1630 if (val >= 0) {
1631 if (file->f_mode & FMODE_READ) {
1632 stop_adc(s);
1633 s->dma_adc.ready = 0;
1634 set_adc_rate(s, val);
1635 }
1636 if (file->f_mode & FMODE_WRITE) {
1637 stop_dac(s);
1638 s->dma_dac.ready = 0;
1639 set_dac_rate(s, val);
1640 }
1641 }
1642 spin_unlock_irqrestore(&card->lock, flags);
1643 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1644
1645 case SNDCTL_DSP_STEREO:
1646 get_user_ret(val, p, -EFAULT);
1647 spin_lock_irqsave(&card->lock, flags);
1648 fmtd = 0;
1649 fmtm = ~0;
1650 if (file->f_mode & FMODE_READ) {
1651 stop_adc(s);
1652 s->dma_adc.ready = 0;
1653 if (val)
1654 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
1655 else
1656 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
1657 }
1658 if (file->f_mode & FMODE_WRITE) {
1659 stop_dac(s);
1660 s->dma_dac.ready = 0;
1661 if (val)
1662 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
1663 else
1664 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
1665 }
1666 set_fmt(s, fmtm, fmtd);
1667 spin_unlock_irqrestore(&card->lock, flags);
1668 return 0;
1669
1670 case SNDCTL_DSP_CHANNELS:
1671 get_user_ret(val, p, -EFAULT);
1672 spin_lock_irqsave(&card->lock, flags);
1673 if (val != 0) {
1674 fmtd = 0;
1675 fmtm = ~0;
1676 if (file->f_mode & FMODE_READ) {
1677 stop_adc(s);
1678 s->dma_adc.ready = 0;
1679 if (val >= 2)
1680 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
1681 else
1682 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
1683 }
1684 if (file->f_mode & FMODE_WRITE) {
1685 stop_dac(s);
1686 s->dma_dac.ready = 0;
1687 if (val >= 2)
1688 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
1689 else
1690 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
1691 }
1692 set_fmt(s, fmtm, fmtd);
1693 }
1694 spin_unlock_irqrestore(&card->lock, flags);
1695 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
1696 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, p);
1697
1698 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1699 return put_user(AFMT_U8|AFMT_S16_LE, p);
1700
1701 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1702 get_user_ret(val, p, -EFAULT);
1703 spin_lock_irqsave(&card->lock, flags);
1704 if (val != AFMT_QUERY) {
1705 fmtd = 0;
1706 fmtm = ~0;
1707 if (file->f_mode & FMODE_READ) {
1708 stop_adc(s);
1709 s->dma_adc.ready = 0;
1710 if (val == AFMT_S16_LE)
1711 fmtd |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
1712 else
1713 fmtm &= ~(ESS_FMT_16BIT << ESS_ADC_SHIFT);
1714 }
1715 if (file->f_mode & FMODE_WRITE) {
1716 stop_dac(s);
1717 s->dma_dac.ready = 0;
1718 if (val == AFMT_S16_LE)
1719 fmtd |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
1720 else
1721 fmtm &= ~(ESS_FMT_16BIT << ESS_DAC_SHIFT);
1722 }
1723 set_fmt(s, fmtm, fmtd);
1724 }
1725 spin_unlock_irqrestore(&card->lock, flags);
1726 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ?
1727 (ESS_FMT_16BIT << ESS_ADC_SHIFT)
1728 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ?
1729 AFMT_S16_LE :
1730 AFMT_U8,
1731 p);
1732
1733 case SNDCTL_DSP_POST:
1734 return 0;
1735
1736 case SNDCTL_DSP_GETTRIGGER:
1737 val = 0;
1738 if ((file->f_mode & FMODE_READ) && (s->enable & ADC_RUNNING))
1739 val |= PCM_ENABLE_INPUT;
1740 if ((file->f_mode & FMODE_WRITE) && (s->enable & DAC_RUNNING))
1741 val |= PCM_ENABLE_OUTPUT;
1742 return put_user(val, p);
1743
1744 case SNDCTL_DSP_SETTRIGGER:
1745 get_user_ret(val, p, -EFAULT);
1746 if (file->f_mode & FMODE_READ) {
1747 if (val & PCM_ENABLE_INPUT) {
1748 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1749 return ret;
1750 start_adc(s);
1751 } else
1752 stop_adc(s);
1753 }
1754 if (file->f_mode & FMODE_WRITE) {
1755 if (val & PCM_ENABLE_OUTPUT) {
1756 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1757 return ret;
1758 start_dac(s);
1759 } else
1760 stop_dac(s);
1761 }
1762 return 0;
1763
1764 case SNDCTL_DSP_GETOSPACE:
1765 if (!(file->f_mode & FMODE_WRITE))
1766 return -EINVAL;
1767 if (!(s->enable & DAC_RUNNING) && (val = prog_dmabuf(s, 0)) != 0)
1768 return val;
1769 spin_lock_irqsave(&card->lock, flags);
1770 m3_update_ptr(s);
1771 abinfo.fragsize = s->dma_dac.fragsize;
1772 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
1773 abinfo.fragstotal = s->dma_dac.numfrag;
1774 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1775 spin_unlock_irqrestore(&card->lock, flags);
1776 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1777
1778 case SNDCTL_DSP_GETISPACE:
1779 if (!(file->f_mode & FMODE_READ))
1780 return -EINVAL;
1781 if (!(s->enable & ADC_RUNNING) && (val = prog_dmabuf(s, 1)) != 0)
1782 return val;
1783 spin_lock_irqsave(&card->lock, flags);
1784 m3_update_ptr(s);
1785 abinfo.fragsize = s->dma_adc.fragsize;
1786 abinfo.bytes = s->dma_adc.count;
1787 abinfo.fragstotal = s->dma_adc.numfrag;
1788 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1789 spin_unlock_irqrestore(&card->lock, flags);
1790 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1791
1792 case SNDCTL_DSP_NONBLOCK:
1793 file->f_flags |= O_NONBLOCK;
1794 return 0;
1795
1796 case SNDCTL_DSP_GETODELAY:
1797 if (!(file->f_mode & FMODE_WRITE))
1798 return -EINVAL;
1799 spin_lock_irqsave(&card->lock, flags);
1800 m3_update_ptr(s);
1801 val = s->dma_dac.count;
1802 spin_unlock_irqrestore(&card->lock, flags);
1803 return put_user(val, p);
1804
1805 case SNDCTL_DSP_GETIPTR:
1806 if (!(file->f_mode & FMODE_READ))
1807 return -EINVAL;
1808 spin_lock_irqsave(&card->lock, flags);
1809 m3_update_ptr(s);
1810 cinfo.bytes = s->dma_adc.total_bytes;
1811 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
1812 cinfo.ptr = s->dma_adc.hwptr;
1813 if (s->dma_adc.mapped)
1814 s->dma_adc.count &= s->dma_adc.fragsize-1;
1815 spin_unlock_irqrestore(&card->lock, flags);
1816 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1817 return -EFAULT;
1818 return 0;
1819
1820 case SNDCTL_DSP_GETOPTR:
1821 if (!(file->f_mode & FMODE_WRITE))
1822 return -EINVAL;
1823 spin_lock_irqsave(&card->lock, flags);
1824 m3_update_ptr(s);
1825 cinfo.bytes = s->dma_dac.total_bytes;
1826 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
1827 cinfo.ptr = s->dma_dac.hwptr;
1828 if (s->dma_dac.mapped)
1829 s->dma_dac.count &= s->dma_dac.fragsize-1;
1830 spin_unlock_irqrestore(&card->lock, flags);
1831 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1832 return -EFAULT;
1833 return 0;
1834
1835 case SNDCTL_DSP_GETBLKSIZE:
1836 if (file->f_mode & FMODE_WRITE) {
1837 if ((val = prog_dmabuf(s, 0)))
1838 return val;
1839 return put_user(s->dma_dac.fragsize, p);
1840 }
1841 if ((val = prog_dmabuf(s, 1)))
1842 return val;
1843 return put_user(s->dma_adc.fragsize, p);
1844
1845 case SNDCTL_DSP_SETFRAGMENT:
1846 get_user_ret(val, p, -EFAULT);
1847 spin_lock_irqsave(&card->lock, flags);
1848 if (file->f_mode & FMODE_READ) {
1849 s->dma_adc.ossfragshift = val & 0xffff;
1850 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1851 if (s->dma_adc.ossfragshift < 4)
1852 s->dma_adc.ossfragshift = 4;
1853 if (s->dma_adc.ossfragshift > 15)
1854 s->dma_adc.ossfragshift = 15;
1855 if (s->dma_adc.ossmaxfrags < 4)
1856 s->dma_adc.ossmaxfrags = 4;
1857 }
1858 if (file->f_mode & FMODE_WRITE) {
1859 s->dma_dac.ossfragshift = val & 0xffff;
1860 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1861 if (s->dma_dac.ossfragshift < 4)
1862 s->dma_dac.ossfragshift = 4;
1863 if (s->dma_dac.ossfragshift > 15)
1864 s->dma_dac.ossfragshift = 15;
1865 if (s->dma_dac.ossmaxfrags < 4)
1866 s->dma_dac.ossmaxfrags = 4;
1867 }
1868 spin_unlock_irqrestore(&card->lock, flags);
1869 return 0;
1870
1871 case SNDCTL_DSP_SUBDIVIDE:
1872 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1873 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1874 return -EINVAL;
1875 get_user_ret(val, p, -EFAULT);
1876 if (val != 1 && val != 2 && val != 4)
1877 return -EINVAL;
1878 if (file->f_mode & FMODE_READ)
1879 s->dma_adc.subdivision = val;
1880 if (file->f_mode & FMODE_WRITE)
1881 s->dma_dac.subdivision = val;
1882 return 0;
1883
1884 case SOUND_PCM_READ_RATE:
1885 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1886
1887 case SOUND_PCM_READ_CHANNELS:
1888 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
1889 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, p);
1890
1891 case SOUND_PCM_READ_BITS:
1892 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_16BIT << ESS_ADC_SHIFT)
1893 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ? 16 : 8, p);
1894
1895 case SOUND_PCM_WRITE_FILTER:
1896 case SNDCTL_DSP_SETSYNCRO:
1897 case SOUND_PCM_READ_FILTER:
1898 return -EINVAL;
1899
1900 }
1901 return -EINVAL;
1902 }
1903
1904 static int
1905 allocate_dmabuf(struct pci_dev *pci_dev, struct dmabuf *db)
1906 {
1907 int order;
1908
1909 DPRINTK(DPSTR,"allocating for dmabuf %p\n", db);
1910
1911 /*
1912 * alloc as big a chunk as we can, start with
1913 * 64k 'cause we're insane. based on order cause
1914 * the amazingly complicated prog_dmabuf wants it.
1915 *
1916 * pci_alloc_sonsistent guarantees that it won't cross a natural
1917 * boundary; the m3 hardware can't have dma cross a 64k bus
1918 * address boundary.
1919 */
1920 for (order = 16-PAGE_SHIFT; order >= 1; order--) {
1921 db->rawbuf = pci_alloc_consistent(pci_dev, PAGE_SIZE << order,
1922 &(db->handle));
1923 if(db->rawbuf)
1924 break;
1925 }
1926
1927 if (!db->rawbuf)
1928 return 1;
1929
1930 DPRINTK(DPSTR,"allocated %ld (%d) bytes at %p\n",
1931 PAGE_SIZE<<order, order, db->rawbuf);
1932
1933 {
1934 struct page *page, *pend;
1935
1936 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << order) - 1);
1937 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
1938 SetPageReserved(page);
1939 }
1940
1941
1942 db->buforder = order;
1943 db->ready = 0;
1944 db->mapped = 0;
1945
1946 return 0;
1947 }
1948
1949 static void
1950 nuke_lists(struct m3_card *card, struct dmabuf *db)
1951 {
1952 m3_remove_list(card, &(card->dma_list), db->dma_index);
1953 m3_remove_list(card, &(card->msrc_list), db->msrc_index);
1954 db->in_lists = 0;
1955 }
1956
1957 static void
1958 free_dmabuf(struct pci_dev *pci_dev, struct dmabuf *db)
1959 {
1960 if(db->rawbuf == NULL)
1961 return;
1962
1963 DPRINTK(DPSTR,"freeing %p from dmabuf %p\n",db->rawbuf, db);
1964
1965 {
1966 struct page *page, *pend;
1967 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1968 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
1969 ClearPageReserved(page);
1970 }
1971
1972
1973 pci_free_consistent(pci_dev, PAGE_SIZE << db->buforder,
1974 db->rawbuf, db->handle);
1975
1976 db->rawbuf = NULL;
1977 db->buforder = 0;
1978 db->mapped = 0;
1979 db->ready = 0;
1980 }
1981
1982 static int m3_open(struct inode *inode, struct file *file)
1983 {
1984 unsigned int minor = iminor(inode);
1985 struct m3_card *c;
1986 struct m3_state *s = NULL;
1987 int i;
1988 unsigned char fmtm = ~0, fmts = 0;
1989 unsigned long flags;
1990
1991 /*
1992 * Scan the cards and find the channel. We only
1993 * do this at open time so it is ok
1994 */
1995 for(c = devs ; c != NULL ; c = c->next) {
1996
1997 for(i=0;i<NR_DSPS;i++) {
1998
1999 if(c->channels[i].dev_audio < 0)
2000 continue;
2001 if((c->channels[i].dev_audio ^ minor) & ~0xf)
2002 continue;
2003
2004 s = &c->channels[i];
2005 break;
2006 }
2007 }
2008
2009 if (!s)
2010 return -ENODEV;
2011
2012 VALIDATE_STATE(s);
2013
2014 file->private_data = s;
2015
2016 /* wait for device to become free */
2017 mutex_lock(&s->open_mutex);
2018 while (s->open_mode & file->f_mode) {
2019 if (file->f_flags & O_NONBLOCK) {
2020 mutex_unlock(&s->open_mutex);
2021 return -EWOULDBLOCK;
2022 }
2023 mutex_unlock(&s->open_mutex);
2024 interruptible_sleep_on(&s->open_wait);
2025 if (signal_pending(current))
2026 return -ERESTARTSYS;
2027 mutex_lock(&s->open_mutex);
2028 }
2029
2030 spin_lock_irqsave(&c->lock, flags);
2031
2032 if (file->f_mode & FMODE_READ) {
2033 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_ADC_SHIFT);
2034 if ((minor & 0xf) == SND_DEV_DSP16)
2035 fmts |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
2036
2037 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2038 set_adc_rate(s, 8000);
2039 }
2040 if (file->f_mode & FMODE_WRITE) {
2041 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_DAC_SHIFT);
2042 if ((minor & 0xf) == SND_DEV_DSP16)
2043 fmts |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
2044
2045 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2046 set_dac_rate(s, 8000);
2047 }
2048 set_fmt(s, fmtm, fmts);
2049 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2050
2051 mutex_unlock(&s->open_mutex);
2052 spin_unlock_irqrestore(&c->lock, flags);
2053 return nonseekable_open(inode, file);
2054 }
2055
2056 static int m3_release(struct inode *inode, struct file *file)
2057 {
2058 struct m3_state *s = (struct m3_state *)file->private_data;
2059 struct m3_card *card=s->card;
2060 unsigned long flags;
2061
2062 VALIDATE_STATE(s);
2063 if (file->f_mode & FMODE_WRITE)
2064 drain_dac(s, file->f_flags & O_NONBLOCK);
2065
2066 mutex_lock(&s->open_mutex);
2067 spin_lock_irqsave(&card->lock, flags);
2068
2069 if (file->f_mode & FMODE_WRITE) {
2070 stop_dac(s);
2071 if(s->dma_dac.in_lists) {
2072 m3_remove_list(s->card, &(s->card->mixer_list), s->dma_dac.mixer_index);
2073 nuke_lists(s->card, &(s->dma_dac));
2074 }
2075 }
2076 if (file->f_mode & FMODE_READ) {
2077 stop_adc(s);
2078 if(s->dma_adc.in_lists) {
2079 m3_remove_list(s->card, &(s->card->adc1_list), s->dma_adc.adc1_index);
2080 nuke_lists(s->card, &(s->dma_adc));
2081 }
2082 }
2083
2084 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
2085
2086 spin_unlock_irqrestore(&card->lock, flags);
2087 mutex_unlock(&s->open_mutex);
2088 wake_up(&s->open_wait);
2089
2090 return 0;
2091 }
2092
2093 /*
2094 * Wait for the ac97 serial bus to be free.
2095 * return nonzero if the bus is still busy.
2096 */
2097 static int m3_ac97_wait(struct m3_card *card)
2098 {
2099 int i = 10000;
2100
2101 while( (m3_inb(card, 0x30) & 1) && i--) ;
2102
2103 return i == 0;
2104 }
2105
2106 static u16 m3_ac97_read(struct ac97_codec *codec, u8 reg)
2107 {
2108 u16 ret = 0;
2109 struct m3_card *card = codec->private_data;
2110
2111 spin_lock(&card->ac97_lock);
2112
2113 if(m3_ac97_wait(card)) {
2114 printk(KERN_ERR PFX "serial bus busy reading reg 0x%x\n",reg);
2115 goto out;
2116 }
2117
2118 m3_outb(card, 0x80 | (reg & 0x7f), 0x30);
2119
2120 if(m3_ac97_wait(card)) {
2121 printk(KERN_ERR PFX "serial bus busy finishing read reg 0x%x\n",reg);
2122 goto out;
2123 }
2124
2125 ret = m3_inw(card, 0x32);
2126 DPRINTK(DPCRAP,"reading 0x%04x from 0x%02x\n",ret, reg);
2127
2128 out:
2129 spin_unlock(&card->ac97_lock);
2130 return ret;
2131 }
2132
2133 static void m3_ac97_write(struct ac97_codec *codec, u8 reg, u16 val)
2134 {
2135 struct m3_card *card = codec->private_data;
2136
2137 spin_lock(&card->ac97_lock);
2138
2139 if(m3_ac97_wait(card)) {
2140 printk(KERN_ERR PFX "serial bus busy writing 0x%x to 0x%x\n",val, reg);
2141 goto out;
2142 }
2143 DPRINTK(DPCRAP,"writing 0x%04x to 0x%02x\n", val, reg);
2144
2145 m3_outw(card, val, 0x32);
2146 m3_outb(card, reg & 0x7f, 0x30);
2147 out:
2148 spin_unlock(&card->ac97_lock);
2149 }
2150 /* OSS /dev/mixer file operation methods */
2151 static int m3_open_mixdev(struct inode *inode, struct file *file)
2152 {
2153 unsigned int minor = iminor(inode);
2154 struct m3_card *card = devs;
2155
2156 for (card = devs; card != NULL; card = card->next) {
2157 if((card->ac97 != NULL) && (card->ac97->dev_mixer == minor))
2158 break;
2159 }
2160
2161 if (!card) {
2162 return -ENODEV;
2163 }
2164
2165 file->private_data = card->ac97;
2166
2167 return nonseekable_open(inode, file);
2168 }
2169
2170 static int m3_release_mixdev(struct inode *inode, struct file *file)
2171 {
2172 return 0;
2173 }
2174
2175 static int m3_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2176 unsigned long arg)
2177 {
2178 struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2179
2180 return codec->mixer_ioctl(codec, cmd, arg);
2181 }
2182
2183 static struct file_operations m3_mixer_fops = {
2184 .owner = THIS_MODULE,
2185 .llseek = no_llseek,
2186 .ioctl = m3_ioctl_mixdev,
2187 .open = m3_open_mixdev,
2188 .release = m3_release_mixdev,
2189 };
2190
2191 static void remote_codec_config(int io, int isremote)
2192 {
2193 isremote = isremote ? 1 : 0;
2194
2195 outw( (inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2196 io + RING_BUS_CTRL_B);
2197 outw( (inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2198 io + SDO_OUT_DEST_CTRL);
2199 outw( (inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2200 io + SDO_IN_DEST_CTRL);
2201 }
2202
2203 /*
2204 * hack, returns non zero on err
2205 */
2206 static int try_read_vendor(struct m3_card *card)
2207 {
2208 u16 ret;
2209
2210 if(m3_ac97_wait(card))
2211 return 1;
2212
2213 m3_outb(card, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2214
2215 if(m3_ac97_wait(card))
2216 return 1;
2217
2218 ret = m3_inw(card, 0x32);
2219
2220 return (ret == 0) || (ret == 0xffff);
2221 }
2222
2223 static void m3_codec_reset(struct m3_card *card, int busywait)
2224 {
2225 u16 dir;
2226 int delay1 = 0, delay2 = 0, i;
2227 int io = card->iobase;
2228
2229 switch (card->card_type) {
2230 /*
2231 * the onboard codec on the allegro seems
2232 * to want to wait a very long time before
2233 * coming back to life
2234 */
2235 case ESS_ALLEGRO:
2236 delay1 = 50;
2237 delay2 = 800;
2238 break;
2239 case ESS_MAESTRO3:
2240 case ESS_MAESTRO3HW:
2241 delay1 = 20;
2242 delay2 = 500;
2243 break;
2244 }
2245
2246 for(i = 0; i < 5; i ++) {
2247 dir = inw(io + GPIO_DIRECTION);
2248 dir |= 0x10; /* assuming pci bus master? */
2249
2250 remote_codec_config(io, 0);
2251
2252 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2253 udelay(20);
2254
2255 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2256 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2257 outw(0, io + GPIO_DATA);
2258 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2259
2260 if(busywait) {
2261 mdelay(delay1);
2262 } else {
2263 set_current_state(TASK_UNINTERRUPTIBLE);
2264 schedule_timeout((delay1 * HZ) / 1000);
2265 }
2266
2267 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2268 udelay(5);
2269 /* ok, bring back the ac-link */
2270 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2271 outw(~0, io + GPIO_MASK);
2272
2273 if(busywait) {
2274 mdelay(delay2);
2275 } else {
2276 set_current_state(TASK_UNINTERRUPTIBLE);
2277 schedule_timeout((delay2 * HZ) / 1000);
2278 }
2279 if(! try_read_vendor(card))
2280 break;
2281
2282 delay1 += 10;
2283 delay2 += 100;
2284
2285 DPRINTK(DPMOD, "retrying codec reset with delays of %d and %d ms\n",
2286 delay1, delay2);
2287 }
2288
2289 #if 0
2290 /* more gung-ho reset that doesn't
2291 * seem to work anywhere :)
2292 */
2293 tmp = inw(io + RING_BUS_CTRL_A);
2294 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2295 mdelay(20);
2296 outw(tmp, io + RING_BUS_CTRL_A);
2297 mdelay(50);
2298 #endif
2299 }
2300
2301 static int __devinit m3_codec_install(struct m3_card *card)
2302 {
2303 struct ac97_codec *codec;
2304
2305 if ((codec = ac97_alloc_codec()) == NULL)
2306 return -ENOMEM;
2307
2308 codec->private_data = card;
2309 codec->codec_read = m3_ac97_read;
2310 codec->codec_write = m3_ac97_write;
2311 /* someday we should support secondary codecs.. */
2312 codec->id = 0;
2313
2314 if (ac97_probe_codec(codec) == 0) {
2315 printk(KERN_ERR PFX "codec probe failed\n");
2316 ac97_release_codec(codec);
2317 return -1;
2318 }
2319
2320 if ((codec->dev_mixer = register_sound_mixer(&m3_mixer_fops, -1)) < 0) {
2321 printk(KERN_ERR PFX "couldn't register mixer!\n");
2322 ac97_release_codec(codec);
2323 return -1;
2324 }
2325
2326 card->ac97 = codec;
2327
2328 return 0;
2329 }
2330
2331
2332 #define MINISRC_LPF_LEN 10
2333 static u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2334 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2335 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2336 };
2337 static void m3_assp_init(struct m3_card *card)
2338 {
2339 int i;
2340
2341 /* zero kernel data */
2342 for(i = 0 ; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2343 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2344 KDATA_BASE_ADDR + i, 0);
2345
2346 /* zero mixer data? */
2347 for(i = 0 ; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2348 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2349 KDATA_BASE_ADDR2 + i, 0);
2350
2351 /* init dma pointer */
2352 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2353 KDATA_CURRENT_DMA,
2354 KDATA_DMA_XFER0);
2355
2356 /* write kernel into code memory.. */
2357 for(i = 0 ; i < sizeof(assp_kernel_image) / 2; i++) {
2358 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2359 REV_B_CODE_MEMORY_BEGIN + i,
2360 assp_kernel_image[i]);
2361 }
2362
2363 /*
2364 * We only have this one client and we know that 0x400
2365 * is free in our kernel's mem map, so lets just
2366 * drop it there. It seems that the minisrc doesn't
2367 * need vectors, so we won't bother with them..
2368 */
2369 for(i = 0 ; i < sizeof(assp_minisrc_image) / 2; i++) {
2370 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2371 0x400 + i,
2372 assp_minisrc_image[i]);
2373 }
2374
2375 /*
2376 * write the coefficients for the low pass filter?
2377 */
2378 for(i = 0; i < MINISRC_LPF_LEN ; i++) {
2379 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2380 0x400 + MINISRC_COEF_LOC + i,
2381 minisrc_lpf[i]);
2382 }
2383
2384 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2385 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2386 0x8000);
2387
2388 /*
2389 * the minisrc is the only thing on
2390 * our task list..
2391 */
2392 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2393 KDATA_TASK0,
2394 0x400);
2395
2396 /*
2397 * init the mixer number..
2398 */
2399
2400 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2401 KDATA_MIXER_TASK_NUMBER,0);
2402
2403 /*
2404 * EXTREME KERNEL MASTER VOLUME
2405 */
2406 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2407 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2408 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2409 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2410
2411 card->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2412 card->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2413 card->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2414 card->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2415 card->dma_list.mem_addr = KDATA_DMA_XFER0;
2416 card->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2417 card->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2418 card->msrc_list.max = MAX_INSTANCE_MINISRC;
2419 }
2420
2421 static int setup_msrc(struct m3_card *card,
2422 struct assp_instance *inst, int index)
2423 {
2424 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2425 MINISRC_IN_BUFFER_SIZE / 2 +
2426 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2427 int address, i;
2428
2429 /*
2430 * the revb memory map has 0x1100 through 0x1c00
2431 * free.
2432 */
2433
2434 /*
2435 * align instance address to 256 bytes so that it's
2436 * shifted list address is aligned.
2437 * list address = (mem address >> 1) >> 7;
2438 */
2439 data_bytes = (data_bytes + 255) & ~255;
2440 address = 0x1100 + ((data_bytes/2) * index);
2441
2442 if((address + (data_bytes/2)) >= 0x1c00) {
2443 printk(KERN_ERR PFX "no memory for %d bytes at ind %d (addr 0x%x)\n",
2444 data_bytes, index, address);
2445 return -1;
2446 }
2447
2448 for(i = 0; i < data_bytes/2 ; i++)
2449 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2450 address + i, 0);
2451
2452 inst->code = 0x400;
2453 inst->data = address;
2454
2455 return 0;
2456 }
2457
2458 static int m3_assp_client_init(struct m3_state *s)
2459 {
2460 setup_msrc(s->card, &(s->dac_inst), s->index * 2);
2461 setup_msrc(s->card, &(s->adc_inst), (s->index * 2) + 1);
2462
2463 return 0;
2464 }
2465
2466 static void m3_amp_enable(struct m3_card *card, int enable)
2467 {
2468 /*
2469 * this works for the reference board, have to find
2470 * out about others
2471 *
2472 * this needs more magic for 4 speaker, but..
2473 */
2474 int io = card->iobase;
2475 u16 gpo, polarity_port, polarity;
2476
2477 if(!external_amp)
2478 return;
2479
2480 if (gpio_pin >= 0 && gpio_pin <= 15) {
2481 polarity_port = 0x1000 + (0x100 * gpio_pin);
2482 } else {
2483 switch (card->card_type) {
2484 case ESS_ALLEGRO:
2485 polarity_port = 0x1800;
2486 break;
2487 default:
2488 polarity_port = 0x1100;
2489 /* Panasonic toughbook CF72 has to be different... */
2490 if(card->pcidev->subsystem_vendor == 0x10F7 && card->pcidev->subsystem_device == 0x833D)
2491 polarity_port = 0x1D00;
2492 break;
2493 }
2494 }
2495
2496 gpo = (polarity_port >> 8) & 0x0F;
2497 polarity = polarity_port >> 12;
2498 if ( enable )
2499 polarity = !polarity;
2500 polarity = polarity << gpo;
2501 gpo = 1 << gpo;
2502
2503 outw(~gpo , io + GPIO_MASK);
2504
2505 outw( inw(io + GPIO_DIRECTION) | gpo ,
2506 io + GPIO_DIRECTION);
2507
2508 outw( (GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity) ,
2509 io + GPIO_DATA);
2510
2511 outw(0xffff , io + GPIO_MASK);
2512 }
2513
2514 static int
2515 maestro_config(struct m3_card *card)
2516 {
2517 struct pci_dev *pcidev = card->pcidev;
2518 u32 n;
2519 u8 t; /* makes as much sense as 'n', no? */
2520
2521 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2522 n &= REDUCED_DEBOUNCE;
2523 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2524 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2525
2526 outb(RESET_ASSP, card->iobase + ASSP_CONTROL_B);
2527 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2528 n &= ~INT_CLK_SELECT;
2529 if(card->card_type >= ESS_MAESTRO3) {
2530 n &= ~INT_CLK_MULT_ENABLE;
2531 n |= INT_CLK_SRC_NOT_PCI;
2532 }
2533 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2534 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2535
2536 if(card->card_type <= ESS_ALLEGRO) {
2537 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2538 n |= IN_CLK_12MHZ_SELECT;
2539 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2540 }
2541
2542 t = inb(card->iobase + ASSP_CONTROL_A);
2543 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2544 t |= ASSP_CLK_49MHZ_SELECT;
2545 t |= ASSP_0_WS_ENABLE;
2546 outb(t, card->iobase + ASSP_CONTROL_A);
2547
2548 outb(RUN_ASSP, card->iobase + ASSP_CONTROL_B);
2549
2550 return 0;
2551 }
2552
2553 static void m3_enable_ints(struct m3_card *card)
2554 {
2555 unsigned long io = card->iobase;
2556
2557 outw(ASSP_INT_ENABLE, io + HOST_INT_CTRL);
2558 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2559 io + ASSP_CONTROL_C);
2560 }
2561
2562 static struct file_operations m3_audio_fops = {
2563 .owner = THIS_MODULE,
2564 .llseek = no_llseek,
2565 .read = m3_read,
2566 .write = m3_write,
2567 .poll = m3_poll,
2568 .ioctl = m3_ioctl,
2569 .mmap = m3_mmap,
2570 .open = m3_open,
2571 .release = m3_release,
2572 };
2573
2574 #ifdef CONFIG_PM
2575 static int alloc_dsp_suspendmem(struct m3_card *card)
2576 {
2577 int len = sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH);
2578
2579 if( (card->suspend_mem = vmalloc(len)) == NULL)
2580 return 1;
2581
2582 return 0;
2583 }
2584
2585 #else
2586 #define alloc_dsp_suspendmem(args...) 0
2587 #endif
2588
2589 /*
2590 * great day! this function is ugly as hell.
2591 */
2592 static int __devinit m3_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
2593 {
2594 u32 n;
2595 int i;
2596 struct m3_card *card = NULL;
2597 int ret = 0;
2598 int card_type = pci_id->driver_data;
2599
2600 DPRINTK(DPMOD, "in maestro_install\n");
2601
2602 if (pci_enable_device(pci_dev))
2603 return -EIO;
2604
2605 if (pci_set_dma_mask(pci_dev, M3_PCI_DMA_MASK)) {
2606 printk(KERN_ERR PFX "architecture does not support limiting to 28bit PCI bus addresses\n");
2607 return -ENODEV;
2608 }
2609
2610 pci_set_master(pci_dev);
2611
2612 if( (card = kmalloc(sizeof(struct m3_card), GFP_KERNEL)) == NULL) {
2613 printk(KERN_WARNING PFX "out of memory\n");
2614 return -ENOMEM;
2615 }
2616 memset(card, 0, sizeof(struct m3_card));
2617 card->pcidev = pci_dev;
2618 init_waitqueue_head(&card->suspend_queue);
2619
2620 if ( ! request_region(pci_resource_start(pci_dev, 0),
2621 pci_resource_len (pci_dev, 0), M3_MODULE_NAME)) {
2622
2623 printk(KERN_WARNING PFX "unable to reserve I/O space.\n");
2624 ret = -EBUSY;
2625 goto out;
2626 }
2627
2628 card->iobase = pci_resource_start(pci_dev, 0);
2629
2630 if(alloc_dsp_suspendmem(card)) {
2631 printk(KERN_WARNING PFX "couldn't alloc %d bytes for saving dsp state on suspend\n",
2632 REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH);
2633 ret = -ENOMEM;
2634 goto out;
2635 }
2636
2637 card->card_type = card_type;
2638 card->irq = pci_dev->irq;
2639 card->next = devs;
2640 card->magic = M3_CARD_MAGIC;
2641 spin_lock_init(&card->lock);
2642 spin_lock_init(&card->ac97_lock);
2643 devs = card;
2644 for(i = 0; i<NR_DSPS; i++) {
2645 struct m3_state *s = &(card->channels[i]);
2646 s->dev_audio = -1;
2647 }
2648
2649 printk(KERN_INFO PFX "Configuring ESS %s found at IO 0x%04X IRQ %d\n",
2650 card_names[card->card_type], card->iobase, card->irq);
2651
2652 pci_read_config_dword(pci_dev, PCI_SUBSYSTEM_VENDOR_ID, &n);
2653 printk(KERN_INFO PFX " subvendor id: 0x%08x\n",n);
2654
2655 maestro_config(card);
2656 m3_assp_halt(card);
2657
2658 m3_codec_reset(card, 0);
2659
2660 if(m3_codec_install(card)) {
2661 ret = -EIO;
2662 goto out;
2663 }
2664
2665 m3_assp_init(card);
2666 m3_amp_enable(card, 1);
2667
2668 for(i=0;i<NR_DSPS;i++) {
2669 struct m3_state *s=&card->channels[i];
2670
2671 s->index = i;
2672
2673 s->card = card;
2674 init_waitqueue_head(&s->dma_adc.wait);
2675 init_waitqueue_head(&s->dma_dac.wait);
2676 init_waitqueue_head(&s->open_wait);
2677 mutex_init(&(s->open_mutex));
2678 s->magic = M3_STATE_MAGIC;
2679
2680 m3_assp_client_init(s);
2681
2682 if(s->dma_adc.ready || s->dma_dac.ready || s->dma_adc.rawbuf)
2683 printk(KERN_WARNING PFX "initing a dsp device that is already in use?\n");
2684 /* register devices */
2685 if ((s->dev_audio = register_sound_dsp(&m3_audio_fops, -1)) < 0) {
2686 break;
2687 }
2688
2689 if( allocate_dmabuf(card->pcidev, &(s->dma_adc)) ||
2690 allocate_dmabuf(card->pcidev, &(s->dma_dac))) {
2691 ret = -ENOMEM;
2692 goto out;
2693 }
2694 }
2695
2696 if(request_irq(card->irq, m3_interrupt, IRQF_SHARED, card_names[card->card_type], card)) {
2697
2698 printk(KERN_ERR PFX "unable to allocate irq %d,\n", card->irq);
2699
2700 ret = -EIO;
2701 goto out;
2702 }
2703
2704 pci_set_drvdata(pci_dev, card);
2705
2706 m3_enable_ints(card);
2707 m3_assp_continue(card);
2708
2709 out:
2710 if(ret) {
2711 if(card->iobase)
2712 release_region(pci_resource_start(pci_dev, 0), pci_resource_len(pci_dev, 0));
2713 vfree(card->suspend_mem);
2714 if(card->ac97) {
2715 unregister_sound_mixer(card->ac97->dev_mixer);
2716 kfree(card->ac97);
2717 }
2718 for(i=0;i<NR_DSPS;i++)
2719 {
2720 struct m3_state *s = &card->channels[i];
2721 if(s->dev_audio != -1)
2722 unregister_sound_dsp(s->dev_audio);
2723 }
2724 kfree(card);
2725 }
2726
2727 return ret;
2728 }
2729
2730 static void m3_remove(struct pci_dev *pci_dev)
2731 {
2732 struct m3_card *card;
2733
2734 unregister_reboot_notifier(&m3_reboot_nb);
2735
2736 while ((card = devs)) {
2737 int i;
2738 devs = devs->next;
2739
2740 free_irq(card->irq, card);
2741 unregister_sound_mixer(card->ac97->dev_mixer);
2742 kfree(card->ac97);
2743
2744 for(i=0;i<NR_DSPS;i++)
2745 {
2746 struct m3_state *s = &card->channels[i];
2747 if(s->dev_audio < 0)
2748 continue;
2749
2750 unregister_sound_dsp(s->dev_audio);
2751 free_dmabuf(card->pcidev, &s->dma_adc);
2752 free_dmabuf(card->pcidev, &s->dma_dac);
2753 }
2754
2755 release_region(card->iobase, 256);
2756 vfree(card->suspend_mem);
2757 kfree(card);
2758 }
2759 devs = NULL;
2760 }
2761
2762 /*
2763 * some bioses like the sound chip to be powered down
2764 * at shutdown. We're just calling _suspend to
2765 * achieve that..
2766 */
2767 static int m3_notifier(struct notifier_block *nb, unsigned long event, void *buf)
2768 {
2769 struct m3_card *card;
2770
2771 DPRINTK(DPMOD, "notifier suspending all cards\n");
2772
2773 for(card = devs; card != NULL; card = card->next) {
2774 if(!card->in_suspend)
2775 m3_suspend(card->pcidev, PMSG_SUSPEND); /* XXX legal? */
2776 }
2777 return 0;
2778 }
2779
2780 static int m3_suspend(struct pci_dev *pci_dev, pm_message_t state)
2781 {
2782 unsigned long flags;
2783 int i;
2784 struct m3_card *card = pci_get_drvdata(pci_dev);
2785
2786 /* must be a better way.. */
2787 spin_lock_irqsave(&card->lock, flags);
2788
2789 DPRINTK(DPMOD, "pm in dev %p\n",card);
2790
2791 for(i=0;i<NR_DSPS;i++) {
2792 struct m3_state *s = &card->channels[i];
2793
2794 if(s->dev_audio == -1)
2795 continue;
2796
2797 DPRINTK(DPMOD, "stop_adc/dac() device %d\n",i);
2798 stop_dac(s);
2799 stop_adc(s);
2800 }
2801
2802 mdelay(10); /* give the assp a chance to idle.. */
2803
2804 m3_assp_halt(card);
2805
2806 if(card->suspend_mem) {
2807 int index = 0;
2808
2809 DPRINTK(DPMOD, "saving code\n");
2810 for(i = REV_B_CODE_MEMORY_BEGIN ; i <= REV_B_CODE_MEMORY_END; i++)
2811 card->suspend_mem[index++] =
2812 m3_assp_read(card, MEMTYPE_INTERNAL_CODE, i);
2813 DPRINTK(DPMOD, "saving data\n");
2814 for(i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2815 card->suspend_mem[index++] =
2816 m3_assp_read(card, MEMTYPE_INTERNAL_DATA, i);
2817 }
2818
2819 DPRINTK(DPMOD, "powering down apci regs\n");
2820 m3_outw(card, 0xffff, 0x54);
2821 m3_outw(card, 0xffff, 0x56);
2822
2823 card->in_suspend = 1;
2824
2825 spin_unlock_irqrestore(&card->lock, flags);
2826
2827 return 0;
2828 }
2829
2830 static int m3_resume(struct pci_dev *pci_dev)
2831 {
2832 unsigned long flags;
2833 int index;
2834 int i;
2835 struct m3_card *card = pci_get_drvdata(pci_dev);
2836
2837 spin_lock_irqsave(&card->lock, flags);
2838 card->in_suspend = 0;
2839
2840 DPRINTK(DPMOD, "resuming\n");
2841
2842 /* first lets just bring everything back. .*/
2843
2844 DPRINTK(DPMOD, "bringing power back on card 0x%p\n",card);
2845 m3_outw(card, 0, 0x54);
2846 m3_outw(card, 0, 0x56);
2847
2848 DPRINTK(DPMOD, "restoring pci configs and reseting codec\n");
2849 maestro_config(card);
2850 m3_assp_halt(card);
2851 m3_codec_reset(card, 1);
2852
2853 DPRINTK(DPMOD, "restoring dsp code card\n");
2854 index = 0;
2855 for(i = REV_B_CODE_MEMORY_BEGIN ; i <= REV_B_CODE_MEMORY_END; i++)
2856 m3_assp_write(card, MEMTYPE_INTERNAL_CODE, i,
2857 card->suspend_mem[index++]);
2858 for(i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2859 m3_assp_write(card, MEMTYPE_INTERNAL_DATA, i,
2860 card->suspend_mem[index++]);
2861
2862 /* tell the dma engine to restart itself */
2863 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2864 KDATA_DMA_ACTIVE, 0);
2865
2866 DPRINTK(DPMOD, "resuming dsp\n");
2867 m3_assp_continue(card);
2868
2869 DPRINTK(DPMOD, "enabling ints\n");
2870 m3_enable_ints(card);
2871
2872 /* bring back the old school flavor */
2873 for(i = 0; i < SOUND_MIXER_NRDEVICES ; i++) {
2874 int state = card->ac97->mixer_state[i];
2875 if (!supported_mixer(card->ac97, i))
2876 continue;
2877
2878 card->ac97->write_mixer(card->ac97, i,
2879 state & 0xff, (state >> 8) & 0xff);
2880 }
2881
2882 m3_amp_enable(card, 1);
2883
2884 /*
2885 * now we flip on the music
2886 */
2887 for(i=0;i<NR_DSPS;i++) {
2888 struct m3_state *s = &card->channels[i];
2889 if(s->dev_audio == -1)
2890 continue;
2891 /*
2892 * db->ready makes it so these guys can be
2893 * called unconditionally..
2894 */
2895 DPRINTK(DPMOD, "turning on dacs ind %d\n",i);
2896 start_dac(s);
2897 start_adc(s);
2898 }
2899
2900 spin_unlock_irqrestore(&card->lock, flags);
2901
2902 /*
2903 * all right, we think things are ready,
2904 * wake up people who were using the device
2905 * when we suspended
2906 */
2907 wake_up(&card->suspend_queue);
2908
2909 return 0;
2910 }
2911
2912 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>");
2913 MODULE_DESCRIPTION("ESS Maestro3/Allegro Driver");
2914 MODULE_LICENSE("GPL");
2915
2916 #ifdef M_DEBUG
2917 module_param(debug, int, 0);
2918 #endif
2919 module_param(external_amp, int, 0);
2920 module_param(gpio_pin, int, 0);
2921
2922 static struct pci_driver m3_pci_driver = {
2923 .name = "ess_m3_audio",
2924 .id_table = m3_id_table,
2925 .probe = m3_probe,
2926 .remove = m3_remove,
2927 .suspend = m3_suspend,
2928 .resume = m3_resume,
2929 };
2930
2931 static int __init m3_init_module(void)
2932 {
2933 printk(KERN_INFO PFX "version " DRIVER_VERSION " built at " __TIME__ " " __DATE__ "\n");
2934
2935 if (register_reboot_notifier(&m3_reboot_nb)) {
2936 printk(KERN_WARNING PFX "reboot notifier registration failed\n");
2937 return -ENODEV; /* ? */
2938 }
2939
2940 if (pci_register_driver(&m3_pci_driver)) {
2941 unregister_reboot_notifier(&m3_reboot_nb);
2942 return -ENODEV;
2943 }
2944 return 0;
2945 }
2946
2947 static void __exit m3_cleanup_module(void)
2948 {
2949 pci_unregister_driver(&m3_pci_driver);
2950 }
2951
2952 module_init(m3_init_module);
2953 module_exit(m3_cleanup_module);
2954
2955 void check_suspend(struct m3_card *card)
2956 {
2957 DECLARE_WAITQUEUE(wait, current);
2958
2959 if(!card->in_suspend)
2960 return;
2961
2962 card->in_suspend++;
2963 add_wait_queue(&card->suspend_queue, &wait);
2964 set_current_state(TASK_UNINTERRUPTIBLE);
2965 schedule();
2966 remove_wait_queue(&card->suspend_queue, &wait);
2967 set_current_state(TASK_RUNNING);
2968 }
WandBoard kernel