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Merge branch 'linux-2.6'
[wandboard.git] / drivers / ide / pci / pdc202xx_new.c
blob2cdd629c653db9f2a61438d02b3e49d68e93ac8f
1 /*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2006 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/mm.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #ifdef CONFIG_PPC_PMAC
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif
39
40 #define PDC202_DEBUG_CABLE 0
41
42 #undef DEBUG
43
44 #ifdef DEBUG
45 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
46 #else
47 #define DBG(fmt, args...)
48 #endif
49
50 static const char *pdc_quirk_drives[] = {
51 "QUANTUM FIREBALLlct08 08",
52 "QUANTUM FIREBALLP KA6.4",
53 "QUANTUM FIREBALLP KA9.1",
54 "QUANTUM FIREBALLP LM20.4",
55 "QUANTUM FIREBALLP KX13.6",
56 "QUANTUM FIREBALLP KX20.5",
57 "QUANTUM FIREBALLP KX27.3",
58 "QUANTUM FIREBALLP LM20.5",
59 NULL
60 };
61
62 static u8 max_dma_rate(struct pci_dev *pdev)
63 {
64 u8 mode;
65
66 switch(pdev->device) {
67 case PCI_DEVICE_ID_PROMISE_20277:
68 case PCI_DEVICE_ID_PROMISE_20276:
69 case PCI_DEVICE_ID_PROMISE_20275:
70 case PCI_DEVICE_ID_PROMISE_20271:
71 case PCI_DEVICE_ID_PROMISE_20269:
72 mode = 4;
73 break;
74 case PCI_DEVICE_ID_PROMISE_20270:
75 case PCI_DEVICE_ID_PROMISE_20268:
76 mode = 3;
77 break;
78 default:
79 return 0;
80 }
81
82 return mode;
83 }
84
85 static u8 pdcnew_ratemask(ide_drive_t *drive)
86 {
87 u8 mode = max_dma_rate(HWIF(drive)->pci_dev);
88
89 if (!eighty_ninty_three(drive))
90 mode = min_t(u8, mode, 1);
91
92 return mode;
93 }
94
95 /**
96 * get_indexed_reg - Get indexed register
97 * @hwif: for the port address
98 * @index: index of the indexed register
99 */
100 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
101 {
102 u8 value;
103
104 outb(index, hwif->dma_vendor1);
105 value = inb(hwif->dma_vendor3);
106
107 DBG("index[%02X] value[%02X]\n", index, value);
108 return value;
109 }
110
111 /**
112 * set_indexed_reg - Set indexed register
113 * @hwif: for the port address
114 * @index: index of the indexed register
115 */
116 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
117 {
118 outb(index, hwif->dma_vendor1);
119 outb(value, hwif->dma_vendor3);
120 DBG("index[%02X] value[%02X]\n", index, value);
121 }
122
123 /*
124 * ATA Timing Tables based on 133 MHz PLL output clock.
125 *
126 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
127 * the timing registers automatically when "set features" command is
128 * issued to the device. However, if the PLL output clock is 133 MHz,
129 * the following tables must be used.
130 */
131 static struct pio_timing {
132 u8 reg0c, reg0d, reg13;
133 } pio_timings [] = {
134 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
135 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
136 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
137 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
138 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
139 };
140
141 static struct mwdma_timing {
142 u8 reg0e, reg0f;
143 } mwdma_timings [] = {
144 { 0xdf, 0x5f }, /* MWDMA mode 0 */
145 { 0x6b, 0x27 }, /* MWDMA mode 1 */
146 { 0x69, 0x25 }, /* MWDMA mode 2 */
147 };
148
149 static struct udma_timing {
150 u8 reg10, reg11, reg12;
151 } udma_timings [] = {
152 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
153 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
154 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
155 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
156 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
157 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
158 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
159 };
160
161 static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
162 {
163 ide_hwif_t *hwif = HWIF(drive);
164 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
165 int err;
166
167 speed = ide_rate_filter(pdcnew_ratemask(drive), speed);
168
169 /*
170 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
171 * automatically set the timing registers based on 100 MHz PLL output.
172 */
173 err = ide_config_drive_speed(drive, speed);
174
175 /*
176 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
177 * chips, we must override the default register settings...
178 */
179 if (max_dma_rate(hwif->pci_dev) == 4) {
180 u8 mode = speed & 0x07;
181
182 switch (speed) {
183 case XFER_UDMA_6:
184 case XFER_UDMA_5:
185 case XFER_UDMA_4:
186 case XFER_UDMA_3:
187 case XFER_UDMA_2:
188 case XFER_UDMA_1:
189 case XFER_UDMA_0:
190 set_indexed_reg(hwif, 0x10 + adj,
191 udma_timings[mode].reg10);
192 set_indexed_reg(hwif, 0x11 + adj,
193 udma_timings[mode].reg11);
194 set_indexed_reg(hwif, 0x12 + adj,
195 udma_timings[mode].reg12);
196 break;
197
198 case XFER_MW_DMA_2:
199 case XFER_MW_DMA_1:
200 case XFER_MW_DMA_0:
201 set_indexed_reg(hwif, 0x0e + adj,
202 mwdma_timings[mode].reg0e);
203 set_indexed_reg(hwif, 0x0f + adj,
204 mwdma_timings[mode].reg0f);
205 break;
206 case XFER_PIO_4:
207 case XFER_PIO_3:
208 case XFER_PIO_2:
209 case XFER_PIO_1:
210 case XFER_PIO_0:
211 set_indexed_reg(hwif, 0x0c + adj,
212 pio_timings[mode].reg0c);
213 set_indexed_reg(hwif, 0x0d + adj,
214 pio_timings[mode].reg0d);
215 set_indexed_reg(hwif, 0x13 + adj,
216 pio_timings[mode].reg13);
217 break;
218 default:
219 printk(KERN_ERR "pdc202xx_new: "
220 "Unknown speed %d ignored\n", speed);
221 }
222 } else if (speed == XFER_UDMA_2) {
223 /* Set tHOLD bit to 0 if using UDMA mode 2 */
224 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
225
226 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
227 }
228
229 return err;
230 }
231
232 static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
233 {
234 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
235 (void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
236 }
237
238 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
239 {
240 return get_indexed_reg(hwif, 0x0b) & 0x04;
241 }
242
243 static int config_chipset_for_dma(ide_drive_t *drive)
244 {
245 struct hd_driveid *id = drive->id;
246 ide_hwif_t *hwif = HWIF(drive);
247 u8 ultra_66 = (id->dma_ultra & 0x0078) ? 1 : 0;
248 u8 cable = pdcnew_cable_detect(hwif);
249 u8 speed;
250
251 if (ultra_66 && cable) {
252 printk(KERN_WARNING "Warning: %s channel "
253 "requires an 80-pin cable for operation.\n",
254 hwif->channel ? "Secondary" : "Primary");
255 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
256 }
257
258 if (id->capability & 4) {
259 /*
260 * Set IORDY_EN & PREFETCH_EN (this seems to have
261 * NO real effect since this register is reloaded
262 * by hardware when the transfer mode is selected)
263 */
264 u8 tmp, adj = (drive->dn & 1) ? 0x08 : 0x00;
265
266 tmp = get_indexed_reg(hwif, 0x13 + adj);
267 set_indexed_reg(hwif, 0x13 + adj, tmp | 0x03);
268 }
269
270 speed = ide_dma_speed(drive, pdcnew_ratemask(drive));
271
272 if (!speed)
273 return 0;
274
275 (void) hwif->speedproc(drive, speed);
276 return ide_dma_enable(drive);
277 }
278
279 static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
280 {
281 drive->init_speed = 0;
282
283 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
284 return 0;
285
286 if (ide_use_fast_pio(drive))
287 pdcnew_tune_drive(drive, 255);
288
289 return -1;
290 }
291
292 static int pdcnew_quirkproc(ide_drive_t *drive)
293 {
294 const char **list, *model = drive->id->model;
295
296 for (list = pdc_quirk_drives; *list != NULL; list++)
297 if (strstr(model, *list) != NULL)
298 return 2;
299 return 0;
300 }
301
302 static void pdcnew_reset(ide_drive_t *drive)
303 {
304 /*
305 * Deleted this because it is redundant from the caller.
306 */
307 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
308 HWIF(drive)->channel ? "Secondary" : "Primary");
309 }
310
311 /**
312 * read_counter - Read the byte count registers
313 * @dma_base: for the port address
314 */
315 static long __devinit read_counter(u32 dma_base)
316 {
317 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
318 u8 cnt0, cnt1, cnt2, cnt3;
319 long count = 0, last;
320 int retry = 3;
321
322 do {
323 last = count;
324
325 /* Read the current count */
326 outb(0x20, pri_dma_base + 0x01);
327 cnt0 = inb(pri_dma_base + 0x03);
328 outb(0x21, pri_dma_base + 0x01);
329 cnt1 = inb(pri_dma_base + 0x03);
330 outb(0x20, sec_dma_base + 0x01);
331 cnt2 = inb(sec_dma_base + 0x03);
332 outb(0x21, sec_dma_base + 0x01);
333 cnt3 = inb(sec_dma_base + 0x03);
334
335 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
336
337 /*
338 * The 30-bit decrementing counter is read in 4 pieces.
339 * Incorrect value may be read when the most significant bytes
340 * are changing...
341 */
342 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
343
344 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
345 cnt0, cnt1, cnt2, cnt3);
346
347 return count;
348 }
349
350 /**
351 * detect_pll_input_clock - Detect the PLL input clock in Hz.
352 * @dma_base: for the port address
353 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
354 */
355 static long __devinit detect_pll_input_clock(unsigned long dma_base)
356 {
357 long start_count, end_count;
358 long pll_input;
359 u8 scr1;
360
361 start_count = read_counter(dma_base);
362
363 /* Start the test mode */
364 outb(0x01, dma_base + 0x01);
365 scr1 = inb(dma_base + 0x03);
366 DBG("scr1[%02X]\n", scr1);
367 outb(scr1 | 0x40, dma_base + 0x03);
368
369 /* Let the counter run for 10 ms. */
370 mdelay(10);
371
372 end_count = read_counter(dma_base);
373
374 /* Stop the test mode */
375 outb(0x01, dma_base + 0x01);
376 scr1 = inb(dma_base + 0x03);
377 DBG("scr1[%02X]\n", scr1);
378 outb(scr1 & ~0x40, dma_base + 0x03);
379
380 /*
381 * Calculate the input clock in Hz
382 * (the clock counter is 30 bit wide and counts down)
383 */
384 pll_input = ((start_count - end_count) & 0x3ffffff) * 100;
385
386 DBG("start[%ld] end[%ld]\n", start_count, end_count);
387
388 return pll_input;
389 }
390
391 #ifdef CONFIG_PPC_PMAC
392 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
393 {
394 struct device_node *np = pci_device_to_OF_node(pdev);
395 unsigned int class_rev = 0;
396 u8 conf;
397
398 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
399 return;
400
401 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
402 class_rev &= 0xff;
403
404 if (class_rev >= 0x03) {
405 /* Setup chip magic config stuff (from darwin) */
406 pci_read_config_byte (pdev, 0x40, &conf);
407 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
408 }
409 }
410 #endif /* CONFIG_PPC_PMAC */
411
412 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
413 {
414 unsigned long dma_base = pci_resource_start(dev, 4);
415 unsigned long sec_dma_base = dma_base + 0x08;
416 long pll_input, pll_output, ratio;
417 int f, r;
418 u8 pll_ctl0, pll_ctl1;
419
420 if (dev->resource[PCI_ROM_RESOURCE].start) {
421 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
422 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
423 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
424 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
425 }
426
427 #ifdef CONFIG_PPC_PMAC
428 apple_kiwi_init(dev);
429 #endif
430
431 /* Calculate the required PLL output frequency */
432 switch(max_dma_rate(dev)) {
433 case 4: /* it's 133 MHz for Ultra133 chips */
434 pll_output = 133333333;
435 break;
436 case 3: /* and 100 MHz for Ultra100 chips */
437 default:
438 pll_output = 100000000;
439 break;
440 }
441
442 /*
443 * Detect PLL input clock.
444 * On some systems, where PCI bus is running at non-standard clock rate
445 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
446 * PDC20268 and newer chips employ PLL circuit to help correct timing
447 * registers setting.
448 */
449 pll_input = detect_pll_input_clock(dma_base);
450 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
451
452 /* Sanity check */
453 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
454 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
455 name, pll_input);
456 goto out;
457 }
458
459 #ifdef DEBUG
460 DBG("pll_output is %ld Hz\n", pll_output);
461
462 /* Show the current clock value of PLL control register
463 * (maybe already configured by the BIOS)
464 */
465 outb(0x02, sec_dma_base + 0x01);
466 pll_ctl0 = inb(sec_dma_base + 0x03);
467 outb(0x03, sec_dma_base + 0x01);
468 pll_ctl1 = inb(sec_dma_base + 0x03);
469
470 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
471 #endif
472
473 /*
474 * Calculate the ratio of F, R and NO
475 * POUT = (F + 2) / (( R + 2) * NO)
476 */
477 ratio = pll_output / (pll_input / 1000);
478 if (ratio < 8600L) { /* 8.6x */
479 /* Using NO = 0x01, R = 0x0d */
480 r = 0x0d;
481 } else if (ratio < 12900L) { /* 12.9x */
482 /* Using NO = 0x01, R = 0x08 */
483 r = 0x08;
484 } else if (ratio < 16100L) { /* 16.1x */
485 /* Using NO = 0x01, R = 0x06 */
486 r = 0x06;
487 } else if (ratio < 64000L) { /* 64x */
488 r = 0x00;
489 } else {
490 /* Invalid ratio */
491 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
492 goto out;
493 }
494
495 f = (ratio * (r + 2)) / 1000 - 2;
496
497 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
498
499 if (unlikely(f < 0 || f > 127)) {
500 /* Invalid F */
501 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
502 goto out;
503 }
504
505 pll_ctl0 = (u8) f;
506 pll_ctl1 = (u8) r;
507
508 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
509
510 outb(0x02, sec_dma_base + 0x01);
511 outb(pll_ctl0, sec_dma_base + 0x03);
512 outb(0x03, sec_dma_base + 0x01);
513 outb(pll_ctl1, sec_dma_base + 0x03);
514
515 /* Wait the PLL circuit to be stable */
516 mdelay(30);
517
518 #ifdef DEBUG
519 /*
520 * Show the current clock value of PLL control register
521 */
522 outb(0x02, sec_dma_base + 0x01);
523 pll_ctl0 = inb(sec_dma_base + 0x03);
524 outb(0x03, sec_dma_base + 0x01);
525 pll_ctl1 = inb(sec_dma_base + 0x03);
526
527 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
528 #endif
529
530 out:
531 return dev->irq;
532 }
533
534 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
535 {
536 hwif->autodma = 0;
537
538 hwif->tuneproc = &pdcnew_tune_drive;
539 hwif->quirkproc = &pdcnew_quirkproc;
540 hwif->speedproc = &pdcnew_tune_chipset;
541 hwif->resetproc = &pdcnew_reset;
542
543 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
544
545 hwif->atapi_dma = 1;
546 hwif->ultra_mask = 0x7f;
547 hwif->mwdma_mask = 0x07;
548
549 hwif->err_stops_fifo = 1;
550
551 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
552
553 if (!hwif->udma_four)
554 hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1;
555
556 if (!noautodma)
557 hwif->autodma = 1;
558 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
559
560 #if PDC202_DEBUG_CABLE
561 printk(KERN_DEBUG "%s: %s-pin cable\n",
562 hwif->name, hwif->udma_four ? "80" : "40");
563 #endif /* PDC202_DEBUG_CABLE */
564 }
565
566 static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
567 {
568 return ide_setup_pci_device(dev, d);
569 }
570
571 static int __devinit init_setup_pdc20270(struct pci_dev *dev,
572 ide_pci_device_t *d)
573 {
574 struct pci_dev *findev = NULL;
575 int ret;
576
577 if ((dev->bus->self &&
578 dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
579 (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
580 if (PCI_SLOT(dev->devfn) & 2)
581 return -ENODEV;
582 d->extra = 0;
583 while ((findev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
584 if ((findev->vendor == dev->vendor) &&
585 (findev->device == dev->device) &&
586 (PCI_SLOT(findev->devfn) & 2)) {
587 if (findev->irq != dev->irq) {
588 findev->irq = dev->irq;
589 }
590 ret = ide_setup_pci_devices(dev, findev, d);
591 pci_dev_put(findev);
592 return ret;
593 }
594 }
595 }
596 return ide_setup_pci_device(dev, d);
597 }
598
599 static int __devinit init_setup_pdc20276(struct pci_dev *dev,
600 ide_pci_device_t *d)
601 {
602 if ((dev->bus->self) &&
603 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
604 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
605 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
606 printk(KERN_INFO "ide: Skipping Promise PDC20276 "
607 "attached to I2O RAID controller.\n");
608 return -ENODEV;
609 }
610 return ide_setup_pci_device(dev, d);
611 }
612
613 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
614 { /* 0 */
615 .name = "PDC20268",
616 .init_setup = init_setup_pdcnew,
617 .init_chipset = init_chipset_pdcnew,
618 .init_hwif = init_hwif_pdc202new,
619 .channels = 2,
620 .autodma = AUTODMA,
621 .bootable = OFF_BOARD,
622 },{ /* 1 */
623 .name = "PDC20269",
624 .init_setup = init_setup_pdcnew,
625 .init_chipset = init_chipset_pdcnew,
626 .init_hwif = init_hwif_pdc202new,
627 .channels = 2,
628 .autodma = AUTODMA,
629 .bootable = OFF_BOARD,
630 },{ /* 2 */
631 .name = "PDC20270",
632 .init_setup = init_setup_pdc20270,
633 .init_chipset = init_chipset_pdcnew,
634 .init_hwif = init_hwif_pdc202new,
635 .channels = 2,
636 .autodma = AUTODMA,
637 .bootable = OFF_BOARD,
638 },{ /* 3 */
639 .name = "PDC20271",
640 .init_setup = init_setup_pdcnew,
641 .init_chipset = init_chipset_pdcnew,
642 .init_hwif = init_hwif_pdc202new,
643 .channels = 2,
644 .autodma = AUTODMA,
645 .bootable = OFF_BOARD,
646 },{ /* 4 */
647 .name = "PDC20275",
648 .init_setup = init_setup_pdcnew,
649 .init_chipset = init_chipset_pdcnew,
650 .init_hwif = init_hwif_pdc202new,
651 .channels = 2,
652 .autodma = AUTODMA,
653 .bootable = OFF_BOARD,
654 },{ /* 5 */
655 .name = "PDC20276",
656 .init_setup = init_setup_pdc20276,
657 .init_chipset = init_chipset_pdcnew,
658 .init_hwif = init_hwif_pdc202new,
659 .channels = 2,
660 .autodma = AUTODMA,
661 .bootable = OFF_BOARD,
662 },{ /* 6 */
663 .name = "PDC20277",
664 .init_setup = init_setup_pdcnew,
665 .init_chipset = init_chipset_pdcnew,
666 .init_hwif = init_hwif_pdc202new,
667 .channels = 2,
668 .autodma = AUTODMA,
669 .bootable = OFF_BOARD,
670 }
671 };
672
673 /**
674 * pdc202new_init_one - called when a pdc202xx is found
675 * @dev: the pdc202new device
676 * @id: the matching pci id
677 *
678 * Called when the PCI registration layer (or the IDE initialization)
679 * finds a device matching our IDE device tables.
680 */
681
682 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
683 {
684 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
685
686 return d->init_setup(dev, d);
687 }
688
689 static struct pci_device_id pdc202new_pci_tbl[] = {
690 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
691 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
692 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
693 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
694 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
695 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
696 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
697 { 0, },
698 };
699 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
700
701 static struct pci_driver driver = {
702 .name = "Promise_IDE",
703 .id_table = pdc202new_pci_tbl,
704 .probe = pdc202new_init_one,
705 };
706
707 static int __init pdc202new_ide_init(void)
708 {
709 return ide_pci_register_driver(&driver);
710 }
711
712 module_init(pdc202new_ide_init);
713
714 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
715 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
716 MODULE_LICENSE("GPL");
WandBoard kernel