clext.c

   1 //
   2 //  QEMU Cirrus CLGD 54xx VGABIOS Extension.
   3 //
   4 //  Copyright (c) 2004 Makoto Suzuki (suzu)
   5 //
   6 //  This library is free software; you can redistribute it and/or
   7 //  modify it under the terms of the GNU Lesser General Public
   8 //  License as published by the Free Software Foundation; either
   9 //  version 2 of the License, or (at your option) any later version.
  10 //
  11 //  This library is distributed in the hope that it will be useful,
  12 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 //  Lesser General Public License for more details.
  15 //
  16 //  You should have received a copy of the GNU Lesser General Public
  17 //  License along with this library; if not, write to the Free Software
  18 //  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19 //
  20
  21 //#define CIRRUS_VESA3_PMINFO
  22 #ifdef VBE
  23 #undef CIRRUS_VESA3_PMINFO
  24 #endif
  25
  26 #define PM_BIOSMEM_CURRENT_MODE 0x449
  27 #define PM_BIOSMEM_CRTC_ADDRESS 0x463
  28 #define PM_BIOSMEM_VBE_MODE 0x4BA
  29
  30 typedef struct
  31 {
  32   /* + 0 */
  33   unsigned short mode;
  34   unsigned short width;
  35   unsigned short height;
  36   unsigned short depth;
  37   /* + 8 */
  38   unsigned short hidden_dac; /* 0x3c6 */
  39   unsigned short *seq; /* 0x3c4 */
  40   unsigned short *graph; /* 0x3ce */
  41   unsigned short *crtc; /* 0x3d4 */
  42   /* +16 */
  43   unsigned char bitsperpixel;
  44   unsigned char vesacolortype;
  45   unsigned char vesaredmask;
  46   unsigned char vesaredpos;
  47   unsigned char vesagreenmask;
  48   unsigned char vesagreenpos;
  49   unsigned char vesabluemask;
  50   unsigned char vesabluepos;
  51   /* +24 */
  52   unsigned char vesareservedmask;
  53   unsigned char vesareservedpos;
  54 } cirrus_mode_t;
  55 #define CIRRUS_MODE_SIZE 26
  56
  57
  58 /* For VESA BIOS 3.0 */
  59 #define CIRRUS_PM16INFO_SIZE 20
  60
  61 /* VGA */
  62 unsigned short cseq_vga[] = {0x0007,0xffff};
  63 unsigned short cgraph_vga[] = {0x0009,0x000a,0x000b,0xffff};
  64 unsigned short ccrtc_vga[] = {0x001a,0x001b,0x001d,0xffff};
  65
  66 /* extensions */
  67 unsigned short cgraph_svgacolor[] = {
  68 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
  69 0x0009,0x000a,0x000b,
  70 0xffff
  71 };
  72 /* 640x480x8 */
  73 unsigned short cseq_640x480x8[] = {
  74 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  75 0x580b,0x580c,0x580d,0x580e,
  76 0x0412,0x0013,0x2017,
  77 0x331b,0x331c,0x331d,0x331e,
  78 0xffff
  79 };
  80 unsigned short ccrtc_640x480x8[] = {
  81 0x2c11,
  82 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  83 0x4009,0x000c,0x000d,
  84 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  85 0x001a,0x221b,0x001d,
  86 0xffff
  87 };
  88 /* 640x480x16 */
  89 unsigned short cseq_640x480x16[] = {
  90 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
  91 0x580b,0x580c,0x580d,0x580e,
  92 0x0412,0x0013,0x2017,
  93 0x331b,0x331c,0x331d,0x331e,
  94 0xffff
  95 };
  96 unsigned short ccrtc_640x480x16[] = {
  97 0x2c11,
  98 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  99 0x4009,0x000c,0x000d,
 100 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
 101 0x001a,0x221b,0x001d,
 102 0xffff
 103 };
 104 /* 640x480x24 */
 105 unsigned short cseq_640x480x24[] = {
 106 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 107 0x580b,0x580c,0x580d,0x580e,
 108 0x0412,0x0013,0x2017,
 109 0x331b,0x331c,0x331d,0x331e,
 110 0xffff
 111 };
 112 unsigned short ccrtc_640x480x24[] = {
 113 0x2c11,
 114 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
 115 0x4009,0x000c,0x000d,
 116 0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
 117 0x001a,0x321b,0x001d,
 118 0xffff
 119 };
 120 /* 800x600x8 */
 121 unsigned short cseq_800x600x8[] = {
 122 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 123 0x230b,0x230c,0x230d,0x230e,
 124 0x0412,0x0013,0x2017,
 125 0x141b,0x141c,0x141d,0x141e,
 126 0xffff
 127 };
 128 unsigned short ccrtc_800x600x8[] = {
 129 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 130 0x6009,0x000c,0x000d,
 131 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
 132 0x001a,0x221b,0x001d,
 133 0xffff
 134 };
 135 /* 800x600x16 */
 136 unsigned short cseq_800x600x16[] = {
 137 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 138 0x230b,0x230c,0x230d,0x230e,
 139 0x0412,0x0013,0x2017,
 140 0x141b,0x141c,0x141d,0x141e,
 141 0xffff
 142 };
 143 unsigned short ccrtc_800x600x16[] = {
 144 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 145 0x6009,0x000c,0x000d,
 146 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
 147 0x001a,0x221b,0x001d,
 148 0xffff
 149 };
 150 /* 800x600x24 */
 151 unsigned short cseq_800x600x24[] = {
 152 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 153 0x230b,0x230c,0x230d,0x230e,
 154 0x0412,0x0013,0x2017,
 155 0x141b,0x141c,0x141d,0x141e,
 156 0xffff
 157 };
 158 unsigned short ccrtc_800x600x24[] = {
 159 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 160 0x6009,0x000c,0x000d,
 161 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
 162 0x001a,0x321b,0x001d,
 163 0xffff
 164 };
 165 /* 1024x768x8 */
 166 unsigned short cseq_1024x768x8[] = {
 167 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 168 0x760b,0x760c,0x760d,0x760e,
 169 0x0412,0x0013,0x2017,
 170 0x341b,0x341c,0x341d,0x341e,
 171 0xffff
 172 };
 173 unsigned short ccrtc_1024x768x8[] = {
 174 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 175 0x6009,0x000c,0x000d,
 176 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 177 0x001a,0x221b,0x001d,
 178 0xffff
 179 };
 180 /* 1024x768x16 */
 181 unsigned short cseq_1024x768x16[] = {
 182 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 183 0x760b,0x760c,0x760d,0x760e,
 184 0x0412,0x0013,0x2017,
 185 0x341b,0x341c,0x341d,0x341e,
 186 0xffff
 187 };
 188 unsigned short ccrtc_1024x768x16[] = {
 189 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 190 0x6009,0x000c,0x000d,
 191 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
 192 0x001a,0x321b,0x001d,
 193 0xffff
 194 };
 195 /* 1024x768x24 */
 196 unsigned short cseq_1024x768x24[] = {
 197 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 198 0x760b,0x760c,0x760d,0x760e,
 199 0x0412,0x0013,0x2017,
 200 0x341b,0x341c,0x341d,0x341e,
 201 0xffff
 202 };
 203 unsigned short ccrtc_1024x768x24[] = {
 204 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 205 0x6009,0x000c,0x000d,
 206 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 207 0x001a,0x321b,0x001d,
 208 0xffff
 209 };
 210 /* 1280x1024x8 */
 211 unsigned short cseq_1280x1024x8[] = {
 212 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 213 0x760b,0x760c,0x760d,0x760e,
 214 0x0412,0x0013,0x2017,
 215 0x341b,0x341c,0x341d,0x341e,
 216 0xffff
 217 };
 218 unsigned short ccrtc_1280x1024x8[] = {
 219 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 220 0x6009,0x000c,0x000d,
 221 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 222 0x001a,0x221b,0x001d,
 223 0xffff
 224 };
 225 /* 1280x1024x16 */
 226 unsigned short cseq_1280x1024x16[] = {
 227 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 228 0x760b,0x760c,0x760d,0x760e,
 229 0x0412,0x0013,0x2017,
 230 0x341b,0x341c,0x341d,0x341e,
 231 0xffff
 232 };
 233 unsigned short ccrtc_1280x1024x16[] = {
 234 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 235 0x6009,0x000c,0x000d,
 236 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
 237 0x001a,0x321b,0x001d,
 238 0xffff
 239 };
 240
 241
 242 cirrus_mode_t cirrus_modes[] =
 243 {
 244  {0x5f,640,480,8,0x00,
 245    cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
 246    4,0,0,0,0,0,0,0,0},
 247  {0x64,640,480,16,0xe1,
 248    cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
 249    6,5,11,6,5,5,0,0,0},
 250  {0x66,640,480,15,0xf0,
 251    cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
 252    6,5,10,5,5,5,0,1,15},
 253  {0x71,640,480,24,0xe5,
 254    cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
 255    6,8,16,8,8,8,0,0,0},
 256
 257  {0x5c,800,600,8,0x00,
 258    cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
 259    4,0,0,0,0,0,0,0,0},
 260  {0x65,800,600,16,0xe1,
 261    cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
 262    6,5,11,6,5,5,0,0,0},
 263  {0x67,800,600,15,0xf0,
 264    cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
 265    6,5,10,5,5,5,0,1,15},
 266
 267  {0x60,1024,768,8,0x00,
 268    cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
 269    4,0,0,0,0,0,0,0,0},
 270  {0x74,1024,768,16,0xe1,
 271    cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
 272    6,5,11,6,5,5,0,0,0},
 273  {0x68,1024,768,15,0xf0,
 274    cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
 275    6,5,10,5,5,5,0,1,15},
 276
 277  {0x78,800,600,24,0xe5,
 278    cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
 279    6,8,16,8,8,8,0,0,0},
 280  {0x79,1024,768,24,0xe5,
 281    cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
 282    6,8,16,8,8,8,0,0,0},
 283
 284  {0x6d,1280,1024,8,0x00,
 285    cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
 286    4,0,0,0,0,0,0,0,0},
 287  {0x69,1280,1024,15,0xf0,
 288    cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
 289    6,5,10,5,5,5,0,1,15},
 290  {0x75,1280,1024,16,0xe1,
 291    cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
 292    6,5,11,6,5,5,0,0,0},
 293
 294  {0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
 295    0xff,0,0,0,0,0,0,0,0},
 296  {0xff,0,0,0,0,0,0,0,0,
 297    0xff,0,0,0,0,0,0,0,0},
 298 };
 299
 300 unsigned char cirrus_id_table[] = {
 301   // 5430
 302   0xA0, 0x32,
 303   // 5446
 304   0xB8, 0x39,
 305
 306   0xff, 0xff
 307 };
 308
 309
 310 unsigned short cirrus_vesa_modelist[] = {
 311 // 640x480x8
 312   0x101, 0x5f,
 313 // 640x480x15
 314   0x110, 0x66,
 315 // 640x480x16
 316   0x111, 0x64,
 317 // 640x480x24
 318   0x112, 0x71,
 319 // 800x600x8
 320   0x103, 0x5c,
 321 // 800x600x15
 322   0x113, 0x67,
 323 // 800x600x16
 324   0x114, 0x65,
 325 // 800x600x24
 326   0x115, 0x78,
 327 // 1024x768x8
 328   0x105, 0x60,
 329 // 1024x768x15
 330   0x116, 0x68,
 331 // 1024x768x16
 332   0x117, 0x74,
 333 // 1024x768x24
 334   0x118, 0x79,
 335 // 1280x1024x8
 336   0x107, 0x6d,
 337 // 1280x1024x15
 338   0x119, 0x69,
 339 // 1280x1024x16
 340   0x11a, 0x75,
 341 // invalid
 342   0xffff,0xffff
 343 };
 344
 345
 346 ASM_START
 347
 348 cirrus_installed:
 349 .ascii "cirrus-compatible VGA is detected"
 350 .byte 0x0d,0x0a
 351 .byte 0x0d,0x0a,0x00
 352
 353 cirrus_not_installed:
 354 .ascii "cirrus-compatible VGA is not detected"
 355 .byte 0x0d,0x0a
 356 .byte 0x0d,0x0a,0x00
 357
 358 cirrus_vesa_vendorname:
 359 cirrus_vesa_productname:
 360 cirrus_vesa_oemname:
 361 .ascii "VGABIOS Cirrus extension"
 362 .byte 0
 363 cirrus_vesa_productrevision:
 364 .ascii "1.0"
 365 .byte 0
 366
 367 cirrus_init:
 368   call cirrus_check
 369   jnz no_cirrus
 370   SET_INT_VECTOR(0x10, #0xC000, #cirrus_int10_handler)
 371   mov al, #0x0f ; memory setup
 372   mov dx, #0x3C4
 373   out dx, al
 374   inc dx
 375   in  al, dx
 376   and al, #0x18
 377   mov ah, al
 378   mov al, #0x0a
 379   dec dx
 380   out dx, ax
 381   mov ax, #0x0007 ; set vga mode
 382   out dx, ax
 383   mov ax, #0x0431 ; reset bitblt
 384   mov dx, #0x3CE
 385   out dx, ax
 386   mov ax, #0x0031
 387   out dx, ax
 388 no_cirrus:
 389   ret
 390
 391 cirrus_display_info:
 392   push ds
 393   push si
 394   push cs
 395   pop ds
 396   call cirrus_check
 397   mov si, #cirrus_not_installed
 398   jnz cirrus_msgnotinstalled
 399   mov si, #cirrus_installed
 400
 401 cirrus_msgnotinstalled:
 402   call _display_string
 403   pop si
 404   pop ds
 405   ret
 406
 407 cirrus_check:
 408   push ax
 409   push dx
 410   mov ax, #0x9206
 411   mov dx, #0x3C4
 412   out dx, ax
 413   inc dx
 414   in al, dx
 415   cmp al, #0x12
 416   pop dx
 417   pop ax
 418   ret
 419
 420
 421 cirrus_int10_handler:
 422   pushf
 423   push bp
 424   cmp ah, #0x00  ;; set video mode
 425   jz cirrus_set_video_mode
 426   cmp ah, #0x12  ;; cirrus extension
 427   jz cirrus_extbios
 428   cmp ah, #0x4F  ;; VESA extension
 429   jz cirrus_vesa
 430
 431 cirrus_unhandled:
 432   pop bp
 433   popf
 434   jmp vgabios_int10_handler
 435
 436 cirrus_return:
 437 #ifdef CIRRUS_DEBUG
 438   call cirrus_debug_dump
 439 #endif
 440   pop bp
 441   popf
 442   iret
 443
 444 cirrus_set_video_mode:
 445 #ifdef CIRRUS_DEBUG
 446   call cirrus_debug_dump
 447 #endif
 448   push si
 449   push ax
 450   push bx
 451   push ds
 452 #ifdef CIRRUS_VESA3_PMINFO
 453  db 0x2e ;; cs:
 454   mov si, [cirrus_vesa_sel0000_data]
 455 #else
 456   xor si, si
 457 #endif
 458   mov ds, si
 459   xor bx, bx
 460   mov [PM_BIOSMEM_VBE_MODE], bx
 461   pop ds
 462   pop bx
 463   call cirrus_get_modeentry
 464   jnc cirrus_set_video_mode_extended
 465   mov al, #0xfe
 466   call cirrus_get_modeentry_nomask
 467   call cirrus_switch_mode
 468   pop ax
 469   pop si
 470   jmp cirrus_unhandled
 471
 472 cirrus_extbios:
 473 #ifdef CIRRUS_DEBUG
 474   call cirrus_debug_dump
 475 #endif
 476   cmp bl, #0x80
 477   jb cirrus_unhandled
 478   cmp bl, #0xAF
 479   ja cirrus_unhandled
 480   push bx
 481   and bx, #0x7F
 482   shl bx, 1
 483  db 0x2e ;; cs:
 484   mov bp, cirrus_extbios_handlers[bx]
 485   pop bx
 486   push #cirrus_return
 487   push bp
 488   ret
 489
 490 cirrus_vesa:
 491 #ifdef CIRRUS_DEBUG
 492   call cirrus_debug_dump
 493 #endif
 494   cmp al, #0x0F
 495   ja cirrus_vesa_not_handled
 496   push bx
 497   xor bx, bx
 498   mov bl, al
 499   shl bx, 1
 500  db 0x2e ;; cs:
 501   mov bp, cirrus_vesa_handlers[bx]
 502   pop bx
 503   push #cirrus_return
 504   push bp
 505   ret
 506
 507 cirrus_vesa_not_handled:
 508   mov ax, #0x014F ;; not implemented
 509   jmp cirrus_return
 510
 511 #ifdef CIRRUS_DEBUG
 512 cirrus_debug_dump:
 513   push es
 514   push ds
 515   pusha
 516   push cs
 517   pop ds
 518   call _cirrus_debugmsg
 519   popa
 520   pop ds
 521   pop es
 522   ret
 523 #endif
 524
 525 cirrus_set_video_mode_extended:
 526   call cirrus_switch_mode
 527   pop ax ;; mode
 528   and al, #0x7f
 529
 530   push ds
 531 #ifdef CIRRUS_VESA3_PMINFO
 532  db 0x2e ;; cs:
 533   mov si, [cirrus_vesa_sel0000_data]
 534 #else
 535   xor si, si
 536 #endif
 537   mov ds, si
 538   mov [PM_BIOSMEM_CURRENT_MODE], al
 539   pop ds
 540
 541   mov al, #0x20
 542
 543   pop si
 544   jmp cirrus_return
 545
 546 cirrus_vesa_pmbios_init:
 547   retf
 548 cirrus_vesa_pmbios_entry:
 549   pushf
 550   push bp
 551   cmp ah, #0x4F
 552   jnz cirrus_vesa_pmbios_unimplemented
 553   cmp al, #0x0F
 554   ja cirrus_vesa_pmbios_unimplemented
 555   push bx
 556   xor bx, bx
 557   mov bl, al
 558   shl bx, 1
 559  db 0x2e ;; cs:
 560   mov bp, cirrus_vesa_handlers[bx]
 561   pop bx
 562   push #cirrus_vesa_pmbios_return
 563   push bp
 564   ret
 565 cirrus_vesa_pmbios_unimplemented:
 566   mov ax, #0x014F
 567 cirrus_vesa_pmbios_return:
 568   pop bp
 569   popf
 570   retf
 571
 572 ; in si:mode table
 573 cirrus_switch_mode:
 574   push ds
 575   push bx
 576   push dx
 577   push cs
 578   pop ds
 579
 580   mov bx, [si+10] ;; seq
 581   mov dx, #0x3c4
 582   mov ax, #0x1206
 583   out dx, ax ;; Unlock cirrus special
 584   call cirrus_switch_mode_setregs
 585
 586   mov bx, [si+12] ;; graph
 587   mov dx, #0x3ce
 588   call cirrus_switch_mode_setregs
 589
 590   mov bx, [si+14] ;; crtc
 591   call cirrus_get_crtc
 592   call cirrus_switch_mode_setregs
 593
 594   mov dx, #0x3c6
 595   mov al, #0x00
 596   out dx, al
 597   in al, dx
 598   in al, dx
 599   in al, dx
 600   in al, dx
 601   mov al, [si+8]  ;; hidden dac
 602   out dx, al
 603   mov al, #0xff
 604   out dx, al
 605
 606   mov al, #0x00
 607   mov bl, [si+17]  ;; memory model
 608   or  bl, bl
 609   jz is_text_mode
 610   mov al, #0x01
 611   cmp bl, #0x03
 612   jnz is_text_mode
 613   or al, #0x40
 614 is_text_mode:
 615   mov bl, #0x10
 616   call biosfn_get_single_palette_reg
 617   and bh, #0xfe
 618   or bh, al
 619   call biosfn_set_single_palette_reg
 620
 621   pop dx
 622   pop bx
 623   pop ds
 624   ret
 625
 626 cirrus_enable_16k_granularity:
 627   push ax
 628   push dx
 629   mov dx, #0x3ce
 630   mov al, #0x0b
 631   out dx, al
 632   inc dx
 633   in al, dx
 634   or al, #0x20 ;; enable 16k
 635   out dx, al
 636   pop dx
 637   pop ax
 638   ret
 639
 640 cirrus_switch_mode_setregs:
 641 csms_1:
 642   mov ax, [bx]
 643   cmp ax, #0xffff
 644   jz csms_2
 645   out dx, ax
 646   add bx, #0x2
 647   jmp csms_1
 648 csms_2:
 649   ret
 650
 651 cirrus_extbios_80h:
 652   push dx
 653   call cirrus_get_crtc
 654   mov al, #0x27
 655   out dx, al
 656   inc dx
 657   in al, dx
 658   mov bx, #_cirrus_id_table
 659 c80h_1:
 660  db 0x2e ;; cs:
 661   mov ah, [bx]
 662   cmp ah, al
 663   jz c80h_2
 664   cmp ah, #0xff
 665   jz c80h_2
 666   inc bx
 667   inc bx
 668   jmp c80h_1
 669 c80h_2:
 670  db 0x2e ;; cs:
 671   mov al, 0x1[bx]
 672   pop dx
 673   mov ah, #0x00
 674   xor bx, bx
 675   ret
 676
 677 cirrus_extbios_81h:
 678   mov ax, #0x100 ;; XXX
 679   ret
 680 cirrus_extbios_82h:
 681   push dx
 682   call cirrus_get_crtc
 683   xor ax, ax
 684   mov al, #0x27
 685   out dx, al
 686   inc dx
 687   in al, dx
 688   and al, #0x03
 689   mov ah, #0xAF
 690   pop dx
 691   ret
 692
 693 cirrus_extbios_85h:
 694   push cx
 695   push dx
 696   mov dx, #0x3C4
 697   mov al, #0x0f ;; get DRAM band width
 698   out dx, al
 699   inc dx
 700   in al, dx
 701   ;; al = 4 << bandwidth
 702   mov cl, al
 703   shr cl, #0x03
 704   and cl, #0x03
 705   cmp cl, #0x03
 706   je c85h2
 707   mov al, #0x04
 708   shl al, cl
 709   jmp c85h3
 710 c85h2:
 711 ;; 4MB or 2MB
 712   and al, #0x80
 713   mov al, #0x20 ;; 2 MB
 714   je c85h3
 715   mov al, #0x40 ;; 4 MB
 716 c85h3:
 717   pop dx
 718   pop cx
 719   ret
 720
 721 cirrus_extbios_9Ah:
 722   mov ax, #0x4060
 723   mov cx, #0x1132
 724   ret
 725
 726 cirrus_extbios_A0h:
 727   call cirrus_get_modeentry
 728   mov ah, #0x01
 729   sbb ah, #0x00
 730   mov bx, cirrus_extbios_A0h_callback
 731   mov si, #0xffff
 732   mov di, bx
 733   mov ds, bx
 734   mov es, bx
 735   ret
 736
 737 cirrus_extbios_A0h_callback:
 738   ;; fatal: not implemented yet
 739   cli
 740   hlt
 741   retf
 742
 743 cirrus_extbios_A1h:
 744   mov bx, #0x0E00 ;; IBM 8512/8513, color
 745   ret
 746
 747 cirrus_extbios_A2h:
 748   mov al, #0x07   ;; HSync 31.5 - 64.0 kHz
 749   ret
 750
 751 cirrus_extbios_AEh:
 752   mov al, #0x01   ;; High Refresh 75Hz
 753   ret
 754
 755 cirrus_extbios_unimplemented:
 756   ret
 757
 758 cirrus_vesa_00h:
 759   push ds
 760   push si
 761   mov bp, di
 762   push es
 763   pop ds
 764   cld
 765   mov ax, [di]
 766   cmp ax, #0x4256 ;; VB
 767   jnz cv00_1
 768   mov ax, [di+2]
 769   cmp ax, #0x3245 ;; E2
 770   jnz cv00_1
 771   ;; VBE2
 772   lea di, 0x14[bp]
 773   mov ax, #0x0100 ;; soft ver.
 774   stosw
 775   mov ax, # cirrus_vesa_vendorname
 776   stosw
 777   mov ax, cs
 778   stosw
 779   mov ax, # cirrus_vesa_productname
 780   stosw
 781   mov ax, cs
 782   stosw
 783   mov ax, # cirrus_vesa_productrevision
 784   stosw
 785   mov ax, cs
 786   stosw
 787 cv00_1:
 788   mov di, bp
 789   mov ax, #0x4556 ;; VE
 790   stosw
 791   mov ax, #0x4153 ;; SA
 792   stosw
 793   mov ax, #0x0200 ;; v2.00
 794   stosw
 795   mov ax, # cirrus_vesa_oemname
 796   stosw
 797   mov ax, cs
 798   stosw
 799   xor ax, ax ;; caps
 800   stosw
 801   stosw
 802   lea ax, 0x40[bp]
 803   stosw
 804   mov ax, es
 805   stosw
 806   call cirrus_extbios_85h ;; vram in 64k
 807   mov ah, #0x00
 808   stosw
 809
 810   push cs
 811   pop ds
 812   lea di, 0x40[bp]
 813   mov si, #_cirrus_vesa_modelist
 814 cv00_2:
 815   lodsw
 816   stosw
 817   add si, #2
 818   cmp ax, #0xffff
 819   jnz cv00_2
 820
 821   mov ax, #0x004F
 822   mov di, bp
 823   pop si
 824   pop ds
 825   ret
 826
 827 cirrus_vesa_01h:
 828   mov ax, cx
 829   and ax, #0x3fff
 830   call cirrus_vesamode_to_mode
 831   cmp ax, #0xffff
 832   jnz cirrus_vesa_01h_1
 833   jmp cirrus_vesa_unimplemented
 834 cirrus_vesa_01h_1:
 835   push ds
 836   push si
 837   push cx
 838   push dx
 839   push bx
 840   mov bp, di
 841   cld
 842   push cs
 843   pop ds
 844   call cirrus_get_modeentry_nomask
 845
 846   push di
 847   xor ax, ax
 848   mov cx, #0x80
 849   rep
 850     stosw ;; clear buffer
 851   pop di
 852
 853   mov ax, #0x003b ;; mode
 854   stosw
 855   mov ax, #0x0007 ;; attr
 856   stosw
 857   mov ax, #0x0010 ;; granularity =16K
 858   stosw
 859   mov ax, #0x0040 ;; size =64K
 860   stosw
 861   mov ax, #0xA000 ;; segment A
 862   stosw
 863   xor ax, ax ;; no segment B
 864   stosw
 865   mov ax, #cirrus_vesa_05h_farentry
 866   stosw
 867   mov ax, cs
 868   stosw
 869   call cirrus_get_line_offset_entry
 870   stosw ;; bytes per scan line
 871   mov ax, [si+2] ;; width
 872   stosw
 873   mov ax, [si+4] ;; height
 874   stosw
 875   mov ax, #0x08
 876   stosb
 877   mov ax, #0x10
 878   stosb
 879   mov al, #1 ;; count of planes
 880   stosb
 881   mov al, [si+6] ;; bpp
 882   stosb
 883   mov al, #0x1 ;; XXX number of banks
 884   stosb
 885   mov al, [si+17]
 886   stosb ;; memory model
 887   mov al, #0x0   ;; XXX size of bank in K
 888   stosb
 889   call cirrus_get_line_offset_entry
 890   mov bx, [si+4]
 891   mul bx ;; dx:ax=vramdisp
 892   or ax, ax
 893   jz cirrus_vesa_01h_3
 894   inc dx
 895 cirrus_vesa_01h_3:
 896   call cirrus_extbios_85h ;; al=vram in 64k
 897   mov ah, #0x00
 898   mov cx, dx
 899   xor dx, dx
 900   div cx
 901   dec ax
 902   stosb  ;; number of image pages = vramtotal/vramdisp-1
 903   mov al, #0x00
 904   stosb
 905
 906   ;; v1.2+ stuffs
 907   push si
 908   add si, #18
 909   movsw
 910   movsw
 911   movsw
 912   movsw
 913   pop si
 914
 915   mov ah, [si+16]
 916   mov al, #0x0
 917   sub ah, #9
 918   rcl al, #1 ; bit 0=palette flag
 919   stosb ;; direct screen mode info
 920
 921   ;; v2.0+ stuffs
 922   ;; 32-bit LFB address
 923   xor ax, ax
 924   stosw
 925   call cirrus_get_lfb_addr
 926   stosw
 927   or ax, ax
 928   jz cirrus_vesa_01h_4
 929   push di
 930   mov di, bp
 931  db 0x26 ;; es:
 932   mov ax, [di]
 933   or ax, #0x0080 ;; mode bit 7:LFB
 934   stosw
 935   pop di
 936 cirrus_vesa_01h_4:
 937
 938   xor ax, ax
 939   stosw ; reserved
 940   stosw ; reserved
 941   stosw ; reserved
 942
 943   mov ax, #0x004F
 944   mov di, bp
 945   pop bx
 946   pop dx
 947   pop cx
 948   pop si
 949   pop ds
 950
 951   test cx, #0x4000 ;; LFB flag
 952   jz cirrus_vesa_01h_5
 953   push cx
 954  db 0x26 ;; es:
 955   mov cx, [di]
 956   cmp cx, #0x0080 ;; is LFB supported?
 957   jnz cirrus_vesa_01h_6
 958   mov ax, #0x014F ;; error - no LFB
 959 cirrus_vesa_01h_6:
 960   pop cx
 961 cirrus_vesa_01h_5:
 962   ret
 963
 964 cirrus_vesa_02h:
 965   ;; XXX support CRTC registers
 966   test bx, #0x3e00
 967   jnz cirrus_vesa_02h_2 ;; unknown flags
 968   mov ax, bx
 969   and ax, #0x1ff ;; bit 8-0 mode
 970   cmp ax, #0x100 ;; legacy VGA mode
 971   jb cirrus_vesa_02h_legacy
 972   call cirrus_vesamode_to_mode
 973   cmp ax, #0xffff
 974   jnz cirrus_vesa_02h_1
 975 cirrus_vesa_02h_2:
 976   jmp cirrus_vesa_unimplemented
 977 cirrus_vesa_02h_legacy:
 978 #ifdef CIRRUS_VESA3_PMINFO
 979  db 0x2e ;; cs:
 980   cmp byte ptr [cirrus_vesa_is_protected_mode], #0
 981   jnz cirrus_vesa_02h_2
 982 #endif // CIRRUS_VESA3_PMINFO
 983   int #0x10
 984   mov ax, #0x004F
 985   ret
 986 cirrus_vesa_02h_1:
 987   push si
 988   push ax
 989   call cirrus_get_modeentry_nomask
 990   call cirrus_switch_mode
 991   test bx, #0x4000 ;; LFB
 992   jnz cirrus_vesa_02h_3
 993   call cirrus_enable_16k_granularity
 994 cirrus_vesa_02h_3:
 995   pop ax
 996   push ds
 997 #ifdef CIRRUS_VESA3_PMINFO
 998  db 0x2e ;; cs:
 999   mov si, [cirrus_vesa_sel0000_data]
1000 #else
1001   xor si, si
1002 #endif
1003   mov ds, si
1004   mov [PM_BIOSMEM_CURRENT_MODE], al
1005   mov [PM_BIOSMEM_VBE_MODE], bx
1006   pop ds
1007   pop si
1008   mov ax, #0x004F
1009   ret
1010
1011 cirrus_vesa_03h:
1012   push ds
1013 #ifdef CIRRUS_VESA3_PMINFO
1014  db 0x2e ;; cs:
1015   mov ax, [cirrus_vesa_sel0000_data]
1016 #else
1017   xor ax, ax
1018 #endif
1019   mov  ds, ax
1020   mov  bx, # PM_BIOSMEM_VBE_MODE
1021   mov  ax, [bx]
1022   mov  bx, ax
1023   test bx, bx
1024   jnz   cirrus_vesa_03h_1
1025   mov  bx, # PM_BIOSMEM_CURRENT_MODE
1026   mov  al, [bx]
1027   mov  bl, al
1028   xor  bh, bh
1029 cirrus_vesa_03h_1:
1030   mov  ax, #0x004f
1031   pop  ds
1032   ret
1033
1034 cirrus_vesa_05h_farentry:
1035   call cirrus_vesa_05h
1036   retf
1037
1038 cirrus_vesa_05h:
1039   cmp bl, #0x01
1040   ja cirrus_vesa_05h_1
1041   cmp bh, #0x00
1042   jz cirrus_vesa_05h_setmempage
1043   cmp bh, #0x01
1044   jz cirrus_vesa_05h_getmempage
1045 cirrus_vesa_05h_1:
1046   jmp cirrus_vesa_unimplemented
1047 cirrus_vesa_05h_setmempage:
1048   or dh, dh ; address must be < 0x100
1049   jnz cirrus_vesa_05h_1
1050   push dx
1051   mov al, bl ;; bl=bank number
1052   add al, #0x09
1053   mov ah, dl ;; dx=window address in granularity
1054   mov dx, #0x3ce
1055   out dx, ax
1056   pop dx
1057   mov ax, #0x004F
1058   ret
1059 cirrus_vesa_05h_getmempage:
1060   mov al, bl ;; bl=bank number
1061   add al, #0x09
1062   mov dx, #0x3ce
1063   out dx, al
1064   inc dx
1065   in al, dx
1066   xor dx, dx
1067   mov dl, al ;; dx=window address in granularity
1068   mov ax, #0x004F
1069   ret
1070
1071 cirrus_vesa_06h:
1072   mov  ax, cx
1073   cmp  bl, #0x01
1074   je   cirrus_vesa_06h_3
1075   cmp  bl, #0x02
1076   je   cirrus_vesa_06h_2
1077   jb   cirrus_vesa_06h_1
1078   mov  ax, #0x0100
1079   ret
1080 cirrus_vesa_06h_1:
1081   call cirrus_get_bpp_bytes
1082   mov  bl, al
1083   xor  bh, bh
1084   mov  ax, cx
1085   mul  bx
1086 cirrus_vesa_06h_2:
1087   call cirrus_set_line_offset
1088 cirrus_vesa_06h_3:
1089   call cirrus_get_bpp_bytes
1090   mov  bl, al
1091   xor  bh, bh
1092   xor  dx, dx
1093   call cirrus_get_line_offset
1094   push ax
1095   div  bx
1096   mov  cx, ax
1097   pop  bx
1098   call cirrus_extbios_85h ;; al=vram in 64k
1099   xor  dx, dx
1100   mov  dl, al
1101   xor  ax, ax
1102   div  bx
1103   mov  dx, ax
1104   mov  ax, #0x004f
1105   ret
1106
1107 cirrus_vesa_07h:
1108   cmp  bl, #0x80
1109   je   cirrus_vesa_07h_1
1110   cmp  bl, #0x01
1111   je   cirrus_vesa_07h_2
1112   jb   cirrus_vesa_07h_1
1113   mov  ax, #0x0100
1114   ret
1115 cirrus_vesa_07h_1:
1116   push dx
1117   call cirrus_get_bpp_bytes
1118   mov  bl, al
1119   xor  bh, bh
1120   mov  ax, cx
1121   mul  bx
1122   pop  bx
1123   push ax
1124   call cirrus_get_line_offset
1125   mul  bx
1126   pop  bx
1127   add  ax, bx
1128   jnc  cirrus_vesa_07h_3
1129   inc  dx
1130 cirrus_vesa_07h_3:
1131   push dx
1132   and  dx, #0x0003
1133   mov  bx, #0x04
1134   div  bx
1135   pop  dx
1136   shr  dx, #2
1137   call cirrus_set_start_addr
1138   mov  ax, #0x004f
1139   ret
1140 cirrus_vesa_07h_2:
1141   call cirrus_get_start_addr
1142   shl  dx, #2
1143   push dx
1144   mov  bx, #0x04
1145   mul  bx
1146   pop  bx
1147   or   dx, bx
1148   push ax
1149   call cirrus_get_line_offset
1150   mov  bx, ax
1151   pop  ax
1152   div  bx
1153   push ax
1154   push dx
1155   call cirrus_get_bpp_bytes
1156   mov  bl, al
1157   xor  bh, bh
1158   pop  ax
1159   xor  dx, dx
1160   div  bx
1161   mov  cx, ax
1162   pop  dx
1163   mov  ax, #0x004f
1164   ret
1165
1166 cirrus_vesa_unimplemented:
1167   mov ax, #0x014F ;; not implemented
1168   ret
1169
1170
1171 ;; in ax:vesamode, out ax:cirrusmode
1172 cirrus_vesamode_to_mode:
1173   push ds
1174   push cx
1175   push si
1176   push cs
1177   pop ds
1178   mov cx, #0xffff
1179   mov si, #_cirrus_vesa_modelist
1180 cvtm_1:
1181   cmp [si],ax
1182   jz cvtm_2
1183   cmp [si],cx
1184   jz cvtm_2
1185   add si, #4
1186   jmp cvtm_1
1187 cvtm_2:
1188   mov ax,[si+2]
1189   pop si
1190   pop cx
1191   pop ds
1192   ret
1193
1194   ; cirrus_get_crtc
1195   ;; NOTE - may be called in protected mode
1196 cirrus_get_crtc:
1197   push ds
1198   push ax
1199   mov  dx, #0x3cc
1200   in   al, dx
1201   and  al, #0x01
1202   shl  al, #5
1203   mov  dx, #0x3b4
1204   add  dl, al
1205   pop  ax
1206   pop  ds
1207   ret
1208
1209 ;; in - al:mode, out - cflag:result, si:table, ax:destroyed
1210 cirrus_get_modeentry:
1211   and al, #0x7f
1212 cirrus_get_modeentry_nomask:
1213   mov si, #_cirrus_modes
1214 cgm_1:
1215  db 0x2e ;; cs:
1216   mov ah, [si]
1217   cmp al, ah
1218   jz cgm_2
1219   cmp ah, #0xff
1220   jz cgm_4
1221   add si, # CIRRUS_MODE_SIZE
1222   jmp cgm_1
1223 cgm_4:
1224   xor si, si
1225   stc ;; video mode is not supported
1226   jmp cgm_3
1227 cgm_2:
1228   clc ;; video mode is supported
1229 cgm_3:
1230   ret
1231
1232   ; get LFB address
1233   ; out - ax:LFB address (high 16 bit)
1234   ;; NOTE - may be called in protected mode
1235 cirrus_get_lfb_addr:
1236   push cx
1237   push dx
1238   push eax
1239     xor cx, cx
1240     mov dl, #0x00
1241     call cirrus_pci_read
1242     cmp ax, #0xffff
1243     jz cirrus_get_lfb_addr_5
1244  cirrus_get_lfb_addr_3:
1245     mov dl, #0x00
1246     call cirrus_pci_read
1247     cmp ax, #0x1013 ;; cirrus
1248     jz cirrus_get_lfb_addr_4
1249     add cx, #0x8
1250     cmp cx, #0x200 ;; search bus #0 and #1
1251     jb cirrus_get_lfb_addr_3
1252  cirrus_get_lfb_addr_5:
1253     xor dx, dx ;; no LFB
1254     jmp cirrus_get_lfb_addr_6
1255  cirrus_get_lfb_addr_4:
1256     mov dl, #0x10 ;; I/O space #0
1257     call cirrus_pci_read
1258     test ax, #0xfff1
1259     jnz cirrus_get_lfb_addr_5
1260     shr eax, #16
1261     mov dx, ax ;; LFB address
1262  cirrus_get_lfb_addr_6:
1263   pop eax
1264   mov ax, dx
1265   pop dx
1266   pop cx
1267   ret
1268
1269 cirrus_pci_read:
1270   mov eax, #0x00800000
1271   mov ax, cx
1272   shl eax, #8
1273   mov al, dl
1274   mov dx, #0xcf8
1275   out dx, eax
1276   add dl, #4
1277   in  eax, dx
1278   ret
1279
1280 ;; out - al:bytes per pixel
1281 cirrus_get_bpp_bytes:
1282   push dx
1283   mov  dx, #0x03c4
1284   mov  al, #0x07
1285   out  dx, al
1286   inc  dx
1287   in   al, dx
1288   and  al, #0x0e
1289   cmp  al, #0x06
1290   jne  cirrus_get_bpp_bytes_1
1291   and  al, #0x02
1292 cirrus_get_bpp_bytes_1:
1293   shr  al, #1
1294   cmp  al, #0x04
1295   je  cirrus_get_bpp_bytes_2
1296   inc  al
1297 cirrus_get_bpp_bytes_2:
1298   pop  dx
1299   ret
1300
1301 ;; in - ax: new line offset
1302 cirrus_set_line_offset:
1303   shr  ax, #3
1304   push ax
1305   call cirrus_get_crtc
1306   mov  al, #0x13
1307   out  dx, al
1308   inc  dx
1309   pop  ax
1310   out  dx, al
1311   dec  dx
1312   mov  al, #0x1b
1313   out  dx, al
1314   inc  dx
1315   shl  ah, #4
1316   in   al, dx
1317   and  al, #ef
1318   or   al, ah
1319   out  dx, al
1320   ret
1321
1322 ;; out - ax: active line offset
1323 cirrus_get_line_offset:
1324   push dx
1325   push bx
1326   call cirrus_get_crtc
1327   mov  al, #0x13
1328   out  dx, al
1329   inc  dx
1330   in   al, dx
1331   mov  bl, al
1332   dec  dx
1333   mov  al, #0x1b
1334   out  dx, al
1335   inc  dx
1336   in   al, dx
1337   mov  ah, al
1338   shr  ah, #4
1339   and  ah, #0x01
1340   mov  al, bl
1341   shl  ax, #3
1342   pop  bx
1343   pop  dx
1344   ret
1345
1346 ;; in - si: table
1347 ;; out - ax: line offset for mode
1348 cirrus_get_line_offset_entry:
1349   push bx
1350   mov  bx, [si+14] ;; crtc table
1351   push bx
1352 offset_loop1:
1353   mov  ax, [bx]
1354   cmp  al, #0x13
1355   je   offset_found1
1356   inc  bx
1357   inc  bx
1358   jnz  offset_loop1
1359 offset_found1:
1360   xor  al, al
1361   shr  ax, #5
1362   pop  bx
1363   push ax
1364 offset_loop2:
1365   mov  ax, [bx]
1366   cmp  al, #0x1b
1367   je offset_found2
1368   inc  bx
1369   inc  bx
1370   jnz offset_loop2
1371 offset_found2:
1372   pop  bx
1373   and  ax, #0x1000
1374   shr  ax, #1
1375   or   ax, bx
1376   pop  bx
1377   ret
1378
1379 ;; in - new address in DX:AX
1380 cirrus_set_start_addr:
1381   push bx
1382   push dx
1383   push ax
1384   call cirrus_get_crtc
1385   mov  al, #0x0d
1386   out  dx, al
1387   inc  dx
1388   pop  ax
1389   out  dx, al
1390   dec  dx
1391   mov  al, #0x0c
1392   out  dx, al
1393   inc  dx
1394   mov  al, ah
1395   out  dx, al
1396   dec  dx
1397   mov  al, #0x1d
1398   out  dx, al
1399   inc  dx
1400   in   al, dx
1401   and  al, #0x7f
1402   pop  bx
1403   mov  ah, bl
1404   shl  bl, #4
1405   and  bl, #0x80
1406   or   al, bl
1407   out  dx, al
1408   dec  dx
1409   mov  bl, ah
1410   and  ah, #0x01
1411   shl  bl, #1
1412   and  bl, #0x0c
1413   or   ah, bl
1414   mov  al, #0x1b
1415   out  dx, al
1416   inc  dx
1417   in   al, dx
1418   and  al, #0xf2
1419   or   al, ah
1420   out  dx, al
1421   pop  bx
1422   ret
1423
1424 ;; out - current address in DX:AX
1425 cirrus_get_start_addr:
1426   push bx
1427   call cirrus_get_crtc
1428   mov  al, #0x0c
1429   out  dx, al
1430   inc  dx
1431   in   al, dx
1432   mov  ah, al
1433   dec  dx
1434   mov  al, #0x0d
1435   out  dx, al
1436   inc  dx
1437   in   al, dx
1438   push ax
1439   dec  dx
1440   mov  al, #0x1b
1441   out  dx, al
1442   inc  dx
1443   in   al, dx
1444   dec  dx
1445   mov  bl, al
1446   and  al, #0x01
1447   and  bl, #0x0c
1448   shr  bl, #1
1449   or   bl, al
1450   mov  al, #0x1d
1451   out  dx, al
1452   inc  dx
1453   in   al, dx
1454   and  al, #0x80
1455   shr  al, #4
1456   or   bl, al
1457   mov  dl, bl
1458   xor  dh, dh
1459   pop  ax
1460   pop  bx
1461   ret
1462
1463 cirrus_extbios_handlers:
1464   ;; 80h
1465   dw cirrus_extbios_80h
1466   dw cirrus_extbios_81h
1467   dw cirrus_extbios_82h
1468   dw cirrus_extbios_unimplemented
1469   ;; 84h
1470   dw cirrus_extbios_unimplemented
1471   dw cirrus_extbios_85h
1472   dw cirrus_extbios_unimplemented
1473   dw cirrus_extbios_unimplemented
1474   ;; 88h
1475   dw cirrus_extbios_unimplemented
1476   dw cirrus_extbios_unimplemented
1477   dw cirrus_extbios_unimplemented
1478   dw cirrus_extbios_unimplemented
1479   ;; 8Ch
1480   dw cirrus_extbios_unimplemented
1481   dw cirrus_extbios_unimplemented
1482   dw cirrus_extbios_unimplemented
1483   dw cirrus_extbios_unimplemented
1484   ;; 90h
1485   dw cirrus_extbios_unimplemented
1486   dw cirrus_extbios_unimplemented
1487   dw cirrus_extbios_unimplemented
1488   dw cirrus_extbios_unimplemented
1489   ;; 94h
1490   dw cirrus_extbios_unimplemented
1491   dw cirrus_extbios_unimplemented
1492   dw cirrus_extbios_unimplemented
1493   dw cirrus_extbios_unimplemented
1494   ;; 98h
1495   dw cirrus_extbios_unimplemented
1496   dw cirrus_extbios_unimplemented
1497   dw cirrus_extbios_9Ah
1498   dw cirrus_extbios_unimplemented
1499   ;; 9Ch
1500   dw cirrus_extbios_unimplemented
1501   dw cirrus_extbios_unimplemented
1502   dw cirrus_extbios_unimplemented
1503   dw cirrus_extbios_unimplemented
1504   ;; A0h
1505   dw cirrus_extbios_A0h
1506   dw cirrus_extbios_A1h
1507   dw cirrus_extbios_A2h
1508   dw cirrus_extbios_unimplemented
1509   ;; A4h
1510   dw cirrus_extbios_unimplemented
1511   dw cirrus_extbios_unimplemented
1512   dw cirrus_extbios_unimplemented
1513   dw cirrus_extbios_unimplemented
1514   ;; A8h
1515   dw cirrus_extbios_unimplemented
1516   dw cirrus_extbios_unimplemented
1517   dw cirrus_extbios_unimplemented
1518   dw cirrus_extbios_unimplemented
1519   ;; ACh
1520   dw cirrus_extbios_unimplemented
1521   dw cirrus_extbios_unimplemented
1522   dw cirrus_extbios_AEh
1523   dw cirrus_extbios_unimplemented
1524
1525 cirrus_vesa_handlers:
1526   ;; 00h
1527   dw cirrus_vesa_00h
1528   dw cirrus_vesa_01h
1529   dw cirrus_vesa_02h
1530   dw cirrus_vesa_03h
1531   ;; 04h
1532   dw cirrus_vesa_unimplemented
1533   dw cirrus_vesa_05h
1534   dw cirrus_vesa_06h
1535   dw cirrus_vesa_07h
1536   ;; 08h
1537   dw cirrus_vesa_unimplemented
1538   dw cirrus_vesa_unimplemented
1539   dw cirrus_vesa_unimplemented
1540   dw cirrus_vesa_unimplemented
1541   ;; 0Ch
1542   dw cirrus_vesa_unimplemented
1543   dw cirrus_vesa_unimplemented
1544   dw cirrus_vesa_unimplemented
1545   dw cirrus_vesa_unimplemented
1546
1547
1548
1549 ASM_END
1550
1551 #ifdef CIRRUS_VESA3_PMINFO
1552 ASM_START
1553 cirrus_vesa_pminfo:
1554   /* + 0 */
1555   .byte 0x50,0x4d,0x49,0x44 ;; signature[4]
1556   /* + 4 */
1557   dw cirrus_vesa_pmbios_entry ;; entry_bios
1558   dw cirrus_vesa_pmbios_init  ;; entry_init
1559   /* + 8 */
1560 cirrus_vesa_sel0000_data:
1561   dw 0x0000 ;; sel_00000
1562 cirrus_vesa_selA000_data:
1563   dw 0xA000 ;; sel_A0000
1564   /* +12 */
1565 cirrus_vesa_selB000_data:
1566   dw 0xB000 ;; sel_B0000
1567 cirrus_vesa_selB800_data:
1568   dw 0xB800 ;; sel_B8000
1569   /* +16 */
1570 cirrus_vesa_selC000_data:
1571   dw 0xC000 ;; sel_C0000
1572 cirrus_vesa_is_protected_mode:
1573   ;; protected mode flag and checksum
1574   dw (~((0xf2 + (cirrus_vesa_pmbios_entry >> 8) + (cirrus_vesa_pmbios_entry) \
1575      + (cirrus_vesa_pmbios_init >> 8) + (cirrus_vesa_pmbios_init)) & 0xff) << 8) + 0x01
1576 ASM_END
1577 #endif // CIRRUS_VESA3_PMINFO
1578
1579
1580 #ifdef CIRRUS_DEBUG
1581 static void cirrus_debugmsg(DI, SI, BP, SP, BX, DX, CX, AX, DS, ES, FLAGS)
1582   Bit16u DI, SI, BP, SP, BX, DX, CX, AX, ES, DS, FLAGS;
1583 {
1584  if((GET_AH()!=0x0E)&&(GET_AH()!=0x02)&&(GET_AH()!=0x09)&&(AX!=0x4F05))
1585   printf("vgabios call ah%02x al%02x bx%04x cx%04x dx%04x\n",GET_AH(),GET_AL(),BX,CX,DX);
1586 }
1587 #endif