VEX/priv/host_arm64_defs.h

   1
   2 /*---------------------------------------------------------------*/
   3 /*--- begin                                 host_arm64_defs.h ---*/
   4 /*---------------------------------------------------------------*/
   5
   6 /*
   7    This file is part of Valgrind, a dynamic binary instrumentation
   8    framework.
   9
  10    Copyright (C) 2013-2017 OpenWorks
  11       info@open-works.net
  12
  13    This program is free software; you can redistribute it and/or
  14    modify it under the terms of the GNU General Public License as
  15    published by the Free Software Foundation; either version 2 of the
  16    License, or (at your option) any later version.
  17
  18    This program is distributed in the hope that it will be useful, but
  19    WITHOUT ANY WARRANTY; without even the implied warranty of
  20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21    General Public License for more details.
  22
  23    You should have received a copy of the GNU General Public License
  24    along with this program; if not, see <http://www.gnu.org/licenses/>.
  25
  26    The GNU General Public License is contained in the file COPYING.
  27 */
  28
  29 #ifndef __VEX_HOST_ARM64_DEFS_H
  30 #define __VEX_HOST_ARM64_DEFS_H
  31
  32 #include "libvex_basictypes.h"
  33 #include "libvex.h"                      // VexArch
  34 #include "host_generic_regs.h"           // HReg
  35
  36
  37 /* --------- Registers. --------- */
  38
  39 #define ST_IN static inline
  40 ST_IN HReg hregARM64_X22 ( void ) { return mkHReg(False, HRcInt64,  22,  0); }
  41 ST_IN HReg hregARM64_X23 ( void ) { return mkHReg(False, HRcInt64,  23,  1); }
  42 ST_IN HReg hregARM64_X24 ( void ) { return mkHReg(False, HRcInt64,  24,  2); }
  43 ST_IN HReg hregARM64_X25 ( void ) { return mkHReg(False, HRcInt64,  25,  3); }
  44 ST_IN HReg hregARM64_X26 ( void ) { return mkHReg(False, HRcInt64,  26,  4); }
  45 ST_IN HReg hregARM64_X27 ( void ) { return mkHReg(False, HRcInt64,  27,  5); }
  46 ST_IN HReg hregARM64_X28 ( void ) { return mkHReg(False, HRcInt64,  28,  6); }
  47
  48 ST_IN HReg hregARM64_X0  ( void ) { return mkHReg(False, HRcInt64,  0,   7); }
  49 ST_IN HReg hregARM64_X1  ( void ) { return mkHReg(False, HRcInt64,  1,   8); }
  50 ST_IN HReg hregARM64_X2  ( void ) { return mkHReg(False, HRcInt64,  2,   9); }
  51 ST_IN HReg hregARM64_X3  ( void ) { return mkHReg(False, HRcInt64,  3,  10); }
  52 ST_IN HReg hregARM64_X4  ( void ) { return mkHReg(False, HRcInt64,  4,  11); }
  53 ST_IN HReg hregARM64_X5  ( void ) { return mkHReg(False, HRcInt64,  5,  12); }
  54 ST_IN HReg hregARM64_X6  ( void ) { return mkHReg(False, HRcInt64,  6,  13); }
  55 ST_IN HReg hregARM64_X7  ( void ) { return mkHReg(False, HRcInt64,  7,  14); }
  56
  57 ST_IN HReg hregARM64_Q16 ( void ) { return mkHReg(False, HRcVec128, 16, 15); }
  58 ST_IN HReg hregARM64_Q17 ( void ) { return mkHReg(False, HRcVec128, 17, 16); }
  59 ST_IN HReg hregARM64_Q18 ( void ) { return mkHReg(False, HRcVec128, 18, 17); }
  60 ST_IN HReg hregARM64_Q19 ( void ) { return mkHReg(False, HRcVec128, 19, 18); }
  61 ST_IN HReg hregARM64_Q20 ( void ) { return mkHReg(False, HRcVec128, 20, 19); }
  62
  63 ST_IN HReg hregARM64_D8  ( void ) { return mkHReg(False, HRcFlt64,  8,  20); }
  64 ST_IN HReg hregARM64_D9  ( void ) { return mkHReg(False, HRcFlt64,  9,  21); }
  65 ST_IN HReg hregARM64_D10 ( void ) { return mkHReg(False, HRcFlt64,  10, 22); }
  66 ST_IN HReg hregARM64_D11 ( void ) { return mkHReg(False, HRcFlt64,  11, 23); }
  67 ST_IN HReg hregARM64_D12 ( void ) { return mkHReg(False, HRcFlt64,  12, 24); }
  68 ST_IN HReg hregARM64_D13 ( void ) { return mkHReg(False, HRcFlt64,  13, 25); }
  69
  70 ST_IN HReg hregARM64_X8  ( void ) { return mkHReg(False, HRcInt64,  8,  26); }
  71 ST_IN HReg hregARM64_X9  ( void ) { return mkHReg(False, HRcInt64,  9,  27); }
  72 ST_IN HReg hregARM64_X21 ( void ) { return mkHReg(False, HRcInt64, 21,  28); }
  73
  74 // This is the integer register with encoding 31.  Be *very* careful how you
  75 // use it, since its meaning is dependent on the instruction and indeed even
  76 // the position within an instruction, that it appears.  It denotes either the
  77 // zero register or the stack pointer.
  78 ST_IN HReg hregARM64_XZR_XSP ( void ) { return mkHReg(False,
  79                                                       HRcInt64, 31, 29); }
  80 #undef ST_IN
  81
  82 extern UInt ppHRegARM64 ( HReg );
  83
  84 /* Number of registers used arg passing in function calls */
  85 #define ARM64_N_ARGREGS 8   /* x0 .. x7 */
  86
  87
  88 /* --------- Condition codes. --------- */
  89
  90 typedef
  91    enum {
  92       ARM64cc_EQ  = 0,  /* equal                         : Z=1 */
  93       ARM64cc_NE  = 1,  /* not equal                     : Z=0 */
  94
  95       ARM64cc_CS  = 2,  /* >=u (higher or same)          : C=1 */
  96       ARM64cc_CC  = 3,  /* <u  (lower)                   : C=0 */
  97
  98       ARM64cc_MI  = 4,  /* minus (negative)              : N=1 */
  99       ARM64cc_PL  = 5,  /* plus (zero or +ve)            : N=0 */
 100
 101       ARM64cc_VS  = 6,  /* overflow                      : V=1 */
 102       ARM64cc_VC  = 7,  /* no overflow                   : V=0 */
 103
 104       ARM64cc_HI  = 8,  /* >u   (higher)                 :   C=1 && Z=0 */
 105       ARM64cc_LS  = 9,  /* <=u  (lower or same)          : !(C=1 && Z=0) */
 106
 107       ARM64cc_GE  = 10, /* >=s (signed greater or equal) :   N=V */
 108       ARM64cc_LT  = 11, /* <s  (signed less than)        : !(N=V) */
 109
 110       ARM64cc_GT  = 12, /* >s  (signed greater)          :   Z=0 && N=V */
 111       ARM64cc_LE  = 13, /* <=s (signed less or equal)    : !(Z=0 && N=V) */
 112
 113       ARM64cc_AL  = 14, /* always (unconditional) */
 114       ARM64cc_NV  = 15  /* in 64-bit mode also means "always" */
 115    }
 116    ARM64CondCode;
 117
 118
 119 /* --------- Memory address expressions (amodes). --------- */
 120
 121 typedef
 122    enum {
 123       ARM64am_RI9=10, /* reg + simm9 */
 124       ARM64am_RI12,   /* reg + uimm12 * szB (iow, scaled by access size) */
 125       ARM64am_RR      /* reg1 + reg2 */
 126    }
 127    ARM64AModeTag;
 128
 129 typedef
 130    struct {
 131       ARM64AModeTag tag;
 132       union {
 133          struct {
 134             HReg reg;
 135             Int  simm9; /* -256 .. +255 */
 136          } RI9;
 137          struct {
 138             HReg  reg;
 139             UInt  uimm12; /* 0 .. 4095 */
 140             UChar szB;    /* 1, 2, 4, 8 (16 ?) */
 141          } RI12;
 142          struct {
 143             HReg base;
 144             HReg index;
 145          } RR;
 146       } ARM64am;
 147    }
 148    ARM64AMode;
 149
 150 extern ARM64AMode* ARM64AMode_RI9  ( HReg reg, Int simm9 );
 151 extern ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB );
 152 extern ARM64AMode* ARM64AMode_RR   ( HReg base, HReg index );
 153
 154
 155 /* --------- Reg or uimm12 or (uimm12 << 12) operands --------- */
 156
 157 typedef
 158    enum {
 159       ARM64riA_I12=20, /* uimm12 << 0 or 12 only */
 160       ARM64riA_R       /* reg */
 161    }
 162    ARM64RIATag;
 163
 164 typedef
 165    struct {
 166       ARM64RIATag tag;
 167       union {
 168          struct {
 169             UShort imm12;  /* 0 .. 4095 */
 170             UChar  shift;  /* 0 or 12 only */
 171          } I12;
 172          struct {
 173             HReg reg;
 174          } R;
 175       } ARM64riA;
 176    }
 177    ARM64RIA;
 178
 179 extern ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift );
 180 extern ARM64RIA* ARM64RIA_R   ( HReg );
 181
 182
 183 /* --------- Reg or "bitfield" (logic immediate) operands --------- */
 184
 185 typedef
 186    enum {
 187       ARM64riL_I13=6, /* wierd-o bitfield immediate, 13 bits in total */
 188       ARM64riL_R      /* reg */
 189    }
 190    ARM64RILTag;
 191
 192 typedef
 193    struct {
 194       ARM64RILTag tag;
 195       union {
 196          struct {
 197             UChar bitN; /* 0 .. 1 */
 198             UChar immR; /* 0 .. 63 */
 199             UChar immS; /* 0 .. 63 */
 200          } I13;
 201          struct {
 202             HReg reg;
 203          } R;
 204       } ARM64riL;
 205    }
 206    ARM64RIL;
 207
 208 extern ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS );
 209 extern ARM64RIL* ARM64RIL_R   ( HReg );
 210
 211
 212 /* --------------- Reg or uimm6 operands --------------- */
 213
 214 typedef
 215    enum {
 216       ARM64ri6_I6=30, /* uimm6, 1 .. 63 only */
 217       ARM64ri6_R      /* reg */
 218    }
 219    ARM64RI6Tag;
 220
 221 typedef
 222    struct {
 223       ARM64RI6Tag tag;
 224       union {
 225          struct {
 226             UInt imm6;   /* 1 .. 63 */
 227          } I6;
 228          struct {
 229             HReg reg;
 230          } R;
 231       } ARM64ri6;
 232    }
 233    ARM64RI6;
 234
 235 extern ARM64RI6* ARM64RI6_I6 ( UInt imm6 );
 236 extern ARM64RI6* ARM64RI6_R  ( HReg );
 237
 238
 239 /* --------------------- Instructions --------------------- */
 240
 241 typedef
 242    enum {
 243       ARM64lo_AND=40,
 244       ARM64lo_OR,
 245       ARM64lo_XOR
 246    }
 247    ARM64LogicOp;
 248
 249 typedef
 250    enum {
 251       ARM64sh_SHL=50,
 252       ARM64sh_SHR,
 253       ARM64sh_SAR
 254    }
 255    ARM64ShiftOp;
 256
 257 typedef
 258    enum {
 259       ARM64un_NEG=60,
 260       ARM64un_NOT,
 261       ARM64un_CLZ,
 262    }
 263    ARM64UnaryOp;
 264
 265 typedef
 266    enum {
 267       ARM64mul_PLAIN=70, /* lo64(64 * 64)  */
 268       ARM64mul_ZX,       /* hi64(64 *u 64) */
 269       ARM64mul_SX        /* hi64(64 *s 64) */
 270    }
 271    ARM64MulOp;
 272
 273 typedef
 274    /* These characterise an integer-FP conversion, but don't imply any
 275       particular direction. */
 276    enum {
 277       ARM64cvt_F32_I32S=80,
 278       ARM64cvt_F64_I32S,
 279       ARM64cvt_F32_I64S,
 280       ARM64cvt_F64_I64S,
 281       ARM64cvt_F32_I32U,
 282       ARM64cvt_F64_I32U,
 283       ARM64cvt_F32_I64U,
 284       ARM64cvt_F64_I64U,
 285       ARM64cvt_INVALID
 286    }
 287    ARM64CvtOp;
 288
 289 typedef
 290    enum {
 291       ARM64fpb_ADD=100,
 292       ARM64fpb_SUB,
 293       ARM64fpb_MUL,
 294       ARM64fpb_DIV,
 295       ARM64fpb_INVALID
 296    }
 297    ARM64FpBinOp;
 298
 299 typedef
 300    enum {
 301       ARM64fpt_FMADD=105,
 302       ARM64fpt_FMSUB,
 303       ARM64fpt_INVALID
 304    }
 305    ARM64FpTriOp;
 306
 307 typedef
 308    enum {
 309       ARM64fpu_NEG=110,
 310       ARM64fpu_ABS,
 311       ARM64fpu_SQRT,
 312       ARM64fpu_RINT,
 313       ARM64fpu_RECPX,
 314       ARM64fpu_INVALID
 315    }
 316    ARM64FpUnaryOp;
 317
 318 typedef
 319    enum {
 320       ARM64vecb_ADD64x2=120, ARM64vecb_ADD32x4,
 321       ARM64vecb_ADD16x8,     ARM64vecb_ADD8x16,
 322       ARM64vecb_SUB64x2,     ARM64vecb_SUB32x4,
 323       ARM64vecb_SUB16x8,     ARM64vecb_SUB8x16,
 324                              ARM64vecb_MUL32x4,
 325       ARM64vecb_MUL16x8,     ARM64vecb_MUL8x16,
 326       ARM64vecb_FADD64x2,    ARM64vecb_FADD32x4,
 327       ARM64vecb_FSUB64x2,    ARM64vecb_FSUB32x4,
 328       ARM64vecb_FMUL64x2,    ARM64vecb_FMUL32x4,
 329       ARM64vecb_FDIV64x2,    ARM64vecb_FDIV32x4,
 330       ARM64vecb_FMAX64x2,    ARM64vecb_FMAX32x4,
 331       ARM64vecb_FMIN64x2,    ARM64vecb_FMIN32x4,
 332                              ARM64vecb_UMAX32x4,
 333       ARM64vecb_UMAX16x8,    ARM64vecb_UMAX8x16,
 334                              ARM64vecb_UMIN32x4,
 335       ARM64vecb_UMIN16x8,    ARM64vecb_UMIN8x16,
 336                              ARM64vecb_SMAX32x4,
 337       ARM64vecb_SMAX16x8,    ARM64vecb_SMAX8x16,
 338                              ARM64vecb_SMIN32x4,
 339       ARM64vecb_SMIN16x8,    ARM64vecb_SMIN8x16,
 340       ARM64vecb_AND,
 341       ARM64vecb_ORR,
 342       ARM64vecb_XOR,
 343       ARM64vecb_CMEQ64x2,    ARM64vecb_CMEQ32x4,
 344       ARM64vecb_CMEQ16x8,    ARM64vecb_CMEQ8x16,
 345       ARM64vecb_CMHI64x2,    ARM64vecb_CMHI32x4, /* >u */
 346       ARM64vecb_CMHI16x8,    ARM64vecb_CMHI8x16,
 347       ARM64vecb_CMGT64x2,    ARM64vecb_CMGT32x4, /* >s */
 348       ARM64vecb_CMGT16x8,    ARM64vecb_CMGT8x16,
 349       ARM64vecb_FCMEQ64x2,   ARM64vecb_FCMEQ32x4,
 350       ARM64vecb_FCMGE64x2,   ARM64vecb_FCMGE32x4,
 351       ARM64vecb_FCMGT64x2,   ARM64vecb_FCMGT32x4,
 352       ARM64vecb_TBL1,
 353       ARM64vecb_UZP164x2,    ARM64vecb_UZP132x4,
 354       ARM64vecb_UZP116x8,    ARM64vecb_UZP18x16,
 355       ARM64vecb_UZP264x2,    ARM64vecb_UZP232x4,
 356       ARM64vecb_UZP216x8,    ARM64vecb_UZP28x16,
 357       ARM64vecb_ZIP132x4,    ARM64vecb_ZIP116x8,
 358       ARM64vecb_ZIP18x16,    ARM64vecb_ZIP232x4,
 359       ARM64vecb_ZIP216x8,    ARM64vecb_ZIP28x16,
 360                              ARM64vecb_PMUL8x16,
 361                              ARM64vecb_PMULL8x8,
 362                              ARM64vecb_UMULL2DSS,
 363       ARM64vecb_UMULL4SHH,   ARM64vecb_UMULL8HBB,
 364                              ARM64vecb_SMULL2DSS,
 365       ARM64vecb_SMULL4SHH,   ARM64vecb_SMULL8HBB,
 366       ARM64vecb_SQADD64x2,   ARM64vecb_SQADD32x4,
 367       ARM64vecb_SQADD16x8,   ARM64vecb_SQADD8x16,
 368       ARM64vecb_UQADD64x2,   ARM64vecb_UQADD32x4,
 369       ARM64vecb_UQADD16x8,   ARM64vecb_UQADD8x16,
 370       ARM64vecb_SQSUB64x2,   ARM64vecb_SQSUB32x4,
 371       ARM64vecb_SQSUB16x8,   ARM64vecb_SQSUB8x16,
 372       ARM64vecb_UQSUB64x2,   ARM64vecb_UQSUB32x4,
 373       ARM64vecb_UQSUB16x8,   ARM64vecb_UQSUB8x16,
 374                              ARM64vecb_SQDMULL2DSS,
 375       ARM64vecb_SQDMULL4SHH,
 376                              ARM64vecb_SQDMULH32x4,
 377       ARM64vecb_SQDMULH16x8,
 378                              ARM64vecb_SQRDMULH32x4,
 379       ARM64vecb_SQRDMULH16x8,
 380       ARM64vecb_SQSHL64x2,   ARM64vecb_SQSHL32x4,
 381       ARM64vecb_SQSHL16x8,   ARM64vecb_SQSHL8x16,
 382       ARM64vecb_UQSHL64x2,   ARM64vecb_UQSHL32x4,
 383       ARM64vecb_UQSHL16x8,   ARM64vecb_UQSHL8x16,
 384       ARM64vecb_SQRSHL64x2,  ARM64vecb_SQRSHL32x4,
 385       ARM64vecb_SQRSHL16x8,  ARM64vecb_SQRSHL8x16,
 386       ARM64vecb_UQRSHL64x2,  ARM64vecb_UQRSHL32x4,
 387       ARM64vecb_UQRSHL16x8,  ARM64vecb_UQRSHL8x16,
 388       ARM64vecb_SSHL64x2,    ARM64vecb_SSHL32x4,
 389       ARM64vecb_SSHL16x8,    ARM64vecb_SSHL8x16,
 390       ARM64vecb_USHL64x2,    ARM64vecb_USHL32x4,
 391       ARM64vecb_USHL16x8,    ARM64vecb_USHL8x16,
 392       ARM64vecb_SRSHL64x2,   ARM64vecb_SRSHL32x4,
 393       ARM64vecb_SRSHL16x8,   ARM64vecb_SRSHL8x16,
 394       ARM64vecb_URSHL64x2,   ARM64vecb_URSHL32x4,
 395       ARM64vecb_URSHL16x8,   ARM64vecb_URSHL8x16,
 396       ARM64vecb_FRECPS64x2,  ARM64vecb_FRECPS32x4,
 397       ARM64vecb_FRSQRTS64x2, ARM64vecb_FRSQRTS32x4,
 398       ARM64vecb_INVALID
 399    }
 400    ARM64VecBinOp;
 401
 402 typedef
 403    enum {
 404       ARM64vecmo_SUQADD64x2=300, ARM64vecmo_SUQADD32x4,
 405       ARM64vecmo_SUQADD16x8,     ARM64vecmo_SUQADD8x16,
 406       ARM64vecmo_USQADD64x2,     ARM64vecmo_USQADD32x4,
 407       ARM64vecmo_USQADD16x8,     ARM64vecmo_USQADD8x16,
 408       ARM64vecmo_INVALID
 409    }
 410    ARM64VecModifyOp;
 411
 412 typedef
 413    enum {
 414       ARM64vecu_FNEG64x2=350, ARM64vecu_FNEG32x4,
 415       ARM64vecu_FABS64x2,     ARM64vecu_FABS32x4,
 416       ARM64vecu_NOT,
 417       ARM64vecu_ABS64x2,      ARM64vecu_ABS32x4,
 418       ARM64vecu_ABS16x8,      ARM64vecu_ABS8x16,
 419       ARM64vecu_CLS32x4,      ARM64vecu_CLS16x8,      ARM64vecu_CLS8x16,
 420       ARM64vecu_CLZ32x4,      ARM64vecu_CLZ16x8,      ARM64vecu_CLZ8x16,
 421       ARM64vecu_CNT8x16,
 422       ARM64vecu_RBIT,
 423       ARM64vecu_REV1616B,
 424       ARM64vecu_REV3216B,     ARM64vecu_REV328H,
 425       ARM64vecu_REV6416B,     ARM64vecu_REV648H,      ARM64vecu_REV644S,
 426       ARM64vecu_URECPE32x4,
 427       ARM64vecu_URSQRTE32x4,
 428       ARM64vecu_FRECPE64x2,   ARM64vecu_FRECPE32x4,
 429       ARM64vecu_FRSQRTE64x2,  ARM64vecu_FRSQRTE32x4,
 430       ARM64vecu_FSQRT64x2,    ARM64vecu_FSQRT32x4,
 431       ARM64vecu_INVALID
 432    }
 433    ARM64VecUnaryOp;
 434
 435 typedef
 436    enum {
 437       ARM64vecshi_USHR64x2=400, ARM64vecshi_USHR32x4,
 438       ARM64vecshi_USHR16x8,     ARM64vecshi_USHR8x16,
 439       ARM64vecshi_SSHR64x2,     ARM64vecshi_SSHR32x4,
 440       ARM64vecshi_SSHR16x8,     ARM64vecshi_SSHR8x16,
 441       ARM64vecshi_SHL64x2,      ARM64vecshi_SHL32x4,
 442       ARM64vecshi_SHL16x8,      ARM64vecshi_SHL8x16,
 443       /* These narrowing shifts zero out the top half of the destination
 444          register. */
 445       ARM64vecshi_SQSHRN2SD,    ARM64vecshi_SQSHRN4HS,   ARM64vecshi_SQSHRN8BH,
 446       ARM64vecshi_UQSHRN2SD,    ARM64vecshi_UQSHRN4HS,   ARM64vecshi_UQSHRN8BH,
 447       ARM64vecshi_SQSHRUN2SD,   ARM64vecshi_SQSHRUN4HS,  ARM64vecshi_SQSHRUN8BH,
 448       ARM64vecshi_SQRSHRN2SD,   ARM64vecshi_SQRSHRN4HS,  ARM64vecshi_SQRSHRN8BH,
 449       ARM64vecshi_UQRSHRN2SD,   ARM64vecshi_UQRSHRN4HS,  ARM64vecshi_UQRSHRN8BH,
 450       ARM64vecshi_SQRSHRUN2SD,  ARM64vecshi_SQRSHRUN4HS, ARM64vecshi_SQRSHRUN8BH,
 451       /* Saturating left shifts, of various flavours. */
 452       ARM64vecshi_UQSHL64x2,    ARM64vecshi_UQSHL32x4,
 453       ARM64vecshi_UQSHL16x8,    ARM64vecshi_UQSHL8x16,
 454       ARM64vecshi_SQSHL64x2,    ARM64vecshi_SQSHL32x4,
 455       ARM64vecshi_SQSHL16x8,    ARM64vecshi_SQSHL8x16,
 456       ARM64vecshi_SQSHLU64x2,   ARM64vecshi_SQSHLU32x4,
 457       ARM64vecshi_SQSHLU16x8,   ARM64vecshi_SQSHLU8x16,
 458       ARM64vecshi_INVALID
 459    }
 460    ARM64VecShiftImmOp;
 461
 462 typedef
 463    enum {
 464       ARM64vecna_XTN=450,
 465       ARM64vecna_SQXTN,
 466       ARM64vecna_UQXTN,
 467       ARM64vecna_SQXTUN,
 468       ARM64vecna_INVALID
 469    }
 470    ARM64VecNarrowOp;
 471
 472 typedef
 473    enum {
 474       /* baseline */
 475       ARM64in_Arith=1220,
 476       ARM64in_Cmp,
 477       ARM64in_Logic,
 478       ARM64in_Test,
 479       ARM64in_Shift,
 480       ARM64in_Unary,
 481       ARM64in_Set64,
 482       ARM64in_MovI,        /* int reg-reg move */
 483       ARM64in_Imm64,
 484       ARM64in_LdSt64,
 485       ARM64in_LdSt32,      /* w/ ZX loads */
 486       ARM64in_LdSt16,      /* w/ ZX loads */
 487       ARM64in_LdSt8,       /* w/ ZX loads */
 488       ARM64in_XDirect,     /* direct transfer to GA */
 489       ARM64in_XIndir,      /* indirect transfer to GA */
 490       ARM64in_XAssisted,   /* assisted transfer to GA */
 491       ARM64in_CSel,
 492       ARM64in_Call,
 493       ARM64in_AddToSP,     /* move SP by small, signed constant */
 494       ARM64in_FromSP,      /* move SP to integer register */
 495       ARM64in_Mul,
 496       ARM64in_LdrEX,
 497       ARM64in_StrEX,
 498       ARM64in_CAS,
 499       ARM64in_CASP,
 500       ARM64in_MFence,
 501       ARM64in_ClrEX,
 502       /* ARM64in_V*: scalar ops involving vector registers */
 503       ARM64in_VLdStH,   /* ld/st to/from low 16 bits of vec reg, imm offset */
 504       ARM64in_VLdStS,   /* ld/st to/from low 32 bits of vec reg, imm offset */
 505       ARM64in_VLdStD,   /* ld/st to/from low 64 bits of vec reg, imm offset */
 506       ARM64in_VLdStQ,   /* ld/st to/from all 128 bits of vec reg, no offset */
 507       ARM64in_VCvtI2F,
 508       ARM64in_VCvtF2I,
 509       ARM64in_VCvtSD,   /* scalar 32 bit FP <--> 64 bit FP */
 510       ARM64in_VCvtHS,   /* scalar 16 bit FP <--> 32 bit FP */
 511       ARM64in_VCvtHD,   /* scalar 16 bit FP <--> 64 bit FP */
 512       ARM64in_VUnaryD,
 513       ARM64in_VUnaryS,
 514       ARM64in_VBinD,
 515       ARM64in_VBinS,
 516       ARM64in_VTriD,
 517       ARM64in_VTriS,
 518       ARM64in_VCmpD,
 519       ARM64in_VCmpS,
 520       ARM64in_VFCSel,
 521       ARM64in_FPCR,
 522       ARM64in_FPSR,
 523       /* ARM64in_V*V: vector ops on vector registers */
 524       ARM64in_VBinV,
 525       ARM64in_VModifyV,
 526       ARM64in_VUnaryV,
 527       ARM64in_VNarrowV,
 528       ARM64in_VShiftImmV,
 529       ARM64in_VExtV,
 530       ARM64in_VImmQ,
 531       ARM64in_VDfromX,    /* Move an Xreg to a Dreg */
 532       ARM64in_VQfromX,    /* Move an Xreg to a Qreg lo64, and zero hi64 */
 533       ARM64in_VQfromXX,   /* Move 2 Xregs to a Qreg */
 534       ARM64in_VXfromQ,    /* Move half a Qreg to an Xreg */
 535       ARM64in_VXfromDorS, /* Move Dreg or Sreg(ZX) to an Xreg */
 536       ARM64in_VMov,       /* vector reg-reg move, 16, 8 or 4 bytes */
 537       /* infrastructure */
 538       ARM64in_EvCheck,    /* Event check */
 539       ARM64in_ProfInc     /* 64-bit profile counter increment */
 540    }
 541    ARM64InstrTag;
 542
 543 /* Destinations are on the LEFT (first operand) */
 544
 545 typedef
 546    struct {
 547       ARM64InstrTag tag;
 548       union {
 549          /* --- INTEGER INSTRUCTIONS --- */
 550          /* 64 bit ADD/SUB reg, reg or uimm12<<{0,12} */
 551          struct {
 552             HReg      dst;
 553             HReg      argL;
 554             ARM64RIA* argR;
 555             Bool      isAdd;
 556          } Arith;
 557          /* 64 or 32 bit CMP reg, reg or aimm (SUB and set flags) */
 558          struct {
 559             HReg      argL;
 560             ARM64RIA* argR;
 561             Bool      is64;
 562          } Cmp;
 563          /* 64 bit AND/OR/XOR reg, reg or bitfield-immediate */
 564          struct {
 565             HReg         dst;
 566             HReg         argL;
 567             ARM64RIL*    argR;
 568             ARM64LogicOp op;
 569          } Logic;
 570          /* 64 bit TST reg, reg or bimm (AND and set flags) */
 571          struct {
 572             HReg      argL;
 573             ARM64RIL* argR;
 574          } Test;
 575          /* 64 bit SHL/SHR/SAR, 2nd arg is reg or imm */
 576          struct {
 577             HReg         dst;
 578             HReg         argL;
 579             ARM64RI6*    argR;
 580             ARM64ShiftOp op;
 581          } Shift;
 582          /* NOT/NEG/CLZ, 64 bit only */
 583          struct {
 584             HReg         dst;
 585             HReg         src;
 586             ARM64UnaryOp op;
 587          } Unary;
 588          /* CSET -- Convert a condition code to a 64-bit value (0 or 1). */
 589          struct {
 590             HReg          dst;
 591             ARM64CondCode cond;
 592          } Set64;
 593          /* MOV dst, src -- reg-reg move for integer registers */
 594          struct {
 595             HReg dst;
 596             HReg src;
 597          } MovI;
 598          /* Pseudo-insn; make a 64-bit immediate */
 599          struct {
 600             HReg  dst;
 601             ULong imm64;
 602          } Imm64;
 603          /* 64-bit load or store */
 604          struct {
 605             Bool        isLoad;
 606             HReg        rD;
 607             ARM64AMode* amode;
 608          } LdSt64;
 609          /* zx-32-to-64-bit load, or 32-bit store */
 610          struct {
 611             Bool        isLoad;
 612             HReg        rD;
 613             ARM64AMode* amode;
 614          } LdSt32;
 615          /* zx-16-to-64-bit load, or 16-bit store */
 616          struct {
 617             Bool        isLoad;
 618             HReg        rD;
 619             ARM64AMode* amode;
 620          } LdSt16;
 621          /* zx-8-to-64-bit load, or 8-bit store */
 622          struct {
 623             Bool        isLoad;
 624             HReg        rD;
 625             ARM64AMode* amode;
 626          } LdSt8;
 627          /* Update the guest PC value, then exit requesting to chain
 628             to it.  May be conditional.  Urr, use of Addr64 implicitly
 629             assumes that wordsize(guest) == wordsize(host). */
 630          struct {
 631             Addr64        dstGA;    /* next guest address */
 632             ARM64AMode*   amPC;     /* amode in guest state for PC */
 633             ARM64CondCode cond;     /* can be ARM64cc_AL */
 634             Bool          toFastEP; /* chain to the slow or fast point? */
 635          } XDirect;
 636          /* Boring transfer to a guest address not known at JIT time.
 637             Not chainable.  May be conditional. */
 638          struct {
 639             HReg          dstGA;
 640             ARM64AMode*   amPC;
 641             ARM64CondCode cond; /* can be ARM64cc_AL */
 642          } XIndir;
 643          /* Assisted transfer to a guest address, most general case.
 644             Not chainable.  May be conditional. */
 645          struct {
 646             HReg          dstGA;
 647             ARM64AMode*   amPC;
 648             ARM64CondCode cond; /* can be ARM64cc_AL */
 649             IRJumpKind    jk;
 650          } XAssisted;
 651          /* CSEL: dst = if cond then argL else argR.  cond may be anything. */
 652           struct {
 653             HReg          dst;
 654             HReg          argL;
 655             HReg          argR;
 656             ARM64CondCode cond;
 657          } CSel;
 658          /* Pseudo-insn.  Call target (an absolute address), on given
 659             condition (which could be ARM64cc_AL). */
 660          struct {
 661             RetLoc        rloc;     /* where the return value will be */
 662             Addr64        target;
 663             ARM64CondCode cond;
 664             Int           nArgRegs; /* # regs carrying args: 0 .. 8 */
 665          } Call;
 666          /* move SP by small, signed constant */
 667          struct {
 668             Int simm; /* needs to be 0 % 16 and in the range -4095
 669                          .. 4095 inclusive */
 670          } AddToSP;
 671          /* move SP to integer register */
 672          struct {
 673             HReg dst;
 674          } FromSP;
 675          /* Integer multiply, with 3 variants:
 676               (PLAIN) lo64(64 *  64)
 677               (ZX)    hi64(64 *u 64)
 678               (SX)    hi64(64 *s 64)
 679          */
 680          struct {
 681             HReg       dst;
 682             HReg       argL;
 683             HReg       argR;
 684             ARM64MulOp op;
 685          } Mul;
 686          /* LDXR{,H,B} x2, [x4] */
 687          struct {
 688             Int  szB; /* 1, 2, 4 or 8 */
 689          } LdrEX;
 690          /* STXR{,H,B} w0, x2, [x4] */
 691          struct {
 692             Int  szB; /* 1, 2, 4 or 8 */
 693          } StrEX;
 694          /* x1 = CAS(x3(addr), x5(expected) -> x7(new)),
 695             where x1[8*szB-1 : 0] == x5[8*szB-1 : 0] indicates success,
 696                   x1[8*szB-1 : 0] != x5[8*szB-1 : 0] indicates failure.
 697             Uses x8 as scratch (but that's not allocatable).
 698             Hence: RD x3, x5, x7; WR x1
 699
 700            loop:
 701             (szB=8)  mov  x8, x5
 702             (szB=4)  and  x8, x5, #0xFFFFFFFF
 703             (szB=2)  and  x8, x5, #0xFFFF
 704             (szB=1)  and  x8, x5, #0xFF
 705             -- x8 is correctly zero-extended expected value
 706             ldxr    x1, [x3]
 707             -- x1 is correctly zero-extended actual value
 708             cmp     x1, x8
 709             bne     after
 710             -- if branch taken, failure; x1[[8*szB-1 : 0] holds old value
 711             -- attempt to store
 712             stxr    w8, x7, [x3]
 713             -- if store successful, x1==0, so the eor is "x1 := x5"
 714             -- if store failed,     branch back and try again.
 715             cbne    w8, loop
 716            after:
 717          */
 718          struct {
 719             Int szB; /* 1, 2, 4 or 8 */
 720          } CAS;
 721          struct {
 722             Int szB; /* 4 or 8 */
 723          } CASP;
 724          /* Mem fence.  An insn which fences all loads and stores as
 725             much as possible before continuing.  On ARM64 we emit the
 726             sequence "dsb sy ; dmb sy ; isb sy", which is probably
 727             total nuclear overkill, but better safe than sorry. */
 728          struct {
 729          } MFence;
 730          /* A CLREX instruction. */
 731          struct {
 732          } ClrEX;
 733          /* --- INSTRUCTIONS INVOLVING VECTOR REGISTERS --- */
 734          /* ld/st to/from low 16 bits of vec reg, imm offset */
 735          struct {
 736             Bool isLoad;
 737             HReg hD;
 738             HReg rN;
 739             UInt uimm12;  /* 0 .. 8190 inclusive, 0 % 2 */
 740          } VLdStH;
 741          /* ld/st to/from low 32 bits of vec reg, imm offset */
 742          struct {
 743             Bool isLoad;
 744             HReg sD;
 745             HReg rN;
 746             UInt uimm12;  /* 0 .. 16380 inclusive, 0 % 4 */
 747          } VLdStS;
 748          /* ld/st to/from low 64 bits of vec reg, imm offset */
 749          struct {
 750             Bool isLoad;
 751             HReg dD;
 752             HReg rN;
 753             UInt uimm12;  /* 0 .. 32760 inclusive, 0 % 8 */
 754          } VLdStD;
 755          /* ld/st to/from all 128 bits of vec reg, no offset */
 756          struct {
 757             Bool isLoad;
 758             HReg rQ; // data
 759             HReg rN; // address
 760          } VLdStQ;
 761          /* Scalar conversion of int to float. */
 762          struct {
 763             ARM64CvtOp how;
 764             HReg       rD; // dst, a D or S register
 765             HReg       rS; // src, a W or X register
 766          } VCvtI2F;
 767          /* Scalar conversion of float to int, w/ specified RM. */
 768          struct {
 769             ARM64CvtOp how;
 770             HReg       rD; // dst, a W or X register
 771             HReg       rS; // src, a D or S register
 772             UChar      armRM; // ARM encoded RM:
 773                               // 00=nearest, 01=+inf, 10=-inf, 11=zero
 774          } VCvtF2I;
 775          /* Convert between 32-bit and 64-bit FP values (both ways). (FCVT) */
 776          struct {
 777             Bool sToD; /* True: F32->F64.  False: F64->F32 */
 778             HReg dst;
 779             HReg src;
 780          } VCvtSD;
 781          /* Convert between 16-bit and 32-bit FP values (both ways). (FCVT) */
 782          struct {
 783             Bool hToS; /* True: F16->F32.  False: F32->F16 */
 784             HReg dst;
 785             HReg src;
 786          } VCvtHS;
 787          /* Convert between 16-bit and 64-bit FP values (both ways). (FCVT) */
 788          struct {
 789             Bool hToD; /* True: F16->F64.  False: F64->F16 */
 790             HReg dst;
 791             HReg src;
 792          } VCvtHD;
 793          /* 64-bit FP unary */
 794          struct {
 795             ARM64FpUnaryOp op;
 796             HReg           dst;
 797             HReg           src;
 798          } VUnaryD;
 799          /* 32-bit FP unary */
 800          struct {
 801             ARM64FpUnaryOp op;
 802             HReg           dst;
 803             HReg           src;
 804          } VUnaryS;
 805          /* 64-bit FP binary arithmetic */
 806          struct {
 807             ARM64FpBinOp op;
 808             HReg         dst;
 809             HReg         argL;
 810             HReg         argR;
 811          } VBinD;
 812          /* 32-bit FP binary arithmetic */
 813          struct {
 814             ARM64FpBinOp op;
 815             HReg         dst;
 816             HReg         argL;
 817             HReg         argR;
 818          } VBinS;
 819          /* 64-bit FP ternary arithmetic */
 820          struct {
 821             ARM64FpTriOp op;
 822             HReg         dst;
 823             HReg         arg1;
 824             HReg         arg2;
 825             HReg         arg3;
 826          } VTriD;
 827          /* 32-bit FP ternary arithmetic */
 828          struct {
 829             ARM64FpTriOp op;
 830             HReg         dst;
 831             HReg         arg1;
 832             HReg         arg2;
 833             HReg         arg3;
 834          } VTriS;
 835          /* 64-bit FP compare */
 836          struct {
 837             HReg argL;
 838             HReg argR;
 839          } VCmpD;
 840          /* 32-bit FP compare */
 841          struct {
 842             HReg argL;
 843             HReg argR;
 844          } VCmpS;
 845          /* 32- or 64-bit FP conditional select */
 846          struct {
 847             HReg          dst;
 848             HReg          argL;
 849             HReg          argR;
 850             ARM64CondCode cond;
 851             Bool          isD;
 852          }
 853          VFCSel;
 854          /* Move a 32-bit value to/from the FPCR */
 855          struct {
 856             Bool toFPCR;
 857             HReg iReg;
 858          } FPCR;
 859          /* Move a 32-bit value to/from the FPSR */
 860          struct {
 861             Bool toFPSR;
 862             HReg iReg;
 863          } FPSR;
 864          /* binary vector operation on vector registers */
 865          struct {
 866             ARM64VecBinOp op;
 867             HReg          dst;
 868             HReg          argL;
 869             HReg          argR;
 870          } VBinV;
 871          /* binary vector operation on vector registers.
 872             Dst reg is also a src. */
 873          struct {
 874             ARM64VecModifyOp op;
 875             HReg             mod;
 876             HReg             arg;
 877          } VModifyV;
 878          /* unary vector operation on vector registers */
 879          struct {
 880             ARM64VecUnaryOp op;
 881             HReg            dst;
 882             HReg            arg;
 883          } VUnaryV;
 884          /* vector narrowing, Q -> Q.  Result goes in the bottom half
 885             of dst and the top half is zeroed out.  Iow one of the
 886             XTN family. */
 887         struct {
 888            ARM64VecNarrowOp op;
 889            UInt             dszBlg2; // 0: 16to8_x8  1: 32to16_x4  2: 64to32_x2
 890            HReg             dst;     // Q reg
 891            HReg             src;     // Q reg
 892         } VNarrowV;
 893         /* Vector shift by immediate.  For left shifts, |amt| must be
 894            >= 0 and < implied lane size of |op|.  For right shifts,
 895            |amt| must be > 0 and <= implied lane size of |op|.  Shifts
 896            beyond these ranges are not allowed. */
 897         struct {
 898            ARM64VecShiftImmOp op;
 899            HReg               dst;
 900            HReg               src;
 901            UInt               amt;
 902         } VShiftImmV;
 903         struct {
 904            HReg dst;
 905            HReg srcLo;
 906            HReg srcHi;
 907            UInt amtB;
 908         } VExtV;
 909          struct {
 910             HReg   rQ;
 911             UShort imm; /* Same 1-bit-per-byte encoding as IR */
 912          } VImmQ;
 913          struct {
 914             HReg rD;
 915             HReg rX;
 916          } VDfromX;
 917          struct {
 918             HReg rQ;
 919             HReg rXlo;
 920          } VQfromX;
 921          struct {
 922             HReg rQ;
 923             HReg rXhi;
 924             HReg rXlo;
 925          } VQfromXX;
 926          struct {
 927             HReg rX;
 928             HReg rQ;
 929             UInt laneNo; /* either 0 or 1 */
 930          } VXfromQ;
 931          struct {
 932             HReg rX;
 933             HReg rDorS;
 934             Bool fromD;
 935          } VXfromDorS;
 936          /* MOV dst, src -- reg-reg move for vector registers */
 937          struct {
 938             UInt szB; // 16=mov qD,qS;  8=mov dD,dS;  4=mov sD,sS
 939             HReg dst;
 940             HReg src;
 941          } VMov;
 942          struct {
 943             ARM64AMode* amCounter;
 944             ARM64AMode* amFailAddr;
 945          } EvCheck;
 946          struct {
 947             /* No fields.  The address of the counter to inc is
 948                installed later, post-translation, by patching it in,
 949                as it is not known at translation time. */
 950          } ProfInc;
 951       } ARM64in;
 952    }
 953    ARM64Instr;
 954
 955
 956 extern ARM64Instr* ARM64Instr_Arith   ( HReg, HReg, ARM64RIA*, Bool isAdd );
 957 extern ARM64Instr* ARM64Instr_Cmp     ( HReg, ARM64RIA*, Bool is64 );
 958 extern ARM64Instr* ARM64Instr_Logic   ( HReg, HReg, ARM64RIL*, ARM64LogicOp );
 959 extern ARM64Instr* ARM64Instr_Test    ( HReg, ARM64RIL* );
 960 extern ARM64Instr* ARM64Instr_Shift   ( HReg, HReg, ARM64RI6*, ARM64ShiftOp );
 961 extern ARM64Instr* ARM64Instr_Unary   ( HReg, HReg, ARM64UnaryOp );
 962 extern ARM64Instr* ARM64Instr_Set64   ( HReg, ARM64CondCode );
 963 extern ARM64Instr* ARM64Instr_MovI    ( HReg, HReg );
 964 extern ARM64Instr* ARM64Instr_Imm64   ( HReg, ULong );
 965 extern ARM64Instr* ARM64Instr_LdSt64  ( Bool isLoad, HReg, ARM64AMode* );
 966 extern ARM64Instr* ARM64Instr_LdSt32  ( Bool isLoad, HReg, ARM64AMode* );
 967 extern ARM64Instr* ARM64Instr_LdSt16  ( Bool isLoad, HReg, ARM64AMode* );
 968 extern ARM64Instr* ARM64Instr_LdSt8   ( Bool isLoad, HReg, ARM64AMode* );
 969 extern ARM64Instr* ARM64Instr_XDirect ( Addr64 dstGA, ARM64AMode* amPC,
 970                                         ARM64CondCode cond, Bool toFastEP );
 971 extern ARM64Instr* ARM64Instr_XIndir  ( HReg dstGA, ARM64AMode* amPC,
 972                                         ARM64CondCode cond );
 973 extern ARM64Instr* ARM64Instr_XAssisted ( HReg dstGA, ARM64AMode* amPC,
 974                                           ARM64CondCode cond, IRJumpKind jk );
 975 extern ARM64Instr* ARM64Instr_CSel    ( HReg dst, HReg argL, HReg argR,
 976                                         ARM64CondCode cond );
 977 extern ARM64Instr* ARM64Instr_Call    ( ARM64CondCode, Addr64, Int nArgRegs,
 978                                         RetLoc rloc );
 979 extern ARM64Instr* ARM64Instr_AddToSP ( Int simm );
 980 extern ARM64Instr* ARM64Instr_FromSP  ( HReg dst );
 981 extern ARM64Instr* ARM64Instr_Mul     ( HReg dst, HReg argL, HReg argR,
 982                                         ARM64MulOp op );
 983 extern ARM64Instr* ARM64Instr_LdrEX   ( Int szB );
 984 extern ARM64Instr* ARM64Instr_StrEX   ( Int szB );
 985 extern ARM64Instr* ARM64Instr_CAS     ( Int szB );
 986 extern ARM64Instr* ARM64Instr_CASP    ( Int szB );
 987 extern ARM64Instr* ARM64Instr_MFence  ( void );
 988 extern ARM64Instr* ARM64Instr_ClrEX   ( void );
 989 extern ARM64Instr* ARM64Instr_VLdStH  ( Bool isLoad, HReg sD, HReg rN,
 990                                         UInt uimm12 /* 0 .. 8190, 0 % 2 */ );
 991 extern ARM64Instr* ARM64Instr_VLdStS  ( Bool isLoad, HReg sD, HReg rN,
 992                                         UInt uimm12 /* 0 .. 16380, 0 % 4 */ );
 993 extern ARM64Instr* ARM64Instr_VLdStD  ( Bool isLoad, HReg dD, HReg rN,
 994                                         UInt uimm12 /* 0 .. 32760, 0 % 8 */ );
 995 extern ARM64Instr* ARM64Instr_VLdStQ  ( Bool isLoad, HReg rQ, HReg rN );
 996 extern ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS );
 997 extern ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS,
 998                                         UChar armRM );
 999 extern ARM64Instr* ARM64Instr_VCvtSD  ( Bool sToD, HReg dst, HReg src );
1000 extern ARM64Instr* ARM64Instr_VCvtHS  ( Bool hToS, HReg dst, HReg src );
1001 extern ARM64Instr* ARM64Instr_VCvtHD  ( Bool hToD, HReg dst, HReg src );
1002 extern ARM64Instr* ARM64Instr_VUnaryD ( ARM64FpUnaryOp op, HReg dst, HReg src );
1003 extern ARM64Instr* ARM64Instr_VUnaryS ( ARM64FpUnaryOp op, HReg dst, HReg src );
1004 extern ARM64Instr* ARM64Instr_VBinD   ( ARM64FpBinOp op, HReg, HReg, HReg );
1005 extern ARM64Instr* ARM64Instr_VBinS   ( ARM64FpBinOp op, HReg, HReg, HReg );
1006 extern ARM64Instr* ARM64Instr_VTriD   ( ARM64FpTriOp op, HReg dst,
1007                                         HReg, HReg, HReg );
1008 extern ARM64Instr* ARM64Instr_VTriS   ( ARM64FpTriOp op, HReg dst,
1009                                         HReg, HReg, HReg );
1010 extern ARM64Instr* ARM64Instr_VCmpD   ( HReg argL, HReg argR );
1011 extern ARM64Instr* ARM64Instr_VCmpS   ( HReg argL, HReg argR );
1012 extern ARM64Instr* ARM64Instr_VFCSel  ( HReg dst, HReg argL, HReg argR,
1013                                         ARM64CondCode cond, Bool isD );
1014 extern ARM64Instr* ARM64Instr_FPCR    ( Bool toFPCR, HReg iReg );
1015 extern ARM64Instr* ARM64Instr_FPSR    ( Bool toFPSR, HReg iReg );
1016 extern ARM64Instr* ARM64Instr_VBinV   ( ARM64VecBinOp op, HReg, HReg, HReg );
1017 extern ARM64Instr* ARM64Instr_VModifyV ( ARM64VecModifyOp, HReg, HReg );
1018 extern ARM64Instr* ARM64Instr_VUnaryV ( ARM64VecUnaryOp op, HReg, HReg );
1019 extern ARM64Instr* ARM64Instr_VNarrowV ( ARM64VecNarrowOp op, UInt dszBlg2,
1020                                          HReg dst, HReg src );
1021 extern ARM64Instr* ARM64Instr_VShiftImmV ( ARM64VecShiftImmOp op,
1022                                            HReg dst, HReg src, UInt amt );
1023 extern ARM64Instr* ARM64Instr_VExtV   ( HReg dst,
1024                                         HReg srcLo, HReg srcHi, UInt amtB );
1025 extern ARM64Instr* ARM64Instr_VImmQ   ( HReg, UShort );
1026 extern ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX );
1027 extern ARM64Instr* ARM64Instr_VQfromX ( HReg rQ, HReg rXlo );
1028 extern ARM64Instr* ARM64Instr_VQfromXX( HReg rQ, HReg rXhi, HReg rXlo );
1029 extern ARM64Instr* ARM64Instr_VXfromQ ( HReg rX, HReg rQ, UInt laneNo );
1030 extern ARM64Instr* ARM64Instr_VXfromDorS ( HReg rX, HReg rDorS, Bool fromD );
1031 extern ARM64Instr* ARM64Instr_VMov    ( UInt szB, HReg dst, HReg src );
1032
1033 extern ARM64Instr* ARM64Instr_EvCheck ( ARM64AMode* amCounter,
1034                                         ARM64AMode* amFailAddr );
1035 extern ARM64Instr* ARM64Instr_ProfInc ( void );
1036
1037 extern void ppARM64Instr ( const ARM64Instr* );
1038
1039
1040 /* Some functions that insulate the register allocator from details
1041    of the underlying instruction set. */
1042 extern void getRegUsage_ARM64Instr ( HRegUsage*, const ARM64Instr*, Bool );
1043 extern void mapRegs_ARM64Instr     ( HRegRemap*, ARM64Instr*, Bool );
1044 extern Int  emit_ARM64Instr        ( /*MB_MOD*/Bool* is_profInc,
1045                                      UChar* buf, Int nbuf, const ARM64Instr* i,
1046                                      Bool mode64,
1047                                      VexEndness endness_host,
1048                                      const void* disp_cp_chain_me_to_slowEP,
1049                                      const void* disp_cp_chain_me_to_fastEP,
1050                                      const void* disp_cp_xindir,
1051                                      const void* disp_cp_xassisted );
1052
1053 extern void genSpill_ARM64  ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1054                               HReg rreg, Int offset, Bool );
1055 extern void genReload_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1056                               HReg rreg, Int offset, Bool );
1057 extern ARM64Instr* genMove_ARM64(HReg from, HReg to, Bool);
1058
1059 extern const RRegUniverse* getRRegUniverse_ARM64 ( void );
1060
1061 extern HInstrArray* iselSB_ARM64 ( const IRSB*,
1062                                    VexArch,
1063                                    const VexArchInfo*,
1064                                    const VexAbiInfo*,
1065                                    Int offs_Host_EvC_Counter,
1066                                    Int offs_Host_EvC_FailAddr,
1067                                    Bool chainingAllowed,
1068                                    Bool addProfInc,
1069                                    Addr max_ga );
1070
1071 /* How big is an event check?  This is kind of a kludge because it
1072    depends on the offsets of host_EvC_FAILADDR and
1073    host_EvC_COUNTER. */
1074 extern Int evCheckSzB_ARM64 (void);
1075
1076 /* Perform a chaining and unchaining of an XDirect jump. */
1077 extern VexInvalRange chainXDirect_ARM64 ( VexEndness endness_host,
1078                                           void* place_to_chain,
1079                                           const void* disp_cp_chain_me_EXPECTED,
1080                                           const void* place_to_jump_to );
1081
1082 extern VexInvalRange unchainXDirect_ARM64 ( VexEndness endness_host,
1083                                             void* place_to_unchain,
1084                                             const void* place_to_jump_to_EXPECTED,
1085                                             const void* disp_cp_chain_me );
1086
1087 /* Patch the counter location into an existing ProfInc point. */
1088 extern VexInvalRange patchProfInc_ARM64 ( VexEndness endness_host,
1089                                           void*  place_to_patch,
1090                                           const ULong* location_of_counter );
1091
1092
1093 #endif /* ndef __VEX_HOST_ARM64_DEFS_H */
1094
1095 /*---------------------------------------------------------------*/
1096 /*--- end                                   host_arm64_defs.h ---*/
1097 /*---------------------------------------------------------------*/