VEX/priv/host_amd64_defs.h

   1
   2 /*---------------------------------------------------------------*/
   3 /*--- begin                                 host_amd64_defs.h ---*/
   4 /*---------------------------------------------------------------*/
   5
   6 /*
   7    This file is part of Valgrind, a dynamic binary instrumentation
   8    framework.
   9
  10    Copyright (C) 2004-2017 OpenWorks LLP
  11       info@open-works.net
  12
  13    This program is free software; you can redistribute it and/or
  14    modify it under the terms of the GNU General Public License as
  15    published by the Free Software Foundation; either version 2 of the
  16    License, or (at your option) any later version.
  17
  18    This program is distributed in the hope that it will be useful, but
  19    WITHOUT ANY WARRANTY; without even the implied warranty of
  20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21    General Public License for more details.
  22
  23    You should have received a copy of the GNU General Public License
  24    along with this program; if not, see <http://www.gnu.org/licenses/>.
  25
  26    The GNU General Public License is contained in the file COPYING.
  27
  28    Neither the names of the U.S. Department of Energy nor the
  29    University of California nor the names of its contributors may be
  30    used to endorse or promote products derived from this software
  31    without prior written permission.
  32 */
  33
  34 #ifndef __VEX_HOST_AMD64_DEFS_H
  35 #define __VEX_HOST_AMD64_DEFS_H
  36
  37 #include "libvex_basictypes.h"
  38 #include "libvex.h"                      // VexArch
  39 #include "host_generic_regs.h"           // HReg
  40
  41 /* --------- Registers. --------- */
  42
  43 /* The usual HReg abstraction.  There are 16 real int regs, 6 real
  44    float regs, and 16 real vector regs.
  45 */
  46
  47 #define ST_IN static inline
  48 ST_IN HReg hregAMD64_R12   ( void ) { return mkHReg(False, HRcInt64,  12,  0); }
  49 ST_IN HReg hregAMD64_R13   ( void ) { return mkHReg(False, HRcInt64,  13,  1); }
  50 ST_IN HReg hregAMD64_R14   ( void ) { return mkHReg(False, HRcInt64,  14,  2); }
  51 ST_IN HReg hregAMD64_R15   ( void ) { return mkHReg(False, HRcInt64,  15,  3); }
  52 ST_IN HReg hregAMD64_RBX   ( void ) { return mkHReg(False, HRcInt64,   3,  4); }
  53 ST_IN HReg hregAMD64_RSI   ( void ) { return mkHReg(False, HRcInt64,   6,  5); }
  54 ST_IN HReg hregAMD64_RDI   ( void ) { return mkHReg(False, HRcInt64,   7,  6); }
  55 ST_IN HReg hregAMD64_R8    ( void ) { return mkHReg(False, HRcInt64,   8,  7); }
  56 ST_IN HReg hregAMD64_R9    ( void ) { return mkHReg(False, HRcInt64,   9,  8); }
  57 ST_IN HReg hregAMD64_R10   ( void ) { return mkHReg(False, HRcInt64,  10,  9); }
  58
  59 ST_IN HReg hregAMD64_XMM3  ( void ) { return mkHReg(False, HRcVec128,  3, 10); }
  60 ST_IN HReg hregAMD64_XMM4  ( void ) { return mkHReg(False, HRcVec128,  4, 11); }
  61 ST_IN HReg hregAMD64_XMM5  ( void ) { return mkHReg(False, HRcVec128,  5, 12); }
  62 ST_IN HReg hregAMD64_XMM6  ( void ) { return mkHReg(False, HRcVec128,  6, 13); }
  63 ST_IN HReg hregAMD64_XMM7  ( void ) { return mkHReg(False, HRcVec128,  7, 14); }
  64 ST_IN HReg hregAMD64_XMM8  ( void ) { return mkHReg(False, HRcVec128,  8, 15); }
  65 ST_IN HReg hregAMD64_XMM9  ( void ) { return mkHReg(False, HRcVec128,  9, 16); }
  66 ST_IN HReg hregAMD64_XMM10 ( void ) { return mkHReg(False, HRcVec128, 10, 17); }
  67 ST_IN HReg hregAMD64_XMM11 ( void ) { return mkHReg(False, HRcVec128, 11, 18); }
  68 ST_IN HReg hregAMD64_XMM12 ( void ) { return mkHReg(False, HRcVec128, 12, 19); }
  69
  70 ST_IN HReg hregAMD64_RAX   ( void ) { return mkHReg(False, HRcInt64,   0, 20); }
  71 ST_IN HReg hregAMD64_RCX   ( void ) { return mkHReg(False, HRcInt64,   1, 21); }
  72 ST_IN HReg hregAMD64_RDX   ( void ) { return mkHReg(False, HRcInt64,   2, 22); }
  73 ST_IN HReg hregAMD64_RSP   ( void ) { return mkHReg(False, HRcInt64,   4, 23); }
  74 ST_IN HReg hregAMD64_RBP   ( void ) { return mkHReg(False, HRcInt64,   5, 24); }
  75 ST_IN HReg hregAMD64_R11   ( void ) { return mkHReg(False, HRcInt64,  11, 25); }
  76
  77 ST_IN HReg hregAMD64_XMM0  ( void ) { return mkHReg(False, HRcVec128,  0, 26); }
  78 ST_IN HReg hregAMD64_XMM1  ( void ) { return mkHReg(False, HRcVec128,  1, 27); }
  79 #undef ST_IN
  80
  81 extern UInt ppHRegAMD64 ( HReg );
  82
  83
  84 /* --------- Condition codes, AMD encoding. --------- */
  85
  86 typedef
  87    enum {
  88       Acc_O      = 0,  /* overflow           */
  89       Acc_NO     = 1,  /* no overflow        */
  90
  91       Acc_B      = 2,  /* below              */
  92       Acc_NB     = 3,  /* not below          */
  93
  94       Acc_Z      = 4,  /* zero               */
  95       Acc_NZ     = 5,  /* not zero           */
  96
  97       Acc_BE     = 6,  /* below or equal     */
  98       Acc_NBE    = 7,  /* not below or equal */
  99
 100       Acc_S      = 8,  /* negative           */
 101       Acc_NS     = 9,  /* not negative       */
 102
 103       Acc_P      = 10, /* parity even        */
 104       Acc_NP     = 11, /* not parity even    */
 105
 106       Acc_L      = 12, /* jump less          */
 107       Acc_NL     = 13, /* not less           */
 108
 109       Acc_LE     = 14, /* less or equal      */
 110       Acc_NLE    = 15, /* not less or equal  */
 111
 112       Acc_ALWAYS = 16  /* the usual hack     */
 113    }
 114    AMD64CondCode;
 115
 116 extern const HChar* showAMD64CondCode ( AMD64CondCode );
 117
 118
 119 /* --------- Memory address expressions (amodes). --------- */
 120
 121 typedef
 122    enum {
 123      Aam_IR,        /* Immediate + Reg */
 124      Aam_IRRS       /* Immediate + Reg1 + (Reg2 << Shift) */
 125    }
 126    AMD64AModeTag;
 127
 128 typedef
 129    struct {
 130       AMD64AModeTag tag;
 131       union {
 132          struct {
 133             UInt imm;
 134             HReg reg;
 135          } IR;
 136          struct {
 137             UInt imm;
 138             HReg base;
 139             HReg index;
 140             Int  shift; /* 0, 1, 2 or 3 only */
 141          } IRRS;
 142       } Aam;
 143    }
 144    AMD64AMode;
 145
 146 extern AMD64AMode* AMD64AMode_IR   ( UInt, HReg );
 147 extern AMD64AMode* AMD64AMode_IRRS ( UInt, HReg, HReg, Int );
 148
 149 extern AMD64AMode* dopyAMD64AMode ( AMD64AMode* );
 150
 151 extern void ppAMD64AMode ( AMD64AMode* );
 152
 153
 154 /* --------- Operand, which can be reg, immediate or memory. --------- */
 155
 156 typedef
 157    enum {
 158       Armi_Imm,
 159       Armi_Reg,
 160       Armi_Mem
 161    }
 162    AMD64RMITag;
 163
 164 typedef
 165    struct {
 166       AMD64RMITag tag;
 167       union {
 168          struct {
 169             UInt imm32;
 170          } Imm;
 171          struct {
 172             HReg reg;
 173          } Reg;
 174          struct {
 175             AMD64AMode* am;
 176          } Mem;
 177       }
 178       Armi;
 179    }
 180    AMD64RMI;
 181
 182 extern AMD64RMI* AMD64RMI_Imm ( UInt );
 183 extern AMD64RMI* AMD64RMI_Reg ( HReg );
 184 extern AMD64RMI* AMD64RMI_Mem ( AMD64AMode* );
 185
 186 extern void ppAMD64RMI      ( AMD64RMI* );
 187 extern void ppAMD64RMI_lo32 ( AMD64RMI* );
 188
 189
 190 /* --------- Operand, which can be reg or immediate only. --------- */
 191
 192 typedef
 193    enum {
 194       Ari_Imm,
 195       Ari_Reg
 196    }
 197    AMD64RITag;
 198
 199 typedef
 200    struct {
 201       AMD64RITag tag;
 202       union {
 203          struct {
 204             UInt imm32;
 205          } Imm;
 206          struct {
 207             HReg reg;
 208          } Reg;
 209       }
 210       Ari;
 211    }
 212    AMD64RI;
 213
 214 extern AMD64RI* AMD64RI_Imm ( UInt );
 215 extern AMD64RI* AMD64RI_Reg ( HReg );
 216
 217 extern void ppAMD64RI ( AMD64RI* );
 218
 219
 220 /* --------- Operand, which can be reg or memory only. --------- */
 221
 222 typedef
 223    enum {
 224       Arm_Reg,
 225       Arm_Mem
 226    }
 227    AMD64RMTag;
 228
 229 typedef
 230    struct {
 231       AMD64RMTag tag;
 232       union {
 233          struct {
 234             HReg reg;
 235          } Reg;
 236          struct {
 237             AMD64AMode* am;
 238          } Mem;
 239       }
 240       Arm;
 241    }
 242    AMD64RM;
 243
 244 extern AMD64RM* AMD64RM_Reg ( HReg );
 245 extern AMD64RM* AMD64RM_Mem ( AMD64AMode* );
 246
 247 extern void ppAMD64RM ( AMD64RM* );
 248
 249
 250 /* --------- Instructions. --------- */
 251
 252 /* --------- */
 253 typedef
 254    enum {
 255       Aun_NEG,
 256       Aun_NOT
 257    }
 258    AMD64UnaryOp;
 259
 260 extern const HChar* showAMD64UnaryOp ( AMD64UnaryOp );
 261
 262
 263 /* --------- */
 264 typedef
 265    enum {
 266       Aalu_INVALID,
 267       Aalu_MOV,
 268       Aalu_CMP,
 269       Aalu_ADD, Aalu_SUB, Aalu_ADC, Aalu_SBB,
 270       Aalu_AND, Aalu_OR, Aalu_XOR,
 271       Aalu_MUL
 272    }
 273    AMD64AluOp;
 274
 275 extern const HChar* showAMD64AluOp ( AMD64AluOp );
 276
 277
 278 /* --------- */
 279 typedef
 280    enum {
 281       Ash_INVALID,
 282       Ash_SHL, Ash_SHR, Ash_SAR
 283    }
 284    AMD64ShiftOp;
 285
 286 extern const HChar* showAMD64ShiftOp ( AMD64ShiftOp );
 287
 288
 289 /* --------- */
 290 typedef
 291    enum {
 292       Afp_INVALID,
 293       /* Binary */
 294       Afp_SCALE, Afp_ATAN, Afp_YL2X, Afp_YL2XP1, Afp_PREM, Afp_PREM1,
 295       /* Unary */
 296       Afp_SQRT,
 297       Afp_SIN, Afp_COS, Afp_TAN,
 298       Afp_ROUND, Afp_2XM1
 299    }
 300    A87FpOp;
 301
 302 extern const HChar* showA87FpOp ( A87FpOp );
 303
 304
 305 /* --------- */
 306 typedef
 307    enum {
 308       Asse_INVALID,
 309       /* mov */
 310       Asse_MOV,
 311       /* Floating point binary */
 312       Asse_ADDF, Asse_SUBF, Asse_MULF, Asse_DIVF,
 313       Asse_MAXF, Asse_MINF,
 314       Asse_CMPEQF, Asse_CMPLTF, Asse_CMPLEF, Asse_CMPUNF,
 315       /* Floating point unary */
 316       Asse_RCPF, Asse_RSQRTF, Asse_SQRTF,
 317       /* Floating point conversion */
 318       Asse_I2F, // i32-signed to float conversion, aka cvtdq2ps in vec form
 319       Asse_F2I, // float to i32-signed conversion, aka cvtps2dq in vec form
 320       /* Bitwise */
 321       Asse_AND, Asse_OR, Asse_XOR, Asse_ANDN,
 322       Asse_ADD8, Asse_ADD16, Asse_ADD32, Asse_ADD64,
 323       Asse_QADD8U, Asse_QADD16U,
 324       Asse_QADD8S, Asse_QADD16S,
 325       Asse_SUB8, Asse_SUB16, Asse_SUB32, Asse_SUB64,
 326       Asse_QSUB8U, Asse_QSUB16U,
 327       Asse_QSUB8S, Asse_QSUB16S,
 328       Asse_MUL16,
 329       Asse_MULHI16U,
 330       Asse_MULHI16S,
 331       Asse_AVG8U, Asse_AVG16U,
 332       Asse_MAX16S,
 333       Asse_MAX8U,
 334       Asse_MIN16S,
 335       Asse_MIN8U,
 336       Asse_CMPEQ8, Asse_CMPEQ16, Asse_CMPEQ32,
 337       Asse_CMPGT8S, Asse_CMPGT16S, Asse_CMPGT32S,
 338       Asse_SHL16, Asse_SHL32, Asse_SHL64, Asse_SHL128,
 339       Asse_SHR16, Asse_SHR32, Asse_SHR64, Asse_SHR128,
 340       Asse_SAR16, Asse_SAR32,
 341       Asse_PACKSSD, Asse_PACKSSW, Asse_PACKUSW,
 342       Asse_UNPCKHB, Asse_UNPCKHW, Asse_UNPCKHD, Asse_UNPCKHQ,
 343       Asse_UNPCKLB, Asse_UNPCKLW, Asse_UNPCKLD, Asse_UNPCKLQ,
 344       // Only for SSSE3 capable hosts:
 345       Asse_PSHUFB,
 346       Asse_PMADDUBSW,
 347       // Only for F16C capable hosts:
 348       Asse_F32toF16, // F32 to F16 conversion, aka vcvtps2ph
 349       Asse_F16toF32, // F16 to F32 conversion, aka vcvtph2ps
 350    }
 351    AMD64SseOp;
 352
 353 extern const HChar* showAMD64SseOp ( AMD64SseOp );
 354
 355
 356 /* --------- */
 357 typedef
 358    enum {
 359       Ain_Imm64,       /* Generate 64-bit literal to register */
 360       Ain_Alu64R,      /* 64-bit mov/arith/logical, dst=REG */
 361       Ain_Alu64M,      /* 64-bit mov/arith/logical, dst=MEM */
 362       Ain_Sh64,        /* 64-bit shift, dst=REG */
 363       Ain_Sh32,        /* 32-bit shift, dst=REG */
 364       Ain_Test64,      /* 64-bit test (AND, set flags, discard result) */
 365       Ain_Unary64,     /* 64-bit not and neg */
 366       Ain_Lea64,       /* 64-bit compute EA into a reg */
 367       Ain_Alu32R,      /* 32-bit add/sub/and/or/xor/cmp, dst=REG (a la Alu64R) */
 368       Ain_MulL,        /* widening multiply */
 369       Ain_Div,         /* div and mod */
 370       Ain_Push,        /* push 64-bit value on stack */
 371       Ain_Call,        /* call to address in register */
 372       Ain_XDirect,     /* direct transfer to GA */
 373       Ain_XIndir,      /* indirect transfer to GA */
 374       Ain_XAssisted,   /* assisted transfer to GA */
 375       Ain_CMov64,      /* conditional move, 64-bit reg-reg only */
 376       Ain_CLoad,       /* cond. load to int reg, 32 bit ZX or 64 bit only */
 377       Ain_CStore,      /* cond. store from int reg, 32 or 64 bit only */
 378       Ain_MovxLQ,      /* reg-reg move, zx-ing/sx-ing top half */
 379       Ain_LoadEX,      /* mov{s,z}{b,w,l}q from mem to reg */
 380       Ain_Store,       /* store 32/16/8 bit value in memory */
 381       Ain_Set64,       /* convert condition code to 64-bit value */
 382       Ain_Bsfr64,      /* 64-bit bsf/bsr */
 383       Ain_MFence,      /* mem fence */
 384       Ain_ACAS,        /* 8/16/32/64-bit lock;cmpxchg */
 385       Ain_DACAS,       /* lock;cmpxchg8b/16b (doubleword ACAS, 2 x
 386                           32-bit or 2 x 64-bit only) */
 387       Ain_A87Free,     /* free up x87 registers */
 388       Ain_A87PushPop,  /* x87 loads/stores */
 389       Ain_A87FpOp,     /* x87 operations */
 390       Ain_A87LdCW,     /* load x87 control word */
 391       Ain_A87StSW,     /* store x87 status word */
 392       Ain_LdMXCSR,     /* load %mxcsr */
 393       Ain_SseUComIS,   /* ucomisd/ucomiss, then get %rflags into int
 394                           register */
 395       Ain_SseSI2SF,    /* scalar 32/64 int to 32/64 float conversion */
 396       Ain_SseSF2SI,    /* scalar 32/64 float to 32/64 int conversion */
 397       Ain_SseSDSS,     /* scalar float32 to/from float64 */
 398       Ain_SseLdSt,     /* SSE load/store 32/64/128 bits, no alignment
 399                           constraints, upper 96/64/0 bits arbitrary */
 400       Ain_SseCStore,   /* SSE conditional store, 128 bit only, any alignment */
 401       Ain_SseCLoad,    /* SSE conditional load, 128 bit only, any alignment */
 402       Ain_SseLdzLO,    /* SSE load low 32/64 bits, zero remainder of reg */
 403       Ain_Sse32Fx4,    /* SSE binary, 32Fx4 */
 404       Ain_Sse32FLo,    /* SSE binary, 32F in lowest lane only */
 405       Ain_Sse64Fx2,    /* SSE binary, 64Fx2 */
 406       Ain_Sse64FLo,    /* SSE binary, 64F in lowest lane only */
 407       Ain_SseReRg,     /* SSE binary general reg-reg, Re, Rg */
 408       Ain_SseCMov,     /* SSE conditional move */
 409       Ain_SseShuf,     /* SSE2 shuffle (pshufd) */
 410       Ain_SseShiftN,   /* SSE2 shift by immediate */
 411       Ain_SseMOVQ,     /* SSE2 moves of xmm[63:0] to/from GPR */
 412       //uu Ain_AvxLdSt,     /* AVX load/store 256 bits,
 413       //uu                     no alignment constraints */
 414       //uu Ain_AvxReRg,     /* AVX binary general reg-reg, Re, Rg */
 415       Ain_EvCheck,     /* Event check */
 416       Ain_ProfInc      /* 64-bit profile counter increment */
 417    }
 418    AMD64InstrTag;
 419
 420 /* Destinations are on the RIGHT (second operand) */
 421
 422 typedef
 423    struct {
 424       AMD64InstrTag tag;
 425       union {
 426          struct {
 427             ULong imm64;
 428             HReg  dst;
 429          } Imm64;
 430          struct {
 431             AMD64AluOp op;
 432             AMD64RMI*  src;
 433             HReg       dst;
 434          } Alu64R;
 435          struct {
 436             AMD64AluOp  op;
 437             AMD64RI*    src;
 438             AMD64AMode* dst;
 439          } Alu64M;
 440          struct {
 441             AMD64ShiftOp op;
 442             UInt         src;  /* shift amount, or 0 means %cl */
 443             HReg         dst;
 444          } Sh64;
 445          struct {
 446             AMD64ShiftOp op;
 447             UInt         src;  /* shift amount, or 0 means %cl */
 448             HReg         dst;
 449          } Sh32;
 450          struct {
 451             UInt   imm32;
 452             HReg   dst;
 453          } Test64;
 454          /* Not and Neg */
 455          struct {
 456             AMD64UnaryOp op;
 457             HReg         dst;
 458          } Unary64;
 459          /* 64-bit compute EA into a reg */
 460          struct {
 461             AMD64AMode* am;
 462             HReg        dst;
 463          } Lea64;
 464          /* 32-bit add/sub/and/or/xor/cmp, dst=REG (a la Alu64R) */
 465          struct {
 466             AMD64AluOp op;
 467             AMD64RMI*  src;
 468             HReg       dst;
 469          } Alu32R;
 470          /* 64 x 64 -> 128 bit widening multiply: RDX:RAX = RAX *s/u
 471             r/m64 */
 472          struct {
 473             Bool     syned;
 474             AMD64RM* src;
 475          } MulL;
 476           /* amd64 div/idiv instruction.  Modifies RDX and RAX and
 477              reads src. */
 478          struct {
 479             Bool     syned;
 480             Int      sz; /* 4 or 8 only */
 481             AMD64RM* src;
 482          } Div;
 483          struct {
 484             AMD64RMI* src;
 485          } Push;
 486          /* Pseudo-insn.  Call target (an absolute address), on given
 487             condition (which could be Xcc_ALWAYS). */
 488          struct {
 489             AMD64CondCode cond;
 490             Addr64        target;
 491             Int           regparms; /* 0 .. 6 */
 492             RetLoc        rloc;     /* where the return value will be */
 493          } Call;
 494          /* Update the guest RIP value, then exit requesting to chain
 495             to it.  May be conditional. */
 496          struct {
 497             Addr64        dstGA;    /* next guest address */
 498             AMD64AMode*   amRIP;    /* amode in guest state for RIP */
 499             AMD64CondCode cond;     /* can be Acc_ALWAYS */
 500             Bool          toFastEP; /* chain to the slow or fast point? */
 501          } XDirect;
 502          /* Boring transfer to a guest address not known at JIT time.
 503             Not chainable.  May be conditional. */
 504          struct {
 505             HReg          dstGA;
 506             AMD64AMode*   amRIP;
 507             AMD64CondCode cond; /* can be Acc_ALWAYS */
 508          } XIndir;
 509          /* Assisted transfer to a guest address, most general case.
 510             Not chainable.  May be conditional. */
 511          struct {
 512             HReg          dstGA;
 513             AMD64AMode*   amRIP;
 514             AMD64CondCode cond; /* can be Acc_ALWAYS */
 515             IRJumpKind    jk;
 516          } XAssisted;
 517          /* Mov src to dst on the given condition, which may not
 518             be the bogus Acc_ALWAYS. */
 519          struct {
 520             AMD64CondCode cond;
 521             HReg          src;
 522             HReg          dst;
 523          } CMov64;
 524          /* conditional load to int reg, 32 bit ZX or 64 bit only.
 525             cond may not be Acc_ALWAYS. */
 526          struct {
 527             AMD64CondCode cond;
 528             UChar         szB; /* 4 or 8 only */
 529             AMD64AMode*   addr;
 530             HReg          dst;
 531          } CLoad;
 532          /* cond. store from int reg, 32 or 64 bit only.
 533             cond may not be Acc_ALWAYS. */
 534          struct {
 535             AMD64CondCode cond;
 536             UChar         szB; /* 4 or 8 only */
 537             HReg          src;
 538             AMD64AMode*   addr;
 539          } CStore;
 540          /* reg-reg move, sx-ing/zx-ing top half */
 541          struct {
 542             Bool syned;
 543             HReg src;
 544             HReg dst;
 545          } MovxLQ;
 546          /* Sign/Zero extending loads.  Dst size is always 64 bits. */
 547          struct {
 548             UChar       szSmall; /* only 1, 2 or 4 */
 549             Bool        syned;
 550             AMD64AMode* src;
 551             HReg        dst;
 552          } LoadEX;
 553          /* 32/16/8 bit stores. */
 554          struct {
 555             UChar       sz; /* only 1, 2 or 4 */
 556             HReg        src;
 557             AMD64AMode* dst;
 558          } Store;
 559          /* Convert an amd64 condition code to a 64-bit value (0 or 1). */
 560          struct {
 561             AMD64CondCode cond;
 562             HReg          dst;
 563          } Set64;
 564          /* 64-bit bsf or bsr. */
 565          struct {
 566             Bool isFwds;
 567             HReg src;
 568             HReg dst;
 569          } Bsfr64;
 570          /* Mem fence.  In short, an insn which flushes all preceding
 571             loads and stores as much as possible before continuing.
 572             On AMD64 we emit a real "mfence". */
 573          struct {
 574          } MFence;
 575          struct {
 576             AMD64AMode* addr;
 577             UChar       sz; /* 1, 2, 4 or 8 */
 578          } ACAS;
 579          struct {
 580             AMD64AMode* addr;
 581             UChar       sz; /* 4 or 8 only */
 582          } DACAS;
 583
 584          /* --- X87 --- */
 585
 586          /* A very minimal set of x87 insns, that operate exactly in a
 587             stack-like way so no need to think about x87 registers. */
 588
 589          /* Do 'ffree' on %st(7) .. %st(7-nregs) */
 590          struct {
 591             Int nregs; /* 1 <= nregs <= 7 */
 592          } A87Free;
 593
 594          /* Push a 32- or 64-bit FP value from memory onto the stack,
 595             or move a value from the stack to memory and remove it
 596             from the stack. */
 597          struct {
 598             AMD64AMode* addr;
 599             Bool        isPush;
 600             UChar       szB; /* 4 or 8 */
 601          } A87PushPop;
 602
 603          /* Do an operation on the top-of-stack.  This can be unary, in
 604             which case it is %st0 = OP( %st0 ), or binary: %st0 = OP(
 605             %st0, %st1 ). */
 606          struct {
 607             A87FpOp op;
 608          } A87FpOp;
 609
 610          /* Load the FPU control word. */
 611          struct {
 612             AMD64AMode* addr;
 613          } A87LdCW;
 614
 615          /* Store the FPU status word (fstsw m16) */
 616          struct {
 617             AMD64AMode* addr;
 618          } A87StSW;
 619
 620          /* --- SSE --- */
 621
 622          /* Load 32 bits into %mxcsr. */
 623          struct {
 624             AMD64AMode* addr;
 625          }
 626          LdMXCSR;
 627          /* ucomisd/ucomiss, then get %rflags into int register */
 628          struct {
 629             UChar   sz;   /* 4 or 8 only */
 630             HReg    srcL; /* xmm */
 631             HReg    srcR; /* xmm */
 632             HReg    dst;  /* int */
 633          } SseUComIS;
 634          /* scalar 32/64 int to 32/64 float conversion */
 635          struct {
 636             UChar szS; /* 4 or 8 */
 637             UChar szD; /* 4 or 8 */
 638             HReg  src; /* i class */
 639             HReg  dst; /* v class */
 640          } SseSI2SF;
 641          /* scalar 32/64 float to 32/64 int conversion */
 642          struct {
 643             UChar szS; /* 4 or 8 */
 644             UChar szD; /* 4 or 8 */
 645             HReg  src; /* v class */
 646             HReg  dst; /* i class */
 647          } SseSF2SI;
 648          /* scalar float32 to/from float64 */
 649          struct {
 650             Bool from64; /* True: 64->32; False: 32->64 */
 651             HReg src;
 652             HReg dst;
 653          } SseSDSS;
 654          struct {
 655             Bool        isLoad;
 656             UChar       sz; /* 4, 8 or 16 only */
 657             HReg        reg;
 658             AMD64AMode* addr;
 659          } SseLdSt;
 660          struct {
 661             AMD64CondCode cond; /* may not be Acc_ALWAYS */
 662             HReg          src;
 663             AMD64AMode*   addr;
 664          } SseCStore;
 665          struct {
 666             AMD64CondCode cond; /* may not be Acc_ALWAYS */
 667             AMD64AMode*   addr;
 668             HReg          dst;
 669          } SseCLoad;
 670          struct {
 671             Int         sz; /* 4 or 8 only */
 672             HReg        reg;
 673             AMD64AMode* addr;
 674          } SseLdzLO;
 675          struct {
 676             AMD64SseOp op;
 677             HReg       src;
 678             HReg       dst;
 679          } Sse32Fx4;
 680          struct {
 681             AMD64SseOp op;
 682             HReg       src;
 683             HReg       dst;
 684          } Sse32FLo;
 685          struct {
 686             AMD64SseOp op;
 687             HReg       src;
 688             HReg       dst;
 689          } Sse64Fx2;
 690          struct {
 691             AMD64SseOp op;
 692             HReg       src;
 693             HReg       dst;
 694          } Sse64FLo;
 695          struct {
 696             AMD64SseOp op;
 697             HReg       src;
 698             HReg       dst;
 699          } SseReRg;
 700          /* Mov src to dst on the given condition, which may not
 701             be the bogus Xcc_ALWAYS. */
 702          struct {
 703             AMD64CondCode cond;
 704             HReg          src;
 705             HReg          dst;
 706          } SseCMov;
 707          struct {
 708             Int    order; /* 0 <= order <= 0xFF */
 709             HReg   src;
 710             HReg   dst;
 711          } SseShuf;
 712          struct {
 713             AMD64SseOp op;
 714             UInt       shiftBits;
 715             HReg       dst;
 716          } SseShiftN;
 717          struct {
 718             HReg gpr;
 719             HReg xmm;
 720             Bool toXMM; // when moving to xmm, xmm[127:64] is zeroed out
 721          } SseMOVQ;
 722          //uu struct {
 723          //uu    Bool        isLoad;
 724          //uu    HReg        reg;
 725          //uu    AMD64AMode* addr;
 726          //uu } AvxLdSt;
 727          //uu struct {
 728          //uu    AMD64SseOp op;
 729          //uu    HReg       src;
 730          //uu    HReg       dst;
 731          //uu } AvxReRg;
 732          struct {
 733             AMD64AMode* amCounter;
 734             AMD64AMode* amFailAddr;
 735          } EvCheck;
 736          struct {
 737             /* No fields.  The address of the counter to inc is
 738                installed later, post-translation, by patching it in,
 739                as it is not known at translation time. */
 740          } ProfInc;
 741
 742       } Ain;
 743    }
 744    AMD64Instr;
 745
 746 extern AMD64Instr* AMD64Instr_Imm64      ( ULong imm64, HReg dst );
 747 extern AMD64Instr* AMD64Instr_Alu64R     ( AMD64AluOp, AMD64RMI*, HReg );
 748 extern AMD64Instr* AMD64Instr_Alu64M     ( AMD64AluOp, AMD64RI*,  AMD64AMode* );
 749 extern AMD64Instr* AMD64Instr_Unary64    ( AMD64UnaryOp op, HReg dst );
 750 extern AMD64Instr* AMD64Instr_Lea64      ( AMD64AMode* am, HReg dst );
 751 extern AMD64Instr* AMD64Instr_Alu32R     ( AMD64AluOp, AMD64RMI*, HReg );
 752 extern AMD64Instr* AMD64Instr_Sh64       ( AMD64ShiftOp, UInt, HReg );
 753 extern AMD64Instr* AMD64Instr_Sh32       ( AMD64ShiftOp, UInt, HReg );
 754 extern AMD64Instr* AMD64Instr_Test64     ( UInt imm32, HReg dst );
 755 extern AMD64Instr* AMD64Instr_MulL       ( Bool syned, AMD64RM* );
 756 extern AMD64Instr* AMD64Instr_Div        ( Bool syned, Int sz, AMD64RM* );
 757 extern AMD64Instr* AMD64Instr_Push       ( AMD64RMI* );
 758 extern AMD64Instr* AMD64Instr_Call       ( AMD64CondCode, Addr64, Int, RetLoc );
 759 extern AMD64Instr* AMD64Instr_XDirect    ( Addr64 dstGA, AMD64AMode* amRIP,
 760                                            AMD64CondCode cond, Bool toFastEP );
 761 extern AMD64Instr* AMD64Instr_XIndir     ( HReg dstGA, AMD64AMode* amRIP,
 762                                            AMD64CondCode cond );
 763 extern AMD64Instr* AMD64Instr_XAssisted  ( HReg dstGA, AMD64AMode* amRIP,
 764                                            AMD64CondCode cond, IRJumpKind jk );
 765 extern AMD64Instr* AMD64Instr_CMov64     ( AMD64CondCode, HReg src, HReg dst );
 766 extern AMD64Instr* AMD64Instr_CLoad      ( AMD64CondCode cond, UChar szB,
 767                                            AMD64AMode* addr, HReg dst );
 768 extern AMD64Instr* AMD64Instr_CStore     ( AMD64CondCode cond, UChar szB,
 769                                            HReg src, AMD64AMode* addr );
 770 extern AMD64Instr* AMD64Instr_MovxLQ     ( Bool syned, HReg src, HReg dst );
 771 extern AMD64Instr* AMD64Instr_LoadEX     ( UChar szSmall, Bool syned,
 772                                            AMD64AMode* src, HReg dst );
 773 extern AMD64Instr* AMD64Instr_Store      ( UChar sz, HReg src, AMD64AMode* dst );
 774 extern AMD64Instr* AMD64Instr_Set64      ( AMD64CondCode cond, HReg dst );
 775 extern AMD64Instr* AMD64Instr_Bsfr64     ( Bool isFwds, HReg src, HReg dst );
 776 extern AMD64Instr* AMD64Instr_MFence     ( void );
 777 extern AMD64Instr* AMD64Instr_ACAS       ( AMD64AMode* addr, UChar sz );
 778 extern AMD64Instr* AMD64Instr_DACAS      ( AMD64AMode* addr, UChar sz );
 779
 780 extern AMD64Instr* AMD64Instr_A87Free    ( Int nregs );
 781 extern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB );
 782 extern AMD64Instr* AMD64Instr_A87FpOp    ( A87FpOp op );
 783 extern AMD64Instr* AMD64Instr_A87LdCW    ( AMD64AMode* addr );
 784 extern AMD64Instr* AMD64Instr_A87StSW    ( AMD64AMode* addr );
 785 extern AMD64Instr* AMD64Instr_LdMXCSR    ( AMD64AMode* );
 786 extern AMD64Instr* AMD64Instr_SseUComIS  ( Int sz, HReg srcL, HReg srcR, HReg dst );
 787 extern AMD64Instr* AMD64Instr_SseSI2SF   ( Int szS, Int szD, HReg src, HReg dst );
 788 extern AMD64Instr* AMD64Instr_SseSF2SI   ( Int szS, Int szD, HReg src, HReg dst );
 789 extern AMD64Instr* AMD64Instr_SseSDSS    ( Bool from64, HReg src, HReg dst );
 790 extern AMD64Instr* AMD64Instr_SseLdSt    ( Bool isLoad, Int sz, HReg, AMD64AMode* );
 791 extern AMD64Instr* AMD64Instr_SseCStore  ( AMD64CondCode, HReg, AMD64AMode* );
 792 extern AMD64Instr* AMD64Instr_SseCLoad   ( AMD64CondCode, AMD64AMode*, HReg );
 793 extern AMD64Instr* AMD64Instr_SseLdzLO   ( Int sz, HReg, AMD64AMode* );
 794 extern AMD64Instr* AMD64Instr_Sse32Fx4   ( AMD64SseOp, HReg, HReg );
 795 extern AMD64Instr* AMD64Instr_Sse32FLo   ( AMD64SseOp, HReg, HReg );
 796 extern AMD64Instr* AMD64Instr_Sse64Fx2   ( AMD64SseOp, HReg, HReg );
 797 extern AMD64Instr* AMD64Instr_Sse64FLo   ( AMD64SseOp, HReg, HReg );
 798 extern AMD64Instr* AMD64Instr_SseReRg    ( AMD64SseOp, HReg, HReg );
 799 extern AMD64Instr* AMD64Instr_SseCMov    ( AMD64CondCode, HReg src, HReg dst );
 800 extern AMD64Instr* AMD64Instr_SseShuf    ( Int order, HReg src, HReg dst );
 801 extern AMD64Instr* AMD64Instr_SseShiftN  ( AMD64SseOp,
 802                                            UInt shiftBits, HReg dst );
 803 extern AMD64Instr* AMD64Instr_SseMOVQ    ( HReg gpr, HReg xmm, Bool toXMM );
 804 //uu extern AMD64Instr* AMD64Instr_AvxLdSt    ( Bool isLoad, HReg, AMD64AMode* );
 805 //uu extern AMD64Instr* AMD64Instr_AvxReRg    ( AMD64SseOp, HReg, HReg );
 806 extern AMD64Instr* AMD64Instr_EvCheck    ( AMD64AMode* amCounter,
 807                                            AMD64AMode* amFailAddr );
 808 extern AMD64Instr* AMD64Instr_ProfInc    ( void );
 809
 810
 811 extern void ppAMD64Instr ( const AMD64Instr*, Bool );
 812
 813 /* Some functions that insulate the register allocator from details
 814    of the underlying instruction set. */
 815 extern void getRegUsage_AMD64Instr ( HRegUsage*, const AMD64Instr*, Bool );
 816 extern void mapRegs_AMD64Instr     ( HRegRemap*, AMD64Instr*, Bool );
 817 extern Int          emit_AMD64Instr   ( /*MB_MOD*/Bool* is_profInc,
 818                                         UChar* buf, Int nbuf,
 819                                         const AMD64Instr* i,
 820                                         Bool mode64,
 821                                         VexEndness endness_host,
 822                                         const void* disp_cp_chain_me_to_slowEP,
 823                                         const void* disp_cp_chain_me_to_fastEP,
 824                                         const void* disp_cp_xindir,
 825                                         const void* disp_cp_xassisted );
 826
 827 extern void genSpill_AMD64  ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
 828                               HReg rreg, Int offset, Bool );
 829 extern void genReload_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
 830                               HReg rreg, Int offset, Bool );
 831 extern AMD64Instr* genMove_AMD64(HReg from, HReg to, Bool);
 832 extern AMD64Instr* directReload_AMD64 ( AMD64Instr* i,
 833                                         HReg vreg, Short spill_off );
 834
 835 extern const RRegUniverse* getRRegUniverse_AMD64 ( void );
 836
 837 extern HInstrArray* iselSB_AMD64           ( const IRSB*,
 838                                              VexArch,
 839                                              const VexArchInfo*,
 840                                              const VexAbiInfo*,
 841                                              Int offs_Host_EvC_Counter,
 842                                              Int offs_Host_EvC_FailAddr,
 843                                              Bool chainingAllowed,
 844                                              Bool addProfInc,
 845                                              Addr max_ga );
 846
 847 /* How big is an event check?  This is kind of a kludge because it
 848    depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER,
 849    and so assumes that they are both <= 128, and so can use the short
 850    offset encoding.  This is all checked with assertions, so in the
 851    worst case we will merely assert at startup. */
 852 extern Int evCheckSzB_AMD64 (void);
 853
 854 /* Perform a chaining and unchaining of an XDirect jump. */
 855 extern VexInvalRange chainXDirect_AMD64 ( VexEndness endness_host,
 856                                           void* place_to_chain,
 857                                           const void* disp_cp_chain_me_EXPECTED,
 858                                           const void* place_to_jump_to );
 859
 860 extern VexInvalRange unchainXDirect_AMD64 ( VexEndness endness_host,
 861                                             void* place_to_unchain,
 862                                             const void* place_to_jump_to_EXPECTED,
 863                                             const void* disp_cp_chain_me );
 864
 865 /* Patch the counter location into an existing ProfInc point. */
 866 extern VexInvalRange patchProfInc_AMD64 ( VexEndness endness_host,
 867                                           void*  place_to_patch,
 868                                           const ULong* location_of_counter );
 869
 870
 871 #endif /* ndef __VEX_HOST_AMD64_DEFS_H */
 872
 873 /*---------------------------------------------------------------*/
 874 /*--- end                                   host_amd64_defs.h ---*/
 875 /*---------------------------------------------------------------*/