coregrind/m_gdbserver/valgrind-low-nanomips.c

   1 /* Low level interface to valgrind, for the remote server for GDB integrated
   2    in valgrind.
   3    Copyright (C) 2012
   4    Free Software Foundation, Inc.
   5
   6    This file is part of VALGRIND.
   7    It has been inspired from a file from gdbserver in gdb 6.6.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 51 Franklin Street, Fifth Floor,
  22    Boston, MA 02110-1301, USA.  */
  23
  24 #include "server.h"
  25 #include "target.h"
  26 #include "regdef.h"
  27 #include "regcache.h"
  28
  29 #include "pub_core_machine.h"
  30 #include "pub_core_debuginfo.h"
  31 #include "pub_core_threadstate.h"
  32 #include "pub_core_transtab.h"
  33 #include "pub_core_gdbserver.h"
  34
  35 #include "valgrind_low.h"
  36
  37 #include "libvex_guest_mips32.h"
  38
  39 static struct reg regs[] = {
  40   { "r0", 0, 32 },
  41   { "r1", 32, 32 },
  42   { "r2", 64, 32 },
  43   { "r3", 96, 32 },
  44   { "r4", 128, 32 },
  45   { "r5", 160, 32 },
  46   { "r6", 192, 32 },
  47   { "r7", 224, 32 },
  48   { "r8", 256, 32 },
  49   { "r9", 288, 32 },
  50   { "r10", 320, 32 },
  51   { "r11", 352, 32 },
  52   { "r12", 384, 32 },
  53   { "r13", 416, 32 },
  54   { "r14", 448, 32 },
  55   { "r15", 480, 32 },
  56   { "r16", 512, 32 },
  57   { "r17", 544, 32 },
  58   { "r18", 576, 32 },
  59   { "r19", 608, 32 },
  60   { "r20", 640, 32 },
  61   { "r21", 672, 32 },
  62   { "r22", 704, 32 },
  63   { "r23", 736, 32 },
  64   { "r24", 768, 32 },
  65   { "r25", 800, 32 },
  66   { "r26", 832, 32 },
  67   { "r27", 864, 32 },
  68   { "r28", 896, 32 },
  69   { "r29", 928, 32 },
  70   { "r30", 960, 32 },
  71   { "r31", 992, 32 },
  72   { "status", 1024, 32 },
  73   { "badvaddr", 1120, 32 },
  74   { "cause", 1152, 32 },
  75   { "pc", 1184, 32 },
  76 };
  77
  78 #define num_regs (sizeof (regs) / sizeof (regs[0]))
  79
  80 static const char *expedite_regs[] = { "r29", "pc", 0 };
  81
  82 static
  83 CORE_ADDR get_pc (void)
  84 {
  85    unsigned long pc;
  86
  87    collect_register_by_name ("pc", &pc);
  88
  89    dlog(1, "stop pc is %p\n", (void *) pc);
  90    return pc;
  91 }
  92
  93 static
  94 void set_pc (CORE_ADDR newpc)
  95 {
  96    supply_register_by_name ("pc", &newpc);
  97 }
  98
  99 /* These are the fields of 32 bit mips instructions. */
 100 #define itype_op(x) (x >> 26)
 101 #define itype_rs(x) ((x >> 21) & 0x1f)
 102 #define itype_rt(x) ((x >> 16) & 0x1f)
 103 #define rtype_funct(x) (x & 0x3f)
 104
 105 static inline UInt getUInt(UChar * p) __attribute__((unused));
 106 /* Do a endian load of a 32-bit word, regardless of the
 107    endianness of the underlying host. */
 108 static inline UInt getUInt(UChar * p)
 109 {
 110    UInt w = 0;
 111 #if defined (_MIPSEL)
 112    w = (w << 8) | p[3];
 113    w = (w << 8) | p[2];
 114    w = (w << 8) | p[1];
 115    w = (w << 8) | p[0];
 116 #elif defined (_MIPSEB)
 117    w = (w << 8) | p[0];
 118    w = (w << 8) | p[1];
 119    w = (w << 8) | p[2];
 120    w = (w << 8) | p[3];
 121 #endif
 122    return w;
 123 }
 124
 125 /* store registers in the guest state (gdbserver_to_valgrind)
 126    or fetch register from the guest state (valgrind_to_gdbserver). */
 127 static
 128 void transfer_register (ThreadId tid, int abs_regno, void * buf,
 129                         transfer_direction dir, int size, Bool *mod)
 130 {
 131    ThreadState* tst = VG_(get_ThreadState)(tid);
 132    int set = abs_regno / num_regs;
 133    int regno = abs_regno % num_regs;
 134    *mod = False;
 135
 136    VexGuestMIPS32State* mips1 = (VexGuestMIPS32State*) get_arch (set, tst);
 137
 138    switch (regno) {
 139    case 0:  VG_(transfer) (&mips1->guest_r0,  buf, dir, size, mod); break;
 140    case 1:  VG_(transfer) (&mips1->guest_r1,  buf, dir, size, mod); break;
 141    case 2:  VG_(transfer) (&mips1->guest_r2,  buf, dir, size, mod); break;
 142    case 3:  VG_(transfer) (&mips1->guest_r3,  buf, dir, size, mod); break;
 143    case 4:  VG_(transfer) (&mips1->guest_r4,  buf, dir, size, mod); break;
 144    case 5:  VG_(transfer) (&mips1->guest_r5,  buf, dir, size, mod); break;
 145    case 6:  VG_(transfer) (&mips1->guest_r6,  buf, dir, size, mod); break;
 146    case 7:  VG_(transfer) (&mips1->guest_r7,  buf, dir, size, mod); break;
 147    case 8:  VG_(transfer) (&mips1->guest_r8,  buf, dir, size, mod); break;
 148    case 9:  VG_(transfer) (&mips1->guest_r9,  buf, dir, size, mod); break;
 149    case 10: VG_(transfer) (&mips1->guest_r10,  buf, dir, size, mod); break;
 150    case 11: VG_(transfer) (&mips1->guest_r11,  buf, dir, size, mod); break;
 151    case 12: VG_(transfer) (&mips1->guest_r12, buf, dir, size, mod); break;
 152    case 13: VG_(transfer) (&mips1->guest_r13, buf, dir, size, mod); break;
 153    case 14: VG_(transfer) (&mips1->guest_r14, buf, dir, size, mod); break;
 154    case 15: VG_(transfer) (&mips1->guest_r15, buf, dir, size, mod); break;
 155    case 16: VG_(transfer) (&mips1->guest_r16, buf, dir, size, mod); break;
 156    case 17: VG_(transfer) (&mips1->guest_r17, buf, dir, size, mod); break;
 157    case 18: VG_(transfer) (&mips1->guest_r18,  buf, dir, size, mod); break;
 158    case 19: VG_(transfer) (&mips1->guest_r19,  buf, dir, size, mod); break;
 159    case 20: VG_(transfer) (&mips1->guest_r20,  buf, dir, size, mod); break;
 160    case 21: VG_(transfer) (&mips1->guest_r21,  buf, dir, size, mod); break;
 161    case 22: VG_(transfer) (&mips1->guest_r22,  buf, dir, size, mod); break;
 162    case 23: VG_(transfer) (&mips1->guest_r23,  buf, dir, size, mod); break;
 163    case 24: VG_(transfer) (&mips1->guest_r24,  buf, dir, size, mod); break;
 164    case 25: VG_(transfer) (&mips1->guest_r25,  buf, dir, size, mod); break;
 165    case 26: VG_(transfer) (&mips1->guest_r26,  buf, dir, size, mod); break;
 166    case 27: VG_(transfer) (&mips1->guest_r27,  buf, dir, size, mod); break;
 167    case 28: VG_(transfer) (&mips1->guest_r28, buf, dir, size, mod); break;
 168    case 29: VG_(transfer) (&mips1->guest_r29, buf, dir, size, mod); break;
 169    case 30: VG_(transfer) (&mips1->guest_r30, buf, dir, size, mod); break;
 170    case 31: VG_(transfer) (&mips1->guest_r31, buf, dir, size, mod); break;
 171    case 32: *mod = False; break; // GDBTD???? VEX { "status", 1024, 32 },
 172    case 33: VG_(transfer) (&mips1->guest_LO, buf, dir, size, mod); break;
 173    case 34: VG_(transfer) (&mips1->guest_HI, buf, dir, size, mod); break;
 174    case 35: *mod = False; break; // GDBTD???? VEX { "badvaddr", 1120, 32 },
 175    case 36: *mod = False; break; // GDBTD???? VEX { "cause", 1152, 32 },
 176    case 37: VG_(transfer) (&mips1->guest_PC,  buf, dir, size, mod); break;
 177    case 72: *mod = False; break; // GDBTD???? VEX{ "restart", 2304, 32 },
 178    default: VG_(printf)("regno: %d\n", regno); vg_assert(0);
 179    }
 180 }
 181
 182 static
 183 const char* target_xml (Bool shadow_mode)
 184 {
 185    if (shadow_mode) {
 186       return "mips-linux-valgrind.xml";
 187    } else {
 188       return "mips-linux.xml";
 189    }
 190 }
 191
 192 static CORE_ADDR** target_get_dtv (ThreadState *tst)
 193 {
 194    VexGuestMIPS32State* mips32 = (VexGuestMIPS32State*)&tst->arch.vex;
 195    // Top of nanoMIPS tcbhead structure is located 0x7000 bytes before the value
 196    // of ULR. Dtv is the first of two pointers in tcbhead structure.
 197    return (CORE_ADDR**)((CORE_ADDR)mips32->guest_ULR
 198                         - 0x7000 - 2 * sizeof(CORE_ADDR));
 199 }
 200
 201 static struct valgrind_target_ops low_target = {
 202    num_regs,
 203    29, //sp = r29, which is register offset 29 in regs
 204    regs,
 205    transfer_register,
 206    get_pc,
 207    set_pc,
 208    "mips",
 209    target_xml,
 210    target_get_dtv
 211 };
 212
 213 void nanomips_init_architecture (struct valgrind_target_ops *target)
 214 {
 215    *target = low_target;
 216    set_register_cache (regs, num_regs);
 217    gdbserver_expedite_regs = expedite_regs;
 218 }