coregrind/m_gdbserver/valgrind-low-arm.c

   1 /* Low level interface to valgrind, for the remote server for GDB integrated
   2    in valgrind.
   3    Copyright (C) 2011
   4    Free Software Foundation, Inc.
   5
   6    This file is part of VALGRIND.
   7    It has been inspired from a file from gdbserver in gdb 6.6.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 51 Franklin Street, Fifth Floor,
  22    Boston, MA 02110-1301, USA.  */
  23
  24 #include "server.h"
  25 #include "target.h"
  26 #include "regdef.h"
  27 #include "regcache.h"
  28
  29 #include "pub_core_machine.h"
  30 #include "pub_core_threadstate.h"
  31 #include "pub_core_transtab.h"
  32 #include "pub_core_gdbserver.h"
  33 #include "pub_core_debuginfo.h"
  34
  35 #include "valgrind_low.h"
  36
  37 #include "libvex_guest_arm.h"
  38
  39 static struct reg regs[] = {
  40   { "r0", 0, 32 },
  41   { "r1", 32, 32 },
  42   { "r2", 64, 32 },
  43   { "r3", 96, 32 },
  44   { "r4", 128, 32 },
  45   { "r5", 160, 32 },
  46   { "r6", 192, 32 },
  47   { "r7", 224, 32 },
  48   { "r8", 256, 32 },
  49   { "r9", 288, 32 },
  50   { "r10", 320, 32 },
  51   { "r11", 352, 32 },
  52   { "r12", 384, 32 },
  53   { "sp", 416, 32 },
  54   { "lr", 448, 32 },
  55   { "pc", 480, 32 },
  56   { "", 512, 0 }, // It seems these entries are needed
  57   { "", 512, 0 }, // as previous versions of arm <-> gdb placed
  58   { "", 512, 0 }, // some floating point registers here. So, cpsr
  59   { "", 512, 0 }, // must be register 25.
  60   { "", 512, 0 },
  61   { "", 512, 0 },
  62   { "", 512, 0 },
  63   { "", 512, 0 },
  64   { "", 512, 0 },
  65   { "cpsr", 512, 32 },
  66   { "d0", 544, 64 },
  67   { "d1", 608, 64 },
  68   { "d2", 672, 64 },
  69   { "d3", 736, 64 },
  70   { "d4", 800, 64 },
  71   { "d5", 864, 64 },
  72   { "d6", 928, 64 },
  73   { "d7", 992, 64 },
  74   { "d8", 1056, 64 },
  75   { "d9", 1120, 64 },
  76   { "d10", 1184, 64 },
  77   { "d11", 1248, 64 },
  78   { "d12", 1312, 64 },
  79   { "d13", 1376, 64 },
  80   { "d14", 1440, 64 },
  81   { "d15", 1504, 64 },
  82   { "d16", 1568, 64 },
  83   { "d17", 1632, 64 },
  84   { "d18", 1696, 64 },
  85   { "d19", 1760, 64 },
  86   { "d20", 1824, 64 },
  87   { "d21", 1888, 64 },
  88   { "d22", 1952, 64 },
  89   { "d23", 2016, 64 },
  90   { "d24", 2080, 64 },
  91   { "d25", 2144, 64 },
  92   { "d26", 2208, 64 },
  93   { "d27", 2272, 64 },
  94   { "d28", 2336, 64 },
  95   { "d29", 2400, 64 },
  96   { "d30", 2464, 64 },
  97   { "d31", 2528, 64 },
  98   { "fpscr", 2592, 32 }
  99 };
 100 static const char *expedite_regs[] = { "r11", "sp", "pc", 0 };
 101 #define num_regs (sizeof (regs) / sizeof (regs[0]))
 102
 103 static
 104 CORE_ADDR get_pc (void)
 105 {
 106    unsigned long pc;
 107
 108    collect_register_by_name ("pc", &pc);
 109
 110    dlog(1, "stop pc is %p\n", (void *) pc);
 111    return pc;
 112 }
 113
 114 static
 115 void set_pc (CORE_ADDR newpc)
 116 {
 117    supply_register_by_name ("pc", &newpc);
 118 }
 119
 120 Addr thumb_pc (Addr pc)
 121 {
 122    // If the thumb bit (bit 0) is already set, we trust it.
 123    if (pc & 1) {
 124       dlog (1, "%p = thumb (bit0 is set)\n", C2v (pc));
 125       return pc;
 126    }
 127
 128    // Here, bit 0 is not set.
 129    // For a pc aligned on 4 bytes, we have to use the debug
 130    // info to determine the thumb-ness.
 131    // else (aligned on 2 bytes), we trust this is a thumb
 132    // address and we set the thumb bit.
 133
 134    if (pc & 2) {
 135       dlog (1, "bit0 not set, bit1 set => %p = thumb\n", C2v (pc));
 136       return pc | 1;
 137    }
 138
 139    // pc aligned on 4 bytes. We need to use debug info.
 140    {
 141       const HChar *fnname;
 142       SymAVMAs avmas;
 143       // If this is a thumb instruction, we need to ask
 144       // the debug info with the bit0 set
 145       // (why can't debug info do that for us ???)
 146       // (why if this is a 4 bytes thumb instruction ???)
 147
 148       // Used to check if the instruction is a thumb instruction,
 149       // typically for a live address, so cur_ep is a reasonable choice.
 150       const DiEpoch cur_ep = VG_(current_DiEpoch)();
 151
 152       if (VG_(get_fnname_raw) (cur_ep, pc | 1, &fnname)) {
 153          if (VG_(lookup_symbol_SLOW)( cur_ep, "*", fnname, &avmas )) {
 154             dlog (1, "fnname %s lookupsym %p => %p %s.\n",
 155                   fnname, C2v(avmas.main), C2v(pc),
 156                   (avmas.main & 1 ? "thumb" : "arm"));
 157             if (avmas.main & 1)
 158                return pc | 1;
 159             else
 160                return pc;
 161
 162          } else {
 163             dlog (1, "%p fnname %s lookupsym failed?. Assume arm\n",
 164                   C2v (pc), fnname);
 165             return pc;
 166          }
 167       } else {
 168          // Can't find function name. We assume this is arm
 169          dlog (1, "%p unknown fnname?. Assume arm\n", C2v (pc));
 170          return pc;
 171       }
 172    }
 173 }
 174
 175 /* store registers in the guest state (gdbserver_to_valgrind)
 176    or fetch register from the guest state (valgrind_to_gdbserver). */
 177 static
 178 void transfer_register (ThreadId tid, int abs_regno, void * buf,
 179                         transfer_direction dir, int size, Bool *mod)
 180 {
 181    ThreadState* tst = VG_(get_ThreadState)(tid);
 182    int set = abs_regno / num_regs;
 183    int regno = abs_regno % num_regs;
 184    *mod = False;
 185
 186    VexGuestARMState* arm = (VexGuestARMState*) get_arch (set, tst);
 187
 188    switch (regno) {
 189    // numbers here have to match the order of regs above
 190    // Attention: gdb order does not match valgrind order.
 191    case 0:  VG_(transfer) (&arm->guest_R0,   buf, dir, size, mod); break;
 192    case 1:  VG_(transfer) (&arm->guest_R1,   buf, dir, size, mod); break;
 193    case 2:  VG_(transfer) (&arm->guest_R2,   buf, dir, size, mod); break;
 194    case 3:  VG_(transfer) (&arm->guest_R3,   buf, dir, size, mod); break;
 195    case 4:  VG_(transfer) (&arm->guest_R4,   buf, dir, size, mod); break;
 196    case 5:  VG_(transfer) (&arm->guest_R5,   buf, dir, size, mod); break;
 197    case 6:  VG_(transfer) (&arm->guest_R6,   buf, dir, size, mod); break;
 198    case 7:  VG_(transfer) (&arm->guest_R7,   buf, dir, size, mod); break;
 199    case 8:  VG_(transfer) (&arm->guest_R8,   buf, dir, size, mod); break;
 200    case 9:  VG_(transfer) (&arm->guest_R9,   buf, dir, size, mod); break;
 201    case 10: VG_(transfer) (&arm->guest_R10,  buf, dir, size, mod); break;
 202    case 11: VG_(transfer) (&arm->guest_R11,  buf, dir, size, mod); break;
 203    case 12: VG_(transfer) (&arm->guest_R12,  buf, dir, size, mod); break;
 204    case 13: VG_(transfer) (&arm->guest_R13,  buf, dir, size, mod); break;
 205    case 14: VG_(transfer) (&arm->guest_R14,  buf, dir, size, mod); break;
 206    case 15: {
 207       VG_(transfer) (&arm->guest_R15T, buf, dir, size, mod);
 208       if (dir == gdbserver_to_valgrind && *mod) {
 209          // If gdb is changing the PC, we have to set the thumb bit
 210          // if needed.
 211          arm->guest_R15T = thumb_pc(arm->guest_R15T);
 212       }
 213       break;
 214    }
 215    case 16:
 216    case 17:
 217    case 18:
 218    case 19:
 219    case 20: /* 9 "empty registers". See struct reg regs above. */
 220    case 21:
 221    case 22:
 222    case 23:
 223    case 24: *mod = False; break;
 224    case 25: {
 225       UInt cpsr = LibVEX_GuestARM_get_cpsr (arm);
 226       if (dir == valgrind_to_gdbserver) {
 227          VG_(transfer) (&cpsr, buf, dir, size, mod);
 228       } else {
 229 #      if 0
 230          UInt newcpsr;
 231          VG_(transfer) (&newcpsr, buf, dir, size, mod);
 232          *mod = newcpsr != cpsr;
 233          // GDBTD ???? see FIXME in guest_arm_helpers.c
 234          LibVEX_GuestARM_put_flags (newcpsr, arm);
 235 #      else
 236          *mod = False;
 237 #      endif
 238       }
 239       break;
 240    }
 241    case 26: VG_(transfer) (&arm->guest_D0,  buf, dir, size, mod); break;
 242    case 27: VG_(transfer) (&arm->guest_D1,  buf, dir, size, mod); break;
 243    case 28: VG_(transfer) (&arm->guest_D2,  buf, dir, size, mod); break;
 244    case 29: VG_(transfer) (&arm->guest_D3,  buf, dir, size, mod); break;
 245    case 30: VG_(transfer) (&arm->guest_D4,  buf, dir, size, mod); break;
 246    case 31: VG_(transfer) (&arm->guest_D5,  buf, dir, size, mod); break;
 247    case 32: VG_(transfer) (&arm->guest_D6,  buf, dir, size, mod); break;
 248    case 33: VG_(transfer) (&arm->guest_D7,  buf, dir, size, mod); break;
 249    case 34: VG_(transfer) (&arm->guest_D8,  buf, dir, size, mod); break;
 250    case 35: VG_(transfer) (&arm->guest_D9,  buf, dir, size, mod); break;
 251    case 36: VG_(transfer) (&arm->guest_D10, buf, dir, size, mod); break;
 252    case 37: VG_(transfer) (&arm->guest_D11, buf, dir, size, mod); break;
 253    case 38: VG_(transfer) (&arm->guest_D12, buf, dir, size, mod); break;
 254    case 39: VG_(transfer) (&arm->guest_D13, buf, dir, size, mod); break;
 255    case 40: VG_(transfer) (&arm->guest_D14, buf, dir, size, mod); break;
 256    case 41: VG_(transfer) (&arm->guest_D15, buf, dir, size, mod); break;
 257    case 42: VG_(transfer) (&arm->guest_D16, buf, dir, size, mod); break;
 258    case 43: VG_(transfer) (&arm->guest_D17, buf, dir, size, mod); break;
 259    case 44: VG_(transfer) (&arm->guest_D18, buf, dir, size, mod); break;
 260    case 45: VG_(transfer) (&arm->guest_D19, buf, dir, size, mod); break;
 261    case 46: VG_(transfer) (&arm->guest_D20, buf, dir, size, mod); break;
 262    case 47: VG_(transfer) (&arm->guest_D21, buf, dir, size, mod); break;
 263    case 48: VG_(transfer) (&arm->guest_D22, buf, dir, size, mod); break;
 264    case 49: VG_(transfer) (&arm->guest_D23, buf, dir, size, mod); break;
 265    case 50: VG_(transfer) (&arm->guest_D24, buf, dir, size, mod); break;
 266    case 51: VG_(transfer) (&arm->guest_D25, buf, dir, size, mod); break;
 267    case 52: VG_(transfer) (&arm->guest_D26, buf, dir, size, mod); break;
 268    case 53: VG_(transfer) (&arm->guest_D27, buf, dir, size, mod); break;
 269    case 54: VG_(transfer) (&arm->guest_D28, buf, dir, size, mod); break;
 270    case 55: VG_(transfer) (&arm->guest_D29, buf, dir, size, mod); break;
 271    case 56: VG_(transfer) (&arm->guest_D30, buf, dir, size, mod); break;
 272    case 57: VG_(transfer) (&arm->guest_D31, buf, dir, size, mod); break;
 273    case 58: VG_(transfer) (&arm->guest_FPSCR, buf, dir, size, mod); break;
 274    default: vg_assert(0);
 275    }
 276 }
 277
 278 static
 279 const char* target_xml (Bool shadow_mode)
 280 {
 281    if (shadow_mode) {
 282       return "arm-with-vfpv3-valgrind.xml";
 283    } else {
 284       return "arm-with-vfpv3.xml";
 285    }
 286 }
 287
 288 static CORE_ADDR** target_get_dtv (ThreadState *tst)
 289 {
 290    VexGuestARMState* arm = (VexGuestARMState*)&tst->arch.vex;
 291    // arm dtv is pointed to by TPIDRURO
 292    return (CORE_ADDR**)((CORE_ADDR)arm->guest_TPIDRURO);
 293 }
 294
 295 static struct valgrind_target_ops low_target = {
 296    num_regs,
 297    13, //SP
 298    regs,
 299    transfer_register,
 300    get_pc,
 301    set_pc,
 302    "arm",
 303    target_xml,
 304    target_get_dtv
 305 };
 306
 307 void arm_init_architecture (struct valgrind_target_ops *target)
 308 {
 309    *target = low_target;
 310    set_register_cache (regs, num_regs);
 311    gdbserver_expedite_regs = expedite_regs;
 312 }