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Remove warning caused by D demangle testcase
[valgrind.git] / VEX / priv / host_ppc_defs.h
blob39dca08a2e8d63362c05db46c1aa2a4769bba631
1
2 /*---------------------------------------------------------------*/
3 /*--- begin host_ppc_defs.h ---*/
4 /*---------------------------------------------------------------*/
5
6 /*
7 This file is part of Valgrind, a dynamic binary instrumentation
8 framework.
9
10 Copyright (C) 2004-2017 OpenWorks LLP
11 info@open-works.net
12
13 This program is free software; you can redistribute it and/or
14 modify it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 2 of the
16 License, or (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful, but
19 WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, see <http://www.gnu.org/licenses/>.
25
26 The GNU General Public License is contained in the file COPYING.
27
28 Neither the names of the U.S. Department of Energy nor the
29 University of California nor the names of its contributors may be
30 used to endorse or promote products derived from this software
31 without prior written permission.
32 */
33
34 #ifndef __VEX_HOST_PPC_DEFS_H
35 #define __VEX_HOST_PPC_DEFS_H
36
37 #include "libvex_basictypes.h"
38 #include "libvex.h" // VexArch
39 #include "host_generic_regs.h" // HReg
40
41
42 /* --------- Registers. --------- */
43
44 #define ST_IN static inline
45
46 #define GPR(_mode64, _enc, _ix64, _ix32) \
47 mkHReg(False, (_mode64) ? HRcInt64 : HRcInt32, \
48 (_enc), (_mode64) ? (_ix64) : (_ix32))
49
50 #define FPR(_mode64, _enc, _ix64, _ix32) \
51 mkHReg(False, HRcFlt64, \
52 (_enc), (_mode64) ? (_ix64) : (_ix32))
53
54 #define VR(_mode64, _enc, _ix64, _ix32) \
55 mkHReg(False, HRcVec128, \
56 (_enc), (_mode64) ? (_ix64) : (_ix32))
57
58 ST_IN HReg hregPPC_GPR14 ( Bool mode64 ) { return GPR(mode64, 14, 0, 0); }
59 ST_IN HReg hregPPC_GPR15 ( Bool mode64 ) { return GPR(mode64, 15, 1, 1); }
60 ST_IN HReg hregPPC_GPR16 ( Bool mode64 ) { return GPR(mode64, 16, 2, 2); }
61 ST_IN HReg hregPPC_GPR17 ( Bool mode64 ) { return GPR(mode64, 17, 3, 3); }
62 ST_IN HReg hregPPC_GPR18 ( Bool mode64 ) { return GPR(mode64, 18, 4, 4); }
63 ST_IN HReg hregPPC_GPR19 ( Bool mode64 ) { return GPR(mode64, 19, 5, 5); }
64 ST_IN HReg hregPPC_GPR20 ( Bool mode64 ) { return GPR(mode64, 20, 6, 6); }
65 ST_IN HReg hregPPC_GPR21 ( Bool mode64 ) { return GPR(mode64, 21, 7, 7); }
66 ST_IN HReg hregPPC_GPR22 ( Bool mode64 ) { return GPR(mode64, 22, 8, 8); }
67 ST_IN HReg hregPPC_GPR23 ( Bool mode64 ) { return GPR(mode64, 23, 9, 9); }
68 ST_IN HReg hregPPC_GPR24 ( Bool mode64 ) { return GPR(mode64, 24, 10, 10); }
69 ST_IN HReg hregPPC_GPR25 ( Bool mode64 ) { return GPR(mode64, 25, 11, 11); }
70 ST_IN HReg hregPPC_GPR26 ( Bool mode64 ) { return GPR(mode64, 26, 12, 12); }
71 ST_IN HReg hregPPC_GPR27 ( Bool mode64 ) { return GPR(mode64, 27, 13, 13); }
72 ST_IN HReg hregPPC_GPR28 ( Bool mode64 ) { return GPR(mode64, 28, 14, 14); }
73
74 ST_IN HReg hregPPC_GPR3 ( Bool mode64 ) { return GPR(mode64, 3, 15, 15); }
75 ST_IN HReg hregPPC_GPR4 ( Bool mode64 ) { return GPR(mode64, 4, 16, 16); }
76 ST_IN HReg hregPPC_GPR5 ( Bool mode64 ) { return GPR(mode64, 5, 17, 17); }
77 ST_IN HReg hregPPC_GPR6 ( Bool mode64 ) { return GPR(mode64, 6, 18, 18); }
78 ST_IN HReg hregPPC_GPR7 ( Bool mode64 ) { return GPR(mode64, 7, 19, 19); }
79 ST_IN HReg hregPPC_GPR8 ( Bool mode64 ) { return GPR(mode64, 8, 20, 20); }
80 ST_IN HReg hregPPC_GPR9 ( Bool mode64 ) { return GPR(mode64, 9, 21, 21); }
81 ST_IN HReg hregPPC_GPR10 ( Bool mode64 ) { return GPR(mode64, 10, 22, 22); }
82
83 // r11 and r12 are only allocatable in 32-bit mode. Hence the 64-bit
84 // index numbering doesn't advance for these two.
85 ST_IN HReg hregPPC_GPR11 ( Bool mode64 ) { return GPR(mode64, 11, 22, 23); }
86 ST_IN HReg hregPPC_GPR12 ( Bool mode64 ) { return GPR(mode64, 12, 22, 24); }
87
88 ST_IN HReg hregPPC_FPR14 ( Bool mode64 ) { return FPR(mode64, 14, 23, 25); }
89 ST_IN HReg hregPPC_FPR15 ( Bool mode64 ) { return FPR(mode64, 15, 24, 26); }
90 ST_IN HReg hregPPC_FPR16 ( Bool mode64 ) { return FPR(mode64, 16, 25, 27); }
91 ST_IN HReg hregPPC_FPR17 ( Bool mode64 ) { return FPR(mode64, 17, 26, 28); }
92 ST_IN HReg hregPPC_FPR18 ( Bool mode64 ) { return FPR(mode64, 18, 27, 29); }
93 ST_IN HReg hregPPC_FPR19 ( Bool mode64 ) { return FPR(mode64, 19, 28, 30); }
94 ST_IN HReg hregPPC_FPR20 ( Bool mode64 ) { return FPR(mode64, 20, 29, 31); }
95 ST_IN HReg hregPPC_FPR21 ( Bool mode64 ) { return FPR(mode64, 21, 30, 32); }
96
97 ST_IN HReg hregPPC_VR20 ( Bool mode64 ) { return VR (mode64, 20, 31, 33); }
98 ST_IN HReg hregPPC_VR21 ( Bool mode64 ) { return VR (mode64, 21, 32, 34); }
99 ST_IN HReg hregPPC_VR22 ( Bool mode64 ) { return VR (mode64, 22, 33, 35); }
100 ST_IN HReg hregPPC_VR23 ( Bool mode64 ) { return VR (mode64, 23, 34, 36); }
101 ST_IN HReg hregPPC_VR24 ( Bool mode64 ) { return VR (mode64, 24, 35, 37); }
102 ST_IN HReg hregPPC_VR25 ( Bool mode64 ) { return VR (mode64, 25, 36, 38); }
103 ST_IN HReg hregPPC_VR26 ( Bool mode64 ) { return VR (mode64, 26, 37, 39); }
104 ST_IN HReg hregPPC_VR27 ( Bool mode64 ) { return VR (mode64, 27, 38, 40); }
105
106 ST_IN HReg hregPPC_GPR1 ( Bool mode64 ) { return GPR(mode64, 1, 39, 41); }
107 ST_IN HReg hregPPC_GPR29 ( Bool mode64 ) { return GPR(mode64, 29, 40, 42); }
108 ST_IN HReg hregPPC_GPR30 ( Bool mode64 ) { return GPR(mode64, 30, 41, 43); }
109 ST_IN HReg hregPPC_GPR31 ( Bool mode64 ) { return GPR(mode64, 31, 42, 44); }
110 ST_IN HReg hregPPC_VR29 ( Bool mode64 ) { return VR (mode64, 29, 43, 45); }
111
112 #undef ST_IN
113 #undef GPR
114 #undef FPR
115 #undef VR
116
117 #define StackFramePtr(_mode64) hregPPC_GPR1(_mode64)
118 #define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64)
119
120 /* Num registers used for function calls */
121 #define PPC_N_REGPARMS 8
122
123 extern UInt ppHRegPPC ( HReg );
124
125
126 /* --------- Condition codes --------- */
127
128 /* This gives names from bitfields in CR; hence it names BI numbers */
129 /* Using IBM/hardware indexing convention */
130 typedef
131 enum {
132 // CR7, which we use for integer compares
133 Pcf_7LT = 28, /* neg | lt */
134 Pcf_7GT = 29, /* pos | gt */
135 Pcf_7EQ = 30, /* zero | equal */
136 Pcf_7SO = 31, /* summary overflow */
137 Pcf_NONE = 32 /* no condition; used with Pct_ALWAYS */
138 }
139 PPCCondFlag;
140
141 typedef
142 enum { /* Maps bc bitfield BO */
143 Pct_FALSE = 0x4, /* associated PPCCondFlag must not be Pcf_NONE */
144 Pct_TRUE = 0xC, /* associated PPCCondFlag must not be Pcf_NONE */
145 Pct_ALWAYS = 0x14 /* associated PPCCondFlag must be Pcf_NONE */
146 }
147 PPCCondTest;
148
149 typedef
150 struct {
151 PPCCondFlag flag;
152 PPCCondTest test;
153 }
154 PPCCondCode;
155
156 extern const HChar* showPPCCondCode ( PPCCondCode );
157
158 /* constructor */
159 extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag );
160
161 /* false->true, true->false */
162 extern PPCCondTest invertCondTest ( PPCCondTest );
163
164
165
166
167 /* --------- Memory address expressions (amodes). --------- */
168
169 typedef
170 enum {
171 Pam_IR=1, /* Immediate (signed 16-bit) + Reg */
172 Pam_RR=2 /* Reg1 + Reg2 */
173 }
174 PPCAModeTag;
175
176 typedef
177 struct {
178 PPCAModeTag tag;
179 union {
180 struct {
181 HReg base;
182 Int index;
183 } IR;
184 struct {
185 HReg base;
186 HReg index;
187 } RR;
188 } Pam;
189 }
190 PPCAMode;
191
192 extern PPCAMode* PPCAMode_IR ( Int, HReg );
193 extern PPCAMode* PPCAMode_RR ( HReg, HReg );
194
195 extern PPCAMode* dopyPPCAMode ( PPCAMode* );
196
197 extern void ppPPCAMode ( PPCAMode* );
198
199
200 /* --------- Operand, which can be a reg or a u16/s16. --------- */
201 /* ("RH" == "Register or Halfword immediate") */
202 typedef
203 enum {
204 Prh_Imm=3,
205 Prh_Reg=4
206 }
207 PPCRHTag;
208
209 typedef
210 struct {
211 PPCRHTag tag;
212 union {
213 struct {
214 Bool syned;
215 UShort imm16;
216 } Imm;
217 struct {
218 HReg reg;
219 } Reg;
220 }
221 Prh;
222 }
223 PPCRH;
224
225 extern PPCRH* PPCRH_Imm ( Bool, UShort );
226 extern PPCRH* PPCRH_Reg ( HReg );
227
228 extern void ppPPCRH ( PPCRH* );
229
230
231 /* --------- Operand, which can be a reg or a u32/64. --------- */
232
233 typedef
234 enum {
235 Pri_Imm=5,
236 Pri_Reg=6
237 }
238 PPCRITag;
239
240 typedef
241 struct {
242 PPCRITag tag;
243 union {
244 ULong Imm;
245 HReg Reg;
246 }
247 Pri;
248 }
249 PPCRI;
250
251 extern PPCRI* PPCRI_Imm ( ULong );
252 extern PPCRI* PPCRI_Reg( HReg );
253
254 extern void ppPPCRI ( PPCRI* );
255
256
257 /* --------- Operand, which can be a vector reg or a s6. --------- */
258 /* ("VI" == "Vector Register or Immediate") */
259 typedef
260 enum {
261 Pvi_Imm=7,
262 Pvi_Reg=8
263 }
264 PPCVI5sTag;
265
266 typedef
267 struct {
268 PPCVI5sTag tag;
269 union {
270 Char Imm5s;
271 HReg Reg;
272 }
273 Pvi;
274 }
275 PPCVI5s;
276
277 extern PPCVI5s* PPCVI5s_Imm ( Char );
278 extern PPCVI5s* PPCVI5s_Reg ( HReg );
279
280 extern void ppPPCVI5s ( PPCVI5s* );
281
282
283 /* --------- Instructions. --------- */
284
285 /* --------- */
286 typedef
287 enum {
288 Pun_NEG,
289 Pun_NOT,
290 Pun_CLZ32,
291 Pun_CLZ64,
292 Pun_EXTSW,
293 Pun_POP32, // popcntw
294 Pun_POP64 // popcntd
295 }
296 PPCUnaryOp;
297
298 extern const HChar* showPPCUnaryOp ( PPCUnaryOp );
299
300
301 /* --------- */
302 typedef
303 enum {
304 Palu_INVALID,
305 Palu_ADD, Palu_SUB,
306 Palu_AND, Palu_OR, Palu_XOR,
307 }
308 PPCAluOp;
309
310 extern
311 const HChar* showPPCAluOp ( PPCAluOp,
312 Bool /* is the 2nd operand an immediate? */);
313
314
315 /* --------- */
316 typedef
317 enum {
318 Pshft_INVALID,
319 Pshft_SHL, Pshft_SHR, Pshft_SAR,
320 }
321 PPCShftOp;
322
323 extern
324 const HChar* showPPCShftOp ( PPCShftOp,
325 Bool /* is the 2nd operand an immediate? */,
326 Bool /* is this a 32bit or 64bit op? */ );
327
328
329 /* --------- */
330 typedef
331 enum {
332 Pfp_INVALID,
333
334 /* Ternary */
335 Pfp_MADDD, Pfp_MSUBD,
336 Pfp_MADDS, Pfp_MSUBS,
337 Pfp_FPADDQ, Pfp_FPADDQRNDODD,
338 Pfp_FPSUBQ, Pfp_FPSUBQRNDODD,
339 Pfp_FPMULQ, Pfp_FPMULQRNDODD,
340 Pfp_FPDIVQ, Pfp_FPDIVQRNDODD,
341 Pfp_FPMULADDQ, Pfp_FPMULADDQRNDODD,
342 Pfp_FPMULSUBQ, Pfp_FPMULSUBQRNDODD,
343 Pfp_FPNEGMULADDQ, Pfp_FPNEGMULADDQRNDODD,
344 Pfp_FPNEGMULSUBQ, Pfp_FPNEGMULSUBQRNDODD,
345 Pfp_FPSQRTQ, Pfp_FPSQRTQRNDODD,
346 Pfp_FPQTOD, Pfp_FPQTODRNDODD,
347 Pfp_FPQTOW, Pfp_FPQTOWRNDODD,
348 Pfp_FPDTOQ,
349 Pfp_IDSTOQ,
350 Pfp_IDUTOQ,
351 Pfp_IQSTOQ,
352 Pfp_IQUTOQ,
353 Pfp_TRUNCFPQTOISQ,
354 Pfp_TRUNCFPQTOISD,
355 Pfp_TRUNCFPQTOISW,
356 Pfp_TRUNCFPQTOIUQ,
357 Pfp_TRUNCFPQTOIUD,
358 Pfp_TRUNCFPQTOIUW,
359 Pfp_DFPADD, Pfp_DFPADDQ,
360 Pfp_DFPSUB, Pfp_DFPSUBQ,
361 Pfp_DFPMUL, Pfp_DFPMULQ,
362 Pfp_DFPDIV, Pfp_DFPDIVQ,
363 Pfp_DQUAQ, Pfp_DRRNDQ,
364 Pfp_DFPTOIQ, Pfp_IQUTODFP,
365
366 /* Binary */
367 Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD,
368 Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS,
369 Pfp_DRSP, Pfp_DRDPQ, Pfp_DCTFIX, Pfp_DCTFIXQ, Pfp_DCFFIX,
370 Pfp_DQUA, Pfp_RRDTR, Pfp_DIEX, Pfp_DIEXQ, Pfp_DRINTN,
371
372 /* Unary */
373 Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE,
374 Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ,
375 Pfp_DSCLI, Pfp_DSCRI, Pfp_DSCLIQ, Pfp_DSCRIQ, Pfp_DCTDP,
376 Pfp_DCTQPQ, Pfp_DCFFIXQ, Pfp_DXEX, Pfp_DXEXQ,
377
378 }
379 PPCFpOp;
380
381 extern const HChar* showPPCFpOp ( PPCFpOp );
382
383
384 /* --------- */
385 typedef
386 enum {
387 Pav_INVALID,
388
389 /* Integer Unary */
390 Pav_MOV, /* Mov */
391 Pav_NOT, /* Bitwise */
392 Pav_UNPCKH8S, Pav_UNPCKH16S, /* Unpack */
393 Pav_UNPCKL8S, Pav_UNPCKL16S,
394 Pav_UNPCKHPIX, Pav_UNPCKLPIX,
395
396 /* Integer Binary */
397 Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */
398 Pav_ADDU, Pav_QADDU, Pav_QADDS,
399 Pav_SUBU, Pav_QSUBU, Pav_QSUBS,
400 Pav_MULU,
401 Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS,
402 Pav_AVGU, Pav_AVGS,
403 Pav_MAXU, Pav_MAXS,
404 Pav_MINU, Pav_MINS,
405
406 /* Compare (always affects CR field 6) */
407 Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS,
408
409 /* Shift */
410 Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL,
411
412 /* Pack */
413 Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS,
414 Pav_PACKPXL,
415
416 /* Merge */
417 Pav_MRGHI, Pav_MRGLO,
418
419 /* Concatenation */
420 Pav_CATODD, Pav_CATEVEN,
421
422 /* Polynomial Multipy-Add */
423 Pav_POLYMULADD,
424
425 /* Cipher */
426 Pav_CIPHERV128, Pav_CIPHERLV128, Pav_NCIPHERV128, Pav_NCIPHERLV128,
427 Pav_CIPHERSUBV128,
428
429 /* Hash */
430 Pav_SHA256, Pav_SHA512,
431
432 /* BCD Arithmetic */
433 Pav_BCDAdd, Pav_BCDSub,
434
435 /* Conversion signed 128-bit value to signed BCD 128-bit */
436 Pav_I128StoBCD128,
437
438 /* Conversion signed BCD 128-bit to signed 128-bit value */
439 Pav_BCD128toI128S,
440
441 /* zero count */
442 Pav_ZEROCNTBYTE, Pav_ZEROCNTWORD, Pav_ZEROCNTHALF, Pav_ZEROCNTDBL,
443
444 /* trailing zero count */
445 Pav_TRAILINGZEROCNTBYTE, Pav_TRAILINGZEROCNTWORD,
446 Pav_TRAILINGZEROCNTHALF, Pav_TRAILINGZEROCNTDBL,
447
448 /* Vector bit matrix transpose by byte */
449 Pav_BITMTXXPOSE,
450
451 /* Vector Half-precision format to single precision conversion */
452 Pav_F16toF32x4,
453
454 /* Vector Single precision format to Half-precision conversion */
455 Pav_F32toF16x4,
456
457 /* Vector Half-precision format to Double precision conversion */
458 Pav_F16toF64x2,
459
460 /* Vector Double precision format to Half-precision conversion */
461 Pav_F64toF16x2,
462
463 /* 128 bit mult by 10 */
464 Pav_MulI128by10,
465
466 /* 128 bit mult by 10, carry out */
467 Pav_MulI128by10Carry,
468
469 /* 128 bit mult by 10 plus carry in */
470 Pav_MulI128by10E,
471
472 /* 128 bit mult by 10 plus carry in, carry out */
473 Pav_MulI128by10ECarry,
474
475 /* F128 to I128 */
476 Pav_F128toI128S,
477
478 /* Round F128 to F128 */
479 Pav_ROUNDFPQ,
480 }
481 PPCAvOp;
482
483 extern const HChar* showPPCAvOp ( PPCAvOp );
484
485 typedef
486 enum {
487 Pav_INVALIDBinary128,
488
489 /* 128-bit integer Binary Divide */
490 Pav_DivU128, Pav_DivS128, Pav_DivU128E, Pav_DivS128E,
491 Pav_ModU128, Pav_ModS128,
492 }
493 PPCAvOpBin128;
494
495 extern const HChar* showPPCAvOpBin128 ( PPCAvOpBin128 );
496
497 typedef
498 enum {
499 Pav_INVALIDTri128,
500
501 /* 128-bit integer */
502 Pav_2xMultU64Add128CarryOut,
503 }
504 PPCAvOpTri128;
505
506 extern const HChar* showPPCAvOpTri128 ( PPCAvOpTri128 );
507
508 typedef
509 enum {
510 Px_INVALID_XFormUnary994,
511
512 /* 128-bit integer */
513 Px_DFPTOIQS, Px_IQSTODFP,
514 }
515 PPCXFormUnary994;
516
517 extern const HChar* showXFormUnary994 ( PPCXFormUnary994 );
518
519 /* --------- */
520 typedef
521 enum {
522 Pavfp_INVALID,
523
524 /* Floating point binary */
525 Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF,
526 Pavfp_MAXF, Pavfp_MINF,
527 Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF,
528
529 /* Floating point unary */
530 Pavfp_RCPF, Pavfp_RSQRTF, Pavfp_Log2, Pavfp_Exp2,
531 Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S,
532 Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ,
533 }
534 PPCAvFpOp;
535
536 extern const HChar* showPPCAvFpOp ( PPCAvFpOp );
537
538
539 /* --------- */
540 typedef
541 enum {
542 Pin_LI, /* load word (32/64-bit) immediate (fake insn) */
543 Pin_Alu, /* word add/sub/and/or/xor */
544 Pin_Shft, /* word shl/shr/sar */
545 Pin_AddSubC, /* add/sub with read/write carry */
546 Pin_Cmp, /* word compare */
547 Pin_Unary, /* not, neg, clz */
548 Pin_MulL, /* widening multiply */
549 Pin_Div, /* div */
550 Pin_Call, /* call to address in register */
551 Pin_XDirect, /* direct transfer to GA */
552 Pin_XIndir, /* indirect transfer to GA */
553 Pin_XAssisted, /* assisted transfer to GA */
554 Pin_CMov, /* conditional move */
555 Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */
556 Pin_LoadL, /* load-linked (lwarx/ldarx) 32|64 bit value from mem */
557 Pin_Store, /* store a 8|16|32|64 bit value to mem */
558 Pin_StoreC, /* store-conditional (stwcx./stdcx.) 32|64 bit val */
559 Pin_Set, /* convert condition code to value 0 or 1 */
560 Pin_MfCR, /* move from condition register to GPR */
561 Pin_MFence, /* mem fence */
562
563 Pin_FpUnary, /* FP unary op */
564 Pin_FpBinary, /* FP binary op */
565 Pin_Fp128Unary, /* FP unary op for 128-bit floating point */
566 Pin_Fp128Binary, /* FP binary op for 128-bit floating point */
567 Pin_Fp128Ternary, /* FP ternary op for 128-bit floating point */
568 Pin_FpMulAcc, /* FP multipy-accumulate style op */
569 Pin_FpLdSt, /* FP load/store */
570 Pin_FpSTFIW, /* stfiwx */
571 Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */
572 Pin_FpCftI, /* fcfid[u,s,us]/fctid[u]/fctiw[u] */
573 Pin_FpCMov, /* FP floating point conditional move */
574 Pin_FpLdFPSCR, /* mtfsf */
575 Pin_FpCmp, /* FP compare, generating value into int reg */
576
577 Pin_RdWrLR, /* Read/Write Link Register */
578
579 Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */
580 Pin_AvUnary, /* AV unary general reg=>reg */
581
582 Pin_AvBinary, /* AV binary general reg,reg=>reg */
583 Pin_AvBinaryInt,/* AV binary reg,int=>reg */
584 Pin_AvBinaryInt128,/* AV binary 128-bit reg, 128-bitint => 128-bit reg */
585 Pin_AvTernaryInt128,/* AV ternary 128-bit reg, 128-bitint => 128-bit reg */
586 Pin_AvBin8x16, /* AV binary, 8x4 */
587 Pin_AvBin16x8, /* AV binary, 16x4 */
588 Pin_AvBin32x4, /* AV binary, 32x4 */
589 Pin_AvBin64x2, /* AV binary, 64x2 */
590
591 Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */
592 Pin_AvUn32Fx4, /* AV FP unary, 32Fx4 */
593
594 Pin_AvPerm, /* AV permute (shuffle) */
595 Pin_AvSel, /* AV select */
596 Pin_AvSh, /* AV shift left or right */
597 Pin_AvShlDbl, /* AV shift-left double by imm */
598 Pin_AvSplat, /* One elem repeated throughout dst */
599 Pin_AvLdVSCR, /* mtvscr */
600 Pin_AvCMov, /* AV conditional move */
601 Pin_AvCipherV128Unary, /* AV Vector unary Cipher */
602 Pin_AvCipherV128Binary, /* AV Vector binary Cipher */
603 Pin_AvHashV128Binary, /* AV Vector binary Hash */
604 Pin_AvBCDV128Binary, /* BCD Arithmetic */
605 Pin_Dfp64Unary, /* DFP64 unary op */
606 Pin_Dfp128Unary, /* DFP128 unary op */
607 Pin_DfpShift, /* Decimal floating point shift by immediate value */
608 Pin_Dfp64Binary, /* DFP64 binary op */
609 Pin_Dfp128Binary, /* DFP128 binary op */
610 Pin_DfpShift128, /* 128-bit Decimal floating point shift by
611 * immediate value */
612 Pin_DfpD128toD64, /* DFP 128 to DFP 64 op */
613 Pin_DfpI64StoD128, /* DFP signed integer to DFP 128 */
614 Pin_DfpRound, /* D64 round to D64 */
615 Pin_DfpRound128, /* D128 round to D128 */
616 Pin_ExtractExpD128, /* DFP, extract 64 bit exponent */
617 Pin_InsertExpD128, /* DFP, insert 64 bit exponent and 128 bit binary
618 * significand into a DFP 128-bit value*/
619 Pin_Dfp64Cmp, /* DFP 64-bit compare, generating value into
620 * int reg */
621 Pin_Dfp128Cmp, /* DFP 128-bit compare, generating value into
622 * int reg */
623 Pin_DfpQuantize, /* D64 quantize using register value, significance
624 * round */
625 Pin_DfpQuantize128, /* D128 quantize using register value, significance
626 * round */
627
628 Pin_XFormUnary994, /* X-form instructions with opc1=63, opc2=994 */
629 Pin_EvCheck, /* Event check */
630 Pin_ProfInc /* 64-bit profile counter increment */
631 }
632 PPCInstrTag;
633
634 /* Destinations are on the LEFT (first operand) */
635
636 typedef
637 struct {
638 PPCInstrTag tag;
639 union {
640 /* Get a 32/64-bit literal into a register.
641 May turn into a number of real insns. */
642 struct {
643 HReg dst;
644 ULong imm64;
645 } LI;
646 /* Integer add/sub/and/or/xor. Limitations:
647 - For add, the immediate, if it exists, is a signed 16.
648 - For sub, the immediate, if it exists, is a signed 16
649 which may not be -32768, since no such instruction
650 exists, and so we have to emit addi with +32768, but
651 that is not possible.
652 - For and/or/xor, the immediate, if it exists,
653 is an unsigned 16.
654 */
655 struct {
656 PPCAluOp op;
657 HReg dst;
658 HReg srcL;
659 PPCRH* srcR;
660 } Alu;
661 /* Integer shl/shr/sar.
662 Limitations: the immediate, if it exists,
663 is a signed 5-bit value between 1 and 31 inclusive.
664 */
665 struct {
666 PPCShftOp op;
667 Bool sz32; /* mode64 has both 32 and 64bit shft */
668 HReg dst;
669 HReg srcL;
670 PPCRH* srcR;
671 } Shft;
672 /* */
673 struct {
674 Bool isAdd; /* else sub */
675 Bool setC; /* else read carry */
676 HReg dst;
677 HReg srcL;
678 HReg srcR;
679 } AddSubC;
680 /* If signed, the immediate, if it exists, is a signed 16,
681 else it is an unsigned 16. */
682 struct {
683 Bool syned;
684 Bool sz32; /* mode64 has both 32 and 64bit cmp */
685 UInt crfD;
686 HReg srcL;
687 PPCRH* srcR;
688 } Cmp;
689 /* Not, Neg, Clz32/64, Extsw */
690 struct {
691 PPCUnaryOp op;
692 HReg dst;
693 HReg src;
694 } Unary;
695 struct {
696 Bool syned; /* meaningless if hi32==False */
697 Bool hi; /* False=>low, True=>high */
698 Bool sz32; /* mode64 has both 32 & 64bit mull */
699 HReg dst;
700 HReg srcL;
701 HReg srcR;
702 } MulL;
703 /* ppc32 div/divu instruction. */
704 struct {
705 Bool extended;
706 Bool syned;
707 Bool sz32; /* mode64 has both 32 & 64bit div */
708 HReg dst;
709 HReg srcL;
710 HReg srcR;
711 } Div;
712 /* Pseudo-insn. Call target (an absolute address), on given
713 condition (which could be Pct_ALWAYS). argiregs indicates
714 which of r3 .. r10 carries argument values for this call,
715 using a bit mask (1<<N is set if rN holds an arg, for N in
716 3 .. 10 inclusive). */
717 struct {
718 PPCCondCode cond;
719 Addr64 target;
720 UInt argiregs;
721 RetLoc rloc; /* where the return value will be */
722 } Call;
723 /* Update the guest CIA value, then exit requesting to chain
724 to it. May be conditional. Use of Addr64 in order to cope
725 with 64-bit hosts. */
726 struct {
727 Addr64 dstGA; /* next guest address */
728 PPCAMode* amCIA; /* amode in guest state for CIA */
729 PPCCondCode cond; /* can be ALWAYS */
730 Bool toFastEP; /* chain to the slow or fast point? */
731 } XDirect;
732 /* Boring transfer to a guest address not known at JIT time.
733 Not chainable. May be conditional. */
734 struct {
735 HReg dstGA;
736 PPCAMode* amCIA;
737 PPCCondCode cond; /* can be ALWAYS */
738 } XIndir;
739 /* Assisted transfer to a guest address, most general case.
740 Not chainable. May be conditional. */
741 struct {
742 HReg dstGA;
743 PPCAMode* amCIA;
744 PPCCondCode cond; /* can be ALWAYS */
745 IRJumpKind jk;
746 } XAssisted;
747 /* Mov src to dst on the given condition, which may not
748 be the bogus Pct_ALWAYS. */
749 struct {
750 PPCCondCode cond;
751 HReg dst;
752 PPCRI* src;
753 } CMov;
754 /* Zero extending loads. Dst size is host word size */
755 struct {
756 UChar sz; /* 1|2|4|8 */
757 HReg dst;
758 PPCAMode* src;
759 } Load;
760 /* Load-and-reserve (lwarx, ldarx) */
761 struct {
762 UChar sz; /* 4|8 */
763 HReg dst;
764 HReg src;
765 } LoadL;
766 /* 64/32/16/8 bit stores */
767 struct {
768 UChar sz; /* 1|2|4|8 */
769 PPCAMode* dst;
770 HReg src;
771 } Store;
772 /* Store-conditional (stwcx., stdcx.) */
773 struct {
774 UChar sz; /* 4|8 */
775 HReg dst;
776 HReg src;
777 } StoreC;
778 /* Convert a ppc condition code to value 0 or 1. */
779 struct {
780 PPCCondCode cond;
781 HReg dst;
782 } Set;
783 /* Move the entire CR to a GPR */
784 struct {
785 HReg dst;
786 } MfCR;
787 /* Mem fence. In short, an insn which flushes all preceding
788 loads and stores as much as possible before continuing.
789 On PPC we emit a "sync". */
790 struct {
791 } MFence;
792
793 /* PPC Floating point */
794 struct {
795 PPCFpOp op;
796 HReg dst;
797 HReg src;
798 } FpUnary;
799 struct {
800 PPCFpOp op;
801 HReg dst;
802 HReg srcL;
803 HReg srcR;
804 } FpBinary;
805 struct {
806 PPCFpOp op;
807 HReg dst;
808 HReg src;
809 } Fp128Unary;
810 struct {
811 PPCFpOp op;
812 HReg dst;
813 HReg srcL;
814 HReg srcR;
815 } Fp128Binary;
816 struct {
817 PPCFpOp op;
818 HReg dst;
819 HReg srcL;
820 HReg srcR;
821 } Fp128Ternary;
822 struct {
823 PPCFpOp op;
824 HReg dst;
825 HReg srcML;
826 HReg srcMR;
827 HReg srcAcc;
828 } FpMulAcc;
829 struct {
830 Bool isLoad;
831 UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */
832 HReg reg;
833 PPCAMode* addr;
834 } FpLdSt;
835 struct {
836 HReg addr; /* int reg */
837 HReg data; /* float reg */
838 } FpSTFIW;
839 /* Round 64-bit FP value to 32-bit FP value in an FP reg. */
840 struct {
841 HReg src;
842 HReg dst;
843 } FpRSP;
844 /* fcfid[u,s,us]/fctid[u]/fctiw[u]. Only some combinations
845 of the various fields are allowed. This is asserted for
846 and documented in the code for the constructor,
847 PPCInstr_FpCftI, in host_ppc_defs.c. */
848 struct {
849 Bool fromI; /* True== I->F, False== F->I */
850 Bool int32; /* True== I is 32, False== I is 64 */
851 Bool syned;
852 Bool flt64; /* True== F is 64, False== F is 32 */
853 HReg src;
854 HReg dst;
855 } FpCftI;
856 /* FP mov src to dst on the given condition. */
857 struct {
858 PPCCondCode cond;
859 HReg dst;
860 HReg src;
861 } FpCMov;
862 /* Load FP Status & Control Register */
863 struct {
864 HReg src;
865 UInt dfp_rm;
866 } FpLdFPSCR;
867 /* Do a compare, generating result into an int register. */
868 struct {
869 UChar crfD;
870 HReg dst;
871 HReg srcL;
872 HReg srcR;
873 } FpCmp;
874
875 /* Read/Write Link Register */
876 struct {
877 Bool wrLR;
878 HReg gpr;
879 } RdWrLR;
880
881 /* Simplistic AltiVec */
882 struct {
883 Bool isLoad;
884 UChar sz; /* 8|16|32|128 */
885 HReg reg;
886 PPCAMode* addr;
887 } AvLdSt;
888 struct {
889 PPCAvOp op;
890 HReg dst;
891 HReg src;
892 } AvUnary;
893 struct {
894 PPCAvOp op;
895 HReg dst;
896 HReg srcL;
897 HReg srcR;
898 } AvBinary;
899 struct {
900 PPCAvOp op;
901 HReg dst;
902 HReg src;
903 PPCRI* val;
904 } AvBinaryInt;
905 struct {
906 PPCAvOpBin128 op;
907 HReg dst;
908 HReg src1;
909 HReg src2;
910 } AvBinaryInt128;
911 struct {
912 PPCAvOpTri128 op;
913 HReg dst;
914 HReg src1;
915 HReg src2;
916 HReg src3;
917 } AvTernaryInt128;
918 struct {
919 PPCAvOp op;
920 HReg dst;
921 HReg srcL;
922 HReg srcR;
923 } AvBin8x16;
924 struct {
925 PPCAvOp op;
926 HReg dst;
927 HReg srcL;
928 HReg srcR;
929 } AvBin16x8;
930 struct {
931 PPCAvOp op;
932 HReg dst;
933 HReg srcL;
934 HReg srcR;
935 } AvBin32x4;
936 /* Can only be generated for CPUs capable of ISA 2.07 or above */
937 struct {
938 PPCAvOp op;
939 HReg dst;
940 HReg srcL;
941 HReg srcR;
942 } AvBin64x2;
943 struct {
944 PPCAvFpOp op;
945 HReg dst;
946 HReg srcL;
947 HReg srcR;
948 } AvBin32Fx4;
949 struct {
950 PPCAvFpOp op;
951 HReg dst;
952 HReg src;
953 } AvUn32Fx4;
954 /* Perm,Sel,SlDbl,Splat are all weird AV permutations */
955 struct {
956 HReg dst;
957 HReg srcL;
958 HReg srcR;
959 HReg ctl;
960 } AvPerm;
961 struct {
962 HReg dst;
963 HReg srcL;
964 HReg srcR;
965 HReg ctl;
966 } AvSel;
967 struct {
968 Bool shLeft;
969 HReg dst;
970 PPCAMode* addr;
971 } AvSh;
972 struct {
973 UChar shift;
974 HReg dst;
975 HReg srcL;
976 HReg srcR;
977 } AvShlDbl;
978 struct {
979 UChar sz; /* 8,16,32 */
980 HReg dst;
981 PPCVI5s* src;
982 } AvSplat;
983 /* Mov src to dst on the given condition, which may not
984 be the bogus Xcc_ALWAYS. */
985 struct {
986 PPCCondCode cond;
987 HReg dst;
988 HReg src;
989 } AvCMov;
990 /* Load AltiVec Status & Control Register */
991 struct {
992 HReg src;
993 } AvLdVSCR;
994 struct {
995 PPCAvOp op;
996 HReg dst;
997 HReg src;
998 } AvCipherV128Unary;
999 struct {
1000 PPCAvOp op;
1001 HReg dst;
1002 HReg src;
1003 PPCRI* s_field;
1004 } AvHashV128Binary;
1005 struct {
1006 PPCAvOp op;
1007 HReg dst;
1008 HReg src1;
1009 HReg src2;
1010 } AvBCDV128Binary;
1011 struct {
1012 PPCAvOp op;
1013 HReg dst;
1014 HReg srcL;
1015 HReg srcR;
1016 } AvCipherV128Binary;
1017 struct {
1018 PPCFpOp op;
1019 HReg dst;
1020 HReg src;
1021 } Dfp64Unary;
1022 struct {
1023 PPCFpOp op;
1024 HReg dst;
1025 HReg srcL;
1026 HReg srcR;
1027 } Dfp64Binary;
1028 struct {
1029 PPCFpOp op;
1030 HReg dst;
1031 HReg src;
1032 PPCRI* shift;
1033 } DfpShift;
1034 struct {
1035 PPCFpOp op;
1036 HReg dst_hi;
1037 HReg dst_lo;
1038 HReg src_hi;
1039 HReg src_lo;
1040 } Dfp128Unary;
1041 struct {
1042 /* The dst is used to pass the left source operand in and return
1043 * the result.
1044 */
1045 PPCFpOp op;
1046 HReg dst_hi;
1047 HReg dst_lo;
1048 HReg srcR_hi;
1049 HReg srcR_lo;
1050 } Dfp128Binary;
1051 struct {
1052 PPCFpOp op;
1053 HReg dst_hi;
1054 HReg dst_lo;
1055 HReg src_hi;
1056 HReg src_lo;
1057 PPCRI* shift;
1058 } DfpShift128;
1059 struct {
1060 HReg dst;
1061 HReg src;
1062 PPCRI* r_rmc;
1063 } DfpRound;
1064 struct {
1065 HReg dst_hi;
1066 HReg dst_lo;
1067 HReg src_hi;
1068 HReg src_lo;
1069 PPCRI* r_rmc;
1070 } DfpRound128;
1071 struct {
1072 PPCFpOp op;
1073 HReg dst;
1074 HReg srcL;
1075 HReg srcR;
1076 PPCRI* rmc;
1077 } DfpQuantize;
1078 struct {
1079 PPCFpOp op;
1080 HReg dst_hi;
1081 HReg dst_lo;
1082 HReg src_hi;
1083 HReg src_lo;
1084 PPCRI* rmc;
1085 } DfpQuantize128;
1086 struct {
1087 PPCFpOp op;
1088 HReg dst;
1089 HReg src_hi;
1090 HReg src_lo;
1091 } ExtractExpD128;
1092 struct {
1093 PPCFpOp op;
1094 HReg dst_hi;
1095 HReg dst_lo;
1096 HReg srcL;
1097 HReg srcR_hi;
1098 HReg srcR_lo;
1099 } InsertExpD128;
1100 struct {
1101 PPCFpOp op;
1102 HReg dst;
1103 HReg src_hi;
1104 HReg src_lo;
1105 } DfpD128toD64;
1106 struct {
1107 PPCFpOp op;
1108 HReg dst_hi;
1109 HReg dst_lo;
1110 HReg src;
1111 } DfpI64StoD128;
1112 struct {
1113 UChar crfD;
1114 HReg dst;
1115 HReg srcL;
1116 HReg srcR;
1117 } Dfp64Cmp;
1118 struct {
1119 UChar crfD;
1120 HReg dst;
1121 HReg srcL_hi;
1122 HReg srcL_lo;
1123 HReg srcR_hi;
1124 HReg srcR_lo;
1125 } Dfp128Cmp;
1126 struct {
1127 PPCXFormUnary994 op;
1128 HReg reg0;
1129 HReg reg1;
1130 HReg reg2;
1131 } XFormUnary994;
1132 struct {
1133 PPCAMode* amCounter;
1134 PPCAMode* amFailAddr;
1135 } EvCheck;
1136 struct {
1137 /* No fields. The address of the counter to inc is
1138 installed later, post-translation, by patching it in,
1139 as it is not known at translation time. */
1140 } ProfInc;
1141 } Pin;
1142 }
1143 PPCInstr;
1144
1145
1146 extern PPCInstr* PPCInstr_LI ( HReg, ULong, Bool );
1147 extern PPCInstr* PPCInstr_Alu ( PPCAluOp, HReg, HReg, PPCRH* );
1148 extern PPCInstr* PPCInstr_Shft ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* );
1149 extern PPCInstr* PPCInstr_AddSubC ( Bool, Bool, HReg, HReg, HReg );
1150 extern PPCInstr* PPCInstr_Cmp ( Bool, Bool, UInt, HReg, PPCRH* );
1151 extern PPCInstr* PPCInstr_Unary ( PPCUnaryOp op, HReg dst, HReg src );
1152 extern PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg );
1153 extern PPCInstr* PPCInstr_Div ( Bool extended, Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR );
1154 extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt, RetLoc );
1155 extern PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA,
1156 PPCCondCode cond, Bool toFastEP );
1157 extern PPCInstr* PPCInstr_XIndir ( HReg dstGA, PPCAMode* amCIA,
1158 PPCCondCode cond );
1159 extern PPCInstr* PPCInstr_XAssisted ( HReg dstGA, PPCAMode* amCIA,
1160 PPCCondCode cond, IRJumpKind jk );
1161 extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src );
1162 extern PPCInstr* PPCInstr_Load ( UChar sz,
1163 HReg dst, PPCAMode* src, Bool mode64 );
1164 extern PPCInstr* PPCInstr_LoadL ( UChar sz,
1165 HReg dst, HReg src, Bool mode64 );
1166 extern PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst,
1167 HReg src, Bool mode64 );
1168 extern PPCInstr* PPCInstr_StoreC ( UChar sz, HReg dst, HReg src,
1169 Bool mode64 );
1170 extern PPCInstr* PPCInstr_Set ( PPCCondCode cond, HReg dst );
1171 extern PPCInstr* PPCInstr_MfCR ( HReg dst );
1172 extern PPCInstr* PPCInstr_MFence ( void );
1173
1174 extern PPCInstr* PPCInstr_Fp128Unary ( PPCFpOp op, HReg dst, HReg src );
1175 extern PPCInstr* PPCInstr_Fp128Binary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR );
1176 extern PPCInstr* PPCInstr_Fp128Ternary ( PPCFpOp op, HReg dst, HReg srcL,
1177 HReg srcR);
1178
1179 extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src );
1180 extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR );
1181 extern PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML,
1182 HReg srcMR, HReg srcAcc );
1183 extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* );
1184 extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data );
1185 extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src );
1186 extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, Bool syned,
1187 Bool dst64, HReg dst, HReg src );
1188 extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src );
1189 extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src, Bool dfp_rm );
1190 extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR );
1191
1192 extern PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr );
1193
1194 extern PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* );
1195 extern PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src );
1196 extern PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1197 extern PPCInstr* PPCInstr_AvBinaryInt( PPCAvOp op, HReg dst, HReg src, PPCRI* val );
1198 extern PPCInstr* PPCInstr_AvBinaryInt128( PPCAvOpBin128 op, HReg dst,
1199 HReg src1, HReg src2 );
1200 extern PPCInstr* PPCInstr_AvTernaryInt128( PPCAvOpTri128 op, HReg dst,
1201 HReg src1, HReg src2, HReg src3 );
1202 extern PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1203 extern PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1204 extern PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1205 extern PPCInstr* PPCInstr_AvBin64x2 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR );
1206 extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvFpOp op, HReg dst, HReg srcL, HReg srcR );
1207 extern PPCInstr* PPCInstr_AvUn32Fx4 ( PPCAvFpOp op, HReg dst, HReg src );
1208 extern PPCInstr* PPCInstr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl );
1209 extern PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR );
1210 extern PPCInstr* PPCInstr_AvSh ( Bool shLeft, HReg dst, PPCAMode* am_addr );
1211 extern PPCInstr* PPCInstr_AvShlDbl ( UChar shift, HReg dst, HReg srcL, HReg srcR );
1212 extern PPCInstr* PPCInstr_AvSplat ( UChar sz, HReg dst, PPCVI5s* src );
1213 extern PPCInstr* PPCInstr_AvCMov ( PPCCondCode, HReg dst, HReg src );
1214 extern PPCInstr* PPCInstr_AvLdVSCR ( HReg src );
1215 extern PPCInstr* PPCInstr_AvCipherV128Unary ( PPCAvOp op, HReg dst,
1216 HReg srcR );
1217 extern PPCInstr* PPCInstr_AvCipherV128Binary ( PPCAvOp op, HReg dst,
1218 HReg srcL, HReg srcR );
1219 extern PPCInstr* PPCInstr_AvHashV128Binary ( PPCAvOp op, HReg dst,
1220 HReg src, PPCRI* s_field );
1221 extern PPCInstr* PPCInstr_AvBCDV128Binary ( PPCAvOp op, HReg dst,
1222 HReg src1, HReg src2 );
1223 extern PPCInstr* PPCInstr_Dfp64Unary ( PPCFpOp op, HReg dst, HReg src );
1224 extern PPCInstr* PPCInstr_Dfp64Binary ( PPCFpOp op, HReg dst, HReg srcL,
1225 HReg srcR );
1226 extern PPCInstr* PPCInstr_DfpShift ( PPCFpOp op, HReg dst, HReg src,
1227 PPCRI* shift );
1228 extern PPCInstr* PPCInstr_Dfp128Unary ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
1229 HReg srcR_hi, HReg srcR_lo );
1230 extern PPCInstr* PPCInstr_Dfp128Binary ( PPCFpOp op, HReg dst_hi, HReg dst_lo,
1231 HReg srcR_hi, HReg srcR_lo );
1232 extern PPCInstr* PPCInstr_DfpShift128 ( PPCFpOp op, HReg dst_hi, HReg src_hi,
1233 HReg dst_lo, HReg src_lo,
1234 PPCRI* shift );
1235 extern PPCInstr* PPCInstr_DfpD128toD64 ( PPCFpOp op, HReg dst,
1236 HReg dst_lo, HReg src_lo);
1237 extern PPCInstr* PPCInstr_DfpI64StoD128 ( PPCFpOp op, HReg dst_hi,
1238 HReg dst_lo, HReg src);
1239 extern PPCInstr* PPCInstr_DfpRound ( HReg dst, HReg src, PPCRI* r_rmc );
1240 extern PPCInstr* PPCInstr_DfpRound128 ( HReg dst_hi, HReg dst_lo, HReg src_hi,
1241 HReg src_lo, PPCRI* r_rmc );
1242 extern PPCInstr* PPCInstr_DfpQuantize ( PPCFpOp op, HReg dst, HReg srcL,
1243 HReg srcR, PPCRI* rmc );
1244 extern PPCInstr* PPCInstr_DfpQuantize128 ( PPCFpOp op, HReg dst_hi,
1245 HReg dst_lo,
1246 HReg src_hi,
1247 HReg src_lo, PPCRI* rmc );
1248 extern PPCInstr* PPCInstr_ExtractExpD128 ( PPCFpOp op, HReg dst,
1249 HReg src_hi, HReg src_lo );
1250 extern PPCInstr* PPCInstr_InsertExpD128 ( PPCFpOp op, HReg dst_hi,
1251 HReg dst_lo, HReg srcL,
1252 HReg srcR_hi, HReg srcR_lo );
1253 extern PPCInstr* PPCInstr_Dfp64Cmp ( HReg dst, HReg srcL, HReg srcR );
1254 extern PPCInstr* PPCInstr_Dfp128Cmp ( HReg dst, HReg srcL_hi, HReg srcL_lo,
1255 HReg srcR_hi, HReg srcR_lo );
1256 extern PPCInstr* PPCInstr_XFormUnary994 ( PPCXFormUnary994 op, HReg dst,
1257 HReg srcHi, HReg srcLo );
1258 extern PPCInstr* PPCInstr_EvCheck ( PPCAMode* amCounter,
1259 PPCAMode* amFailAddr );
1260 extern PPCInstr* PPCInstr_ProfInc ( void );
1261
1262 extern void ppPPCInstr(const PPCInstr*, Bool mode64);
1263
1264
1265 /* Some functions that insulate the register allocator from details
1266 of the underlying instruction set. */
1267 extern void getRegUsage_PPCInstr ( HRegUsage*, const PPCInstr*, Bool mode64 );
1268 extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64);
1269 extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
1270 UChar* buf, Int nbuf, const PPCInstr* i,
1271 Bool mode64,
1272 VexEndness endness_host,
1273 const void* disp_cp_chain_me_to_slowEP,
1274 const void* disp_cp_chain_me_to_fastEP,
1275 const void* disp_cp_xindir,
1276 const void* disp_cp_xassisted );
1277
1278 extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1279 HReg rreg, Int offsetB, Bool mode64 );
1280 extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1281 HReg rreg, Int offsetB, Bool mode64 );
1282 extern PPCInstr* genMove_PPC(HReg from, HReg to, Bool mode64);
1283
1284 extern const RRegUniverse* getRRegUniverse_PPC ( Bool mode64 );
1285
1286 extern HInstrArray* iselSB_PPC ( const IRSB*,
1287 VexArch,
1288 const VexArchInfo*,
1289 const VexAbiInfo*,
1290 Int offs_Host_EvC_Counter,
1291 Int offs_Host_EvC_FailAddr,
1292 Bool chainingAllowed,
1293 Bool addProfInc,
1294 Addr max_ga );
1295
1296 /* How big is an event check? This is kind of a kludge because it
1297 depends on the offsets of host_EvC_FAILADDR and
1298 host_EvC_COUNTER. */
1299 extern Int evCheckSzB_PPC (void);
1300
1301 /* Perform a chaining and unchaining of an XDirect jump. */
1302 extern VexInvalRange chainXDirect_PPC ( VexEndness endness_host,
1303 void* place_to_chain,
1304 const void* disp_cp_chain_me_EXPECTED,
1305 const void* place_to_jump_to,
1306 Bool mode64 );
1307
1308 extern VexInvalRange unchainXDirect_PPC ( VexEndness endness_host,
1309 void* place_to_unchain,
1310 const void* place_to_jump_to_EXPECTED,
1311 const void* disp_cp_chain_me,
1312 Bool mode64 );
1313
1314 /* Patch the counter location into an existing ProfInc point. */
1315 extern VexInvalRange patchProfInc_PPC ( VexEndness endness_host,
1316 void* place_to_patch,
1317 const ULong* location_of_counter,
1318 Bool mode64 );
1319
1320
1321 #endif /* ndef __VEX_HOST_PPC_DEFS_H */
1322
1323 /*---------------------------------------------------------------*/
1324 /*--- end host_ppc_defs.h ---*/
1325 /*---------------------------------------------------------------*/
Instrumentation framework for detecting many memory management and threading bugs, and profile your programs in detail.