VEX/priv/host_mips_defs.h

   1
   2 /*---------------------------------------------------------------*/
   3 /*--- begin                                  host_mips_defs.h ---*/
   4 /*---------------------------------------------------------------*/
   5
   6 /*
   7    This file is part of Valgrind, a dynamic binary instrumentation
   8    framework.
   9
  10    Copyright (C) 2010-2017 RT-RK
  11
  12    This program is free software; you can redistribute it and/or
  13    modify it under the terms of the GNU General Public License as
  14    published by the Free Software Foundation; either version 2 of the
  15    License, or (at your option) any later version.
  16
  17    This program is distributed in the hope that it will be useful, but
  18    WITHOUT ANY WARRANTY; without even the implied warranty of
  19    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20    General Public License for more details.
  21
  22    You should have received a copy of the GNU General Public License
  23    along with this program; if not, see <http://www.gnu.org/licenses/>.
  24
  25    The GNU General Public License is contained in the file COPYING.
  26 */
  27
  28 #ifndef __VEX_HOST_MIPS_DEFS_H
  29 #define __VEX_HOST_MIPS_DEFS_H
  30
  31 #include "libvex_basictypes.h"
  32 #include "libvex.h"             /* VexArch */
  33 #include "host_generic_regs.h"  /* HReg */
  34
  35
  36 /* --------- Registers. --------- */
  37
  38 #define ST_IN static inline
  39
  40 #define GPR(_mode64, _enc, _ix64, _ix32) \
  41   mkHReg(False,  (_mode64) ? HRcInt64 : HRcInt32, \
  42          (_enc), (_mode64) ? (_ix64) : (_ix32))
  43
  44 #define FR(_mode64, _enc, _ix64, _ix32) \
  45   mkHReg(False,  (_mode64) ? HRcFlt64 : HRcFlt32, \
  46          (_enc), (_mode64) ? (_ix64) : (_ix32))
  47
  48 #define DR(_mode64, _enc, _ix64, _ix32) \
  49   mkHReg(False,  HRcFlt64, \
  50          (_enc), (_mode64) ? (_ix64) : (_ix32))
  51
  52 #define VEC(_mode64, _enc, _ix64, _ix32) \
  53   mkHReg(False,  HRcVec128, \
  54          (_enc), (_mode64) ? (_ix64) : (_ix32))
  55
  56 ST_IN HReg hregMIPS_GPR16 ( Bool mode64 ) { return GPR(mode64, 16,  0,  0); }
  57 ST_IN HReg hregMIPS_GPR17 ( Bool mode64 ) { return GPR(mode64, 17,  1,  1); }
  58 ST_IN HReg hregMIPS_GPR18 ( Bool mode64 ) { return GPR(mode64, 18,  2,  2); }
  59 ST_IN HReg hregMIPS_GPR19 ( Bool mode64 ) { return GPR(mode64, 19,  3,  3); }
  60 ST_IN HReg hregMIPS_GPR20 ( Bool mode64 ) { return GPR(mode64, 20,  4,  4); }
  61 ST_IN HReg hregMIPS_GPR21 ( Bool mode64 ) { return GPR(mode64, 21,  5,  5); }
  62 ST_IN HReg hregMIPS_GPR22 ( Bool mode64 ) { return GPR(mode64, 22,  6,  6); }
  63
  64 ST_IN HReg hregMIPS_GPR12 ( Bool mode64 ) { return GPR(mode64, 12,  7,  7); }
  65 ST_IN HReg hregMIPS_GPR13 ( Bool mode64 ) { return GPR(mode64, 13,  8,  8); }
  66 ST_IN HReg hregMIPS_GPR14 ( Bool mode64 ) { return GPR(mode64, 14,  9,  9); }
  67 ST_IN HReg hregMIPS_GPR15 ( Bool mode64 ) { return GPR(mode64, 15, 10, 10); }
  68 ST_IN HReg hregMIPS_GPR24 ( Bool mode64 ) { return GPR(mode64, 24, 11, 11); }
  69
  70 ST_IN HReg hregMIPS_F16   ( Bool mode64 ) { return FR (mode64, 16, 12, 12); }
  71 ST_IN HReg hregMIPS_F18   ( Bool mode64 ) { return FR (mode64, 18, 13, 13); }
  72 ST_IN HReg hregMIPS_F20   ( Bool mode64 ) { return FR (mode64, 20, 14, 14); }
  73 ST_IN HReg hregMIPS_F22   ( Bool mode64 ) { return FR (mode64, 22, 15, 15); }
  74 ST_IN HReg hregMIPS_F24   ( Bool mode64 ) { return FR (mode64, 24, 16, 16); }
  75 ST_IN HReg hregMIPS_F26   ( Bool mode64 ) { return FR (mode64, 26, 17, 17); }
  76 ST_IN HReg hregMIPS_F28   ( Bool mode64 ) { return FR (mode64, 28, 18, 18); }
  77 ST_IN HReg hregMIPS_F30   ( Bool mode64 ) { return FR (mode64, 30, 19, 19); }
  78
  79 ST_IN HReg hregMIPS_W16    ( Bool mode64 ) { return VEC(mode64, 1, 20, 20); }
  80 ST_IN HReg hregMIPS_W17    ( Bool mode64 ) { return VEC(mode64, 3, 21, 21); }
  81 ST_IN HReg hregMIPS_W18    ( Bool mode64 ) { return VEC(mode64, 5, 22, 22); }
  82 ST_IN HReg hregMIPS_W19    ( Bool mode64 ) { return VEC(mode64, 7, 23, 23); }
  83 ST_IN HReg hregMIPS_W20    ( Bool mode64 ) { return VEC(mode64, 9, 24, 24); }
  84 ST_IN HReg hregMIPS_W21    ( Bool mode64 ) { return VEC(mode64, 11, 25, 25); }
  85 ST_IN HReg hregMIPS_W22    ( Bool mode64 ) { return VEC(mode64, 13, 26, 26); }
  86 ST_IN HReg hregMIPS_W23    ( Bool mode64 ) { return VEC(mode64, 15, 27, 27); }
  87 ST_IN HReg hregMIPS_W24    ( Bool mode64 ) { return VEC(mode64, 17, 28, 28); }
  88 ST_IN HReg hregMIPS_W25    ( Bool mode64 ) { return VEC(mode64, 19, 29, 29); }
  89 ST_IN HReg hregMIPS_W26    ( Bool mode64 ) { return VEC(mode64, 21, 30, 30); }
  90 ST_IN HReg hregMIPS_W27    ( Bool mode64 ) { return VEC(mode64, 23, 31, 31); }
  91 ST_IN HReg hregMIPS_W28    ( Bool mode64 ) { return VEC(mode64, 25, 32, 32); }
  92 ST_IN HReg hregMIPS_W29    ( Bool mode64 ) { return VEC(mode64, 27, 33, 33); }
  93 ST_IN HReg hregMIPS_W30    ( Bool mode64 ) { return VEC(mode64, 29, 34, 34); }
  94 ST_IN HReg hregMIPS_W31    ( Bool mode64 ) { return VEC(mode64, 31, 35, 35); }
  95
  96 // DRs are only allocatable in 32-bit mode, so the 64-bit index numbering
  97 // doesn't advance here.
  98 ST_IN HReg hregMIPS_D0    ( Bool mode64 ) { vassert(!mode64);
  99                                             return DR (mode64,  0,  0, 36); }
 100 ST_IN HReg hregMIPS_D1    ( Bool mode64 ) { vassert(!mode64);
 101                                             return DR (mode64,  2,  0, 37); }
 102 ST_IN HReg hregMIPS_D2    ( Bool mode64 ) { vassert(!mode64);
 103                                             return DR (mode64,  4,  0, 38); }
 104 ST_IN HReg hregMIPS_D3    ( Bool mode64 ) { vassert(!mode64);
 105                                             return DR (mode64,  6,  0, 39); }
 106 ST_IN HReg hregMIPS_D4    ( Bool mode64 ) { vassert(!mode64);
 107                                             return DR (mode64,  8,  0, 40); }
 108 ST_IN HReg hregMIPS_D5    ( Bool mode64 ) { vassert(!mode64);
 109                                             return DR (mode64, 10,  0, 41); }
 110 ST_IN HReg hregMIPS_D6    ( Bool mode64 ) { vassert(!mode64);
 111                                             return DR (mode64, 12,  0, 42); }
 112 ST_IN HReg hregMIPS_D7    ( Bool mode64 ) { vassert(!mode64);
 113                                             return DR (mode64, 14,  0, 43); }
 114
 115 ST_IN HReg hregMIPS_HI    ( Bool mode64 ) { return FR (mode64, 33, 36, 44); }
 116 ST_IN HReg hregMIPS_LO    ( Bool mode64 ) { return FR (mode64, 34, 37, 45); }
 117
 118 ST_IN HReg hregMIPS_GPR0  ( Bool mode64 ) { return GPR(mode64,  0, 38, 46); }
 119 ST_IN HReg hregMIPS_GPR1  ( Bool mode64 ) { return GPR(mode64,  1, 39, 47); }
 120 ST_IN HReg hregMIPS_GPR2  ( Bool mode64 ) { return GPR(mode64,  2, 40, 48); }
 121 ST_IN HReg hregMIPS_GPR3  ( Bool mode64 ) { return GPR(mode64,  3, 41, 49); }
 122 ST_IN HReg hregMIPS_GPR4  ( Bool mode64 ) { return GPR(mode64,  4, 42, 50); }
 123 ST_IN HReg hregMIPS_GPR5  ( Bool mode64 ) { return GPR(mode64,  5, 43, 51); }
 124 ST_IN HReg hregMIPS_GPR6  ( Bool mode64 ) { return GPR(mode64,  6, 44, 52); }
 125 ST_IN HReg hregMIPS_GPR7  ( Bool mode64 ) { return GPR(mode64,  7, 45, 53); }
 126 ST_IN HReg hregMIPS_GPR8  ( Bool mode64 ) { return GPR(mode64,  8, 46, 54); }
 127 ST_IN HReg hregMIPS_GPR9  ( Bool mode64 ) { return GPR(mode64,  9, 47, 55); }
 128 ST_IN HReg hregMIPS_GPR10 ( Bool mode64 ) { return GPR(mode64, 10, 48, 56); }
 129 ST_IN HReg hregMIPS_GPR11 ( Bool mode64 ) { return GPR(mode64, 11, 49, 57); }
 130 ST_IN HReg hregMIPS_GPR23 ( Bool mode64 ) { return GPR(mode64, 23, 50, 58); }
 131 ST_IN HReg hregMIPS_GPR25 ( Bool mode64 ) { return GPR(mode64, 25, 51, 59); }
 132 ST_IN HReg hregMIPS_GPR29 ( Bool mode64 ) { return GPR(mode64, 29, 52, 60); }
 133 ST_IN HReg hregMIPS_GPR31 ( Bool mode64 ) { return GPR(mode64, 31, 53, 61); }
 134
 135 #undef ST_IN
 136 #undef GPR
 137 #undef FR
 138 #undef DR
 139 #undef VEC
 140
 141 #define GuestStatePointer(_mode64)     hregMIPS_GPR23(_mode64)
 142 #define StackFramePointer(_mode64)     hregMIPS_GPR30(_mode64)
 143 #define StackPointer(_mode64)          hregMIPS_GPR29(_mode64)
 144 #define Zero(_mode64)                  hregMIPS_GPR0(_mode64)
 145
 146 /* guest_COND offset */
 147 #define COND_OFFSET(_mode64) ((_mode64) ? 588 : 448)
 148
 149 /* guest_MSACSR offset */
 150 #define MSACSR_OFFSET(_mode64) ((_mode64) ? 1144 : 1016)
 151
 152 /* Num registers used for function calls */
 153 #if defined(VGP_mips32_linux)
 154   /* a0, a1, a2, a3 */
 155 # define MIPS_N_REGPARMS 4
 156 #else
 157   /* a0, a1, a2, a3, a4, a5, a6, a7 */
 158 # define MIPS_N_REGPARMS 8
 159 #endif
 160
 161 extern UInt ppHRegMIPS ( HReg, Bool );
 162
 163 #define OPC_MSA        0x78000000
 164
 165 /* --------- Condition codes, Intel encoding. --------- */
 166 typedef enum {
 167    MIPScc_EQ = 0,   /* equal */
 168    MIPScc_NE = 1,   /* not equal */
 169
 170    MIPScc_HS = 2,   /* >=u (higher or same) */
 171    MIPScc_LO = 3,   /* <u  (lower) */
 172
 173    MIPScc_MI = 4,   /* minus (negative) */
 174    MIPScc_PL = 5,   /* plus (zero or +ve) */
 175
 176    MIPScc_VS = 6,   /* overflow */
 177    MIPScc_VC = 7,   /* no overflow */
 178
 179    MIPScc_HI = 8,   /* >u   (higher) */
 180    MIPScc_LS = 9,   /* <=u  (lower or same) */
 181
 182    MIPScc_GE = 10,  /* >=s (signed greater or equal) */
 183    MIPScc_LT = 11,  /* <s  (signed less than) */
 184
 185    MIPScc_GT = 12,  /* >s  (signed greater) */
 186    MIPScc_LE = 13,  /* <=s (signed less or equal) */
 187
 188    MIPScc_AL = 14,  /* always (unconditional) */
 189    MIPScc_NV = 15   /* never (unconditional): */
 190 } MIPSCondCode;
 191
 192 extern const HChar *showMIPSCondCode(MIPSCondCode);
 193
 194 /* --------- Memory address expressions (amodes). --------- */
 195 typedef enum {
 196    Mam_IR,        /* Immediate (signed 16-bit) + Reg */
 197    Mam_RR         /* Reg1 + Reg2 */
 198 } MIPSAModeTag;
 199
 200 typedef struct {
 201    MIPSAModeTag tag;
 202    union {
 203       struct {
 204          HReg base;
 205          Int index;
 206       } IR;
 207       struct {
 208          HReg base;
 209          HReg index;
 210       } RR;
 211    } Mam;
 212 } MIPSAMode;
 213
 214 extern MIPSAMode *MIPSAMode_IR(Int, HReg);
 215 extern MIPSAMode *MIPSAMode_RR(HReg, HReg);
 216
 217 extern MIPSAMode *dopyMIPSAMode(MIPSAMode *);
 218 extern MIPSAMode *nextMIPSAModeFloat(MIPSAMode *);
 219 extern MIPSAMode *nextMIPSAModeInt(MIPSAMode *);
 220
 221 extern void ppMIPSAMode(MIPSAMode *, Bool);
 222
 223 /* --------- Operand, which can be a reg or a u16/s16. --------- */
 224 /* ("RH" == "Register or Halfword immediate") */
 225 typedef enum {
 226    Mrh_Imm,
 227    Mrh_Reg
 228 } MIPSRHTag;
 229
 230 typedef struct {
 231    MIPSRHTag tag;
 232    union {
 233       struct {
 234          Bool syned;
 235          UShort imm16;
 236       } Imm;
 237       struct {
 238          HReg reg;
 239       } Reg;
 240    } Mrh;
 241 } MIPSRH;
 242
 243 extern void ppMIPSRH(MIPSRH *, Bool);
 244
 245 extern MIPSRH *MIPSRH_Imm(Bool, UShort);
 246 extern MIPSRH *MIPSRH_Reg(HReg);
 247
 248 /* --------- Instructions. --------- */
 249
 250 /*Tags for operations*/
 251
 252 /* --------- */
 253 typedef enum {
 254    Mun_CLO,
 255    Mun_CLZ,
 256    Mun_DCLO,
 257    Mun_DCLZ,
 258    Mun_NOP,
 259 } MIPSUnaryOp;
 260
 261 extern const HChar *showMIPSUnaryOp(MIPSUnaryOp);
 262 /* --------- */
 263
 264 /* --------- */
 265
 266 typedef enum {
 267    Malu_INVALID,
 268    Malu_ADD, Malu_SUB,
 269    Malu_AND, Malu_OR, Malu_NOR, Malu_XOR,
 270    Malu_DADD, Malu_DSUB,
 271    Malu_SLT
 272 } MIPSAluOp;
 273
 274 extern const HChar *showMIPSAluOp(MIPSAluOp,
 275                             Bool /* is the 2nd operand an immediate? */ );
 276
 277 /* --------- */
 278 typedef enum {
 279    Mshft_INVALID,
 280    Mshft_SLL, Mshft_SRL,
 281    Mshft_SRA
 282 } MIPSShftOp;
 283
 284 extern const HChar *showMIPSShftOp(MIPSShftOp,
 285                              Bool /* is the 2nd operand an immediate? */ ,
 286                              Bool /* is this a 32bit or 64bit op? */ );
 287
 288 /* --------- */
 289 typedef enum {
 290    Macc_ADD,
 291    Macc_SUB
 292 } MIPSMaccOp;
 293
 294 extern const HChar *showMIPSMaccOp(MIPSMaccOp, Bool);
 295 /* --------- */
 296
 297 typedef enum {
 298    MSA_LD = 8,
 299    MSA_ST = 9
 300 } MSAMI10Op;
 301
 302 extern const HChar *showMsaMI10op(MSAMI10Op);
 303
 304 typedef enum {
 305    MSA_SLDI   = 0,
 306    MSA_COPY_S = 2,
 307    MSA_COPY_U = 3,
 308    MSA_INSERT = 4,
 309    MSA_INSVE  = 5,
 310    MSA_MOVE   = 0xBE,
 311    MSA_CFCMSA = 0x7E,
 312    MSA_CTCMSA = 0x3E
 313 } MSAELMOp;
 314
 315 extern const HChar *showMsaElmOp(MSAELMOp);
 316
 317 typedef enum {
 318    MSA_FILL = 0xC0,
 319    MSA_PCNT = 0xC1,
 320    MSA_NLOC = 0xC2,
 321    MSA_NLZC = 0xC3
 322 } MSA2ROp;
 323
 324 extern const HChar *showMsa2ROp(MSA2ROp);
 325
 326 typedef enum {
 327    MSA_FTRUNC_S = 0x191,
 328    MSA_FTRUNC_U = 0x192,
 329    MSA_FFINT_S  = 0x19E,
 330    MSA_FFINT_U  = 0x19F,
 331    MSA_FSQRT    = 0x193,
 332    MSA_FRSQRT   = 0x194,
 333    MSA_FRCP     = 0x195,
 334    MSA_FLOG2    = 0x197,
 335    MSA_FEXUPR   = 0x199,
 336    MSA_FTINT_U  = 0x19D,
 337    MSA_FTINT_S  = 0x19C,
 338 } MSA2RFOp;
 339
 340 extern const HChar *showMsa2RFOp(MSA2RFOp);
 341
 342 typedef enum {
 343    MSA_SLL = 0xD,
 344    MSA_ADDV,
 345    MSA_CEQ,
 346    MSA_ADD_A,
 347    MSA_SUBS_S,
 348    MSA_SLD = 0x14,
 349    MSA_SRA = 0x80000D,
 350    MSA_SUBV,
 351    MSA_SUBS_U = 0x800011,
 352    MSA_SRL = 0x100000D,
 353    MSA_MAX_S,
 354    MSA_CLT_S,
 355    MSA_ADDS_S,
 356    MSA_PCKEV = 0x1000014,
 357    MSA_MAX_U = 0x180000E,
 358    MSA_CLT_U,
 359    MSA_ADDS_U,
 360    MSA_PCKOD = 0x1800014,
 361    MSA_MIN_S = 0x200000E,
 362    MSA_ILVL = 0x2000014,
 363    MSA_MIN_U = 0x280000E,
 364    MSA_ILVR = 0x2800014,
 365    MSA_AVER_S = 0x3000010,
 366    MSA_ILVEV = 0x3000014,
 367    MSA_AVER_U = 0x3800010,
 368    MSA_ILVOD = 0x3800014,
 369    MSA_MULV = 0x0000012,
 370    MSA_SPLAT = 0x0800014,
 371    MSA_DIVS = 0x2000012,
 372    MSA_DIVU = 0x2800012,
 373    MSA_VSHF = 0x0000015,
 374 } MSA3ROp;
 375
 376 extern const HChar *showMsa3ROp(MSA3ROp);
 377
 378 typedef enum {
 379    MSA_FADD   = 0x000001B,
 380    MSA_FCUN   = 0x040001A,
 381    MSA_FSUB   = 0x040001B,
 382    MSA_FCEQ   = 0x080001A,
 383    MSA_FMUL   = 0x080001B,
 384    MSA_FDIV   = 0x0C0001B,
 385    MSA_FMADD  = 0x100001B,
 386    MSA_FCLT   = 0x100001A,
 387    MSA_FMSUB  = 0x140001B,
 388    MSA_FEXP2  = 0x1C0001B,
 389    MSA_FMIN   = 0x300001B,
 390    MSA_FMIN_A = 0x340001B,
 391    MSA_FMAX   = 0x380001B,
 392    MSA_MUL_Q  = 0x100001C,
 393    MSA_FCLE   = 0x180001A,
 394    MSA_FTQ    = 0x280001B,
 395    MSA_FEXDO  = 0x200001B,
 396    MSA_MULR_Q = 0x300001C,
 397 } MSA3RFOp;
 398
 399 extern const HChar *showMsa3RFOp(MSA3RFOp);
 400
 401 typedef enum {
 402    MSA_ANDV,
 403    MSA_ORV,
 404    MSA_NORV,
 405    MSA_XORV
 406 } MSAVECOp;
 407
 408 extern const HChar *showMsaVecOp(MSAVECOp);
 409
 410 typedef enum {
 411    MSA_SLLI = 9,
 412    MSA_SAT_S,
 413    MSA_SRAI = 0x800009,
 414    MSA_SRLI = 0x1000009,
 415    MSA_SRARI = 0x100000A
 416 } MSABITOp;
 417
 418 extern const HChar *showMsaBitOp(MSABITOp);
 419
 420 typedef enum {
 421    MSA_B = 0,
 422    MSA_H = 1,
 423    MSA_W = 2,
 424    MSA_D = 3,
 425 } MSADF;
 426
 427 extern HChar showMsaDF(MSADF df);
 428
 429 typedef enum {
 430    MSA_DFN_B    = 0x00,
 431    MSA_DFN_H    = 0x20,
 432    MSA_DFN_W    = 0x30,
 433    MSA_DFN_D    = 0x38,
 434 } MSADFNMask;
 435
 436 typedef enum {
 437    MSA_F_WH = 0,
 438    MSA_F_DW = 1,
 439 } MSADFFlx;
 440
 441 extern HChar showMsaDFF(MSADFFlx df, int op);
 442
 443
 444 /* ----- Instruction tags ----- */
 445 typedef enum {
 446    Min_LI,         /* load word (32/64-bit) immediate (fake insn) */
 447    Min_Alu,        /* word add/sub/and/or/xor/nor/others? */
 448    Min_Shft,       /* word sll/srl/sra */
 449    Min_Unary,      /* clo, clz, nop, neg */
 450    Min_Ext,        /* ext / dext, dextm, dextu */
 451    Min_Rotx,
 452
 453    Min_Cmp,        /* word compare (fake insn) */
 454
 455    Min_Mul,        /* non-widening, 32-bit, signed multiply */
 456    Min_Mult,       /* widening multiply */
 457    Min_Mulr6,
 458    Min_Div,        /* div */
 459    Min_Divr6,
 460
 461    Min_Call,       /* call to address in register */
 462
 463    /* The following 5 insns are mandated by translation chaining */
 464    Min_XDirect,    /* direct transfer to GA */
 465    Min_XIndir,     /* indirect transfer to GA */
 466    Min_XAssisted,  /* assisted transfer to GA */
 467    Min_EvCheck,    /* Event check */
 468    Min_ProfInc,    /* 64-bit profile counter increment */
 469
 470    Min_RdWrLR,     /* Read/Write Link Register */
 471    Min_Mthi,       /* Move to HI from GP register */
 472    Min_Mtlo,       /* Move to LO from GP register */
 473    Min_Mfhi,       /* Move from HI to GP register */
 474    Min_Mflo,       /* Move from LO to GP register */
 475    Min_Macc,       /* Multiply and accumulate */
 476
 477    Min_Load,       /* zero-extending load a 8|16|32 bit value from mem */
 478    Min_Store,      /* store a 8|16|32 bit value to mem */
 479    Min_Cas,        /* compare and swap */
 480    Min_LoadL,      /* mips Load Linked Word - LL */
 481    Min_StoreC,     /* mips Store Conditional Word - SC */
 482
 483    Min_FpUnary,    /* FP unary op */
 484    Min_FpBinary,   /* FP binary op */
 485    Min_FpTernary,  /* FP ternary op */
 486    Min_FpConvert,  /* FP conversion op */
 487    Min_FpMulAcc,   /* FP multipy-accumulate style op */
 488    Min_FpLdSt,     /* FP load/store */
 489    Min_FpSTFIW,    /* stfiwx */
 490    Min_FpRSP,      /* FP round IEEE754 double to IEEE754 single */
 491    Min_FpCftI,     /* fcfid/fctid/fctiw */
 492    Min_FpCMov,     /* FP floating point conditional move */
 493    Min_MtFCSR,     /* set FCSR register */
 494    Min_MfFCSR,     /* get FCSR register */
 495    Min_FpCompare,  /* FP compare, generating value into int reg */
 496    Min_FpMinMax,    /* FP r6 min and max*/
 497
 498    Min_FpGpMove,   /* Move from/to fpr to/from gpr */
 499    Min_MoveCond,   /* Move Conditional */
 500
 501    Msa_MI10,
 502    Msa_ELM,
 503    Msa_3R,
 504    Msa_2R,
 505    Msa_VEC,
 506    Msa_BIT,
 507    Msa_3RF,
 508    Msa_2RF,
 509 } MIPSInstrTag;
 510
 511 /* --------- */
 512 typedef enum {
 513    Mfp_INVALID,
 514
 515    /* Ternary */
 516    Mfp_MADDD, Mfp_MSUBD,
 517    Mfp_MADDS, Mfp_MSUBS,
 518
 519    /* Binary */
 520    Mfp_ADDD, Mfp_SUBD, Mfp_MULD, Mfp_DIVD,
 521    Mfp_ADDS, Mfp_SUBS, Mfp_MULS, Mfp_DIVS,
 522
 523    /* Unary */
 524    Mfp_SQRTS, Mfp_SQRTD,
 525    Mfp_ABSS, Mfp_ABSD, Mfp_NEGS, Mfp_NEGD, Mfp_MOVS, Mfp_MOVD,
 526
 527    /* FP convert */
 528    Mfp_CVTSD, Mfp_CVTSW, Mfp_CVTWD,
 529    Mfp_CVTWS, Mfp_CVTDL, Mfp_CVTSL, Mfp_CVTLS, Mfp_CVTLD, Mfp_TRULS, Mfp_TRULD,
 530    Mfp_TRUWS, Mfp_TRUWD, Mfp_FLOORWS, Mfp_FLOORWD, Mfp_ROUNDWS, Mfp_ROUNDWD,
 531    Mfp_CVTDW, Mfp_CEILWS, Mfp_CEILWD, Mfp_CEILLS, Mfp_CEILLD, Mfp_CVTDS,
 532    Mfp_ROUNDLD, Mfp_FLOORLD, Mfp_RINTS, Mfp_RINTD,
 533
 534    /* FP compare */
 535    Mfp_CMP_UN, Mfp_CMP_EQ, Mfp_CMP_LT, Mfp_CMP_NGT,
 536
 537    Mfp_CMP_UN_S, Mfp_CMP_EQ_S, Mfp_CMP_LT_S, Mfp_CMP_NGT_S,
 538
 539    /*MAX and MIN*/
 540    Mfp_MAXS, Mfp_MAXD, Mfp_MINS, Mfp_MIND
 541
 542 } MIPSFpOp;
 543
 544 extern const HChar *showMIPSFpOp(MIPSFpOp);
 545
 546 typedef enum {
 547    Rotx32,
 548    Rotx64
 549 } MIPSRotxOp;
 550
 551 extern const HChar *showRotxOp(MIPSRotxOp);
 552
 553 /* Move from/to fpr to/from gpr */
 554 typedef enum {
 555    MFpGpMove_mfc1,   /* Move Word From Floating Point - MIPS32 */
 556    MFpGpMove_dmfc1,  /* Doubleword Move from Floating Point - MIPS64 */
 557    MFpGpMove_mtc1,   /* Move Word to Floating Point - MIPS32 */
 558    MFpGpMove_dmtc1   /* Doubleword Move to Floating Point - MIPS64 */
 559 } MIPSFpGpMoveOp;
 560
 561 extern const HChar *showMIPSFpGpMoveOp ( MIPSFpGpMoveOp );
 562
 563 /* Move Conditional */
 564 typedef enum {
 565    MFpMoveCond_movns,  /* FP Move Conditional on Not Zero - MIPS32 */
 566    MFpMoveCond_movnd,
 567    MMoveCond_movn,      /* Move Conditional on Not Zero */
 568    MSeleqz, /* r6 instructions */
 569    MSelnez,
 570    MFpSels,
 571    MFpSeld
 572 } MIPSMoveCondOp;
 573
 574 extern const HChar *showMIPSMoveCondOp ( MIPSMoveCondOp );
 575
 576 /*--------- Structure for instructions ----------*/
 577 /* Destinations are on the LEFT (first operand) */
 578
 579 typedef struct {
 580    MIPSInstrTag tag;
 581    union {
 582       /* Get a 32/64-bit literal into a register.
 583          May turn into a number of real insns. */
 584       struct {
 585          HReg dst;
 586          ULong imm;
 587       } LI;
 588       /* Integer add/sub/and/or/xor.  Limitations:
 589          - For add, the immediate, if it exists, is a signed 16.
 590          - For sub, the immediate, if it exists, is a signed 16
 591          which may not be -32768, since no such instruction
 592          exists, and so we have to emit addi with +32768, but
 593          that is not possible.
 594          - For and/or/xor,  the immediate, if it exists,
 595          is an unsigned 16.
 596        */
 597       struct {
 598          MIPSAluOp op;
 599          HReg dst;
 600          HReg srcL;
 601          MIPSRH *srcR;
 602       } Alu;
 603       /* Integer shl/shr/sar.
 604          Limitations: the immediate, if it exists,
 605          is a signed 5-bit value between 1 and 31 inclusive.
 606        */
 607       struct {
 608          MIPSShftOp op;
 609          Bool sz32;  /* mode64 has both 32 and 64bit shft */
 610          HReg dst;
 611          HReg srcL;
 612          MIPSRH *srcR;
 613       } Shft;
 614       struct {
 615          MIPSRotxOp op;
 616          HReg rd;
 617          HReg rt;
 618          HReg shift;
 619          HReg shiftx;
 620          HReg stripe;
 621       } Rotx;
 622       /* Clz, Clo, nop */
 623       struct {
 624          MIPSUnaryOp op;
 625          HReg dst;
 626          HReg src;
 627       } Unary;
 628       /* Bit extract */
 629       struct {
 630          HReg dst;
 631          HReg src;
 632          UInt pos;
 633          UInt size;
 634       } Ext;
 635       /* Word compare. Fake instruction, used for basic block ending */
 636       struct {
 637          Bool syned;
 638          Bool sz32;
 639          HReg dst;
 640          HReg srcL;
 641          HReg srcR;
 642
 643          MIPSCondCode cond;
 644       } Cmp;
 645       struct {
 646          Bool widening;  /* True => widening, False => non-widening */
 647          Bool syned;     /* signed/unsigned - meaningless if widenind = False */
 648          Bool sz32;
 649          HReg dst;
 650          HReg srcL;
 651          HReg srcR;
 652       } Mul;
 653       struct {
 654          Bool syned;     /* signed/unsigned */
 655          HReg srcL;
 656          HReg srcR;
 657       } Mult;
 658       struct {
 659          Bool syned;     /* signed/unsigned - meaningless if widenind = False */
 660          Bool sz32;
 661          Bool low;
 662          HReg dst;
 663          HReg srcL;
 664          HReg srcR;
 665       } Mulr6;
 666       struct {
 667          Bool syned;  /* signed/unsigned - meaningless if widenind = False */
 668          Bool sz32;
 669          HReg srcL;
 670          HReg srcR;
 671       } Div;
 672       struct {
 673          Bool syned;     /* signed/unsigned - meaningless if widenind = False */
 674          Bool sz32;
 675          Bool mod;
 676          HReg dst;
 677          HReg srcL;
 678          HReg srcR;
 679       } Divr6;
 680       /* Pseudo-insn.  Call target (an absolute address), on given
 681          condition (which could be Mcc_ALWAYS).  argiregs indicates
 682          which of $4 .. $7 (mips32) or $4 .. $11 (mips64)
 683          carries argument values for this call,
 684          using a bit mask (1<<N is set if $N holds an arg, for N in
 685          $4 .. $7 or $4 .. $11 inclusive).
 686          If cond is != Mcc_ALWAYS, src is checked.
 687          Otherwise, unconditional call */
 688       struct {
 689          MIPSCondCode cond;
 690          Addr64 target;
 691          UInt argiregs;
 692          HReg src;
 693          RetLoc rloc;     /* where the return value will be */
 694       } Call;
 695       /* Update the guest EIP value, then exit requesting to chain
 696          to it.  May be conditional.  Urr, use of Addr32 implicitly
 697          assumes that wordsize(guest) == wordsize(host). */
 698       struct {
 699          Addr64       dstGA;     /* next guest address */
 700          MIPSAMode*   amPC;      /* amode in guest state for PC */
 701          MIPSCondCode cond;      /* can be MIPScc_AL */
 702          Bool         toFastEP;  /* chain to the slow or fast point? */
 703       } XDirect;
 704       /* Boring transfer to a guest address not known at JIT time.
 705          Not chainable.  May be conditional. */
 706       struct {
 707          HReg        dstGA;
 708          MIPSAMode*   amPC;
 709          MIPSCondCode cond; /* can be MIPScc_AL */
 710       } XIndir;
 711       /* Assisted transfer to a guest address, most general case.
 712          Not chainable.  May be conditional. */
 713       struct {
 714          HReg        dstGA;
 715          MIPSAMode*   amPC;
 716          MIPSCondCode cond; /* can be MIPScc_AL */
 717          IRJumpKind  jk;
 718       } XAssisted;
 719       /* Zero extending loads.  Dst size is host word size */
 720       struct {
 721          UChar sz;   /* 1|2|4|8 */
 722          HReg dst;
 723          MIPSAMode *src;
 724       } Load;
 725       struct {
 726          HReg data;
 727          HReg addr;
 728       } MsaLoad;
 729       /* 64/32/16/8 bit stores */
 730       struct {
 731          UChar sz;   /* 1|2|4|8 */
 732          MIPSAMode *dst;
 733          HReg src;
 734       } Store;
 735       struct {
 736          UChar sz;   /* 4|8 */
 737          HReg dst;
 738          MIPSAMode *src;
 739       } LoadL;
 740       struct {
 741          UChar sz;   /* 4|8 */
 742          HReg  old;
 743          HReg  addr;
 744          HReg  expd;
 745          HReg  data;
 746       } Cas;
 747       struct {
 748          UChar sz;   /* 4|8 */
 749          MIPSAMode *dst;
 750          HReg src;
 751       } StoreC;
 752       /* Move from HI/LO register to GP register. */
 753       struct {
 754          HReg dst;
 755       } MfHL;
 756
 757       /* Move to HI/LO register from GP register. */
 758       struct {
 759          HReg src;
 760       } MtHL;
 761
 762       /* Read/Write Link Register */
 763       struct {
 764          Bool wrLR;
 765          HReg gpr;
 766       } RdWrLR;
 767
 768       /* MIPS Multiply and accumulate instructions. */
 769       struct {
 770          MIPSMaccOp op;
 771          Bool syned;
 772
 773          HReg srcL;
 774          HReg srcR;
 775       } Macc;
 776
 777       /* MIPS Floating point */
 778       struct {
 779          MIPSFpOp op;
 780          HReg dst;
 781          HReg src;
 782       } FpUnary;
 783       struct {
 784          MIPSFpOp op;
 785          HReg dst;
 786          HReg srcL;
 787          HReg srcR;
 788       } FpBinary;
 789       struct {
 790          MIPSFpOp op;
 791          HReg dst;
 792          HReg src1;
 793          HReg src2;
 794          HReg src3;
 795       } FpTernary;
 796       struct {
 797          MIPSFpOp op;
 798          HReg dst;
 799          HReg srcML;
 800          HReg srcMR;
 801          HReg srcAcc;
 802       } FpMulAcc;
 803       struct {
 804          Bool isLoad;
 805          UChar sz;   /* only 4 (IEEE single) or 8 (IEEE double) */
 806          HReg reg;
 807          MIPSAMode *addr;
 808       } FpLdSt;
 809
 810       struct {
 811          MIPSFpOp op;
 812          HReg dst;
 813          HReg src;
 814       } FpConvert;
 815       struct {
 816          MIPSFpOp op;
 817          HReg dst;
 818          HReg srcL;
 819          HReg srcR;
 820          UChar cond1;
 821       } FpCompare;
 822       struct {
 823          MIPSFpOp op;
 824          HReg dst;
 825          HReg srcL;
 826          HReg srcR;
 827       } FpMinMax;
 828       /* Move from GP register to FCSR register. */
 829       struct {
 830          HReg src;
 831       } MtFCSR;
 832       /* Move from FCSR register to GP register. */
 833       struct {
 834          HReg dst;
 835       } MfFCSR;
 836       struct {
 837          MIPSAMode* amCounter;
 838          MIPSAMode* amFailAddr;
 839       } EvCheck;
 840       struct {
 841          /* No fields.  The address of the counter to inc is
 842             installed later, post-translation, by patching it in,
 843             as it is not known at translation time. */
 844       } ProfInc;
 845
 846       /* Move from/to fpr to/from gpr */
 847       struct {
 848          MIPSFpGpMoveOp op;
 849          HReg dst;
 850          HReg src;
 851       } FpGpMove;
 852       struct {
 853          MIPSMoveCondOp op;
 854          HReg dst;
 855          HReg src;
 856          HReg cond;
 857       } MoveCond;
 858       struct {
 859          MSAMI10Op op;
 860          UInt s10;
 861          HReg rs;
 862          HReg wd;
 863          MSADF df;
 864       } MsaMi10;
 865       struct {
 866          MSAELMOp op;
 867          HReg ws;
 868          HReg wd;
 869          UInt dfn;
 870       } MsaElm;
 871       struct {
 872          MSA2ROp op;
 873          MSADF df;
 874          HReg ws;
 875          HReg wd;
 876       } Msa2R;
 877       struct {
 878          MSA3ROp op;
 879          MSADF df;
 880          HReg wt;
 881          HReg ws;
 882          HReg wd;
 883       } Msa3R;
 884       struct {
 885          MSAVECOp op;
 886          HReg wt;
 887          HReg ws;
 888          HReg wd;
 889       } MsaVec;
 890       struct {
 891          MSABITOp op;
 892          MSADF df;
 893          UChar ms;
 894          HReg ws;
 895          HReg wd;
 896       }MsaBit;
 897       struct {
 898          MSA3RFOp op;
 899          MSADFFlx df;
 900          HReg wt;
 901          HReg ws;
 902          HReg wd;
 903       } Msa3RF;
 904       struct {
 905          MSA2RFOp op;
 906          MSADFFlx df;
 907          HReg ws;
 908          HReg wd;
 909       } Msa2RF;
 910
 911    } Min;
 912 } MIPSInstr;
 913
 914 extern MIPSInstr *MIPSInstr_LI(HReg, ULong);
 915 extern MIPSInstr *MIPSInstr_Alu(MIPSAluOp, HReg, HReg, MIPSRH *);
 916 extern MIPSInstr *MIPSInstr_Shft(MIPSShftOp, Bool sz32, HReg, HReg, MIPSRH *);
 917 extern MIPSInstr *MIPSInstr_Unary(MIPSUnaryOp op, HReg dst, HReg src);
 918 extern MIPSInstr *MIPSInstr_Ext(HReg, HReg, UInt, UInt);
 919 extern MIPSInstr *MIPSInstr_Cmp(Bool, Bool, HReg, HReg, HReg, MIPSCondCode);
 920 extern MIPSInstr *MIPSInstr_Mul(HReg, HReg, HReg);
 921 extern MIPSInstr *MIPSInstr_Mult(Bool, HReg, HReg);
 922 extern MIPSInstr *MIPSInstr_Mulr6(Bool syned, Bool sz32, Bool low,
 923                                   HReg, HReg, HReg);
 924 extern MIPSInstr *MIPSInstr_Div(Bool syned, Bool sz32, HReg, HReg);
 925 extern MIPSInstr *MIPSInstr_Divr6(Bool syned, Bool sz32, Bool mod,
 926                                   HReg, HReg, HReg);
 927 extern MIPSInstr *MIPSInstr_Madd(Bool, HReg, HReg);
 928 extern MIPSInstr *MIPSInstr_Msub(Bool, HReg, HReg);
 929
 930 extern MIPSInstr *MIPSInstr_Load(UChar sz, HReg dst, MIPSAMode * src,
 931                                  Bool mode64);
 932 extern MIPSInstr *MIPSInstr_Store(UChar sz, MIPSAMode * dst, HReg src,
 933                                   Bool mode64);
 934
 935 extern MIPSInstr *MIPSInstr_LoadL(UChar sz, HReg dst, MIPSAMode * src,
 936                                   Bool mode64);
 937 extern MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src,
 938                                    Bool mode64);
 939 extern MIPSInstr *MIPSInstr_Cas(UChar sz, HReg old, HReg addr,
 940                                 HReg expd, HReg data, Bool mode64);
 941
 942 extern MIPSInstr *MIPSInstr_Call ( MIPSCondCode, Addr64, UInt, HReg, RetLoc );
 943 extern MIPSInstr *MIPSInstr_CallAlways ( MIPSCondCode, Addr64, UInt, RetLoc );
 944
 945 extern MIPSInstr *MIPSInstr_XDirect ( Addr64 dstGA, MIPSAMode* amPC,
 946                                       MIPSCondCode cond, Bool toFastEP );
 947 extern MIPSInstr *MIPSInstr_XIndir(HReg dstGA, MIPSAMode* amPC,
 948                                      MIPSCondCode cond);
 949 extern MIPSInstr *MIPSInstr_XAssisted(HReg dstGA, MIPSAMode* amPC,
 950                                       MIPSCondCode cond, IRJumpKind jk);
 951
 952 extern MIPSInstr *MIPSInstr_FpUnary(MIPSFpOp op, HReg dst, HReg src);
 953 extern MIPSInstr *MIPSInstr_FpBinary(MIPSFpOp op, HReg dst, HReg srcL,
 954                                      HReg srcR);
 955 extern MIPSInstr *MIPSInstr_FpTernary ( MIPSFpOp op, HReg dst, HReg src1,
 956                                         HReg src2, HReg src3 );
 957 extern MIPSInstr *MIPSInstr_FpConvert(MIPSFpOp op, HReg dst, HReg src);
 958 extern MIPSInstr *MIPSInstr_FpCompare(MIPSFpOp op, HReg dst, HReg srcL,
 959                                       HReg srcR);
 960 extern MIPSInstr *MIPSInstr_FpMinMax(MIPSFpOp op, HReg dst, HReg srcL,
 961                                       HReg srcR);
 962 extern MIPSInstr *MIPSInstr_FpMulAcc(MIPSFpOp op, HReg dst, HReg srcML,
 963                                      HReg srcMR, HReg srcAcc);
 964 extern MIPSInstr *MIPSInstr_FpLdSt(Bool isLoad, UChar sz, HReg, MIPSAMode *);
 965 extern MIPSInstr *MIPSInstr_FpSTFIW(HReg addr, HReg data);
 966 extern MIPSInstr *MIPSInstr_FpRSP(HReg dst, HReg src);
 967 extern MIPSInstr *MIPSInstr_FpCftI(Bool fromI, Bool int32, HReg dst, HReg src);
 968 extern MIPSInstr *MIPSInstr_FpCMov(MIPSCondCode, HReg dst, HReg src);
 969 extern MIPSInstr *MIPSInstr_MtFCSR(HReg src);
 970 extern MIPSInstr *MIPSInstr_MfFCSR(HReg dst);
 971 extern MIPSInstr *MIPSInstr_FpCmp(HReg dst, HReg srcL, HReg srcR);
 972
 973 extern MIPSInstr *MIPSInstr_Mfhi(HReg dst);
 974 extern MIPSInstr *MIPSInstr_Mflo(HReg dst);
 975 extern MIPSInstr *MIPSInstr_Mthi(HReg src);
 976 extern MIPSInstr *MIPSInstr_Mtlo(HReg src);
 977
 978 extern MIPSInstr *MIPSInstr_RdWrLR(Bool wrLR, HReg gpr);
 979
 980 extern MIPSInstr *MIPSInstr_MoveCond ( MIPSMoveCondOp op, HReg dst,
 981                                        HReg src, HReg cond );
 982
 983 extern MIPSInstr *MIPSInstr_FpGpMove ( MIPSFpGpMoveOp op, HReg dst, HReg src );
 984
 985 extern MIPSInstr *MIPSInstr_EvCheck(MIPSAMode* amCounter,
 986                                     MIPSAMode* amFailAddr );
 987 extern MIPSInstr *MIPSInstr_ProfInc( void );
 988
 989 extern MIPSInstr* MIPSInstr_MsaMi10(MSAMI10Op op, UInt s10, HReg rs, HReg wd, MSADF df);
 990 extern MIPSInstr* MIPSInstr_MsaElm(MSAELMOp op, HReg ws, HReg wd, UInt dfn);
 991 extern MIPSInstr* MIPSInstr_Msa3R(MSA3ROp op, MSADF df, HReg wd, HReg ws, HReg wt);
 992 extern MIPSInstr* MIPSInstr_Msa2R(MSA2ROp op, MSADF df, HReg ws, HReg wd);
 993 extern MIPSInstr* MIPSInstr_MsaVec(MSAVECOp op, HReg wt, HReg ws, HReg wd);
 994 extern MIPSInstr* MIPSInstr_MsaBit(MSABITOp op, MSADF df, UChar ms, HReg ws, HReg wd);
 995 extern MIPSInstr* MIPSInstr_Msa3RF(MSA3RFOp op, MSADFFlx df, HReg wd, HReg ws, HReg wt);
 996 extern MIPSInstr* MIPSInstr_Msa2RF(MSA2RFOp op, MSADFFlx df, HReg wd, HReg ws);
 997
 998 extern MIPSInstr* MIPSInstr_Bitswap(MIPSRotxOp, HReg, HReg, HReg, HReg, HReg);
 999
1000 extern void ppMIPSInstr(const MIPSInstr *, Bool mode64);
1001
1002 /* Some functions that insulate the register allocator from details
1003    of the underlying instruction set. */
1004 extern void getRegUsage_MIPSInstr (HRegUsage *, const MIPSInstr *, Bool);
1005 extern void mapRegs_MIPSInstr     (HRegRemap *, MIPSInstr *, Bool mode64);
1006 extern Int        emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc,
1007                                   UChar* buf, Int nbuf, const MIPSInstr* i,
1008                                   Bool mode64,
1009                                   VexEndness endness_host,
1010                                   const void* disp_cp_chain_me_to_slowEP,
1011                                   const void* disp_cp_chain_me_to_fastEP,
1012                                   const void* disp_cp_xindir,
1013                                   const void* disp_cp_xassisted );
1014
1015 extern void genSpill_MIPS ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
1016                             HReg rreg, Int offset, Bool);
1017 extern void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2,
1018                             HReg rreg, Int offset, Bool);
1019 extern MIPSInstr* genMove_MIPS(HReg from, HReg to, Bool mode64);
1020
1021 extern const RRegUniverse* getRRegUniverse_MIPS ( Bool mode64 );
1022
1023 extern HInstrArray *iselSB_MIPS          ( const IRSB*,
1024                                            VexArch,
1025                                            const VexArchInfo*,
1026                                            const VexAbiInfo*,
1027                                            Int offs_Host_EvC_Counter,
1028                                            Int offs_Host_EvC_FailAddr,
1029                                            Bool chainingAllowed,
1030                                            Bool addProfInc,
1031                                            Addr max_ga );
1032
1033 /* How big is an event check?  This is kind of a kludge because it
1034    depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER,
1035    and so assumes that they are both <= 128, and so can use the short
1036    offset encoding.  This is all checked with assertions, so in the
1037    worst case we will merely assert at startup. */
1038 extern Int evCheckSzB_MIPS (void);
1039
1040 /* Perform a chaining and unchaining of an XDirect jump. */
1041 extern VexInvalRange chainXDirect_MIPS ( VexEndness endness_host,
1042                                          void* place_to_chain,
1043                                          const void* disp_cp_chain_me_EXPECTED,
1044                                          const void* place_to_jump_to,
1045                                          Bool  mode64 );
1046
1047 extern VexInvalRange unchainXDirect_MIPS ( VexEndness endness_host,
1048                                            void* place_to_unchain,
1049                                            const void* place_to_jump_to_EXPECTED,
1050                                            const void* disp_cp_chain_me,
1051                                            Bool  mode64 );
1052
1053 /* Patch the counter location into an existing ProfInc point. */
1054 extern VexInvalRange patchProfInc_MIPS ( VexEndness endness_host,
1055                                          void*  place_to_patch,
1056                                          const ULong* location_of_counter,
1057                                          Bool  mode64 );
1058
1059
1060 #endif /* ndef __VEX_HOST_MIPS_DEFS_H */
1061
1062 /*---------------------------------------------------------------*/
1063 /*--- end                                    host-mips_defs.h ---*/
1064 /*---------------------------------------------------------------*/