| blob | 85805bb69b8b447d0d5cd362b1fd3e5b9b181c28 |
2 /*---------------------------------------------------------------*/
3 /*--- begin libvex_ir.h ---*/
4 /*---------------------------------------------------------------*/
6 /*
7 This file is part of Valgrind, a dynamic binary instrumentation
8 framework.
10 Copyright (C) 2004-2017 OpenWorks LLP
11 info@open-works.net
13 This program is free software; you can redistribute it and/or
14 modify it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 2 of the
16 License, or (at your option) any later version.
18 This program is distributed in the hope that it will be useful, but
19 WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, see <http://www.gnu.org/licenses/>.
26 The GNU General Public License is contained in the file COPYING.
28 Neither the names of the U.S. Department of Energy nor the
29 University of California nor the names of its contributors may be
30 used to endorse or promote products derived from this software
31 without prior written permission.
32 */
34 #ifndef __LIBVEX_IR_H
35 #define __LIBVEX_IR_H
40 /*---------------------------------------------------------------*/
41 /*--- High-level IR description ---*/
42 /*---------------------------------------------------------------*/
44 /* Vex IR is an architecture-neutral intermediate representation.
45 Unlike some IRs in systems similar to Vex, it is not like assembly
46 language (ie. a list of instructions). Rather, it is more like the
47 IR that might be used in a compiler.
49 Code blocks
50 ~~~~~~~~~~~
51 The code is broken into small code blocks ("superblocks", type:
52 'IRSB'). Each code block typically represents from 1 to perhaps 50
53 instructions. IRSBs are single-entry, multiple-exit code blocks.
54 Each IRSB contains three things:
55 - a type environment, which indicates the type of each temporary
56 value present in the IRSB
57 - a list of statements, which represent code
58 - a jump that exits from the end the IRSB
59 Because the blocks are multiple-exit, there can be additional
60 conditional exit statements that cause control to leave the IRSB
61 before the final exit. Also because of this, IRSBs can cover
62 multiple non-consecutive sequences of code (up to 3). These are
63 recorded in the type VexGuestExtents (see libvex.h).
65 Statements and expressions
66 ~~~~~~~~~~~~~~~~~~~~~~~~~~
67 Statements (type 'IRStmt') represent operations with side-effects,
68 eg. guest register writes, stores, and assignments to temporaries.
69 Expressions (type 'IRExpr') represent operations without
70 side-effects, eg. arithmetic operations, loads, constants.
71 Expressions can contain sub-expressions, forming expression trees,
72 eg. (3 + (4 * load(addr1)).
74 Storage of guest state
75 ~~~~~~~~~~~~~~~~~~~~~~
76 The "guest state" contains the guest registers of the guest machine
77 (ie. the machine that we are simulating). It is stored by default
78 in a block of memory supplied by the user of the VEX library,
79 generally referred to as the guest state (area). To operate on
80 these registers, one must first read ("Get") them from the guest
81 state into a temporary value. Afterwards, one can write ("Put")
82 them back into the guest state.
84 Get and Put are characterised by a byte offset into the guest
85 state, a small integer which effectively gives the identity of the
86 referenced guest register, and a type, which indicates the size of
87 the value to be transferred.
89 The basic "Get" and "Put" operations are sufficient to model normal
90 fixed registers on the guest. Selected areas of the guest state
91 can be treated as a circular array of registers (type:
92 'IRRegArray'), which can be indexed at run-time. This is done with
93 the "GetI" and "PutI" primitives. This is necessary to describe
94 rotating register files, for example the x87 FPU stack, SPARC
95 register windows, and the Itanium register files.
97 Examples, and flattened vs. unflattened code
98 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
99 For example, consider this x86 instruction:
101 addl %eax, %ebx
103 One Vex IR translation for this code would be this:
105 ------ IMark(0x24F275, 7, 0) ------
106 t3 = GET:I32(0) # get %eax, a 32-bit integer
107 t2 = GET:I32(12) # get %ebx, a 32-bit integer
108 t1 = Add32(t3,t2) # addl
109 PUT(0) = t1 # put %eax
111 (For simplicity, this ignores the effects on the condition codes, and
112 the update of the instruction pointer.)
114 The "IMark" is an IR statement that doesn't represent actual code.
115 Instead it indicates the address and length of the original
116 instruction. The numbers 0 and 12 are offsets into the guest state
117 for %eax and %ebx. The full list of offsets for an architecture
118 <ARCH> can be found in the type VexGuest<ARCH>State in the file
119 VEX/pub/libvex_guest_<ARCH>.h.
121 The five statements in this example are:
122 - the IMark
123 - three assignments to temporaries
124 - one register write (put)
126 The six expressions in this example are:
127 - two register reads (gets)
128 - one arithmetic (add) operation
129 - three temporaries (two nested within the Add32, one in the PUT)
131 The above IR is "flattened", ie. all sub-expressions are "atoms",
132 either constants or temporaries. An equivalent, unflattened version
133 would be:
135 PUT(0) = Add32(GET:I32(0), GET:I32(12))
137 IR is guaranteed to be flattened at instrumentation-time. This makes
138 instrumentation easier. Equivalent flattened and unflattened IR
139 typically results in the same generated code.
141 Another example, this one showing loads and stores:
143 addl %edx,4(%eax)
145 This becomes (again ignoring condition code and instruction pointer
146 updates):
148 ------ IMark(0x4000ABA, 3, 0) ------
149 t3 = Add32(GET:I32(0),0x4:I32)
150 t2 = LDle:I32(t3)
151 t1 = GET:I32(8)
152 t0 = Add32(t2,t1)
153 STle(t3) = t0
155 The "le" in "LDle" and "STle" is short for "little-endian".
157 No need for deallocations
158 ~~~~~~~~~~~~~~~~~~~~~~~~~
159 Although there are allocation functions for various data structures
160 in this file, there are no deallocation functions. This is because
161 Vex uses a memory allocation scheme that automatically reclaims the
162 memory used by allocated structures once translation is completed.
163 This makes things easier for tools that instruments/transforms code
164 blocks.
166 SSAness and typing
167 ~~~~~~~~~~~~~~~~~~
168 The IR is fully typed. For every IRSB (IR block) it is possible to
169 say unambiguously whether or not it is correctly typed.
170 Incorrectly typed IR has no meaning and the VEX will refuse to
171 process it. At various points during processing VEX typechecks the
172 IR and aborts if any violations are found. This seems overkill but
173 makes it a great deal easier to build a reliable JIT.
175 IR also has the SSA property. SSA stands for Static Single
176 Assignment, and what it means is that each IR temporary may be
177 assigned to only once. This idea became widely used in compiler
178 construction in the mid to late 90s. It makes many IR-level
179 transformations/code improvements easier, simpler and faster.
180 Whenever it typechecks an IR block, VEX also checks the SSA
181 property holds, and will abort if not so. So SSAness is
182 mechanically and rigidly enforced.
183 */
185 /*---------------------------------------------------------------*/
186 /*--- Type definitions for the IR ---*/
187 /*---------------------------------------------------------------*/
189 /* General comments about naming schemes:
191 All publically visible functions contain the name of the primary
192 type on which they operate (IRFoo, IRBar, etc). Hence you should
193 be able to identify these functions by grepping for "IR[A-Z]".
195 For some type 'IRFoo':
197 - ppIRFoo is the printing method for IRFoo, printing it to the
198 output channel specified in the LibVEX_Initialise call.
200 - eqIRFoo is a structural equality predicate for IRFoos.
202 - deepCopyIRFoo is a deep copy constructor for IRFoos.
203 It recursively traverses the entire argument tree and
204 produces a complete new tree. All types have a deep copy
205 constructor.
207 - shallowCopyIRFoo is the shallow copy constructor for IRFoos.
208 It creates a new top-level copy of the supplied object,
209 but does not copy any sub-objects. Only some types have a
210 shallow copy constructor.
211 */
213 /* ------------------ Types ------------------ */
215 /* A type indicates the size of a value, and whether it's an integer, a
216 float, or a vector (SIMD) value. */
217 typedef
220 Ity_I1,
221 Ity_I8,
222 Ity_I16,
223 Ity_I32,
224 Ity_I64,
234 Ity_V256 /* 256-bit SIMD */
235 }
236 IRType;
238 /* Pretty-print an IRType */
241 /* Get the size (in bytes) of an IRType */
244 /* Translate 1/2/4/8 into Ity_I{8,16,32,64} respectively. Asserts on
245 any other input. */
249 /* ------------------ Endianness ------------------ */
251 /* IREndness is used in load IRExprs and store IRStmts. */
252 typedef
255 Iend_BE /* big endian */
256 }
257 IREndness;
260 /* ------------------ Constants ------------------ */
262 /* IRConsts are used within 'Const' and 'Exit' IRExprs. */
264 /* The various kinds of constant. */
265 typedef
268 Ico_U8,
269 Ico_U16,
270 Ico_U32,
271 Ico_U64,
273 same encoding scheme as V128 */
276 as a IEEE754 single value. */
279 as a IEEE754 double value. */
281 (repeated 8 times) for each of the 16 x 1-byte lanes */
282 Ico_V256 /* 256-bit restricted vector constant, with 1 bit
283 (repeated 8 times) for each of the 32 x 1-byte lanes */
284 }
285 IRConstTag;
287 /* A constant. Stored as a tagged union. 'tag' indicates what kind of
288 constant this is. 'Ico' is the union that holds the fields. If an
289 IRConst 'c' has c.tag equal to Ico_U32, then it's a 32-bit constant,
290 and its value can be accessed with 'c.Ico.U32'. */
291 typedef
293 IRConstTag tag;
295 Bool U1;
296 UChar U8;
297 UShort U16;
298 UInt U32;
299 ULong U64;
300 UShort U128;
301 Float F32;
302 UInt F32i;
303 Double F64;
304 ULong F64i;
308 }
309 IRConst;
311 /* IRConst constructors */
325 /* Deep-copy an IRConst */
328 /* Pretty-print an IRConst */
331 /* Compare two IRConsts for equality */
335 /* ------------------ Call targets ------------------ */
337 /* Describes a helper function to call. The name part is purely for
338 pretty printing and not actually used. regparms=n tells the back
339 end that the callee has been declared
340 "__attribute__((regparm(n)))", although indirectly using the
341 VEX_REGPARM(n) macro. On some targets (x86) the back end will need
342 to construct a non-standard sequence to call a function declared
343 like this.
345 mcx_mask is a sop to Memcheck. It indicates which args should be
346 considered 'always defined' when lazily computing definedness of
347 the result. Bit 0 of mcx_mask corresponds to args[0], bit 1 to
348 args[1], etc. If a bit is set, the corresponding arg is excluded
349 (hence "x" in "mcx") from definedness checking.
350 */
352 typedef
354 Int regparms;
357 UInt mcx_mask;
358 }
359 IRCallee;
361 /* Create an IRCallee. */
364 /* Deep-copy an IRCallee. */
367 /* Pretty-print an IRCallee. */
371 /* ------------------ Guest state arrays ------------------ */
373 /* This describes a section of the guest state that we want to
374 be able to index at run time, so as to be able to describe
375 indexed or rotating register files on the guest. */
376 typedef
381 }
382 IRRegArray;
392 /* ------------------ Temporaries ------------------ */
394 /* This represents a temporary, eg. t1. The IR optimiser relies on the
395 fact that IRTemps are 32-bit ints. Do not change them to be ints of
396 any other size. */
399 /* Pretty-print an IRTemp. */
402 #define IRTemp_INVALID ((IRTemp)0xFFFFFFFF)
405 /* --------------- Primops (arity 1,2,3 and 4) --------------- */
407 /* Primitive operations that are used in Unop, Binop, Triop and Qop
408 IRExprs. Once we take into account integer, floating point and SIMD
409 operations of all the different sizes, there are quite a lot of them.
410 Most instructions supported by the architectures that Vex supports
411 (x86, PPC, etc) are represented. Some more obscure ones (eg. cpuid)
412 are not; they are instead handled with dirty helpers that emulate
413 their functionality. Such obscure ones are thus not directly visible
414 in the IR, but their effects on guest state (memory and registers)
415 are made visible via the annotations in IRDirty structures.
417 2018-Dec-27: some of int<->fp conversion operations have been renamed so as
418 to have a trailing _DEP, meaning "deprecated". This is because they don't
419 specify a rounding mode to be used for the conversion and so are
420 underspecified. Their use should be replaced with equivalents that do
421 specify a rounding mode, either as a first argument or using a suffix on the
422 name, that indicates the rounding mode to use.
423 */
424 typedef
426 /* -- Do not change this ordering. The IR generators rely on
427 (eg) Iop_Add64 == IopAdd8 + 3. -- */
432 /* Signless mul. MullS/MullU is elsewhere. */
440 /* Integer comparisons. */
443 /* Tags for unary ops */
446 /* Exactly like CmpEQ8/16/32/64, but carrying the additional
447 hint that these compute the success/failure of a CAS
448 operation, and hence are almost certainly applied to two
449 copies of the same value, which in turn has implications for
450 Memcheck's instrumentation. */
454 /* Exactly like CmpNE8/16/32/64, but carrying the additional
455 hint that these needs expensive definedness tracking. */
458 /* -- Ordering not important after here. -- */
460 /* Widening multiplies */
464 /* Counting bits */
465 /* Ctz64/Ctz32/Clz64/Clz32 are UNDEFINED when given arguments of zero.
466 You must ensure they are never given a zero argument. As of
467 2018-Nov-14 they are deprecated. Try to use the Nat variants
468 immediately below, if you can.
469 */
472 /* Count leading/trailing zeroes, with "natural" semantics for the
473 case where the input is zero: then the result is the number of bits
474 in the word. */
477 /* Population count -- compute the number of 1 bits in the argument. */
480 /* Standard integer comparisons */
486 /* As a sop to Valgrind-Memcheck, the following are useful. */
492 /* PowerPC-style 3-way integer comparisons. Without them it is
493 difficult to simulate PPC efficiently.
494 op(x,y) | x < y = 0x8 else
495 | x > y = 0x4 else
496 | x == y = 0x2
497 */
501 /* Division */
502 /* TODO: clarify semantics wrt rounding, negative values, whatever */
511 // concat with 32 0's (low))
514 // concat with 64 0's (low))
517 // concat with 128 0's (low))
521 // of which lo half is div and hi half is mod
525 // of which lo half is div and hi half is mod
529 // of which lo half is div and hi half is mod
531 // of which lo half is div and hi half is mod
533 // of which lo half is div and hi half is mod
535 // of which lo half is div and hi half is mod
540 /* Integer conversions. Some of these are redundant (eg
541 Iop_64to8 is the same as Iop_64to32 and then Iop_32to8), but
542 having a complete set reduces the typical dynamic size of IR
543 and makes the instruction selectors easier to write. */
545 /* Widening conversions */
548 Iop_32Uto64,
551 Iop_32Sto64,
553 /* Narrowing conversions */
555 /* 8 <-> 16 bit conversions */
559 /* 16 <-> 32 bit conversions */
563 /* 32 <-> 64 bit conversions */
567 /* 64 <-> 128 bit conversions */
571 /* 1-bit stuff */
585 /* ------ Floating point. We try to be IEEE754 compliant. ------ */
587 /* --- Simple stuff as mandated by 754. --- */
589 /* Binary operations, with rounding. */
590 /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
593 /* :: IRRoundingMode(I32) x F32 x F32 -> F32 */
596 /* Variants of the above which produce a 64-bit result but which
597 round their result to a IEEE float range first. */
598 /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
601 /* Unary operations, without rounding. */
602 /* :: F64 -> F64 */
605 /* :: F32 -> F32 */
608 /* :: F16 -> F16 */
611 /* Unary operations, with rounding. */
612 /* :: IRRoundingMode(I32) x F64 -> F64 */
613 Iop_SqrtF64,
615 /* :: IRRoundingMode(I32) x F32 -> F32 */
616 Iop_SqrtF32,
618 /* :: IRRoundingMode(I32) x F16 -> F16 */
619 Iop_SqrtF16,
621 /* :: IRRoundingMode(I32) x F16 x F16 -> F16 */
624 /* Comparison, yielding GT/LT/EQ/UN(ordered), as per the following:
625 0x45 Unordered
626 0x01 LT
627 0x00 GT
628 0x40 EQ
629 This just happens to be the Intel encoding. The values
630 are recorded in the type IRCmpF64Result.
631 */
632 /* :: F64 x F64 -> IRCmpF64Result(I32) */
633 Iop_CmpF64,
634 Iop_CmpF32,
635 Iop_CmpF16,
636 Iop_CmpF128,
638 /* --- Int to/from FP conversions. --- */
640 /* For the most part, these take a first argument :: Ity_I32 (as
641 IRRoundingMode) which is an indication of the rounding mode
642 to use, as per the following encoding ("the standard
643 encoding"):
644 00b to nearest (the default)
645 01b to -infinity
646 10b to +infinity
647 11b to zero
648 This just happens to be the Intel encoding. For reference only,
649 the PPC encoding is:
650 00b to nearest (the default)
651 01b to zero
652 10b to +infinity
653 11b to -infinity
654 Any PPC -> IR front end will have to translate these PPC
655 encodings, as encoded in the guest state, to the standard
656 encodings, to pass to the primops.
657 For reference only, the ARM VFP encoding is:
658 00b to nearest
659 01b to +infinity
660 10b to -infinity
661 11b to zero
662 Again, this will have to be converted to the standard encoding
663 to pass to primops.
665 If one of these conversions gets an out-of-range condition,
666 or a NaN, as an argument, the result is host-defined. On x86
667 the "integer indefinite" value 0x80..00 is produced. On PPC
668 it is either 0x80..00 or 0x7F..FF depending on the sign of
669 the argument.
671 On ARMvfp, when converting to a signed integer result, the
672 overflow result is 0x80..00 for negative args and 0x7F..FF
673 for positive args. For unsigned integer results it is
674 0x00..00 and 0xFF..FF respectively.
676 Rounding is required whenever the destination type cannot
677 represent exactly all values of the source type.
678 */
702 /* Conversion between floating point formats */
706 /* Reinterpretation. Take an F32/64/128 and produce an I32/64/128
707 with the same bit pattern, or vice versa. */
713 /* Support for 128-bit floating point */
718 /* :: IRRoundingMode(I32) x F128 x F128 -> F128 */
725 /* :: F128 -> F128 */
728 /* :: IRRoundingMode(I32) x F128 -> F128 */
729 Iop_SqrtF128,
749 /* Truncate to the specified value, source and result
750 * are stroed in a F128 register.
751 */
759 /* --- guest x86/amd64 specifics, not mandated by 754. --- */
761 /* Binary ops, with rounding. */
762 /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
771 /* Note that on x86 guest, PRem1{C3210} has the same behaviour
772 as the IEEE mandated RemF64, except it is limited in the
773 range of its operand. Hence the partialness. */
775 /* Unary ops, with rounding. */
776 /* :: IRRoundingMode(I32) x F64 -> F64 */
782 as F128) */
784 as F64) */
786 as F32) */
788 /* --- guest s390 specifics, not mandated by 754. --- */
790 /* Fused multiply-add/sub */
791 /* :: IRRoundingMode(I32) x F32 x F32 x F32 -> F32
792 (computes arg2 * arg3 +/- arg4) */
795 /* --- guest ppc32/64 specifics, not mandated by 754. --- */
797 /* Ternary operations, with rounding. */
798 /* Fused multiply-add/sub, with 112-bit intermediate
799 precision for ppc.
800 Also used to implement fused multiply-add/sub for s390. */
801 /* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64
802 (computes arg2 * arg3 +/- arg4) */
805 /* Variants of the above which produce a 64-bit result but which
806 round their result to a IEEE float range first. */
807 /* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64 */
810 /* :: F64 -> F64 */
817 /* :: F64 -> F32 */
820 /* :: IRRoundingMode(I32) x F64 -> F64 */
822 /* NB: pretty much the same as Iop_F64toF32, except no change
823 of type. */
825 /* --- guest arm64 specifics, not mandated by 754. --- */
830 /* --------- Possibly required by IEEE 754-2008. --------- */
837 /* ------------------ 16-bit scalar FP ------------------ */
845 /* ------------------ 32-bit SIMD Integer ------------------ */
847 /* 32x1 saturating add/sub (ok, well, not really SIMD :) */
848 Iop_QAdd32S,
849 Iop_QSub32S,
851 /* 16x2 add/sub, also signed/unsigned saturating variants */
856 /* 16x2 signed/unsigned halving add/sub. For each lane, these
857 compute bits 16:1 of (eg) sx(argL) + sx(argR),
858 or zx(argL) - zx(argR) etc. */
862 /* 8x4 add/sub, also signed/unsigned saturating variants */
867 /* 8x4 signed/unsigned halving add/sub. For each lane, these
868 compute bits 8:1 of (eg) sx(argL) + sx(argR),
869 or zx(argL) - zx(argR) etc. */
873 /* 8x4 sum of absolute unsigned differences. */
874 Iop_Sad8Ux4,
876 /* MISC (vector integer cmp != 0) */
879 /* Byte swap in a 32-bit word */
880 Iop_Reverse8sIn32_x1,
882 /* ------------------ 64-bit SIMD FP ------------------------ */
884 /* Conversion to/from int */
885 // Deprecated: these don't specify a rounding mode
890 /* Fixed32 format is floating-point number with fixed number of fraction
891 bits. The number of fraction bits is passed as a second argument of
892 type I8. */
896 /* Binary operations */
898 /* Pairwise Min and Max. See integer pairwise operations for more
899 details. */
901 /* Note: For the following compares, the arm front-end assumes a
902 nan in a lane of either argument returns zero for that lane. */
905 /* Vector Reciprocal Estimate finds an approximate reciprocal of each
906 element in the operand vector, and places the results in the destination
907 vector. */
908 Iop_RecipEst32Fx2,
910 /* Vector Reciprocal Step computes (2.0 - arg1 * arg2).
911 Note, that if one of the arguments is zero and another one is infinity
912 of arbitrary sign the result of the operation is 2.0. */
913 Iop_RecipStep32Fx2,
915 /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal
916 square root of each element in the operand vector. */
917 Iop_RSqrtEst32Fx2,
919 /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
920 Note, that of one of the arguments is zero and another one is infiinty
921 of arbitrary sign the result of the operation is 1.5. */
922 Iop_RSqrtStep32Fx2,
924 /* Unary */
927 /* ------------------ 64-bit SIMD Integer. ------------------ */
929 /* MISC (vector integer cmp != 0) */
932 /* ADDITION (normal / unsigned sat / signed sat) */
937 /* PAIRWISE operations */
938 /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) =
939 [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */
945 /* Longening variant is unary. The resulting vector contains two times
946 less elements than operand, but they are two times wider.
947 Example:
948 Iop_PAddL16Ux4( [a,b,c,d] ) = [a+b,c+d]
949 where a+b and c+d are unsigned 32-bit values. */
953 /* SUBTRACTION (normal / unsigned sat / signed sat) */
958 /* ABSOLUTE VALUE */
961 /* MULTIPLICATION (normal / high half of signed/unsigned / plynomial ) */
963 Iop_Mul32Fx2,
964 Iop_MulHi16Ux4,
965 Iop_MulHi16Sx4,
966 /* Plynomial multiplication treats it's arguments as coefficients of
967 polynoms over {0, 1}. */
968 Iop_PolynomialMul8x8,
970 /* Vector Saturating Doubling Multiply Returning High Half and
971 Vector Saturating Rounding Doubling Multiply Returning High Half */
972 /* These IROp's multiply corresponding elements in two vectors, double
973 the results, and place the most significant half of the final results
974 in the destination vector. The results are truncated or rounded. If
975 any of the results overflow, they are saturated. */
979 /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
980 Iop_Avg8Ux8,
981 Iop_Avg16Ux4,
983 /* MIN/MAX */
989 /* COMPARISON */
994 /* COUNT ones / leading zeroes / leading sign bits (not including topmost
995 bit) */
996 Iop_Cnt8x8,
999 Iop_Clz64x2,
1001 /*Vector COUNT trailing zeros */
1004 /* VECTOR x VECTOR SHIFT / ROTATE */
1010 /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
1015 /* VECTOR x VECTOR SATURATING SHIFT */
1018 /* VECTOR x INTEGER SATURATING SHIFT */
1026 /* NARROWING (binary)
1027 -- narrow 2xI64 into 1xI64, hi half from left arg */
1028 /* For saturated narrowing, I believe there are 4 variants of
1029 the basic arithmetic operation, depending on the signedness
1030 of argument and result. Here are examples that exemplify
1031 what I mean:
1033 QNarrow16Uto8U ( UShort x ) if (x >u 255) x = 255;
1034 return x[7:0];
1036 QNarrow16Sto8S ( Short x ) if (x <s -128) x = -128;
1037 if (x >s 127) x = 127;
1038 return x[7:0];
1040 QNarrow16Uto8S ( UShort x ) if (x >u 127) x = 127;
1041 return x[7:0];
1043 QNarrow16Sto8U ( Short x ) if (x <s 0) x = 0;
1044 if (x >s 255) x = 255;
1045 return x[7:0];
1046 */
1047 Iop_QNarrowBin16Sto8Ux8,
1051 /* INTERLEAVING */
1052 /* Interleave lanes from low or high halves of
1053 operands. Most-significant result lane is from the left
1054 arg. */
1057 /* Interleave odd/even lanes of operands. Most-significant result lane
1058 is from the left arg. Note that Interleave{Odd,Even}Lanes32x2 are
1059 identical to Interleave{HI,LO}32x2 and so are omitted.*/
1063 /* CONCATENATION -- build a new value by concatenating either
1064 the even or odd lanes of both operands. Note that
1065 Cat{Odd,Even}Lanes32x2 are identical to Interleave{HI,LO}32x2
1066 and so are omitted. */
1070 /* GET / SET elements of VECTOR
1071 GET is binop (I64, I8) -> I<elem_size>
1072 SET is triop (I64, I8, I<elem_size>) -> I64 */
1073 /* Note: the arm back-end handles only constant second argument */
1077 /* DUPLICATING -- copy value to all lanes */
1080 /* SLICE -- produces the lowest 64 bits of (arg1:arg2) >> (8 * arg3).
1081 arg3 is a shift amount in bytes and may be between 0 and 8
1082 inclusive. When 0, the result is arg2; when 8, the result is arg1.
1083 Not all back ends handle all values. The arm32 and arm64 back
1084 ends handle only immediate arg3 values. */
1087 /* REVERSE the order of chunks in vector lanes. Chunks must be
1088 smaller than the vector lanes (obviously) and so may be 8-, 16- and
1089 32-bit in size. Note that the degenerate case,
1090 Iop_Reverse8sIn64_x1, is a simply a vanilla byte-swap. */
1091 /* Examples:
1092 Reverse8sIn16_x4([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g]
1093 Reverse8sIn32_x2([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e]
1094 Reverse8sIn64_x1([a,b,c,d,e,f,g,h]) = [h,g,f,e,d,c,b,a] */
1095 Iop_Reverse8sIn16_x4,
1099 /* PERMUTING -- copy src bytes to dst,
1100 as indexed by control vector bytes:
1101 for i in 0 .. 7 . result[i] = argL[ argR[i] ]
1102 argR[i] values may only be in the range 0 .. 7, else behaviour
1103 is undefined. That is, argR[i][7:3] must be zero. */
1104 Iop_Perm8x8,
1106 /* PERMUTING with optional zeroing:
1107 for i in 0 .. 7 . result[i] = if argR[i] bit 7 is set
1108 then zero else argL[ argR[i] ]
1109 argR[i][6:3] must be zero, else behaviour is undefined.
1110 */
1111 Iop_PermOrZero8x8,
1113 /* MISC CONVERSION -- get high bits of each byte lane, a la
1114 x86/amd64 pmovmskb */
1117 /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate
1118 See floating-point equivalents for details. */
1121 /* ------------------ Decimal Floating Point ------------------ */
1123 /* ARITHMETIC INSTRUCTIONS 64-bit
1124 ----------------------------------
1125 IRRoundingMode(I32) X D64 X D64 -> D64
1126 */
1129 /* ARITHMETIC INSTRUCTIONS 128-bit
1130 ----------------------------------
1131 IRRoundingMode(I32) X D128 X D128 -> D128
1132 */
1135 /* SHIFT SIGNIFICAND INSTRUCTIONS
1136 * The DFP significand is shifted by the number of digits specified
1137 * by the U8 operand. Digits shifted out of the leftmost digit are
1138 * lost. Zeros are supplied to the vacated positions on the right.
1139 * The sign of the result is the same as the sign of the original
1140 * operand.
1141 *
1142 * D64 x U8 -> D64 left shift and right shift respectively */
1145 /* D128 x U8 -> D128 left shift and right shift respectively */
1149 /* FORMAT CONVERSION INSTRUCTIONS
1150 * D32 -> D64
1151 */
1152 Iop_D32toD64,
1154 /* D64 -> D128 */
1155 Iop_D64toD128,
1157 /* I32S -> D128 */
1158 Iop_I32StoD128,
1160 /* I32U -> D128 */
1161 Iop_I32UtoD128,
1163 /* I64S -> D128 */
1164 Iop_I64StoD128,
1166 /* I64U -> D128 */
1167 Iop_I64UtoD128,
1169 /* IRRoundingMode(I32) x I128S -> D128 */
1170 Iop_I128StoD128,
1172 /* IRRoundingMode(I32) x D64 -> D32 */
1173 Iop_D64toD32,
1175 /* IRRoundingMode(I32) x D128 -> D64 */
1176 Iop_D128toD64,
1178 /* I32S -> D64 */
1179 Iop_I32StoD64,
1181 /* I32U -> D64 */
1182 Iop_I32UtoD64,
1184 /* IRRoundingMode(I32) x I64 -> D64 */
1185 Iop_I64StoD64,
1187 /* IRRoundingMode(I32) x I64 -> D64 */
1188 Iop_I64UtoD64,
1190 /* IRRoundingMode(I32) x D64 -> I32 */
1191 Iop_D64toI32S,
1193 /* IRRoundingMode(I32) x D64 -> I32 */
1194 Iop_D64toI32U,
1196 /* IRRoundingMode(I32) x D64 -> I64 */
1197 Iop_D64toI64S,
1199 /* IRRoundingMode(I32) x D64 -> I64 */
1200 Iop_D64toI64U,
1202 /* IRRoundingMode(I32) x D128 -> I32 */
1203 Iop_D128toI32S,
1205 /* IRRoundingMode(I32) x D128 -> I32 */
1206 Iop_D128toI32U,
1208 /* IRRoundingMode(I32) x D128 -> I64 */
1209 Iop_D128toI64S,
1211 /* IRRoundingMode(I32) x D128 -> I64 */
1212 Iop_D128toI64U,
1214 /* IRRoundingMode(I32) x D128 -> I128 */
1215 Iop_D128toI128S,
1217 /* IRRoundingMode(I32) x F32 -> D32 */
1218 Iop_F32toD32,
1220 /* IRRoundingMode(I32) x F32 -> D64 */
1221 Iop_F32toD64,
1223 /* IRRoundingMode(I32) x F32 -> D128 */
1224 Iop_F32toD128,
1226 /* IRRoundingMode(I32) x F64 -> D32 */
1227 Iop_F64toD32,
1229 /* IRRoundingMode(I32) x F64 -> D64 */
1230 Iop_F64toD64,
1232 /* IRRoundingMode(I32) x F64 -> D128 */
1233 Iop_F64toD128,
1235 /* IRRoundingMode(I32) x F128 -> D32 */
1236 Iop_F128toD32,
1238 /* IRRoundingMode(I32) x F128 -> D64 */
1239 Iop_F128toD64,
1241 /* IRRoundingMode(I32) x F128 -> D128 */
1242 Iop_F128toD128,
1244 /* IRRoundingMode(I32) x D32 -> F32 */
1245 Iop_D32toF32,
1247 /* IRRoundingMode(I32) x D32 -> F64 */
1248 Iop_D32toF64,
1250 /* IRRoundingMode(I32) x D32 -> F128 */
1251 Iop_D32toF128,
1253 /* IRRoundingMode(I32) x D64 -> F32 */
1254 Iop_D64toF32,
1256 /* IRRoundingMode(I32) x D64 -> F64 */
1257 Iop_D64toF64,
1259 /* IRRoundingMode(I32) x D64 -> F128 */
1260 Iop_D64toF128,
1262 /* IRRoundingMode(I32) x D128 -> F32 */
1263 Iop_D128toF32,
1265 /* IRRoundingMode(I32) x D128 -> F64 */
1266 Iop_D128toF64,
1268 /* IRRoundingMode(I32) x D128 -> F128 */
1269 Iop_D128toF128,
1271 /* ROUNDING INSTRUCTIONS
1272 * IRRoundingMode(I32) x D64 -> D64
1273 * The D64 operand, if a finite number, it is rounded to a
1274 * floating point integer value, i.e. no fractional part.
1275 */
1276 Iop_RoundD64toInt,
1278 /* IRRoundingMode(I32) x D128 -> D128 */
1279 Iop_RoundD128toInt,
1281 /* COMPARE INSTRUCTIONS
1282 * D64 x D64 -> IRCmpD64Result(I32) */
1283 Iop_CmpD64,
1285 /* D128 x D128 -> IRCmpD128Result(I32) */
1286 Iop_CmpD128,
1288 /* COMPARE BIASED EXPONENET INSTRUCTIONS
1289 * D64 x D64 -> IRCmpD64Result(I32) */
1290 Iop_CmpExpD64,
1292 /* D128 x D128 -> IRCmpD128Result(I32) */
1293 Iop_CmpExpD128,
1295 /* QUANTIZE AND ROUND INSTRUCTIONS
1296 * The source operand is converted and rounded to the form with the
1297 * immediate exponent specified by the rounding and exponent parameter.
1298 *
1299 * The second operand is converted and rounded to the form
1300 * of the first operand's exponent and the rounded based on the specified
1301 * rounding mode parameter.
1302 *
1303 * IRRoundingMode(I32) x D64 x D64-> D64 */
1304 Iop_QuantizeD64,
1306 /* IRRoundingMode(I32) x D128 x D128 -> D128 */
1307 Iop_QuantizeD128,
1309 /* IRRoundingMode(I32) x I8 x D64 -> D64
1310 * The Decimal Floating point operand is rounded to the requested
1311 * significance given by the I8 operand as specified by the rounding
1312 * mode.
1313 */
1314 Iop_SignificanceRoundD64,
1316 /* IRRoundingMode(I32) x I8 x D128 -> D128 */
1317 Iop_SignificanceRoundD128,
1319 /* EXTRACT AND INSERT INSTRUCTIONS
1320 * D64 -> I64
1321 * The exponent of the D32 or D64 operand is extracted. The
1322 * extracted exponent is converted to a 64-bit signed binary integer.
1323 */
1324 Iop_ExtractExpD64,
1326 /* D128 -> I64 */
1327 Iop_ExtractExpD128,
1329 /* D64 -> I64
1330 * The number of significand digits of the D64 operand is extracted.
1331 * The number is stored as a 64-bit signed binary integer.
1332 */
1333 Iop_ExtractSigD64,
1335 /* D128 -> I64 */
1336 Iop_ExtractSigD128,
1338 /* I64 x D64 -> D64
1339 * The exponent is specified by the first I64 operand the signed
1340 * significand is given by the second I64 value. The result is a D64
1341 * value consisting of the specified significand and exponent whose
1342 * sign is that of the specified significand.
1343 */
1344 Iop_InsertExpD64,
1346 /* I64 x D128 -> D128 */
1347 Iop_InsertExpD128,
1349 /* Support for 128-bit DFP type */
1352 /* I64 -> I64
1353 * Convert 50-bit densely packed BCD string to 60 bit BCD string
1354 */
1355 Iop_DPBtoBCD,
1357 /* I64 -> I64
1358 * Convert 60 bit BCD string to 50-bit densely packed BCD string
1359 */
1360 Iop_BCDtoDPB,
1362 /* BCD arithmetic instructions, (V128, V128) -> V128
1363 * The BCD format is the same as that used in the BCD<->DPB conversion
1364 * routines, except using 124 digits (vs 60) plus the trailing 4-bit
1365 * signed code. */
1368 /* Conversion signed 128-bit integer to signed BCD 128-bit */
1369 Iop_I128StoBCD128,
1371 /* Conversion signed BCD 128-bit to 128-bit integer */
1372 Iop_BCD128toI128S,
1374 /* Conversion I64 -> D64 */
1375 Iop_ReinterpI64asD64,
1377 /* Conversion D64 -> I64 */
1378 Iop_ReinterpD64asI64,
1380 /* ------------------ 128-bit SIMD FP. ------------------ */
1382 /* --- 16x8 vector FP --- */
1384 /* binary :: IRRoundingMode(I32) x V128 -> V128 */
1385 Iop_Sqrt16Fx8,
1387 /* ternary :: IRRoundingMode(I32) x V128 x V128 -> V128 */
1390 /* binary */
1393 /* unary */
1394 Iop_Abs16Fx8,
1395 Iop_Neg16Fx8,
1397 /* --- 32x4 vector FP --- */
1399 /* ternary :: IRRoundingMode(I32) x V128 x V128 -> V128 */
1402 /* binary */
1405 /* Note: For the following compares, the ppc and arm front-ends assume a
1406 nan in a lane of either argument returns zero for that lane. */
1410 /* Pairwise Max and Min. See integer pairwise operations for details. */
1413 /* unary */
1414 Iop_Abs32Fx4,
1415 Iop_Neg32Fx4,
1417 /* binary :: IRRoundingMode(I32) x V128 -> V128 */
1418 Iop_Sqrt32Fx4,
1420 /* Vector Reciprocal Estimate finds an approximate reciprocal of each
1421 element in the operand vector, and places the results in the
1422 destination vector. */
1423 Iop_RecipEst32Fx4,
1425 /* Vector Reciprocal Step computes (2.0 - arg1 * arg2).
1426 Note, that if one of the arguments is zero and another one is infinity
1427 of arbitrary sign the result of the operation is 2.0. */
1428 Iop_RecipStep32Fx4,
1430 /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal
1431 square root of each element in the operand vector. */
1432 Iop_RSqrtEst32Fx4,
1434 /* Scaling of vector with a power of 2 (wd[i] <- ws[i] * 2^wt[i]) */
1435 Iop_Scale2_32Fx4,
1437 /* Vector floating-point base 2 logarithm */
1438 Iop_Log2_32Fx4,
1440 /* Vector floating-point exponential 2^x */
1441 Iop_Exp2_32Fx4,
1443 /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
1444 Note, that of one of the arguments is zero and another one is infiinty
1445 of arbitrary sign the result of the operation is 1.5. */
1446 Iop_RSqrtStep32Fx4,
1448 /* --- Int to/from FP conversion --- */
1449 /* Unlike the standard fp conversions, these irops take no
1450 rounding mode argument. Instead the irop trailers _R{M,P,N,Z}
1451 indicate the mode: {-inf, +inf, nearest, zero} respectively. */
1453 // These carry no rounding mode and are therefore deprecated
1463 /* Fixed32 format is floating-point number with fixed number of fraction
1464 bits. The number of fraction bits is passed as a second argument of
1465 type I8. */
1469 /* --- Single to/from half conversion --- */
1470 /* FIXME: what kind of rounding in F32x4 -> F16x4 case? */
1471 // FIXME these carry no rounding mode
1476 /* -- Double to/from half conversion -- */
1478 Iop_F16toF64x2,
1480 /* Values from two registers converted in smaller type and put in one
1481 IRRoundingMode(I32) x (F32x4 | F32x4) -> Q16x8 */
1482 Iop_F32x4_2toQ16x8,
1485 /* --- 32x4 lowest-lane-only scalar FP --- */
1487 /* In binary cases, upper 3/4 is copied from first operand. In
1488 unary cases, upper 3/4 is copied from the operand. */
1490 /* binary */
1495 /* unary */
1498 /* --- 64x2 vector FP --- */
1500 /* ternary :: IRRoundingMode(I32) x V128 x V128 -> V128 */
1503 /* binary */
1507 /* unary */
1508 Iop_Abs64Fx2,
1509 Iop_Neg64Fx2,
1511 /* binary :: IRRoundingMode(I32) x V128 -> V128 */
1512 Iop_Sqrt64Fx2,
1514 /* Scaling of vector with a power of 2 (wd[i] <- ws[i] * 2^wt[i]) */
1515 Iop_Scale2_64Fx2,
1517 /* Vector floating-point base 2 logarithm */
1518 Iop_Log2_64Fx2,
1520 /* see 32Fx4 variants for description */
1527 /* Values from two registers converted in smaller type and put in one
1528 IRRoundingMode(I32) x (F64x2 | F64x2) -> Q32x4 */
1529 Iop_F64x2_2toQ32x4,
1531 /* --- 64x2 lowest-lane-only scalar FP --- */
1533 /* In binary cases, upper half is copied from first operand. In
1534 unary cases, upper half is copied from the operand. */
1536 /* binary */
1541 /* unary */
1542 Iop_Sqrt64F0x2,
1544 /* --- pack / unpack --- */
1546 /* 64 <-> 128 bit vector */
1551 Iop_64UtoV128,
1552 Iop_SetV128lo64,
1554 /* Copies lower 64/32/16/8 bits, zeroes out the rest. */
1560 /* 32 <-> 128 bit vector */
1561 Iop_32UtoV128,
1565 /* ------------------ 128-bit SIMD Integer. ------------------ */
1567 /* BITWISE OPS */
1568 Iop_NotV128,
1571 /* VECTOR SHIFT (shift amt :: Ity_I8) */
1574 /* MISC (vector integer cmp != 0) */
1576 Iop_CmpNEZ128x1,
1578 /* ADDITION (normal / U->U sat / S->S sat) */
1583 /* ADDITION, ARM64 specific saturating variants. */
1584 /* Unsigned widen left arg, signed widen right arg, add, saturate S->S.
1585 This corresponds to SUQADD. */
1588 /* Signed widen left arg, unsigned widen right arg, add, saturate U->U.
1589 This corresponds to USQADD. */
1593 /* SUBTRACTION (normal / unsigned sat / signed sat) */
1598 /* MULTIPLICATION (normal / high half of signed/unsigned) */
1602 /* (widening signed/unsigned of even lanes, with lowest lane=zero) */
1606 /* Widening multiplies, all of the form (I64, I64) -> V128 */
1611 /* Signed doubling saturating widening multiplies, (I64, I64) -> V128 */
1614 /* Vector Saturating Doubling Multiply Returning High Half and
1615 Vector Saturating Rounding Doubling Multiply Returning High Half.
1616 These IROps multiply corresponding elements in two vectors, double
1617 the results, and place the most significant half of the final results
1618 in the destination vector. The results are truncated or rounded. If
1619 any of the results overflow, they are saturated. To be more precise,
1620 for each lane, the computed result is:
1621 QDMulHi:
1622 hi-half( sign-extend(laneL) *q sign-extend(laneR) *q 2 )
1623 QRDMulHi:
1624 hi-half( sign-extend(laneL) *q sign-extend(laneR) *q 2
1625 +q (1 << (lane-width-in-bits - 1)) )
1626 */
1630 /* Polynomial multiplication treats its arguments as
1631 coefficients of polynomials over {0, 1}. */
1635 /* Vector Polynomial multiplication add. (V128, V128) -> V128
1637 *** Below is the algorithm for the instructions. These Iops could
1638 be emulated to get this functionality, but the emulation would
1639 be long and messy.
1641 Example for polynomial multiply add for vector of bytes
1642 do i = 0 to 15
1643 prod[i].bit[0:14] <- 0
1644 srcA <- VR[argL].byte[i]
1645 srcB <- VR[argR].byte[i]
1646 do j = 0 to 7
1647 do k = 0 to j
1648 gbit <- srcA.bit[k] & srcB.bit[j-k]
1649 prod[i].bit[j] <- prod[i].bit[j] ^ gbit
1650 end
1651 end
1653 do j = 8 to 14
1654 do k = j-7 to 7
1655 gbit <- (srcA.bit[k] & srcB.bit[j-k])
1656 prod[i].bit[j] <- prod[i].bit[j] ^ gbit
1657 end
1658 end
1659 end
1661 do i = 0 to 7
1662 VR[dst].hword[i] <- 0b0 || (prod[2×i] ^ prod[2×i+1])
1663 end
1664 */
1668 /* PAIRWISE operations */
1669 /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) =
1670 [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */
1672 Iop_PwAdd32Fx2,
1674 /* Longening variant is unary. The resulting vector contains two times
1675 less elements than operand, but they are two times wider.
1676 Example:
1677 Iop_PwAddL16Ux4( [a,b,c,d] ) = [a+b,c+d]
1678 where a+b and c+d are unsigned 32-bit values. */
1682 /* This is amd64 PMADDUBSW, (V128, V128) -> V128. For each adjacent pair
1683 of bytes [a,b] in the first arg and [c,d] in the second, computes:
1684 signed/signed sat to 16 bits ( zxTo16(a) * sxTo16(b)
1685 + zxTo16(c) * sxTo16(d) )
1686 This exists because it's frequently used and there's no reasonably
1687 concise way to express it using other IROps.
1688 */
1689 Iop_PwExtUSMulQAdd8x16,
1691 /* Other unary pairwise ops */
1693 /* Vector bit matrix transpose. (V128) -> V128 */
1694 /* For each doubleword element of the source vector, an 8-bit x 8-bit
1695 * matrix transpose is performed. */
1696 Iop_PwBitMtxXpose64x2,
1698 /* ABSOLUTE VALUE */
1701 /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
1705 /* MIN/MAX */
1711 /* COMPARISON */
1716 /* COUNT ones / leading zeroes / leading sign bits (not including topmost
1717 bit) */
1718 Iop_Cnt8x16,
1722 /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
1727 /* VECTOR x VECTOR SHIFT / ROTATE */
1728 /* FIXME: I'm pretty sure the ARM32 front/back ends interpret these
1729 differently from all other targets. The intention is that
1730 the shift amount (2nd arg) is interpreted as unsigned and
1731 only the lowest log2(lane-bits) bits are relevant. But the
1732 ARM32 versions treat the shift amount as an 8 bit signed
1733 number. The ARM32 uses should be replaced by the relevant
1734 vector x vector bidirectional shifts instead. */
1741 /* VECTOR x VECTOR SATURATING SHIFT */
1744 /* VECTOR x INTEGER SATURATING SHIFT */
1752 /* VECTOR x VECTOR BIDIRECTIONAL SATURATING (& MAYBE ROUNDING) SHIFT */
1753 /* All of type (V128, V128) -> V256. */
1754 /* The least significant 8 bits of each lane of the second
1755 operand are used as the shift amount, and interpreted signedly.
1756 Positive values mean a shift left, negative a shift right. The
1757 result is signedly or unsignedly saturated. There are also
1758 rounding variants, which add 2^(shift_amount-1) to the value before
1759 shifting, but only in the shift-right case. Vacated positions
1760 are filled with zeroes. IOW, it's either SHR or SHL, but not SAR.
1762 These operations return 129 bits: one bit ("Q") indicating whether
1763 saturation occurred, and the shift result. The result type is V256,
1764 of which the lower V128 is the shift result, and Q occupies the
1765 least significant bit of the upper V128. All other bits of the
1766 upper V128 are zero. */
1767 // Unsigned saturation, no rounding
1770 // Signed saturation, no rounding
1774 // Unsigned saturation, rounding
1777 // Signed saturation, rounding
1781 /* VECTOR x VECTOR BIDIRECTIONAL (& MAYBE ROUNDING) SHIFT */
1782 /* All of type (V128, V128) -> V128 */
1783 /* The least significant 8 bits of each lane of the second
1784 operand are used as the shift amount, and interpreted signedly.
1785 Positive values mean a shift left, negative a shift right.
1786 There are also rounding variants, which add 2^(shift_amount-1)
1787 to the value before shifting, but only in the shift-right case.
1789 For left shifts, the vacated places are filled with zeroes.
1790 For right shifts, the vacated places are filled with zeroes
1791 for the U variants and sign bits for the S variants. */
1792 // Signed and unsigned, non-rounding
1796 // Signed and unsigned, rounding
1800 /* The least significant 8 bits of each lane of the second
1801 operand are used as the shift amount, and interpreted signedly.
1802 Positive values mean a shift left, negative a shift right. The
1803 result is signedly or unsignedly saturated. There are also
1804 rounding variants, which add 2^(shift_amount-1) to the value before
1805 shifting, but only in the shift-right case. Vacated positions
1806 are filled with zeroes. IOW, it's either SHR or SHL, but not SAR.
1807 */
1809 /* VECTOR x SCALAR SATURATING (& MAYBE ROUNDING) NARROWING SHIFT RIGHT */
1810 /* All of type (V128, I8) -> V128 */
1811 /* The first argument is shifted right, then narrowed to half the width
1812 by saturating it. The second argument is a scalar shift amount that
1813 applies to all lanes, and must be a value in the range 1 to lane_width.
1814 The shift may be done signedly (Sar variants) or unsignedly (Shr
1815 variants). The saturation is done according to the two signedness
1816 indicators at the end of the name. For example 64Sto32U means a
1817 signed 64 bit value is saturated into an unsigned 32 bit value.
1818 Additionally, the QRS variants do rounding, that is, they add the
1819 value (1 << (shift_amount-1)) to each source lane before shifting.
1821 These operations return 65 bits: one bit ("Q") indicating whether
1822 saturation occurred, and the shift result. The result type is V128,
1823 of which the lower half is the shift result, and Q occupies the
1824 least significant bit of the upper half. All other bits of the
1825 upper half are zero. */
1826 // No rounding, sat U->U
1827 Iop_QandQShrNnarrow16Uto8Ux8,
1829 // No rounding, sat S->S
1830 Iop_QandQSarNnarrow16Sto8Sx8,
1832 // No rounding, sat S->U
1833 Iop_QandQSarNnarrow16Sto8Ux8,
1836 // Rounding, sat U->U
1837 Iop_QandQRShrNnarrow16Uto8Ux8,
1839 // Rounding, sat S->S
1840 Iop_QandQRSarNnarrow16Sto8Sx8,
1842 // Rounding, sat S->U
1843 Iop_QandQRSarNnarrow16Sto8Ux8,
1846 /* NARROWING (binary)
1847 -- narrow 2xV128 into 1xV128, hi half from left arg */
1848 /* See comments above w.r.t. U vs S issues in saturated narrowing. */
1854 Iop_NarrowBin64to32x4,
1856 /* NARROWING (unary) -- narrow V128 into I64 */
1858 /* Saturating narrowing from signed source to signed/unsigned
1859 destination */
1862 /* Saturating narrowing from unsigned source to unsigned destination */
1865 /* WIDENING -- sign or zero extend each element of the argument
1866 vector to the twice original size. The resulting vector consists of
1867 the same number of elements but each element and the vector itself
1868 are twice as wide.
1869 All operations are I64->V128.
1870 Example
1871 Iop_Widen32Sto64x2( [a, b] ) = [c, d]
1872 where c = Iop_32Sto64(a) and d = Iop_32Sto64(b) */
1876 /* INTERLEAVING */
1877 /* Interleave lanes from low or high halves of
1878 operands. Most-significant result lane is from the left
1879 arg. */
1884 /* Interleave odd/even lanes of operands. Most-significant result lane
1885 is from the left arg. */
1890 /* Pack even/odd lanes. */
1895 /* CONCATENATION -- build a new value by concatenating either
1896 the even or odd lanes of both operands. Note that
1897 Cat{Odd,Even}Lanes64x2 are identical to Interleave{HI,LO}64x2
1898 and so are omitted. */
1902 /* GET elements of VECTOR
1903 GET is binop (V128, I8) -> I<elem_size>
1904 SET is triop (V128, I8, I<elem_size>) -> V128 */
1905 /* Note: the arm back-end handles only constant second argument. */
1909 /* DUPLICATING -- copy value to all lanes */
1912 /* SLICE -- produces the lowest 128 bits of (arg1:arg2) >> (8 * arg3).
1913 arg3 is a shift amount in bytes and may be between 0 and 16
1914 inclusive. When 0, the result is arg2; when 16, the result is arg1.
1915 Not all back ends handle all values. The arm64 back
1916 end handles only immediate arg3 values. */
1919 /* REVERSE the order of chunks in vector lanes. Chunks must be
1920 smaller than the vector lanes (obviously) and so may be 8-,
1921 16- and 32-bit in size. See definitions of 64-bit SIMD
1922 versions above for examples. */
1923 Iop_Reverse8sIn16_x8,
1928 /* PERMUTING -- copy src bytes to dst,
1929 as indexed by control vector bytes:
1930 for i in 0 .. 15 . result[i] = argL[ argR[i] ]
1931 argR[i] values may only be in the range 0 .. 15, else behaviour
1932 is undefined. That is, argR[i][7:4] must be zero. */
1933 Iop_Perm8x16,
1936 /* PERMUTING with optional zeroing:
1937 for i in 0 .. 15 . result[i] = if argR[i] bit 7 is set
1938 then zero else argL[ argR[i] ]
1939 argR[i][6:4] must be zero, else behaviour is undefined.
1940 */
1941 Iop_PermOrZero8x16,
1943 /* same, but Triop (argL consists of two 128-bit parts) */
1944 /* correct range for argR values is 0..31 */
1945 /* (V128, V128, V128) -> V128 */
1946 /* (ArgL_first, ArgL_second, ArgR) -> result */
1947 Iop_Perm8x16x2,
1949 /* MISC CONVERSION -- get high bits of each byte lane, a la
1950 x86/amd64 pmovmskb */
1953 /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate
1954 See floating-point equivalents for details. */
1957 /* 128-bit multipy by 10 instruction, result is lower 128-bits */
1958 Iop_MulI128by10,
1960 /* 128-bit multipy by 10 instruction, result is carry out from the MSB */
1961 Iop_MulI128by10Carry,
1963 /* 128-bit multipy by 10 instruction, result is lower 128-bits of the
1964 * source times 10 plus the carry in
1965 */
1966 Iop_MulI128by10E,
1968 /* 128-bit multipy by 10 instruction, result is carry out from the MSB
1969 * of the source times 10 plus the carry in
1970 */
1971 Iop_MulI128by10ECarry,
1973 /* 128-bit carry out from ((U64 * U64 -> U128) + (U64 * U64 -> U128)) */
1974 Iop_2xMultU64Add128CarryOut,
1976 /* ------------------ 256-bit SIMD Integer. ------------------ */
1978 /* Pack/unpack */
1980 Iop_V256to64_1,
1981 Iop_V256to64_2,
1985 // first arg is most significant lane
1991 Iop_AndV256,
1992 Iop_OrV256,
1993 Iop_XorV256,
1994 Iop_NotV256,
1996 /* MISC (vector integer cmp != 0) */
2024 Iop_Perm32x8,
2026 /* (V128, V128) -> V128 */
2030 /* Hash instructions, Federal Information Processing Standards
2031 * Publication 180-3 Secure Hash Standard. */
2032 /* (V128, I8) -> V128; The I8 input arg is (ST | SIX), where ST and
2033 * SIX are fields from the insn. See ISA 2.07 description of
2034 * vshasigmad and vshasigmaw insns.*/
2037 /* ------------------ 256-bit SIMD FP. ------------------ */
2039 /* ternary :: IRRoundingMode(I32) x V256 x V256 -> V256 */
2049 Iop_Sqrt32Fx8,
2050 Iop_Sqrt64Fx4,
2051 Iop_RSqrtEst32Fx8,
2052 Iop_RecipEst32Fx8,
2057 Iop_LAST /* must be the last enumerator */
2058 }
2059 IROp;
2061 /* Pretty-print an op. */
2064 /* For a given operand return the types of its arguments and its result. */
2069 /* Might the given primop trap (eg, attempt integer division by zero)? If in
2070 doubt returns True. However, the vast majority of primops will never
2071 trap. */
2074 /* Encoding of IEEE754-specified rounding modes.
2075 Note, various front and back ends rely on the actual numerical
2076 values of these, so do not change them. */
2077 typedef
2085 // precision
2088 }
2089 IRRoundingMode;
2091 /* Binary floating point comparison result values.
2092 This is also derived from what IA32 does. */
2093 typedef
2099 }
2100 IRCmpFResult;
2106 /* Decimal floating point result values. */
2111 /* ------------------ Expressions ------------------ */
2117 /* The different kinds of expressions. Their meaning is explained below
2118 in the comments for IRExpr. */
2119 typedef
2122 Iex_Get,
2123 Iex_GetI,
2124 Iex_RdTmp,
2125 Iex_Qop,
2126 Iex_Triop,
2127 Iex_Binop,
2128 Iex_Unop,
2129 Iex_Load,
2130 Iex_Const,
2131 Iex_ITE,
2132 Iex_CCall,
2133 Iex_VECRET,
2134 Iex_GSPTR
2135 }
2136 IRExprTag;
2138 /* An expression. Stored as a tagged union. 'tag' indicates what kind
2139 of expression this is. 'Iex' is the union that holds the fields. If
2140 an IRExpr 'e' has e.tag equal to Iex_Load, then it's a load
2141 expression, and the fields can be accessed with
2142 'e.Iex.Load.<fieldname>'.
2144 For each kind of expression, we show what it looks like when
2145 pretty-printed with ppIRExpr().
2146 */
2147 typedef
2148 struct _IRExpr
2149 IRExpr;
2152 IRExprTag tag;
2154 /* Used only in pattern matching within Vex. Should not be seen
2155 outside of Vex. */
2157 Int binder;
2160 /* Read a guest register, at a fixed offset in the guest state.
2161 ppIRExpr output: GET:<ty>(<offset>), eg. GET:I32(0)
2162 */
2168 /* Read a guest register at a non-fixed offset in the guest
2169 state. This allows circular indexing into parts of the guest
2170 state, which is essential for modelling situations where the
2171 identity of guest registers is not known until run time. One
2172 example is the x87 FP register stack.
2174 The part of the guest state to be treated as a circular array
2175 is described in the IRRegArray 'descr' field. It holds the
2176 offset of the first element in the array, the type of each
2177 element, and the number of elements.
2179 The array index is indicated rather indirectly, in a way
2180 which makes optimisation easy: as the sum of variable part
2181 (the 'ix' field) and a constant offset (the 'bias' field).
2183 Since the indexing is circular, the actual array index to use
2184 is computed as (ix + bias) % num-of-elems-in-the-array.
2186 Here's an example. The description
2188 (96:8xF64)[t39,-7]
2190 describes an array of 8 F64-typed values, the
2191 guest-state-offset of the first being 96. This array is
2192 being indexed at (t39 - 7) % 8.
2194 It is important to get the array size/type exactly correct
2195 since IR optimisation looks closely at such info in order to
2196 establish aliasing/non-aliasing between seperate GetI and
2197 PutI events, which is used to establish when they can be
2198 reordered, etc. Putting incorrect info in will lead to
2199 obscure IR optimisation bugs.
2201 ppIRExpr output: GETI<descr>[<ix>,<bias]
2202 eg. GETI(128:8xI8)[t1,0]
2203 */
2210 /* The value held by a temporary.
2211 ppIRExpr output: t<tmp>, eg. t1
2212 */
2217 /* A quaternary operation.
2218 ppIRExpr output: <op>(<arg1>, <arg2>, <arg3>, <arg4>),
2219 eg. MAddF64r32(t1, t2, t3, t4)
2220 */
2225 /* A ternary operation.
2226 ppIRExpr output: <op>(<arg1>, <arg2>, <arg3>),
2227 eg. MulF64(1, 2.0, 3.0)
2228 */
2233 /* A binary operation.
2234 ppIRExpr output: <op>(<arg1>, <arg2>), eg. Add32(t1,t2)
2235 */
2242 /* A unary operation.
2243 ppIRExpr output: <op>(<arg>), eg. Neg8(t1)
2244 */
2250 /* A load from memory -- a normal load, not a load-linked.
2251 Load-Linkeds (and Store-Conditionals) are instead represented
2252 by IRStmt.LLSC since Load-Linkeds have side effects and so
2253 are not semantically valid IRExpr's.
2254 ppIRExpr output: LD<end>:<ty>(<addr>), eg. LDle:I32(t1)
2255 */
2262 /* A constant-valued expression.
2263 ppIRExpr output: <con>, eg. 0x4:I32
2264 */
2269 /* A call to a pure (no side-effects) helper C function.
2271 With the 'cee' field, 'name' is the function's name. It is
2272 only used for pretty-printing purposes. The address to call
2273 (host address, of course) is stored in the 'addr' field
2274 inside 'cee'.
2276 The 'args' field is a NULL-terminated array of arguments.
2277 The stated return IRType, and the implied argument types,
2278 must match that of the function being called well enough so
2279 that the back end can actually generate correct code for the
2280 call.
2282 The called function **must** satisfy the following:
2284 * no side effects -- must be a pure function, the result of
2285 which depends only on the passed parameters.
2287 * it may not look at, nor modify, any of the guest state
2288 since that would hide guest state transitions from
2289 instrumenters
2291 * it may not access guest memory, since that would hide
2292 guest memory transactions from the instrumenters
2294 * it must not assume that arguments are being evaluated in a
2295 particular order. The oder of evaluation is unspecified.
2297 This is restrictive, but makes the semantics clean, and does
2298 not interfere with IR optimisation.
2300 If you want to call a helper which can mess with guest state
2301 and/or memory, instead use Ist_Dirty. This is a lot more
2302 flexible, but you have to give a bunch of details about what
2303 the helper does (and you better be telling the truth,
2304 otherwise any derived instrumentation will be wrong). Also
2305 Ist_Dirty inhibits various IR optimisations and so can cause
2306 quite poor code to be generated. Try to avoid it.
2308 In principle it would be allowable to have the arg vector
2309 contain an IRExpr_VECRET(), although not IRExpr_GSPTR(). However,
2310 at the moment there is no requirement for clean helper calls to
2311 be able to return V128 or V256 values. Hence this is not allowed.
2313 ppIRExpr output: <cee>(<args>):<retty>
2314 eg. foo{0x80489304}(t1, t2):I32
2315 */
2322 /* A ternary if-then-else operator. It returns iftrue if cond is
2323 nonzero, iffalse otherwise. Note that it is STRICT, ie. both
2324 iftrue and iffalse are evaluated in all cases.
2326 ppIRExpr output: ITE(<cond>,<iftrue>,<iffalse>),
2327 eg. ITE(t6,t7,t8)
2328 */
2335 };
2337 /* Expression auxiliaries: a ternary expression. */
2343 };
2345 /* Expression auxiliaries: a quarternary expression. */
2352 };
2355 /* Two special kinds of IRExpr, which can ONLY be used in
2356 argument lists for dirty helper calls (IRDirty.args) and in NO
2357 OTHER PLACES. And then only in very limited ways. */
2359 /* Denotes an argument which (in the helper) takes a pointer to a
2360 (naturally aligned) V128 or V256, into which the helper is expected
2361 to write its result. Use of IRExpr_VECRET() is strictly
2362 controlled. If the helper returns a V128 or V256 value then
2363 IRExpr_VECRET() must appear exactly once in the arg list, although
2364 it can appear anywhere, and the helper must have a C 'void' return
2365 type. If the helper returns any other type, IRExpr_VECRET() may
2366 not appear in the argument list. */
2368 /* Denotes an void* argument which is passed to the helper, which at
2369 run time will point to the thread's guest state area. This can
2370 only appear at most once in an argument list, and it may not appear
2371 at all in argument lists for clean helper calls. */
2375 }
2378 /* Expression constructors. */
2396 /* Deep-copy an IRExpr. */
2399 /* Pretty-print an IRExpr. */
2402 /* NULL-terminated IRExpr vector constructors, suitable for
2403 use as arg lists in clean/dirty helper calls. */
2410 IRExpr* );
2423 /* IRExpr copiers:
2424 - shallowCopy: shallow-copy (ie. create a new vector that shares the
2425 elements with the original).
2426 - deepCopy: deep-copy (ie. create a completely new vector). */
2430 /* Make a constant expression from the given host word taking into
2431 account (of course) the host word size. */
2434 /* Convenience function for constructing clean helper calls. */
2435 extern
2441 /* Convenience functions for atoms (IRExprs which are either Iex_Tmp or
2442 * Iex_Const). */
2445 }
2447 /* Are these two IR atoms identical? Causes an assertion
2448 failure if they are passed non-atoms. */
2452 /* ------------------ Jump kinds ------------------ */
2454 /* This describes hints which can be passed to the dispatcher at guest
2455 control-flow transfer points.
2457 Re Ijk_InvalICache and Ijk_FlushDCache: the guest state _must_ have
2458 two pseudo-registers, guest_CMSTART and guest_CMLEN, which specify
2459 the start and length of the region to be invalidated. CM stands
2460 for "Cache Management". These are both the size of a guest word.
2461 It is the responsibility of the relevant toIR.c to ensure that
2462 these are filled in with suitable values before issuing a jump of
2463 kind Ijk_InvalICache or Ijk_FlushDCache.
2465 Ijk_InvalICache requests invalidation of translations taken from
2466 the requested range. Ijk_FlushDCache requests flushing of the D
2467 cache for the specified range.
2469 Re Ijk_EmWarn and Ijk_EmFail: the guest state must have a
2470 pseudo-register guest_EMNOTE, which is 32-bits regardless of the
2471 host or guest word size. That register should be made to hold a
2472 VexEmNote value to indicate the reason for the exit.
2474 In the case of Ijk_EmFail, the exit is fatal (Vex-generated code
2475 cannot continue) and so the jump destination can be anything.
2477 Re Ijk_Sys_ (syscall jumps): the guest state must have a
2478 pseudo-register guest_IP_AT_SYSCALL, which is the size of a guest
2479 word. Front ends should set this to be the IP at the most recently
2480 executed kernel-entering (system call) instruction. This makes it
2481 very much easier (viz, actually possible at all) to back up the
2482 guest to restart a syscall that has been interrupted by a signal.
2483 */
2484 typedef
2506 /* Unfortunately, various guest-dependent syscall kinds. They
2507 all mean: do a syscall before continuing. */
2515 Ijk_Sys_sysenter /* x86 'sysenter'. guest_EIP becomes
2516 invalid at the point this happens. */
2517 }
2518 IRJumpKind;
2523 /* ------------------ Dirty helper calls ------------------ */
2525 /* A dirty call is a flexible mechanism for calling (possibly
2526 conditionally) a helper function or procedure. The helper function
2527 may read, write or modify client memory, and may read, write or
2528 modify client state. It can take arguments and optionally return a
2529 value. It may return different results and/or do different things
2530 when called repeatedly with the same arguments, by means of storing
2531 private state.
2533 If a value is returned, it is assigned to the nominated return
2534 temporary.
2536 Dirty calls are statements rather than expressions for obvious
2537 reasons. If a dirty call is marked as writing guest state, any
2538 pre-existing values derived from the written parts of the guest
2539 state are invalid. Similarly, if the dirty call is stated as
2540 writing memory, any pre-existing loaded values are invalidated by
2541 it.
2543 In order that instrumentation is possible, the call must state, and
2544 state correctly:
2546 * Whether it reads, writes or modifies memory, and if so where.
2548 * Whether it reads, writes or modifies guest state, and if so which
2549 pieces. Several pieces may be stated, and their extents must be
2550 known at translation-time. Each piece is allowed to repeat some
2551 number of times at a fixed interval, if required.
2553 Normally, code is generated to pass just the args to the helper.
2554 However, if IRExpr_GSPTR() is present in the argument list (at most
2555 one instance is allowed), then the guest state pointer is passed for
2556 that arg, so that the callee can access the guest state. It is
2557 invalid for .nFxState to be zero but IRExpr_GSPTR() to be present,
2558 since .nFxState==0 is a claim that the call does not access guest
2559 state.
2561 IMPORTANT NOTE re GUARDS: Dirty calls are strict, very strict. The
2562 arguments and 'mFx' are evaluated REGARDLESS of the guard value.
2563 The order of argument evaluation is unspecified. The guard
2564 expression is evaluated AFTER the arguments and 'mFx' have been
2565 evaluated. 'mFx' is expected (by Memcheck) to be a defined value
2566 even if the guard evaluates to false.
2567 */
2571 /* Effects on resources (eg. registers, memory locations) */
2572 typedef
2578 }
2579 IREffect;
2581 /* Pretty-print an IREffect */
2584 typedef
2586 /* What to call, and details of args/results. .guard must be
2587 non-NULL. If .tmp is not IRTemp_INVALID, then the call
2588 returns a result which is placed in .tmp. If at runtime the
2589 guard evaluates to false, .tmp has an 0x555..555 bit pattern
2590 written to it. Hence conditional calls that assign .tmp are
2591 allowed. */
2594 /* The args vector may contain IRExpr_GSPTR() and/or
2595 IRExpr_VECRET(), in both cases, at most once. */
2599 /* Mem effects; we allow only one R/W/M region to be stated */
2604 /* Guest state effects; up to N allowed */
2608 UShort offset;
2609 UShort size;
2610 UChar nRepeats;
2611 UChar repeatLen;
2613 /* The access can be repeated, as specified by nRepeats and
2614 repeatLen. To describe only a single access, nRepeats and
2615 repeatLen should be zero. Otherwise, repeatLen must be a
2616 multiple of size and greater than size. */
2617 /* Overall, the parts of the guest state denoted by (offset,
2618 size, nRepeats, repeatLen) is
2619 [offset, +size)
2620 and, if nRepeats > 0,
2621 for (i = 1; i <= nRepeats; i++)
2622 [offset + i * repeatLen, +size)
2623 A convenient way to enumerate all segments is therefore
2624 for (i = 0; i < 1 + nRepeats; i++)
2625 [offset + i * repeatLen, +size)
2626 */
2627 }
2628 IRDirty;
2630 /* Pretty-print a dirty call */
2633 /* Allocate an uninitialised dirty call */
2636 /* Deep-copy a dirty call */
2639 /* A handy function which takes some of the tedium out of constructing
2640 dirty helper calls. The called function impliedly does not return
2641 any value and has a constant-True guard. The call is marked as
2642 accessing neither guest state nor memory (hence the "unsafe"
2643 designation) -- you can change this marking later if need be. A
2644 suitable IRCallee is constructed from the supplied bits. */
2645 extern
2649 /* Similarly, make a zero-annotation dirty call which returns a value,
2650 and assign that to the given temp. */
2651 extern
2657 /* --------------- Memory Bus Events --------------- */
2659 typedef
2662 /* Needed only on ARM. It cancels a reservation made by a
2663 preceding Linked-Load, and needs to be handed through to the
2664 back end, just as LL and SC themselves are. */
2665 Imbe_CancelReservation
2666 }
2667 IRMBusEvent;
2672 /* --------------- Compare and Swap --------------- */
2674 /* This denotes an atomic compare and swap operation, either
2675 a single-element one or a double-element one.
2677 In the single-element case:
2679 .addr is the memory address.
2680 .end is the endianness with which memory is accessed
2682 If .addr contains the same value as .expdLo, then .dataLo is
2683 written there, else there is no write. In both cases, the
2684 original value at .addr is copied into .oldLo.
2686 Types: .expdLo, .dataLo and .oldLo must all have the same type.
2687 It may be any integral type, viz: I8, I16, I32 or, for 64-bit
2688 guests, I64.
2690 .oldHi must be IRTemp_INVALID, and .expdHi and .dataHi must
2691 be NULL.
2693 In the double-element case:
2695 .addr is the memory address.
2696 .end is the endianness with which memory is accessed
2698 The operation is the same:
2700 If .addr contains the same value as .expdHi:.expdLo, then
2701 .dataHi:.dataLo is written there, else there is no write. In
2702 both cases the original value at .addr is copied into
2703 .oldHi:.oldLo.
2705 Types: .expdHi, .expdLo, .dataHi, .dataLo, .oldHi, .oldLo must
2706 all have the same type, which may be any integral type, viz: I8,
2707 I16, I32 or, for 64-bit guests, I64.
2709 The double-element case is complicated by the issue of
2710 endianness. In all cases, the two elements are understood to be
2711 located adjacently in memory, starting at the address .addr.
2713 If .end is Iend_LE, then the .xxxLo component is at the lower
2714 address and the .xxxHi component is at the higher address, and
2715 each component is itself stored little-endianly.
2717 If .end is Iend_BE, then the .xxxHi component is at the lower
2718 address and the .xxxLo component is at the higher address, and
2719 each component is itself stored big-endianly.
2721 This allows representing more cases than most architectures can
2722 handle. For example, x86 cannot do DCAS on 8- or 16-bit elements.
2724 How to know if the CAS succeeded?
2726 * if .oldLo == .expdLo (resp. .oldHi:.oldLo == .expdHi:.expdLo),
2727 then the CAS succeeded, .dataLo (resp. .dataHi:.dataLo) is now
2728 stored at .addr, and the original value there was .oldLo (resp
2729 .oldHi:.oldLo).
2731 * if .oldLo != .expdLo (resp. .oldHi:.oldLo != .expdHi:.expdLo),
2732 then the CAS failed, and the original value at .addr was .oldLo
2733 (resp. .oldHi:.oldLo).
2735 Hence it is easy to know whether or not the CAS succeeded.
2736 */
2737 typedef
2740 IRTemp oldLo;
2747 }
2748 IRCAS;
2760 /* ------------------ Circular Array Put ------------------ */
2762 typedef
2778 /* --------------- Guarded loads and stores --------------- */
2780 /* Conditional stores are straightforward. They are the same as
2781 normal stores, with an extra 'guard' field :: Ity_I1 that
2782 determines whether or not the store actually happens. If not,
2783 memory is unmodified.
2785 The semantics of this is that 'addr' and 'data' are fully evaluated
2786 even in the case where 'guard' evaluates to zero (false).
2787 */
2788 typedef
2794 }
2795 IRStoreG;
2797 /* Conditional loads are a little more complex. 'addr' is the
2798 address, 'guard' is the guarding condition. If the load takes
2799 place, the loaded value is placed in 'dst'. If it does not take
2800 place, 'alt' is copied to 'dst'. However, the loaded value is not
2801 placed directly in 'dst' -- it is first subjected to the conversion
2802 specified by 'cvt'.
2804 For example, imagine doing a conditional 8-bit load, in which the
2805 loaded value is zero extended to 32 bits. Hence:
2806 * 'dst' and 'alt' must have type I32
2807 * 'cvt' must be a unary op which converts I8 to I32. In this
2808 example, it would be ILGop_8Uto32.
2810 There is no explicit indication of the type at which the load is
2811 done, since that is inferrable from the arg type of 'cvt'. Note
2812 that the types of 'alt' and 'dst' and the result type of 'cvt' must
2813 all be the same.
2815 Semantically, 'addr' is evaluated even in the case where 'guard'
2816 evaluates to zero (false), and 'alt' is evaluated even when 'guard'
2817 evaluates to one (true). That is, 'addr' and 'alt' are always
2818 evaluated.
2819 */
2820 typedef
2829 ILGop_8Sto32 /* 8 bit load, S-widen to 32 */
2830 }
2831 IRLoadGOp;
2833 typedef
2841 }
2842 IRLoadG;
2859 /* ------------------ Statements ------------------ */
2861 /* The different kinds of statements. Their meaning is explained
2862 below in the comments for IRStmt.
2864 Those marked META do not represent code, but rather extra
2865 information about the code. These statements can be removed
2866 without affecting the functional behaviour of the code, however
2867 they are required by some IR consumers such as tools that
2868 instrument the code.
2869 */
2871 typedef
2876 Ist_Put,
2877 Ist_PutI,
2878 Ist_WrTmp,
2879 Ist_Store,
2880 Ist_LoadG,
2881 Ist_StoreG,
2882 Ist_CAS,
2883 Ist_LLSC,
2884 Ist_Dirty,
2885 Ist_MBE,
2886 Ist_Exit
2887 }
2888 IRStmtTag;
2890 /* A statement. Stored as a tagged union. 'tag' indicates what kind
2891 of expression this is. 'Ist' is the union that holds the fields.
2892 If an IRStmt 'st' has st.tag equal to Iex_Store, then it's a store
2893 statement, and the fields can be accessed with
2894 'st.Ist.Store.<fieldname>'.
2896 For each kind of statement, we show what it looks like when
2897 pretty-printed with ppIRStmt().
2898 */
2899 typedef
2901 IRStmtTag tag;
2903 /* A no-op (usually resulting from IR optimisation). Can be
2904 omitted without any effect.
2906 ppIRStmt output: IR-NoOp
2907 */
2911 /* META: instruction mark. Marks the start of the statements
2912 that represent a single machine instruction (the end of
2913 those statements is marked by the next IMark or the end of
2914 the IRSB). Contains the address and length of the
2915 instruction.
2917 It also contains a delta value. The delta must be
2918 subtracted from a guest program counter value before
2919 attempting to establish, by comparison with the address
2920 and length values, whether or not that program counter
2921 value refers to this instruction. For x86, amd64, ppc32,
2922 ppc64 and arm, the delta value is zero. For Thumb
2923 instructions, the delta value is one. This is because, on
2924 Thumb, guest PC values (guest_R15T) are encoded using the
2925 top 31 bits of the instruction address and a 1 in the lsb;
2926 hence they appear to be (numerically) 1 past the start of
2927 the instruction they refer to. IOW, guest_R15T on ARM
2928 holds a standard ARM interworking address.
2930 ppIRStmt output: ------ IMark(<addr>, <len>, <delta>) ------,
2931 eg. ------ IMark(0x4000792, 5, 0) ------,
2932 */
2937 - delta */
2940 /* META: An ABI hint, which says something about this
2941 platform's ABI.
2943 At the moment, the only AbiHint is one which indicates
2944 that a given chunk of address space, [base .. base+len-1],
2945 has become undefined. This is used on amd64-linux and
2946 some ppc variants to pass stack-redzoning hints to whoever
2947 wants to see them. It also indicates the address of the
2948 next (dynamic) instruction that will be executed. This is
2949 to help Memcheck to origin tracking.
2951 ppIRStmt output: ====== AbiHint(<base>, <len>, <nia>) ======
2952 eg. ====== AbiHint(t1, 16, t2) ======
2953 */
2960 /* Write a guest register, at a fixed offset in the guest state.
2961 ppIRStmt output: PUT(<offset>) = <data>, eg. PUT(60) = t1
2962 */
2968 /* Write a guest register, at a non-fixed offset in the guest
2969 state. See the comment for GetI expressions for more
2970 information.
2972 ppIRStmt output: PUTI<descr>[<ix>,<bias>] = <data>,
2973 eg. PUTI(64:8xF64)[t5,0] = t1
2974 */
2979 /* Assign a value to a temporary. Note that SSA rules require
2980 each tmp is only assigned to once. IR sanity checking will
2981 reject any block containing a temporary which is not assigned
2982 to exactly once.
2984 ppIRStmt output: t<tmp> = <data>, eg. t1 = 3
2985 */
2991 /* Write a value to memory. This is a normal store, not a
2992 Store-Conditional. To represent a Store-Conditional,
2993 instead use IRStmt.LLSC.
2994 ppIRStmt output: ST<end>(<addr>) = <data>, eg. STle(t1) = t2
2995 */
3002 /* Guarded store. Note that this is defined to evaluate all
3003 expression fields (addr, data) even if the guard evaluates
3004 to false.
3005 ppIRStmt output:
3006 if (<guard>) ST<end>(<addr>) = <data> */
3011 /* Guarded load. Note that this is defined to evaluate all
3012 expression fields (addr, alt) even if the guard evaluates
3013 to false.
3014 ppIRStmt output:
3015 t<tmp> = if (<guard>) <cvt>(LD<end>(<addr>)) else <alt> */
3020 /* Do an atomic compare-and-swap operation. Semantics are
3021 described above on a comment at the definition of IRCAS.
3023 ppIRStmt output:
3024 t<tmp> = CAS<end>(<addr> :: <expected> -> <new>)
3025 eg
3026 t1 = CASle(t2 :: t3->Add32(t3,1))
3027 which denotes a 32-bit atomic increment
3028 of a value at address t2
3030 A double-element CAS may also be denoted, in which case <tmp>,
3031 <expected> and <new> are all pairs of items, separated by
3032 commas.
3033 */
3038 /* Either Load-Linked or Store-Conditional, depending on
3039 STOREDATA.
3041 If STOREDATA is NULL then this is a Load-Linked, meaning
3042 that data is loaded from memory as normal, but a
3043 'reservation' for the address is also lodged in the
3044 hardware.
3046 result = Load-Linked(addr, end)
3048 The data transfer type is the type of RESULT (I32, I64,
3049 etc). ppIRStmt output:
3051 result = LD<end>-Linked(<addr>), eg. LDbe-Linked(t1)
3053 If STOREDATA is not NULL then this is a Store-Conditional,
3054 hence:
3056 result = Store-Conditional(addr, storedata, end)
3058 The data transfer type is the type of STOREDATA and RESULT
3059 has type Ity_I1. The store may fail or succeed depending
3060 on the state of a previously lodged reservation on this
3061 address. RESULT is written 1 if the store succeeds and 0
3062 if it fails. eg ppIRStmt output:
3064 result = ( ST<end>-Cond(<addr>) = <storedata> )
3065 eg t3 = ( STbe-Cond(t1, t2) )
3067 In all cases, the address must be naturally aligned for
3068 the transfer type -- any misaligned addresses should be
3069 caught by a dominating IR check and side exit. This
3070 alignment restriction exists because on at least some
3071 LL/SC platforms (ppc), stwcx. etc will trap w/ SIGBUS on
3072 misaligned addresses, and we have to actually generate
3073 stwcx. on the host, and we don't want it trapping on the
3074 host.
3076 Summary of rules for transfer type:
3077 STOREDATA == NULL (LL):
3078 transfer type = type of RESULT
3079 STOREDATA != NULL (SC):
3080 transfer type = type of STOREDATA, and RESULT :: Ity_I1
3081 */
3083 IREndness end;
3084 IRTemp result;
3089 /* Call (possibly conditionally) a C function that has side
3090 effects (ie. is "dirty"). See the comments above the
3091 IRDirty type declaration for more information.
3093 ppIRStmt output:
3094 t<tmp> = DIRTY <guard> <effects>
3095 ::: <callee>(<args>)
3096 eg.
3097 t1 = DIRTY t27 RdFX-gst(16,4) RdFX-gst(60,4)
3098 ::: foo{0x380035f4}(t2)
3099 */
3104 /* A memory bus event - a fence, or acquisition/release of the
3105 hardware bus lock. IR optimisation treats all these as fences
3106 across which no memory references may be moved.
3107 ppIRStmt output: MBusEvent-Fence,
3108 MBusEvent-BusLock, MBusEvent-BusUnlock.
3109 */
3111 IRMBusEvent event;
3114 /* Conditional exit from the middle of an IRSB.
3115 ppIRStmt output: if (<guard>) goto {<jk>} <dst>
3116 eg. if (t69) goto {Boring} 0x4000AAA:I32
3117 If <guard> is true, the guest state is also updated by
3118 PUT-ing <dst> at <offsIP>. This is done because a
3119 taken exit must update the guest program counter.
3120 */
3128 }
3129 IRStmt;
3131 /* Statement constructors. */
3149 Int offsIP );
3151 /* Deep-copy an IRStmt. */
3154 /* Pretty-print an IRStmt. */
3158 /* ------------------ Basic Blocks ------------------ */
3160 /* Type environments: a bunch of statements, expressions, etc, are
3161 incomplete without an environment indicating the type of each
3162 IRTemp. So this provides one. IR temporaries are really just
3163 unsigned ints and so this provides an array, 0 .. n_types_used-1 of
3164 them.
3165 */
3166 typedef
3169 Int types_size;
3170 Int types_used;
3171 }
3172 IRTypeEnv;
3174 /* Obtain a new IRTemp */
3177 /* Deep-copy a type environment */
3180 /* Pretty-print a type environment */
3184 /* Code blocks, which in proper compiler terminology are superblocks
3185 (single entry, multiple exit code sequences) contain:
3187 - A table giving a type for each temp (the "type environment")
3188 - An expandable array of statements
3189 - An expression of type 32 or 64 bits, depending on the
3190 guest's word size, indicating the next destination if the block
3191 executes all the way to the end, without a side exit
3192 - An indication of any special actions (JumpKind) needed
3193 for this final jump.
3194 - Offset of the IP field in the guest state. This will be
3195 updated before the final jump is done.
3197 "IRSB" stands for "IR Super Block".
3198 */
3199 typedef
3203 Int stmts_size;
3204 Int stmts_used;
3206 IRJumpKind jumpkind;
3207 Int offsIP;
3208 }
3209 IRSB;
3211 /* Allocate a new, uninitialised IRSB */
3214 /* Deep-copy an IRSB */
3217 /* Deep-copy an IRSB, except for the statements list, which set to be
3218 a new, empty, list of statements. */
3221 /* Pretty-print an IRSB */
3224 /* Append an IRStmt to an IRSB */
3228 /*---------------------------------------------------------------*/
3229 /*--- Helper functions for the IR ---*/
3230 /*---------------------------------------------------------------*/
3232 /* For messing with IR type environments */
3235 /* What is the type of this expression? */
3240 /* What are the arg and result type for this IRLoadGOp? */
3245 /* Sanity check a BB of IR */
3248 Bool require_flatness,
3249 IRType guest_word_size );
3253 /* Is this any value actually in the enumeration 'IRType' ? */
3257 /*---------------------------------------------------------------*/
3258 /*--- IR injection ---*/
3259 /*---------------------------------------------------------------*/
3266 /*---------------------------------------------------------------*/
3267 /*--- libvex_ir.h ---*/
3268 /*---------------------------------------------------------------*/