VEX/pub/libvex.h

   1
   2 /*---------------------------------------------------------------*/
   3 /*--- begin                                          libvex.h ---*/
   4 /*---------------------------------------------------------------*/
   5
   6 /*
   7    This file is part of Valgrind, a dynamic binary instrumentation
   8    framework.
   9
  10    Copyright (C) 2004-2017 OpenWorks LLP
  11       info@open-works.net
  12
  13    This program is free software; you can redistribute it and/or
  14    modify it under the terms of the GNU General Public License as
  15    published by the Free Software Foundation; either version 2 of the
  16    License, or (at your option) any later version.
  17
  18    This program is distributed in the hope that it will be useful, but
  19    WITHOUT ANY WARRANTY; without even the implied warranty of
  20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21    General Public License for more details.
  22
  23    You should have received a copy of the GNU General Public License
  24    along with this program; if not, see <http://www.gnu.org/licenses/>.
  25
  26    The GNU General Public License is contained in the file COPYING.
  27
  28    Neither the names of the U.S. Department of Energy nor the
  29    University of California nor the names of its contributors may be
  30    used to endorse or promote products derived from this software
  31    without prior written permission.
  32 */
  33
  34 #ifndef __LIBVEX_H
  35 #define __LIBVEX_H
  36
  37
  38 #include "libvex_basictypes.h"
  39 #include "libvex_ir.h"
  40
  41
  42 /*---------------------------------------------------------------*/
  43 /*--- This file defines the top-level interface to LibVEX.    ---*/
  44 /*---------------------------------------------------------------*/
  45
  46 /*-------------------------------------------------------*/
  47 /*--- Architectures, variants, and other arch info    ---*/
  48 /*-------------------------------------------------------*/
  49
  50 typedef
  51    enum {
  52       VexArch_INVALID=0x400,
  53       VexArchX86,
  54       VexArchAMD64,
  55       VexArchARM,
  56       VexArchARM64,
  57       VexArchPPC32,
  58       VexArchPPC64,
  59       VexArchS390X,
  60       VexArchMIPS32,
  61       VexArchMIPS64,
  62       VexArchNANOMIPS,
  63    }
  64    VexArch;
  65
  66
  67 /* Information about endianness. */
  68 typedef
  69    enum {
  70       VexEndness_INVALID=0x600, /* unknown endianness */
  71       VexEndnessLE,             /* little endian */
  72       VexEndnessBE              /* big endian */
  73    }
  74    VexEndness;
  75
  76
  77 /* For a given architecture, these specify extra capabilities beyond
  78    the minimum supported (baseline) capabilities.  They may be OR'd
  79    together, although some combinations don't make sense.  (eg, SSE2
  80    but not SSE1).  LibVEX_Translate will check for nonsensical
  81    combinations. */
  82
  83 /* x86: baseline capability is Pentium-1 (FPU, MMX, but no SSE), with
  84    cmpxchg8b. MMXEXT is a special AMD only subset of SSE1 (Integer SSE). */
  85 #define VEX_HWCAPS_X86_MMXEXT  (1<<1)  /* A subset of SSE1 on early AMD */
  86 #define VEX_HWCAPS_X86_SSE1    (1<<2)  /* SSE1 support (Pentium III) */
  87 #define VEX_HWCAPS_X86_SSE2    (1<<3)  /* SSE2 support (Pentium 4) */
  88 #define VEX_HWCAPS_X86_SSE3    (1<<4)  /* SSE3 support (>= Prescott) */
  89 #define VEX_HWCAPS_X86_LZCNT   (1<<5)  /* SSE4a LZCNT insn */
  90
  91 /* amd64: baseline capability is SSE2, with cmpxchg8b but not
  92    cmpxchg16b. */
  93 #define VEX_HWCAPS_AMD64_SSE3   (1<<5)  /* SSE3 support */
  94 #define VEX_HWCAPS_AMD64_SSSE3  (1<<12) /* Supplemental SSE3 support */
  95 #define VEX_HWCAPS_AMD64_CX16   (1<<6)  /* cmpxchg16b support */
  96 #define VEX_HWCAPS_AMD64_LZCNT  (1<<7)  /* SSE4a LZCNT insn */
  97 #define VEX_HWCAPS_AMD64_AVX    (1<<8)  /* AVX instructions */
  98 #define VEX_HWCAPS_AMD64_RDTSCP (1<<9)  /* RDTSCP instruction */
  99 #define VEX_HWCAPS_AMD64_BMI    (1<<10) /* BMI1 instructions */
 100 #define VEX_HWCAPS_AMD64_AVX2   (1<<11) /* AVX2 instructions */
 101 #define VEX_HWCAPS_AMD64_RDRAND (1<<13) /* RDRAND instructions */
 102 #define VEX_HWCAPS_AMD64_F16C   (1<<14) /* F16C instructions */
 103 #define VEX_HWCAPS_AMD64_RDSEED (1<<15) /* RDSEED instructions */
 104
 105 /* ppc32: baseline capability is integer only */
 106 #define VEX_HWCAPS_PPC32_F     (1<<8)  /* basic (non-optional) FP */
 107 #define VEX_HWCAPS_PPC32_V     (1<<9)  /* Altivec (VMX) */
 108 #define VEX_HWCAPS_PPC32_FX    (1<<10) /* FP extns (fsqrt, fsqrts) */
 109 #define VEX_HWCAPS_PPC32_GX    (1<<11) /* Graphics extns
 110                                           (fres,frsqrte,fsel,stfiwx) */
 111 #define VEX_HWCAPS_PPC32_VX    (1<<12) /* Vector-scalar floating-point (VSX); implies ISA 2.06 or higher  */
 112 #define VEX_HWCAPS_PPC32_DFP   (1<<17) /* Decimal Floating Point (DFP) -- e.g., dadd */
 113 #define VEX_HWCAPS_PPC32_ISA2_07   (1<<19) /* ISA 2.07 -- e.g., mtvsrd */
 114 #define VEX_HWCAPS_PPC32_ISA3_0    (1<<21) /* ISA 3.0  -- e.g., cnttzw */
 115 #define VEX_HWCAPS_PPC32_ISA3_1    (1<<22) /* ISA 3.1  -- e.g., brh */
 116 /* ISA 3.1 not supported in 32-bit mode */
 117
 118 /* ppc64: baseline capability is integer and basic FP insns */
 119 #define VEX_HWCAPS_PPC64_V     (1<<13) /* Altivec (VMX) */
 120 #define VEX_HWCAPS_PPC64_FX    (1<<14) /* FP extns (fsqrt, fsqrts) */
 121 #define VEX_HWCAPS_PPC64_GX    (1<<15) /* Graphics extns
 122                                           (fres,frsqrte,fsel,stfiwx) */
 123 #define VEX_HWCAPS_PPC64_VX    (1<<16) /* Vector-scalar floating-point (VSX); implies ISA 2.06 or higher  */
 124 #define VEX_HWCAPS_PPC64_DFP   (1<<18) /* Decimal Floating Point (DFP) -- e.g., dadd */
 125 #define VEX_HWCAPS_PPC64_ISA2_07   (1<<20) /* ISA 2.07 -- e.g., mtvsrd */
 126 #define VEX_HWCAPS_PPC64_ISA3_0    (1<<22) /* ISA 3.0  -- e.g., cnttzw */
 127 #define VEX_HWCAPS_PPC64_ISA3_1    (1<<23) /* ISA 3.1  -- e.g., brh */
 128 #define VEX_HWCAPS_PPC64_SCV       (1<<24) /* ISA 3.0, Kernel supports scv
 129                                               instruction. */
 130
 131 /* s390x: Hardware capability encoding
 132
 133    Bits [26:31] encode the machine model (see VEX_S390X_MODEL... below)
 134    Bits [0:20]  encode specific hardware capabilities
 135                 (see VEX_HWAPS_S390X_... below)
 136 */
 137
 138 /* Model numbers must be assigned in chronological order.
 139    They are used as array index. */
 140 #define VEX_S390X_MODEL_Z900     0
 141 #define VEX_S390X_MODEL_Z800     1
 142 #define VEX_S390X_MODEL_Z990     2
 143 #define VEX_S390X_MODEL_Z890     3
 144 #define VEX_S390X_MODEL_Z9_EC    4
 145 #define VEX_S390X_MODEL_Z9_BC    5
 146 #define VEX_S390X_MODEL_Z10_EC   6
 147 #define VEX_S390X_MODEL_Z10_BC   7
 148 #define VEX_S390X_MODEL_Z196     8
 149 #define VEX_S390X_MODEL_Z114     9
 150 #define VEX_S390X_MODEL_ZEC12    10
 151 #define VEX_S390X_MODEL_ZBC12    11
 152 #define VEX_S390X_MODEL_Z13      12
 153 #define VEX_S390X_MODEL_Z13S     13
 154 #define VEX_S390X_MODEL_Z14      14
 155 #define VEX_S390X_MODEL_Z14_ZR1  15
 156 #define VEX_S390X_MODEL_Z15      16
 157 #define VEX_S390X_MODEL_Z16      17
 158 #define VEX_S390X_MODEL_UNKNOWN  18     /* always last in list */
 159 #define VEX_S390X_MODEL_MASK     0x3F
 160
 161 #define VEX_HWCAPS_S390X_LDISP (1<<6)   /* Long-displacement facility */
 162 #define VEX_HWCAPS_S390X_EIMM  (1<<7)   /* Extended-immediate facility */
 163 #define VEX_HWCAPS_S390X_GIE   (1<<8)   /* General-instruction-extension facility */
 164 #define VEX_HWCAPS_S390X_DFP   (1<<9)   /* Decimal floating point facility */
 165 #define VEX_HWCAPS_S390X_FGX   (1<<10)  /* FPR-GR transfer facility */
 166 #define VEX_HWCAPS_S390X_ETF2  (1<<11)  /* ETF2-enhancement facility */
 167 #define VEX_HWCAPS_S390X_STFLE (1<<12)  /* STFLE facility */
 168 #define VEX_HWCAPS_S390X_ETF3  (1<<13)  /* ETF3-enhancement facility */
 169 #define VEX_HWCAPS_S390X_STCKF (1<<14)  /* STCKF facility */
 170 #define VEX_HWCAPS_S390X_FPEXT (1<<15)  /* Floating point extension facility */
 171 #define VEX_HWCAPS_S390X_LSC   (1<<16)  /* Conditional load/store facility */
 172 #define VEX_HWCAPS_S390X_PFPO  (1<<17)  /* Perform floating point ops facility */
 173 #define VEX_HWCAPS_S390X_VX    (1<<18)  /* Vector facility */
 174 #define VEX_HWCAPS_S390X_MSA5  (1<<19)  /* message security assistance facility */
 175 #define VEX_HWCAPS_S390X_MI2   (1<<20)  /* miscellaneous-instruction-extensions facility 2 */
 176 #define VEX_HWCAPS_S390X_LSC2  (1<<21)  /* Conditional load/store facility2 */
 177 #define VEX_HWCAPS_S390X_VXE   (1<<22)  /* Vector-enhancements facility */
 178
 179 /* Special value representing all available s390x hwcaps */
 180 #define VEX_HWCAPS_S390X_ALL   (VEX_HWCAPS_S390X_LDISP | \
 181                                 VEX_HWCAPS_S390X_EIMM  | \
 182                                 VEX_HWCAPS_S390X_GIE   | \
 183                                 VEX_HWCAPS_S390X_DFP   | \
 184                                 VEX_HWCAPS_S390X_FGX   | \
 185                                 VEX_HWCAPS_S390X_STFLE | \
 186                                 VEX_HWCAPS_S390X_STCKF | \
 187                                 VEX_HWCAPS_S390X_FPEXT | \
 188                                 VEX_HWCAPS_S390X_LSC   | \
 189                                 VEX_HWCAPS_S390X_ETF3  | \
 190                                 VEX_HWCAPS_S390X_ETF2  | \
 191                                 VEX_HWCAPS_S390X_PFPO  | \
 192                                 VEX_HWCAPS_S390X_VX    | \
 193                                 VEX_HWCAPS_S390X_MSA5  | \
 194                                 VEX_HWCAPS_S390X_MI2   | \
 195                                 VEX_HWCAPS_S390X_LSC2  | \
 196                                 VEX_HWCAPS_S390X_VXE)
 197
 198 #define VEX_HWCAPS_S390X(x)  ((x) & ~VEX_S390X_MODEL_MASK)
 199 #define VEX_S390X_MODEL(x)   ((x) &  VEX_S390X_MODEL_MASK)
 200
 201 /* arm: baseline capability is ARMv4 */
 202 /* Bits 5:0 - architecture level (e.g. 5 for v5, 6 for v6 etc) */
 203 #define VEX_HWCAPS_ARM_VFP    (1<<6)  /* VFP extension */
 204 #define VEX_HWCAPS_ARM_VFP2   (1<<7)  /* VFPv2 */
 205 #define VEX_HWCAPS_ARM_VFP3   (1<<8)  /* VFPv3 */
 206 /* Bits 15:10 reserved for (possible) future VFP revisions */
 207 #define VEX_HWCAPS_ARM_NEON   (1<<16) /* Advanced SIMD also known as NEON */
 208
 209 /* Get an ARM architecure level from HWCAPS */
 210 #define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f)
 211
 212 /* ARM64: baseline capability is AArch64 v8. */
 213 #define VEX_HWCAPS_ARM64_FHM         (1 << 4)
 214 #define VEX_HWCAPS_ARM64_DPBCVAP     (1 << 5)
 215 #define VEX_HWCAPS_ARM64_DPBCVADP    (1 << 6)
 216 #define VEX_HWCAPS_ARM64_SM3         (1 << 7)
 217 #define VEX_HWCAPS_ARM64_SM4         (1 << 8)
 218 #define VEX_HWCAPS_ARM64_SHA3        (1 << 9)
 219 #define VEX_HWCAPS_ARM64_RDM         (1 << 10)
 220 #define VEX_HWCAPS_ARM64_ATOMICS     (1 << 11)
 221 #define VEX_HWCAPS_ARM64_I8MM        (1 << 12)
 222 #define VEX_HWCAPS_ARM64_BF16        (1 << 13)
 223 #define VEX_HWCAPS_ARM64_FP16        (1 << 14)
 224 #define VEX_HWCAPS_ARM64_VFP16       (1 << 15)
 225
 226 /* MIPS baseline capability */
 227 /* Assigned Company values for bits 23:16 of the PRId Register
 228    (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
 229    MTI, the PRId register is defined in this (backwards compatible)
 230    way:
 231
 232   +----------------+----------------+----------------+----------------+
 233   | Company Options| Company ID     | Processor ID   | Revision       |
 234   +----------------+----------------+----------------+----------------+
 235    31            24 23            16 15             8 7
 236
 237 */
 238
 239 #define VEX_PRID_COMP_LEGACY      0x00000000
 240 #define VEX_PRID_COMP_MIPS        0x00010000
 241 #define VEX_PRID_COMP_BROADCOM    0x00020000
 242 #define VEX_PRID_COMP_NETLOGIC    0x000C0000
 243 #define VEX_PRID_COMP_CAVIUM      0x000D0000
 244 #define VEX_PRID_COMP_INGENIC_E1  0x00E10000        /* JZ4780 */
 245
 246 /*
 247  * These are valid when 23:16 == PRID_COMP_LEGACY
 248  */
 249 #define VEX_PRID_IMP_LOONGSON_64        0x6300  /* Loongson-2/3 */
 250
 251 /*
 252  * These are the PRID's for when 23:16 == PRID_COMP_MIPS
 253  */
 254 #define VEX_PRID_IMP_34K                0x9500
 255 #define VEX_PRID_IMP_74K                0x9700
 256 #define VEX_PRID_IMP_P5600              0xa800
 257
 258 /*
 259  * Instead of Company Options values, bits 31:24 will be packed with
 260  * additional information, such as isa level and FP mode.
 261  */
 262 #define VEX_MIPS_CPU_ISA_M32R1      0x01000000
 263 #define VEX_MIPS_CPU_ISA_M32R2      0x02000000
 264 #define VEX_MIPS_CPU_ISA_M64R1      0x04000000
 265 #define VEX_MIPS_CPU_ISA_M64R2      0x08000000
 266 #define VEX_MIPS_CPU_ISA_M32R6      0x10000000
 267 #define VEX_MIPS_CPU_ISA_M64R6      0x20000000
 268 /* FP mode is FR = 1 (32 dbl. prec. FP registers) */
 269 #define VEX_MIPS_HOST_FR            0x40000000
 270 /* Get MIPS Extended Information */
 271 #define VEX_MIPS_EX_INFO(x) ((x) & 0xFF000000)
 272 /* Get MIPS Company ID from HWCAPS */
 273 #define VEX_MIPS_COMP_ID(x) ((x) & 0x00FF0000)
 274 /* Get MIPS Processor ID from HWCAPS */
 275 #define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FF00)
 276 /* Get MIPS Revision from HWCAPS */
 277 #define VEX_MIPS_REV(x) ((x) & 0x000000FF)
 278 /* Get host FP mode */
 279 #define VEX_MIPS_HOST_FP_MODE(x) (!!(VEX_MIPS_EX_INFO(x) & VEX_MIPS_HOST_FR))
 280 /* Check if the processor supports MIPS32R2. */
 281 #define VEX_MIPS_CPU_HAS_MIPS32R2(x) (VEX_MIPS_EX_INFO(x) & \
 282                                       VEX_MIPS_CPU_ISA_M32R2)
 283 /* Check if the processor supports MIPS64R2. */
 284 #define VEX_MIPS_CPU_HAS_MIPS64R2(x) (VEX_MIPS_EX_INFO(x) & \
 285                                       VEX_MIPS_CPU_ISA_M64R2)
 286 /* Check if the processor supports MIPSR6. */
 287 #define VEX_MIPS_CPU_HAS_MIPSR6(x) (VEX_MIPS_EX_INFO(x) & \
 288                                     (VEX_MIPS_CPU_ISA_M32R6 | \
 289                                     VEX_MIPS_CPU_ISA_M64R6))
 290 /* Check if the processor supports DSP ASE Rev 2. */
 291 #define VEX_MIPS_PROC_DSP2(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
 292                                (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_74K))
 293 /* Check if the processor supports DSP ASE Rev 1. */
 294 #define VEX_MIPS_PROC_DSP(x)  (VEX_MIPS_PROC_DSP2(x) || \
 295                                ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
 296                                (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_34K)))
 297
 298 /* Check if the processor supports MIPS MSA (SIMD)*/
 299 #define VEX_MIPS_PROC_MSA(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
 300                               (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_P5600) && \
 301                               (VEX_MIPS_HOST_FP_MODE(x)))
 302
 303 /* These return statically allocated strings. */
 304
 305 extern const HChar* LibVEX_ppVexArch    ( VexArch );
 306 extern const HChar* LibVEX_ppVexEndness ( VexEndness endness );
 307 extern const HChar* LibVEX_ppVexHwCaps  ( VexArch, UInt );
 308
 309
 310 /* The various kinds of caches */
 311 typedef enum {
 312    DATA_CACHE=0x500,
 313    INSN_CACHE,
 314    UNIFIED_CACHE
 315 } VexCacheKind;
 316
 317 /* Information about a particular cache */
 318 typedef struct {
 319    VexCacheKind kind;
 320    UInt level;         /* level this cache is at, e.g. 1 for L1 cache */
 321    UInt sizeB;         /* size of this cache in bytes */
 322    UInt line_sizeB;    /* cache line size in bytes */
 323    UInt assoc;         /* set associativity */
 324    Bool is_trace_cache;  /* False, except for certain Pentium 4 models */
 325 } VexCache;
 326
 327 /* Convenience macro to initialise a VexCache */
 328 #define VEX_CACHE_INIT(_kind, _level, _size, _line_size, _assoc)         \
 329          ({ (VexCache) { .kind = _kind, .level = _level, .sizeB = _size, \
 330                .line_sizeB = _line_size, .assoc = _assoc, \
 331                .is_trace_cache = False }; })
 332
 333 /* Information about the cache system as a whole */
 334 typedef struct {
 335    UInt num_levels;
 336    UInt num_caches;
 337    /* Unordered array of caches for this host. NULL if there are
 338       no caches. The following can always be assumed:
 339       (1) There is at most one cache of a given kind per cache level.
 340       (2) If there exists a unified cache at a particular level then
 341           no other cache exists at that level.
 342       (3) The existence of a cache at level N > 1 implies the existence of
 343           at least one cache at level N-1. */
 344    VexCache *caches;
 345    Bool icaches_maintain_coherence;
 346 } VexCacheInfo;
 347
 348
 349 /* This struct is a bit of a hack, but is needed to carry misc
 350    important bits of info about an arch.  Fields which are meaningless
 351    or ignored for the platform in question should be set to zero.
 352    Nb: if you add fields to the struct make sure to update function
 353    LibVEX_default_VexArchInfo. */
 354
 355 typedef
 356    struct {
 357       /* The following three fields are mandatory. */
 358       UInt         hwcaps;
 359       VexEndness   endness;
 360       VexCacheInfo hwcache_info;
 361       /* PPC32/PPC64 only: size of instruction cache line */
 362       Int ppc_icache_line_szB;
 363       /* PPC32/PPC64 only: sizes zeroed by the dcbz/dcbzl instructions
 364          (bug#135264) */
 365       UInt ppc_dcbz_szB;
 366       /* PPC32/PPC64 only: True scv is supported */
 367       Bool ppc_scv_supported;
 368       UInt ppc_dcbzl_szB; /* 0 means unsupported (SIGILL) */
 369       /* ARM64: I- and D- minimum line sizes in log2(bytes), as
 370          obtained from ctr_el0.DminLine and .IminLine.  For example, a
 371          line size of 64 bytes would be encoded here as 6. */
 372       UInt arm64_dMinLine_lg2_szB;
 373       UInt arm64_iMinLine_lg2_szB;
 374       /* ARM64: does the host require us to use the fallback LLSC
 375          implementation? */
 376       Bool arm64_requires_fallback_LLSC;
 377    }
 378    VexArchInfo;
 379
 380 /* Write default settings info *vai. */
 381 extern
 382 void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai );
 383
 384
 385 /* This struct carries guest and host ABI variant information that may
 386    be needed.  Fields which are meaningless or ignored for the
 387    platform in question should be set to zero.
 388
 389    Settings which are believed to be correct are:
 390
 391    guest_stack_redzone_size
 392       guest is ppc32-linux                ==> 0
 393       guest is ppc64-linux                ==> 288
 394       guest is amd64-linux                ==> 128
 395       guest is other                      ==> inapplicable
 396
 397    guest_amd64_assume_fs_is_const
 398       guest is amd64-linux                ==> True
 399       guest is amd64-darwin               ==> False
 400       guest is amd64-solaris              ==> True
 401       guest is other                      ==> inapplicable
 402
 403    guest_amd64_assume_gs_is_const
 404       guest is amd64-darwin               ==> True
 405       guest is amd64-linux                ==> True
 406       guest is amd64-solaris              ==> False
 407       guest is other                      ==> inapplicable
 408
 409    guest_ppc_zap_RZ_at_blr
 410       guest is ppc64-linux                ==> True
 411       guest is ppc32-linux                ==> False
 412       guest is other                      ==> inapplicable
 413
 414    guest_ppc_zap_RZ_at_bl
 415       guest is ppc64-linux                ==> const True
 416       guest is ppc32-linux                ==> const False
 417       guest is other                      ==> inapplicable
 418
 419    guest__use_fallback_LLSC
 420       guest is mips32                     ==> applicable, default True
 421       guest is mips64                     ==> applicable, default True
 422       guest is arm64                      ==> applicable, default False
 423
 424    host_ppc_calls_use_fndescrs:
 425       host is ppc32-linux                 ==> False
 426       host is ppc64-linux                 ==> True
 427       host is other                       ==> inapplicable
 428 */
 429
 430 typedef
 431    struct {
 432       /* PPC and AMD64 GUESTS only: how many bytes below the
 433          stack pointer are validly addressible? */
 434       Int guest_stack_redzone_size;
 435
 436       /* AMD64 GUESTS only: should we translate %fs-prefixed
 437          instructions using the assumption that %fs always contains
 438          the same value? (typically zero on linux and solaris) */
 439       Bool guest_amd64_assume_fs_is_const;
 440
 441       /* AMD64 GUESTS only: should we translate %gs-prefixed
 442          instructions using the assumption that %gs always contains
 443          the same value? (typically 0x60 on darwin)? */
 444       Bool guest_amd64_assume_gs_is_const;
 445
 446       /* AMD64 GUESTS only: for a misaligned memory access, for which we should
 447          generate a trap, should we generate SigBUS (a la FreeBSD) or SIGSEGV
 448          (Linux, OSX) ?? */
 449       Bool guest_amd64_sigbus_on_misalign;
 450
 451       /* PPC GUESTS only: should we zap the stack red zone at a 'blr'
 452          (function return) ? */
 453       Bool guest_ppc_zap_RZ_at_blr;
 454
 455       /* PPC GUESTS only: should we zap the stack red zone at a 'bl'
 456          (function call) ?  Is supplied with the guest address of the
 457          target of the call since that may be significant.  If NULL,
 458          is assumed equivalent to a fn which always returns False. */
 459       Bool (*guest_ppc_zap_RZ_at_bl)(Addr);
 460
 461       /* Potentially for all guests that use LL/SC: use the fallback
 462          (synthesised) implementation rather than passing LL/SC on to
 463          the host? */
 464       Bool guest__use_fallback_LLSC;
 465
 466       /* PPC32/PPC64 HOSTS only: does '&f' give us a pointer to a
 467          function descriptor on the host, or to the function code
 468          itself?  True => descriptor, False => code. */
 469       Bool host_ppc_calls_use_fndescrs;
 470
 471       /* MIPS32/MIPS64 GUESTS only: emulated FPU mode. */
 472       UInt guest_mips_fp_mode;
 473    }
 474    VexAbiInfo;
 475
 476 /* Write default settings info *vbi. */
 477 extern
 478 void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi );
 479
 480
 481 /*-------------------------------------------------------*/
 482 /*--- Control of Vex's optimiser (iropt).             ---*/
 483 /*-------------------------------------------------------*/
 484
 485
 486 /* VexRegisterUpdates specifies when to ensure that the guest state is
 487    up to date, in order of increasing accuracy but increasing expense.
 488
 489      VexRegUpdSpAtMemAccess: all registers are updated at superblock
 490      exits, and SP is also up to date at memory exception points.  The
 491      SP is described by the arch specific functions
 492      guest_<arch>_state_requires_precise_mem_exns.
 493
 494      VexRegUpdUnwindregsAtMemAccess: registers needed to make a stack
 495      trace are up to date at memory exception points.  Typically,
 496      these are PC/SP/FP.  The minimal registers are described by the
 497      arch specific functions guest_<arch>_state_requires_precise_mem_exns.
 498      This is what Valgrind sets as the default.
 499
 500      VexRegUpdAllregsAtMemAccess: all registers up to date at memory
 501      exception points.  This is what normally might be considered as
 502      providing "precise exceptions for memory", but does not
 503      necessarily provide precise register values at any other kind of
 504      exception.
 505
 506      VexRegUpdAllregsAtEachInsn: all registers up to date at each
 507      instruction.
 508 */
 509 typedef
 510    enum {
 511       VexRegUpd_INVALID=0x700,
 512       VexRegUpdSpAtMemAccess,
 513       VexRegUpdUnwindregsAtMemAccess,
 514       VexRegUpdAllregsAtMemAccess,
 515       VexRegUpdAllregsAtEachInsn
 516    }
 517    VexRegisterUpdates;
 518
 519 /* Control of Vex's optimiser. */
 520
 521 typedef
 522    struct {
 523       /* Controls verbosity of iropt.  0 = no output. */
 524       Int iropt_verbosity;
 525       /* Control aggressiveness of iropt.  0 = no opt, 1 = simple
 526          opts, 2 (default) = max optimisation. */
 527       Int iropt_level;
 528       /* Controls when registers are updated in guest state.  Note
 529          that this is the default value.  The VEX client can override
 530          this on a per-IRSB basis if it wants.  bb_to_IR() will query
 531          the client to ask if it wants a different setting for the
 532          block under construction, and that new setting is transported
 533          back to LibVEX_Translate, which feeds it to iropt via the
 534          various do_iropt_BB calls. */
 535       VexRegisterUpdates iropt_register_updates_default;
 536       /* How aggressive should iropt be in unrolling loops?  Higher
 537          numbers make it more enthusiastic about loop unrolling.
 538          Default=120.  A setting of zero disables unrolling.  */
 539       Int iropt_unroll_thresh;
 540       /* What's the maximum basic block length the front end(s) allow?
 541          BBs longer than this are split up.  Default=60 (guest
 542          insns). */
 543       Int guest_max_insns;
 544       /* Should Vex try to construct superblocks, by chasing unconditional
 545          branches/calls to known destinations, and performing AND/OR idiom
 546          recognition?  It is recommended to set this to True as that possibly
 547          improves performance a bit, and also is important for avoiding certain
 548          kinds of false positives in Memcheck.  Default=True.  */
 549       Bool guest_chase;
 550       /* Register allocator version. Allowed values are:
 551          - '2': previous, good and slow implementation.
 552          - '3': current, faster implementation; perhaps producing slightly worse
 553                 spilling decisions. */
 554       UInt regalloc_version;
 555    }
 556    VexControl;
 557
 558
 559 /* Write the default settings into *vcon. */
 560
 561 extern
 562 void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon );
 563
 564
 565 /*-------------------------------------------------------*/
 566 /*--- Storage management control                      ---*/
 567 /*-------------------------------------------------------*/
 568
 569 /* Allocate in Vex's temporary allocation area.  Be careful with this.
 570    You can only call it inside an instrumentation or optimisation
 571    callback that you have previously specified in a call to
 572    LibVEX_Translate.  The storage allocated will only stay alive until
 573    translation of the current basic block is complete. */
 574 extern void* LibVEX_Alloc ( SizeT nbytes );
 575
 576 /* Show Vex allocation statistics. */
 577 extern void LibVEX_ShowAllocStats ( void );
 578
 579
 580 /*-------------------------------------------------------*/
 581 /*--- Describing guest state layout                   ---*/
 582 /*-------------------------------------------------------*/
 583
 584 /* Describe the guest state enough that the instrumentation
 585    functions can work. */
 586
 587 /* The max number of guest state chunks which we can describe as
 588    always defined (for the benefit of Memcheck). */
 589 #define VEXGLO_N_ALWAYSDEFD  24
 590
 591 typedef
 592    struct {
 593       /* Total size of the guest state, in bytes.  Must be
 594          16-aligned. */
 595       Int total_sizeB;
 596       /* Whereabouts is the stack pointer? */
 597       Int offset_SP;
 598       Int sizeof_SP; /* 4 or 8 */
 599       /* Whereabouts is the frame pointer? */
 600       Int offset_FP;
 601       Int sizeof_FP; /* 4 or 8 */
 602       /* Whereabouts is the instruction pointer? */
 603       Int offset_IP;
 604       Int sizeof_IP; /* 4 or 8 */
 605       /* Describe parts of the guest state regarded as 'always
 606          defined'. */
 607       Int n_alwaysDefd;
 608       struct {
 609          Int offset;
 610          Int size;
 611       } alwaysDefd[VEXGLO_N_ALWAYSDEFD];
 612    }
 613    VexGuestLayout;
 614
 615 /* A note about guest state layout.
 616
 617    LibVEX defines the layout for the guest state, in the file
 618    pub/libvex_guest_<arch>.h.  The struct will have an 16-aligned
 619    size.  Each translated bb is assumed to be entered with a specified
 620    register pointing at such a struct.  Beyond that is two copies of
 621    the shadow state area with the same size as the struct.  Beyond
 622    that is a spill area that LibVEX may spill into.  It must have size
 623    LibVEX_N_SPILL_BYTES, and this must be a 16-aligned number.
 624
 625    On entry, the baseblock pointer register must be 16-aligned.
 626
 627    There must be no holes in between the primary guest state, its two
 628    copies, and the spill area.  In short, all 4 areas must have a
 629    16-aligned size and be 16-aligned, and placed back-to-back.
 630 */
 631
 632 #define LibVEX_N_SPILL_BYTES 4096
 633
 634 /* The size of the guest state must be a multiple of this number. */
 635 #define LibVEX_GUEST_STATE_ALIGN 16
 636
 637 /*-------------------------------------------------------*/
 638 /*--- Initialisation of the library                   ---*/
 639 /*-------------------------------------------------------*/
 640
 641 /* Initialise the library.  You must call this first. */
 642
 643 extern void LibVEX_Init (
 644
 645    /* failure exit function */
 646 #  if defined(__cplusplus) && defined(__GNUC__) && __GNUC__ <= 3
 647    /* g++ 3.x doesn't understand attributes on function parameters.
 648       See #265762. */
 649 #  else
 650    __attribute__ ((noreturn))
 651 #  endif
 652    void (*failure_exit) ( void ),
 653
 654    /* logging output function */
 655    void (*log_bytes) ( const HChar*, SizeT nbytes ),
 656
 657    /* debug paranoia level */
 658    Int debuglevel,
 659
 660    /* Control ... */
 661    const VexControl* vcon
 662 );
 663
 664
 665 /*-------------------------------------------------------*/
 666 /*--- Make a translation                              ---*/
 667 /*-------------------------------------------------------*/
 668
 669 /* Describes the outcome of a translation attempt. */
 670 typedef
 671    struct {
 672       /* overall status */
 673       enum { VexTransOK=0x800,
 674              VexTransAccessFail, VexTransOutputFull } status;
 675       /* The number of extents that have a self-check (0 to 3) */
 676       UInt n_sc_extents;
 677       /* Offset in generated code of the profile inc, or -1 if
 678          none.  Needed for later patching. */
 679       Int offs_profInc;
 680       /* Stats only: the number of guest insns included in the
 681          translation.  It may be zero (!). */
 682       UInt n_guest_instrs;
 683       /* Stats only: the number of unconditional branches incorporated into the
 684          trace. */
 685       UShort n_uncond_in_trace;
 686       /* Stats only: the number of conditional branches incorporated into the
 687          trace. */
 688       UShort n_cond_in_trace;
 689    }
 690    VexTranslateResult;
 691
 692
 693 /* Describes precisely the pieces of guest code that a translation
 694    covers.  Now that Vex can chase across BB boundaries, the old
 695    scheme of describing a chunk of guest code merely by its start
 696    address and length is inadequate.
 697
 698    This struct uses 20 bytes on a 32-bit archtecture and 32 bytes on a
 699    64-bit architecture.  Space is important as clients will have to store
 700    one of these for each translation made.
 701 */
 702 typedef
 703    struct {
 704       Addr   base[3];
 705       UShort len[3];
 706       UShort n_used;
 707    }
 708    VexGuestExtents;
 709
 710
 711 /* A structure to carry arguments for LibVEX_Translate.  There are so
 712    many of them, it seems better to have a structure. */
 713 typedef
 714    struct {
 715       /* IN: The instruction sets we are translating from and to.  And
 716          guest/host misc info. */
 717       VexArch      arch_guest;
 718       VexArchInfo  archinfo_guest;
 719       VexArch      arch_host;
 720       VexArchInfo  archinfo_host;
 721       VexAbiInfo   abiinfo_both;
 722
 723       /* IN: an opaque value which is passed as the first arg to all
 724          callback functions supplied in this struct.  Vex has no idea
 725          what's at the other end of this pointer. */
 726       void*   callback_opaque;
 727
 728       /* IN: the block to translate, and its guest address. */
 729       /* where are the actual bytes in the host's address space? */
 730       const UChar*  guest_bytes;
 731       /* where do the bytes really come from in the guest's aspace?
 732          This is the post-redirection guest address.  Not that Vex
 733          understands anything about redirection; that is all done on
 734          the Valgrind side. */
 735       Addr    guest_bytes_addr;
 736
 737       /* Is it OK to chase into this guest address?  May not be
 738          NULL. */
 739       Bool    (*chase_into_ok) ( /*callback_opaque*/void*, Addr );
 740
 741       /* OUT: which bits of guest code actually got translated */
 742       VexGuestExtents* guest_extents;
 743
 744       /* IN: a place to put the resulting code, and its size */
 745       UChar*  host_bytes;
 746       Int     host_bytes_size;
 747       /* OUT: how much of the output area is used. */
 748       Int*    host_bytes_used;
 749
 750       /* IN: optionally, two instrumentation functions.  May be
 751          NULL. */
 752       IRSB*   (*instrument1) ( /*callback_opaque*/void*,
 753                                IRSB*,
 754                                const VexGuestLayout*,
 755                                const VexGuestExtents*,
 756                                const VexArchInfo*,
 757                                IRType gWordTy, IRType hWordTy );
 758       IRSB*   (*instrument2) ( /*callback_opaque*/void*,
 759                                IRSB*,
 760                                const VexGuestLayout*,
 761                                const VexGuestExtents*,
 762                                const VexArchInfo*,
 763                                IRType gWordTy, IRType hWordTy );
 764
 765       IRSB* (*finaltidy) ( IRSB* );
 766
 767       /* IN: a callback used to ask the caller which of the extents,
 768          if any, a self check is required for.  Must not be NULL.
 769          The returned value is a bitmask with a 1 in position i indicating
 770          that the i'th extent needs a check.  Since there can be at most
 771          3 extents, the returned values must be between 0 and 7.
 772
 773          This call also gives the VEX client the opportunity to change
 774          the precision of register update preservation as performed by
 775          the IR optimiser.  Before the call, VEX will set *pxControl
 776          to hold the default register-update status value as specified
 777          by VexControl::iropt_register_updates_default as passed to
 778          LibVEX_Init at library initialisation time.  The client (in
 779          this callback) can if it wants, inspect the value and change
 780          it to something different, and that value will be used for
 781          subsequent IR optimisation of the block. */
 782       UInt (*needs_self_check)( /*callback_opaque*/void*,
 783                                 /*MAYBE_MOD*/VexRegisterUpdates* pxControl,
 784                                 const VexGuestExtents* );
 785
 786       /* IN: optionally, a callback which allows the caller to add its
 787          own IR preamble following the self-check and any other
 788          VEX-generated preamble, if any.  May be NULL.  If non-NULL,
 789          the IRSB under construction is handed to this function, which
 790          presumably adds IR statements to it.  The callback may
 791          optionally complete the block and direct bb_to_IR not to
 792          disassemble any instructions into it; this is indicated by
 793          the callback returning True.
 794       */
 795       Bool    (*preamble_function)(/*callback_opaque*/void*, IRSB*);
 796
 797       /* IN: debug: trace vex activity at various points */
 798       Int     traceflags;
 799
 800       /* IN: debug: print diagnostics when an illegal instr is detected */
 801       Bool    sigill_diag;
 802
 803       /* IN: profiling: add a 64 bit profiler counter increment to the
 804          translation? */
 805       Bool    addProfInc;
 806
 807       /* IN: address of the dispatcher entry points.  Describes the
 808          places where generated code should jump to at the end of each
 809          bb.
 810
 811          At the end of each translation, the next guest address is
 812          placed in the host's standard return register (x86: %eax,
 813          amd64: %rax, ppc32: %r3, ppc64: %r3).  Optionally, the guest
 814          state pointer register (on host x86: %ebp; amd64: %rbp;
 815          ppc32/64: r31) may be set to a VEX_TRC_ value to indicate any
 816          special action required before the next block is run.
 817
 818          Control is then passed back to the dispatcher (beyond Vex's
 819          control; caller supplies this) in the following way:
 820
 821          - On host archs which lack a link register (x86, amd64), by a
 822            jump to the host address specified in
 823            'dispatcher_assisted', if the guest state pointer has been
 824            changed so as to request some action before the next block
 825            is run, or 'dispatcher_unassisted' (the fast path), in
 826            which it is assumed that the guest state pointer is
 827            unchanged and we wish to continue directly with the next
 828            translation.  Both of these must be non-NULL.
 829
 830          - On host archs which have a link register (ppc32, ppc64), by
 831            a branch to the link register (which is guaranteed to be
 832            unchanged from whatever it was at entry to the
 833            translation).  'dispatch_assisted' and
 834            'dispatch_unassisted' must be NULL.
 835
 836          The aim is to get back and forth between translations and the
 837          dispatcher without creating memory traffic to store return
 838          addresses.
 839
 840          FIXME: update this comment
 841       */
 842       const void* disp_cp_chain_me_to_slowEP;
 843       const void* disp_cp_chain_me_to_fastEP;
 844       const void* disp_cp_xindir;
 845       const void* disp_cp_xassisted;
 846    }
 847    VexTranslateArgs;
 848
 849
 850 /* Runs the entire compilation pipeline. */
 851 extern
 852 VexTranslateResult LibVEX_Translate ( /*MOD*/ VexTranslateArgs* );
 853
 854 /* Runs the first half of the compilation pipeline: lifts guest code to IR,
 855    optimises, instruments and optimises it some more. */
 856 extern
 857 IRSB* LibVEX_FrontEnd ( /*MOD*/ VexTranslateArgs*,
 858                         /*OUT*/ VexTranslateResult* res,
 859                         /*OUT*/ VexRegisterUpdates* pxControl );
 860
 861
 862 /* A subtlety re interaction between self-checking translations and
 863    bb-chasing.  The supplied chase_into_ok function should say NO
 864    (False) when presented with any address for which you might want to
 865    make a self-checking translation.
 866
 867    If it doesn't do that, you may end up with Vex chasing from BB #1
 868    to BB #2 (fine); but if you wanted checking for #2 and not #1, that
 869    would not be the result.  Therefore chase_into_ok should disallow
 870    following into #2.  That will force the caller to eventually
 871    request a new translation starting at #2, at which point Vex will
 872    correctly observe the make-a-self-check flag.
 873
 874    FIXME: is this still up to date? */
 875
 876
 877 /*-------------------------------------------------------*/
 878 /*--- Patch existing translations                     ---*/
 879 /*-------------------------------------------------------*/
 880
 881 /* A host address range that was modified by the functions below.
 882    Callers must request I-cache syncing after the call as appropriate. */
 883 typedef
 884    struct {
 885       HWord start;
 886       HWord len;     /* always > 0 */
 887    }
 888    VexInvalRange;
 889
 890 /* Chain an XDirect jump located at place_to_chain so it jumps to
 891    place_to_jump_to.  It is expected (and checked) that this site
 892    currently contains a call to the dispatcher specified by
 893    disp_cp_chain_me_EXPECTED. */
 894 extern
 895 VexInvalRange LibVEX_Chain ( VexArch     arch_host,
 896                              VexEndness  endhess_host,
 897                              void*       place_to_chain,
 898                              const void* disp_cp_chain_me_EXPECTED,
 899                              const void* place_to_jump_to );
 900
 901 /* Undo an XDirect jump located at place_to_unchain, so it is
 902    converted back into a call to disp_cp_chain_me.  It is expected
 903    (and checked) that this site currently contains a jump directly to
 904    the address specified by place_to_jump_to_EXPECTED. */
 905 extern
 906 VexInvalRange LibVEX_UnChain ( VexArch     arch_host,
 907                                VexEndness  endness_host,
 908                                void*       place_to_unchain,
 909                                const void* place_to_jump_to_EXPECTED,
 910                                const void* disp_cp_chain_me );
 911
 912 /* Returns a constant -- the size of the event check that is put at
 913    the start of every translation.  This makes it possible to
 914    calculate the fast entry point address if the slow entry point
 915    address is known (the usual case), or vice versa. */
 916 extern
 917 Int LibVEX_evCheckSzB ( VexArch arch_host );
 918
 919
 920 /* Patch the counter location into an existing ProfInc point.  The
 921    specified point is checked to make sure it is plausible. */
 922 extern
 923 VexInvalRange LibVEX_PatchProfInc ( VexArch      arch_host,
 924                                     VexEndness   endness_host,
 925                                     void*        place_to_patch,
 926                                     const ULong* location_of_counter );
 927
 928
 929 /*-------------------------------------------------------*/
 930 /*--- Show accumulated statistics                     ---*/
 931 /*-------------------------------------------------------*/
 932
 933 extern void LibVEX_ShowStats ( void );
 934
 935 /*-------------------------------------------------------*/
 936 /*-- IR injection                                      --*/
 937 /*-------------------------------------------------------*/
 938
 939 /* IR Injection Control Block */
 940
 941 #define NO_ROUNDING_MODE (~0u)
 942
 943 typedef
 944    struct {
 945       IROp  op;        // the operation to perform
 946       HWord result;    // address of the result
 947       HWord opnd1;     // address of 1st operand
 948       HWord opnd2;     // address of 2nd operand
 949       HWord opnd3;     // address of 3rd operand
 950       HWord opnd4;     // address of 4th operand
 951       IRType t_result; // type of result
 952       IRType t_opnd1;  // type of 1st operand
 953       IRType t_opnd2;  // type of 2nd operand
 954       IRType t_opnd3;  // type of 3rd operand
 955       IRType t_opnd4;  // type of 4th operand
 956       UInt  rounding_mode;
 957       UInt  num_operands; // excluding rounding mode, if any
 958       /* The following two members describe if this operand has immediate
 959        *  operands. There are a few restrictions:
 960        *    (1) An operator can have at most one immediate operand.
 961        * (2) If there is an immediate operand, it is the right-most operand
 962        *  An immediate_index of 0 means there is no immediate operand.
 963        */
 964       UInt immediate_type;  // size of immediate Ity_I8, Ity_16
 965       UInt immediate_index; // operand number: 1, 2
 966    }
 967    IRICB;
 968
 969 extern void LibVEX_InitIRI ( const IRICB * );
 970
 971 /*-------------------------------------------------------*/
 972 /*--- Notes                                           ---*/
 973 /*-------------------------------------------------------*/
 974
 975 /* Code generation conventions that need to be recorded somewhere.
 976    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 977
 978    x86
 979    ~~~
 980    Generated code should be entered using a JMP instruction.  On
 981    entry, %ebp should point to the guest state, and %esp should be a
 982    valid stack pointer.  The generated code may change %eax, %ebx,
 983    %ecx, %edx, %esi, %edi, all the FP registers and control state, and
 984    all the XMM registers.
 985
 986    On entry, the FPU control word should be set to 0x027F, and the SSE
 987    control word (%mxcsr) should be set to 0x1F80.  On exit, they
 988    should still have those values (after masking off the lowest 6 bits
 989    of %mxcsr).  If they don't, there is a bug in VEX-generated code.
 990
 991    Generated code returns to the scheduler using a JMP instruction, to
 992    the address specified in the .dispatch field of VexTranslateArgs.
 993    %eax (or %eax:%edx, if simulating a 64-bit target) will contain the
 994    guest address of the next block to execute.  %ebp may be changed
 995    to a VEX_TRC_ value, otherwise it should be as it was at entry.
 996
 997    CRITICAL ISSUES in x86 code generation.  The only known critical
 998    issue is that the host FPU and SSE state is not properly saved
 999    across calls to helper functions.  If any helper references any
1000    such state, it is likely (1) to misbehave itself, since the FP
1001    stack tags will not be as expected, and (2) after returning to
1002    generated code, the generated code is likely to go wrong.  This
1003    really should be fixed.
1004
1005    amd64
1006    ~~~~~
1007    Analogous to x86.
1008
1009    ppc32
1010    ~~~~~
1011    On entry, guest state pointer is r31.  .dispatch must be NULL.
1012    Control is returned with a branch to the link register.  Generated
1013    code will not change lr.  At return, r3 holds the next guest addr
1014    (or r3:r4 ?).  r31 may be may be changed to a VEX_TRC_ value,
1015    otherwise it should be as it was at entry.
1016
1017    ppc64
1018    ~~~~~
1019    Same as ppc32.
1020
1021    arm32
1022    ~~~~~
1023    r8 is GSP.
1024
1025    arm64
1026    ~~~~~
1027    r21 is GSP.
1028
1029    ALL GUEST ARCHITECTURES
1030    ~~~~~~~~~~~~~~~~~~~~~~~
1031    The guest state must contain two pseudo-registers, guest_CMSTART
1032    and guest_CMLEN.  These are used to specify guest address ranges,
1033    either of code to be invalidated, when used in conjunction with
1034    Ijk_InvalICache, or of d-cache ranges to be flushed, when used in
1035    conjunction with Ijk_FlushDCache.  In such cases, the two _CM
1036    pseudo-regs should be filled in by the IR, and then an exit with
1037    one of the two abovementioned Ijk_ kinds should happen, so that the
1038    dispatcher can action them.  Both pseudo-regs must have size equal
1039    to the guest word size.
1040
1041    The architecture must a third pseudo-register, guest_NRADDR, also
1042    guest-word-sized.  This is used to record the unredirected guest
1043    address at the start of a translation whose start has been
1044    redirected.  By reading this pseudo-register shortly afterwards,
1045    the translation can find out what the corresponding no-redirection
1046    address was.  Note, this is only set for wrap-style redirects, not
1047    for replace-style ones.
1048 */
1049 #endif /* ndef __LIBVEX_H */
1050
1051 /*---------------------------------------------------------------*/
1052 /*---                                                libvex.h ---*/
1053 /*---------------------------------------------------------------*/