VEX/priv/host_arm64_defs.h

   1
   2 /*---------------------------------------------------------------*/
   3 /*--- begin                                 host_arm64_defs.h ---*/
   4 /*---------------------------------------------------------------*/
   5
   6 /*
   7    This file is part of Valgrind, a dynamic binary instrumentation
   8    framework.
   9
  10    Copyright (C) 2013-2017 OpenWorks
  11       info@open-works.net
  12
  13    This program is free software; you can redistribute it and/or
  14    modify it under the terms of the GNU General Public License as
  15    published by the Free Software Foundation; either version 2 of the
  16    License, or (at your option) any later version.
  17
  18    This program is distributed in the hope that it will be useful, but
  19    WITHOUT ANY WARRANTY; without even the implied warranty of
  20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21    General Public License for more details.
  22
  23    You should have received a copy of the GNU General Public License
  24    along with this program; if not, see <http://www.gnu.org/licenses/>.
  25
  26    The GNU General Public License is contained in the file COPYING.
  27 */
  28
  29 #ifndef __VEX_HOST_ARM64_DEFS_H
  30 #define __VEX_HOST_ARM64_DEFS_H
  31
  32 #include "libvex_basictypes.h"
  33 #include "libvex.h"                      // VexArch
  34 #include "host_generic_regs.h"           // HReg
  35
  36
  37 /* --------- Registers. --------- */
  38
  39 #define ST_IN static inline
  40 ST_IN HReg hregARM64_X22 ( void ) { return mkHReg(False, HRcInt64,  22,  0); }
  41 ST_IN HReg hregARM64_X23 ( void ) { return mkHReg(False, HRcInt64,  23,  1); }
  42 ST_IN HReg hregARM64_X24 ( void ) { return mkHReg(False, HRcInt64,  24,  2); }
  43 ST_IN HReg hregARM64_X25 ( void ) { return mkHReg(False, HRcInt64,  25,  3); }
  44 ST_IN HReg hregARM64_X26 ( void ) { return mkHReg(False, HRcInt64,  26,  4); }
  45 ST_IN HReg hregARM64_X27 ( void ) { return mkHReg(False, HRcInt64,  27,  5); }
  46 ST_IN HReg hregARM64_X28 ( void ) { return mkHReg(False, HRcInt64,  28,  6); }
  47
  48 ST_IN HReg hregARM64_X0  ( void ) { return mkHReg(False, HRcInt64,  0,   7); }
  49 ST_IN HReg hregARM64_X1  ( void ) { return mkHReg(False, HRcInt64,  1,   8); }
  50 ST_IN HReg hregARM64_X2  ( void ) { return mkHReg(False, HRcInt64,  2,   9); }
  51 ST_IN HReg hregARM64_X3  ( void ) { return mkHReg(False, HRcInt64,  3,  10); }
  52 ST_IN HReg hregARM64_X4  ( void ) { return mkHReg(False, HRcInt64,  4,  11); }
  53 ST_IN HReg hregARM64_X5  ( void ) { return mkHReg(False, HRcInt64,  5,  12); }
  54 ST_IN HReg hregARM64_X6  ( void ) { return mkHReg(False, HRcInt64,  6,  13); }
  55 ST_IN HReg hregARM64_X7  ( void ) { return mkHReg(False, HRcInt64,  7,  14); }
  56
  57 ST_IN HReg hregARM64_Q16 ( void ) { return mkHReg(False, HRcVec128, 16, 15); }
  58 ST_IN HReg hregARM64_Q17 ( void ) { return mkHReg(False, HRcVec128, 17, 16); }
  59 ST_IN HReg hregARM64_Q18 ( void ) { return mkHReg(False, HRcVec128, 18, 17); }
  60 ST_IN HReg hregARM64_Q19 ( void ) { return mkHReg(False, HRcVec128, 19, 18); }
  61 ST_IN HReg hregARM64_Q20 ( void ) { return mkHReg(False, HRcVec128, 20, 19); }
  62
  63 ST_IN HReg hregARM64_D8  ( void ) { return mkHReg(False, HRcFlt64,  8,  20); }
  64 ST_IN HReg hregARM64_D9  ( void ) { return mkHReg(False, HRcFlt64,  9,  21); }
  65 ST_IN HReg hregARM64_D10 ( void ) { return mkHReg(False, HRcFlt64,  10, 22); }
  66 ST_IN HReg hregARM64_D11 ( void ) { return mkHReg(False, HRcFlt64,  11, 23); }
  67 ST_IN HReg hregARM64_D12 ( void ) { return mkHReg(False, HRcFlt64,  12, 24); }
  68 ST_IN HReg hregARM64_D13 ( void ) { return mkHReg(False, HRcFlt64,  13, 25); }
  69
  70 ST_IN HReg hregARM64_X8  ( void ) { return mkHReg(False, HRcInt64,  8,  26); }
  71 ST_IN HReg hregARM64_X9  ( void ) { return mkHReg(False, HRcInt64,  9,  27); }
  72 ST_IN HReg hregARM64_X21 ( void ) { return mkHReg(False, HRcInt64, 21,  28); }
  73 #undef ST_IN
  74
  75 extern UInt ppHRegARM64 ( HReg );
  76
  77 /* Number of registers used arg passing in function calls */
  78 #define ARM64_N_ARGREGS 8   /* x0 .. x7 */
  79
  80
  81 /* --------- Condition codes. --------- */
  82
  83 typedef
  84    enum {
  85       ARM64cc_EQ  = 0,  /* equal                         : Z=1 */
  86       ARM64cc_NE  = 1,  /* not equal                     : Z=0 */
  87
  88       ARM64cc_CS  = 2,  /* >=u (higher or same)          : C=1 */
  89       ARM64cc_CC  = 3,  /* <u  (lower)                   : C=0 */
  90
  91       ARM64cc_MI  = 4,  /* minus (negative)              : N=1 */
  92       ARM64cc_PL  = 5,  /* plus (zero or +ve)            : N=0 */
  93
  94       ARM64cc_VS  = 6,  /* overflow                      : V=1 */
  95       ARM64cc_VC  = 7,  /* no overflow                   : V=0 */
  96
  97       ARM64cc_HI  = 8,  /* >u   (higher)                 :   C=1 && Z=0 */
  98       ARM64cc_LS  = 9,  /* <=u  (lower or same)          : !(C=1 && Z=0) */
  99
 100       ARM64cc_GE  = 10, /* >=s (signed greater or equal) :   N=V */
 101       ARM64cc_LT  = 11, /* <s  (signed less than)        : !(N=V) */
 102
 103       ARM64cc_GT  = 12, /* >s  (signed greater)          :   Z=0 && N=V */
 104       ARM64cc_LE  = 13, /* <=s (signed less or equal)    : !(Z=0 && N=V) */
 105
 106       ARM64cc_AL  = 14, /* always (unconditional) */
 107       ARM64cc_NV  = 15  /* in 64-bit mode also means "always" */
 108    }
 109    ARM64CondCode;
 110
 111
 112 /* --------- Memory address expressions (amodes). --------- */
 113
 114 typedef
 115    enum {
 116       ARM64am_RI9=10, /* reg + simm9 */
 117       ARM64am_RI12,   /* reg + uimm12 * szB (iow, scaled by access size) */
 118       ARM64am_RR      /* reg1 + reg2 */
 119    }
 120    ARM64AModeTag;
 121
 122 typedef
 123    struct {
 124       ARM64AModeTag tag;
 125       union {
 126          struct {
 127             HReg reg;
 128             Int  simm9; /* -256 .. +255 */
 129          } RI9;
 130          struct {
 131             HReg  reg;
 132             UInt  uimm12; /* 0 .. 4095 */
 133             UChar szB;    /* 1, 2, 4, 8 (16 ?) */
 134          } RI12;
 135          struct {
 136             HReg base;
 137             HReg index;
 138          } RR;
 139       } ARM64am;
 140    }
 141    ARM64AMode;
 142
 143 extern ARM64AMode* ARM64AMode_RI9  ( HReg reg, Int simm9 );
 144 extern ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB );
 145 extern ARM64AMode* ARM64AMode_RR   ( HReg base, HReg index );
 146
 147
 148 /* --------- Reg or uimm12 or (uimm12 << 12) operands --------- */
 149
 150 typedef
 151    enum {
 152       ARM64riA_I12=20, /* uimm12 << 0 or 12 only */
 153       ARM64riA_R       /* reg */
 154    }
 155    ARM64RIATag;
 156
 157 typedef
 158    struct {
 159       ARM64RIATag tag;
 160       union {
 161          struct {
 162             UShort imm12;  /* 0 .. 4095 */
 163             UChar  shift;  /* 0 or 12 only */
 164          } I12;
 165          struct {
 166             HReg reg;
 167          } R;
 168       } ARM64riA;
 169    }
 170    ARM64RIA;
 171
 172 extern ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift );
 173 extern ARM64RIA* ARM64RIA_R   ( HReg );
 174
 175
 176 /* --------- Reg or "bitfield" (logic immediate) operands --------- */
 177
 178 typedef
 179    enum {
 180       ARM64riL_I13=6, /* wierd-o bitfield immediate, 13 bits in total */
 181       ARM64riL_R      /* reg */
 182    }
 183    ARM64RILTag;
 184
 185 typedef
 186    struct {
 187       ARM64RILTag tag;
 188       union {
 189          struct {
 190             UChar bitN; /* 0 .. 1 */
 191             UChar immR; /* 0 .. 63 */
 192             UChar immS; /* 0 .. 63 */
 193          } I13;
 194          struct {
 195             HReg reg;
 196          } R;
 197       } ARM64riL;
 198    }
 199    ARM64RIL;
 200
 201 extern ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS );
 202 extern ARM64RIL* ARM64RIL_R   ( HReg );
 203
 204
 205 /* --------------- Reg or uimm6 operands --------------- */
 206
 207 typedef
 208    enum {
 209       ARM64ri6_I6=30, /* uimm6, 1 .. 63 only */
 210       ARM64ri6_R      /* reg */
 211    }
 212    ARM64RI6Tag;
 213
 214 typedef
 215    struct {
 216       ARM64RI6Tag tag;
 217       union {
 218          struct {
 219             UInt imm6;   /* 1 .. 63 */
 220          } I6;
 221          struct {
 222             HReg reg;
 223          } R;
 224       } ARM64ri6;
 225    }
 226    ARM64RI6;
 227
 228 extern ARM64RI6* ARM64RI6_I6 ( UInt imm6 );
 229 extern ARM64RI6* ARM64RI6_R  ( HReg );
 230
 231
 232 /* --------------------- Instructions --------------------- */
 233
 234 typedef
 235    enum {
 236       ARM64lo_AND=40,
 237       ARM64lo_OR,
 238       ARM64lo_XOR
 239    }
 240    ARM64LogicOp;
 241
 242 typedef
 243    enum {
 244       ARM64sh_SHL=50,
 245       ARM64sh_SHR,
 246       ARM64sh_SAR
 247    }
 248    ARM64ShiftOp;
 249
 250 typedef
 251    enum {
 252       ARM64un_NEG=60,
 253       ARM64un_NOT,
 254       ARM64un_CLZ,
 255    }
 256    ARM64UnaryOp;
 257
 258 typedef
 259    enum {
 260       ARM64mul_PLAIN=70, /* lo64(64 * 64)  */
 261       ARM64mul_ZX,       /* hi64(64 *u 64) */
 262       ARM64mul_SX        /* hi64(64 *s 64) */
 263    }
 264    ARM64MulOp;
 265
 266 typedef
 267    /* These characterise an integer-FP conversion, but don't imply any
 268       particular direction. */
 269    enum {
 270       ARM64cvt_F32_I32S=80,
 271       ARM64cvt_F64_I32S,
 272       ARM64cvt_F32_I64S,
 273       ARM64cvt_F64_I64S,
 274       ARM64cvt_F32_I32U,
 275       ARM64cvt_F64_I32U,
 276       ARM64cvt_F32_I64U,
 277       ARM64cvt_F64_I64U,
 278       ARM64cvt_INVALID
 279    }
 280    ARM64CvtOp;
 281
 282 typedef
 283    enum {
 284       ARM64fpb_ADD=100,
 285       ARM64fpb_SUB,
 286       ARM64fpb_MUL,
 287       ARM64fpb_DIV,
 288       ARM64fpb_INVALID
 289    }
 290    ARM64FpBinOp;
 291
 292 typedef
 293    enum {
 294       ARM64fpu_NEG=110,
 295       ARM64fpu_ABS,
 296       ARM64fpu_SQRT,
 297       ARM64fpu_RINT,
 298       ARM64fpu_RECPX,
 299       ARM64fpu_INVALID
 300    }
 301    ARM64FpUnaryOp;
 302
 303 typedef
 304    enum {
 305       ARM64vecb_ADD64x2=120, ARM64vecb_ADD32x4,
 306       ARM64vecb_ADD16x8,     ARM64vecb_ADD8x16,
 307       ARM64vecb_SUB64x2,     ARM64vecb_SUB32x4,
 308       ARM64vecb_SUB16x8,     ARM64vecb_SUB8x16,
 309                              ARM64vecb_MUL32x4,
 310       ARM64vecb_MUL16x8,     ARM64vecb_MUL8x16,
 311       ARM64vecb_FADD64x2,    ARM64vecb_FADD32x4,
 312       ARM64vecb_FSUB64x2,    ARM64vecb_FSUB32x4,
 313       ARM64vecb_FMUL64x2,    ARM64vecb_FMUL32x4,
 314       ARM64vecb_FDIV64x2,    ARM64vecb_FDIV32x4,
 315       ARM64vecb_FMAX64x2,    ARM64vecb_FMAX32x4,
 316       ARM64vecb_FMIN64x2,    ARM64vecb_FMIN32x4,
 317                              ARM64vecb_UMAX32x4,
 318       ARM64vecb_UMAX16x8,    ARM64vecb_UMAX8x16,
 319                              ARM64vecb_UMIN32x4,
 320       ARM64vecb_UMIN16x8,    ARM64vecb_UMIN8x16,
 321                              ARM64vecb_SMAX32x4,
 322       ARM64vecb_SMAX16x8,    ARM64vecb_SMAX8x16,
 323                              ARM64vecb_SMIN32x4,
 324       ARM64vecb_SMIN16x8,    ARM64vecb_SMIN8x16,
 325       ARM64vecb_AND,
 326       ARM64vecb_ORR,
 327       ARM64vecb_XOR,
 328       ARM64vecb_CMEQ64x2,    ARM64vecb_CMEQ32x4,
 329       ARM64vecb_CMEQ16x8,    ARM64vecb_CMEQ8x16,
 330       ARM64vecb_CMHI64x2,    ARM64vecb_CMHI32x4, /* >u */
 331       ARM64vecb_CMHI16x8,    ARM64vecb_CMHI8x16,
 332       ARM64vecb_CMGT64x2,    ARM64vecb_CMGT32x4, /* >s */
 333       ARM64vecb_CMGT16x8,    ARM64vecb_CMGT8x16,
 334       ARM64vecb_FCMEQ64x2,   ARM64vecb_FCMEQ32x4,
 335       ARM64vecb_FCMGE64x2,   ARM64vecb_FCMGE32x4,
 336       ARM64vecb_FCMGT64x2,   ARM64vecb_FCMGT32x4,
 337       ARM64vecb_TBL1,
 338       ARM64vecb_UZP164x2,    ARM64vecb_UZP132x4,
 339       ARM64vecb_UZP116x8,    ARM64vecb_UZP18x16,
 340       ARM64vecb_UZP264x2,    ARM64vecb_UZP232x4,
 341       ARM64vecb_UZP216x8,    ARM64vecb_UZP28x16,
 342       ARM64vecb_ZIP132x4,    ARM64vecb_ZIP116x8,
 343       ARM64vecb_ZIP18x16,    ARM64vecb_ZIP232x4,
 344       ARM64vecb_ZIP216x8,    ARM64vecb_ZIP28x16,
 345                              ARM64vecb_PMUL8x16,
 346                              ARM64vecb_PMULL8x8,
 347                              ARM64vecb_UMULL2DSS,
 348       ARM64vecb_UMULL4SHH,   ARM64vecb_UMULL8HBB,
 349                              ARM64vecb_SMULL2DSS,
 350       ARM64vecb_SMULL4SHH,   ARM64vecb_SMULL8HBB,
 351       ARM64vecb_SQADD64x2,   ARM64vecb_SQADD32x4,
 352       ARM64vecb_SQADD16x8,   ARM64vecb_SQADD8x16,
 353       ARM64vecb_UQADD64x2,   ARM64vecb_UQADD32x4,
 354       ARM64vecb_UQADD16x8,   ARM64vecb_UQADD8x16,
 355       ARM64vecb_SQSUB64x2,   ARM64vecb_SQSUB32x4,
 356       ARM64vecb_SQSUB16x8,   ARM64vecb_SQSUB8x16,
 357       ARM64vecb_UQSUB64x2,   ARM64vecb_UQSUB32x4,
 358       ARM64vecb_UQSUB16x8,   ARM64vecb_UQSUB8x16,
 359                              ARM64vecb_SQDMULL2DSS,
 360       ARM64vecb_SQDMULL4SHH,
 361                              ARM64vecb_SQDMULH32x4,
 362       ARM64vecb_SQDMULH16x8,
 363                              ARM64vecb_SQRDMULH32x4,
 364       ARM64vecb_SQRDMULH16x8,
 365       ARM64vecb_SQSHL64x2,   ARM64vecb_SQSHL32x4,
 366       ARM64vecb_SQSHL16x8,   ARM64vecb_SQSHL8x16,
 367       ARM64vecb_UQSHL64x2,   ARM64vecb_UQSHL32x4,
 368       ARM64vecb_UQSHL16x8,   ARM64vecb_UQSHL8x16,
 369       ARM64vecb_SQRSHL64x2,  ARM64vecb_SQRSHL32x4,
 370       ARM64vecb_SQRSHL16x8,  ARM64vecb_SQRSHL8x16,
 371       ARM64vecb_UQRSHL64x2,  ARM64vecb_UQRSHL32x4,
 372       ARM64vecb_UQRSHL16x8,  ARM64vecb_UQRSHL8x16,
 373       ARM64vecb_SSHL64x2,    ARM64vecb_SSHL32x4,
 374       ARM64vecb_SSHL16x8,    ARM64vecb_SSHL8x16,
 375       ARM64vecb_USHL64x2,    ARM64vecb_USHL32x4,
 376       ARM64vecb_USHL16x8,    ARM64vecb_USHL8x16,
 377       ARM64vecb_SRSHL64x2,   ARM64vecb_SRSHL32x4,
 378       ARM64vecb_SRSHL16x8,   ARM64vecb_SRSHL8x16,
 379       ARM64vecb_URSHL64x2,   ARM64vecb_URSHL32x4,
 380       ARM64vecb_URSHL16x8,   ARM64vecb_URSHL8x16,
 381       ARM64vecb_FRECPS64x2,  ARM64vecb_FRECPS32x4,
 382       ARM64vecb_FRSQRTS64x2, ARM64vecb_FRSQRTS32x4,
 383       ARM64vecb_INVALID
 384    }
 385    ARM64VecBinOp;
 386
 387 typedef
 388    enum {
 389       ARM64vecmo_SUQADD64x2=300, ARM64vecmo_SUQADD32x4,
 390       ARM64vecmo_SUQADD16x8,     ARM64vecmo_SUQADD8x16,
 391       ARM64vecmo_USQADD64x2,     ARM64vecmo_USQADD32x4,
 392       ARM64vecmo_USQADD16x8,     ARM64vecmo_USQADD8x16,
 393       ARM64vecmo_INVALID
 394    }
 395    ARM64VecModifyOp;
 396
 397 typedef
 398    enum {
 399       ARM64vecu_FNEG64x2=350, ARM64vecu_FNEG32x4,
 400       ARM64vecu_FABS64x2,     ARM64vecu_FABS32x4,
 401       ARM64vecu_NOT,
 402       ARM64vecu_ABS64x2,      ARM64vecu_ABS32x4,
 403       ARM64vecu_ABS16x8,      ARM64vecu_ABS8x16,
 404       ARM64vecu_CLS32x4,      ARM64vecu_CLS16x8,      ARM64vecu_CLS8x16,
 405       ARM64vecu_CLZ32x4,      ARM64vecu_CLZ16x8,      ARM64vecu_CLZ8x16,
 406       ARM64vecu_CNT8x16,
 407       ARM64vecu_RBIT,
 408       ARM64vecu_REV1616B,
 409       ARM64vecu_REV3216B,     ARM64vecu_REV328H,
 410       ARM64vecu_REV6416B,     ARM64vecu_REV648H,      ARM64vecu_REV644S,
 411       ARM64vecu_URECPE32x4,
 412       ARM64vecu_URSQRTE32x4,
 413       ARM64vecu_FRECPE64x2,   ARM64vecu_FRECPE32x4,
 414       ARM64vecu_FRSQRTE64x2,  ARM64vecu_FRSQRTE32x4,
 415       ARM64vecu_FSQRT64x2,    ARM64vecu_FSQRT32x4,
 416       ARM64vecu_INVALID
 417    }
 418    ARM64VecUnaryOp;
 419
 420 typedef
 421    enum {
 422       ARM64vecshi_USHR64x2=400, ARM64vecshi_USHR32x4,
 423       ARM64vecshi_USHR16x8,     ARM64vecshi_USHR8x16,
 424       ARM64vecshi_SSHR64x2,     ARM64vecshi_SSHR32x4,
 425       ARM64vecshi_SSHR16x8,     ARM64vecshi_SSHR8x16,
 426       ARM64vecshi_SHL64x2,      ARM64vecshi_SHL32x4,
 427       ARM64vecshi_SHL16x8,      ARM64vecshi_SHL8x16,
 428       /* These narrowing shifts zero out the top half of the destination
 429          register. */
 430       ARM64vecshi_SQSHRN2SD,    ARM64vecshi_SQSHRN4HS,   ARM64vecshi_SQSHRN8BH,
 431       ARM64vecshi_UQSHRN2SD,    ARM64vecshi_UQSHRN4HS,   ARM64vecshi_UQSHRN8BH,
 432       ARM64vecshi_SQSHRUN2SD,   ARM64vecshi_SQSHRUN4HS,  ARM64vecshi_SQSHRUN8BH,
 433       ARM64vecshi_SQRSHRN2SD,   ARM64vecshi_SQRSHRN4HS,  ARM64vecshi_SQRSHRN8BH,
 434       ARM64vecshi_UQRSHRN2SD,   ARM64vecshi_UQRSHRN4HS,  ARM64vecshi_UQRSHRN8BH,
 435       ARM64vecshi_SQRSHRUN2SD,  ARM64vecshi_SQRSHRUN4HS, ARM64vecshi_SQRSHRUN8BH,
 436       /* Saturating left shifts, of various flavours. */
 437       ARM64vecshi_UQSHL64x2,    ARM64vecshi_UQSHL32x4,
 438       ARM64vecshi_UQSHL16x8,    ARM64vecshi_UQSHL8x16,
 439       ARM64vecshi_SQSHL64x2,    ARM64vecshi_SQSHL32x4,
 440       ARM64vecshi_SQSHL16x8,    ARM64vecshi_SQSHL8x16,
 441       ARM64vecshi_SQSHLU64x2,   ARM64vecshi_SQSHLU32x4,
 442       ARM64vecshi_SQSHLU16x8,   ARM64vecshi_SQSHLU8x16,
 443       ARM64vecshi_INVALID
 444    }
 445    ARM64VecShiftImmOp;
 446
 447 typedef
 448    enum {
 449       ARM64vecna_XTN=450,
 450       ARM64vecna_SQXTN,
 451       ARM64vecna_UQXTN,
 452       ARM64vecna_SQXTUN,
 453       ARM64vecna_INVALID
 454    }
 455    ARM64VecNarrowOp;
 456
 457 typedef
 458    enum {
 459       /* baseline */
 460       ARM64in_Arith=1220,
 461       ARM64in_Cmp,
 462       ARM64in_Logic,
 463       ARM64in_Test,
 464       ARM64in_Shift,
 465       ARM64in_Unary,
 466       ARM64in_Set64,
 467       ARM64in_MovI,        /* int reg-reg move */
 468       ARM64in_Imm64,
 469       ARM64in_LdSt64,
 470       ARM64in_LdSt32,      /* w/ ZX loads */
 471       ARM64in_LdSt16,      /* w/ ZX loads */
 472       ARM64in_LdSt8,       /* w/ ZX loads */
 473       ARM64in_XDirect,     /* direct transfer to GA */
 474       ARM64in_XIndir,      /* indirect transfer to GA */
 475       ARM64in_XAssisted,   /* assisted transfer to GA */
 476       ARM64in_CSel,
 477       ARM64in_Call,
 478       ARM64in_AddToSP,     /* move SP by small, signed constant */
 479       ARM64in_FromSP,      /* move SP to integer register */
 480       ARM64in_Mul,
 481       ARM64in_LdrEX,
 482       ARM64in_StrEX,
 483       ARM64in_CAS,
 484       ARM64in_CASP,
 485       ARM64in_MFence,
 486       ARM64in_ClrEX,
 487       /* ARM64in_V*: scalar ops involving vector registers */
 488       ARM64in_VLdStH,   /* ld/st to/from low 16 bits of vec reg, imm offset */
 489       ARM64in_VLdStS,   /* ld/st to/from low 32 bits of vec reg, imm offset */
 490       ARM64in_VLdStD,   /* ld/st to/from low 64 bits of vec reg, imm offset */
 491       ARM64in_VLdStQ,   /* ld/st to/from all 128 bits of vec reg, no offset */
 492       ARM64in_VCvtI2F,
 493       ARM64in_VCvtF2I,
 494       ARM64in_VCvtSD,   /* scalar 32 bit FP <--> 64 bit FP */
 495       ARM64in_VCvtHS,   /* scalar 16 bit FP <--> 32 bit FP */
 496       ARM64in_VCvtHD,   /* scalar 16 bit FP <--> 64 bit FP */
 497       ARM64in_VUnaryD,
 498       ARM64in_VUnaryS,
 499       ARM64in_VBinD,
 500       ARM64in_VBinS,
 501       ARM64in_VCmpD,
 502       ARM64in_VCmpS,
 503       ARM64in_VFCSel,
 504       ARM64in_FPCR,
 505       ARM64in_FPSR,
 506       /* ARM64in_V*V: vector ops on vector registers */
 507       ARM64in_VBinV,
 508       ARM64in_VModifyV,
 509       ARM64in_VUnaryV,
 510       ARM64in_VNarrowV,
 511       ARM64in_VShiftImmV,
 512       ARM64in_VExtV,
 513       ARM64in_VImmQ,
 514       ARM64in_VDfromX,    /* Move an Xreg to a Dreg */
 515       ARM64in_VQfromX,    /* Move an Xreg to a Qreg lo64, and zero hi64 */
 516       ARM64in_VQfromXX,   /* Move 2 Xregs to a Qreg */
 517       ARM64in_VXfromQ,    /* Move half a Qreg to an Xreg */
 518       ARM64in_VXfromDorS, /* Move Dreg or Sreg(ZX) to an Xreg */
 519       ARM64in_VMov,       /* vector reg-reg move, 16, 8 or 4 bytes */
 520       /* infrastructure */
 521       ARM64in_EvCheck,    /* Event check */
 522       ARM64in_ProfInc     /* 64-bit profile counter increment */
 523    }
 524    ARM64InstrTag;
 525
 526 /* Destinations are on the LEFT (first operand) */
 527
 528 typedef
 529    struct {
 530       ARM64InstrTag tag;
 531       union {
 532          /* --- INTEGER INSTRUCTIONS --- */
 533          /* 64 bit ADD/SUB reg, reg or uimm12<<{0,12} */
 534          struct {
 535             HReg      dst;
 536             HReg      argL;
 537             ARM64RIA* argR;
 538             Bool      isAdd;
 539          } Arith;
 540          /* 64 or 32 bit CMP reg, reg or aimm (SUB and set flags) */
 541          struct {
 542             HReg      argL;
 543             ARM64RIA* argR;
 544             Bool      is64;
 545          } Cmp;
 546          /* 64 bit AND/OR/XOR reg, reg or bitfield-immediate */
 547          struct {
 548             HReg         dst;
 549             HReg         argL;
 550             ARM64RIL*    argR;
 551             ARM64LogicOp op;
 552          } Logic;
 553          /* 64 bit TST reg, reg or bimm (AND and set flags) */
 554          struct {
 555             HReg      argL;
 556             ARM64RIL* argR;
 557          } Test;
 558          /* 64 bit SHL/SHR/SAR, 2nd arg is reg or imm */
 559          struct {
 560             HReg         dst;
 561             HReg         argL;
 562             ARM64RI6*    argR;
 563             ARM64ShiftOp op;
 564          } Shift;
 565          /* NOT/NEG/CLZ, 64 bit only */
 566          struct {
 567             HReg         dst;
 568             HReg         src;
 569             ARM64UnaryOp op;
 570          } Unary;
 571          /* CSET -- Convert a condition code to a 64-bit value (0 or 1). */
 572          struct {
 573             HReg          dst;
 574             ARM64CondCode cond;
 575          } Set64;
 576          /* MOV dst, src -- reg-reg move for integer registers */
 577          struct {
 578             HReg dst;
 579             HReg src;
 580          } MovI;
 581          /* Pseudo-insn; make a 64-bit immediate */
 582          struct {
 583             HReg  dst;
 584             ULong imm64;
 585          } Imm64;
 586          /* 64-bit load or store */
 587          struct {
 588             Bool        isLoad;
 589             HReg        rD;
 590             ARM64AMode* amode;
 591          } LdSt64;
 592          /* zx-32-to-64-bit load, or 32-bit store */
 593          struct {
 594             Bool        isLoad;
 595             HReg        rD;
 596             ARM64AMode* amode;
 597          } LdSt32;
 598          /* zx-16-to-64-bit load, or 16-bit store */
 599          struct {
 600             Bool        isLoad;
 601             HReg        rD;
 602             ARM64AMode* amode;
 603          } LdSt16;
 604          /* zx-8-to-64-bit load, or 8-bit store */
 605          struct {
 606             Bool        isLoad;
 607             HReg        rD;
 608             ARM64AMode* amode;
 609          } LdSt8;
 610          /* Update the guest PC value, then exit requesting to chain
 611             to it.  May be conditional.  Urr, use of Addr64 implicitly
 612             assumes that wordsize(guest) == wordsize(host). */
 613          struct {
 614             Addr64        dstGA;    /* next guest address */
 615             ARM64AMode*   amPC;     /* amode in guest state for PC */
 616             ARM64CondCode cond;     /* can be ARM64cc_AL */
 617             Bool          toFastEP; /* chain to the slow or fast point? */
 618          } XDirect;
 619          /* Boring transfer to a guest address not known at JIT time.
 620             Not chainable.  May be conditional. */
 621          struct {
 622             HReg          dstGA;
 623             ARM64AMode*   amPC;
 624             ARM64CondCode cond; /* can be ARM64cc_AL */
 625          } XIndir;
 626          /* Assisted transfer to a guest address, most general case.
 627             Not chainable.  May be conditional. */
 628          struct {
 629             HReg          dstGA;
 630             ARM64AMode*   amPC;
 631             ARM64CondCode cond; /* can be ARM64cc_AL */
 632             IRJumpKind    jk;
 633          } XAssisted;
 634          /* CSEL: dst = if cond then argL else argR.  cond may be anything. */
 635           struct {
 636             HReg          dst;
 637             HReg          argL;
 638             HReg          argR;
 639             ARM64CondCode cond;
 640          } CSel;
 641          /* Pseudo-insn.  Call target (an absolute address), on given
 642             condition (which could be ARM64cc_AL). */
 643          struct {
 644             RetLoc        rloc;     /* where the return value will be */
 645             Addr64        target;
 646             ARM64CondCode cond;
 647             Int           nArgRegs; /* # regs carrying args: 0 .. 8 */
 648          } Call;
 649          /* move SP by small, signed constant */
 650          struct {
 651             Int simm; /* needs to be 0 % 16 and in the range -4095
 652                          .. 4095 inclusive */
 653          } AddToSP;
 654          /* move SP to integer register */
 655          struct {
 656             HReg dst;
 657          } FromSP;
 658          /* Integer multiply, with 3 variants:
 659               (PLAIN) lo64(64 *  64)
 660               (ZX)    hi64(64 *u 64)
 661               (SX)    hi64(64 *s 64)
 662          */
 663          struct {
 664             HReg       dst;
 665             HReg       argL;
 666             HReg       argR;
 667             ARM64MulOp op;
 668          } Mul;
 669          /* LDXR{,H,B} x2, [x4] */
 670          struct {
 671             Int  szB; /* 1, 2, 4 or 8 */
 672          } LdrEX;
 673          /* STXR{,H,B} w0, x2, [x4] */
 674          struct {
 675             Int  szB; /* 1, 2, 4 or 8 */
 676          } StrEX;
 677          /* x1 = CAS(x3(addr), x5(expected) -> x7(new)),
 678             where x1[8*szB-1 : 0] == x5[8*szB-1 : 0] indicates success,
 679                   x1[8*szB-1 : 0] != x5[8*szB-1 : 0] indicates failure.
 680             Uses x8 as scratch (but that's not allocatable).
 681             Hence: RD x3, x5, x7; WR x1
 682
 683            loop:
 684             (szB=8)  mov  x8, x5
 685             (szB=4)  and  x8, x5, #0xFFFFFFFF
 686             (szB=2)  and  x8, x5, #0xFFFF
 687             (szB=1)  and  x8, x5, #0xFF
 688             -- x8 is correctly zero-extended expected value
 689             ldxr    x1, [x3]
 690             -- x1 is correctly zero-extended actual value
 691             cmp     x1, x8
 692             bne     after
 693             -- if branch taken, failure; x1[[8*szB-1 : 0] holds old value
 694             -- attempt to store
 695             stxr    w8, x7, [x3]
 696             -- if store successful, x1==0, so the eor is "x1 := x5"
 697             -- if store failed,     branch back and try again.
 698             cbne    w8, loop
 699            after:
 700          */
 701          struct {
 702             Int szB; /* 1, 2, 4 or 8 */
 703          } CAS;
 704          struct {
 705             Int szB; /* 4 or 8 */
 706          } CASP;
 707          /* Mem fence.  An insn which fences all loads and stores as
 708             much as possible before continuing.  On ARM64 we emit the
 709             sequence "dsb sy ; dmb sy ; isb sy", which is probably
 710             total nuclear overkill, but better safe than sorry. */
 711          struct {
 712          } MFence;
 713          /* A CLREX instruction. */
 714          struct {
 715          } ClrEX;
 716          /* --- INSTRUCTIONS INVOLVING VECTOR REGISTERS --- */
 717          /* ld/st to/from low 16 bits of vec reg, imm offset */
 718          struct {
 719             Bool isLoad;
 720             HReg hD;
 721             HReg rN;
 722             UInt uimm12;  /* 0 .. 8190 inclusive, 0 % 2 */
 723          } VLdStH;
 724          /* ld/st to/from low 32 bits of vec reg, imm offset */
 725          struct {
 726             Bool isLoad;
 727             HReg sD;
 728             HReg rN;
 729             UInt uimm12;  /* 0 .. 16380 inclusive, 0 % 4 */
 730          } VLdStS;
 731          /* ld/st to/from low 64 bits of vec reg, imm offset */
 732          struct {
 733             Bool isLoad;
 734             HReg dD;
 735             HReg rN;
 736             UInt uimm12;  /* 0 .. 32760 inclusive, 0 % 8 */
 737          } VLdStD;
 738          /* ld/st to/from all 128 bits of vec reg, no offset */
 739          struct {
 740             Bool isLoad;
 741             HReg rQ; // data
 742             HReg rN; // address
 743          } VLdStQ;
 744          /* Scalar conversion of int to float. */
 745          struct {
 746             ARM64CvtOp how;
 747             HReg       rD; // dst, a D or S register
 748             HReg       rS; // src, a W or X register
 749          } VCvtI2F;
 750          /* Scalar conversion of float to int, w/ specified RM. */
 751          struct {
 752             ARM64CvtOp how;
 753             HReg       rD; // dst, a W or X register
 754             HReg       rS; // src, a D or S register
 755             UChar      armRM; // ARM encoded RM:
 756                               // 00=nearest, 01=+inf, 10=-inf, 11=zero
 757          } VCvtF2I;
 758          /* Convert between 32-bit and 64-bit FP values (both ways). (FCVT) */
 759          struct {
 760             Bool sToD; /* True: F32->F64.  False: F64->F32 */
 761             HReg dst;
 762             HReg src;
 763          } VCvtSD;
 764          /* Convert between 16-bit and 32-bit FP values (both ways). (FCVT) */
 765          struct {
 766             Bool hToS; /* True: F16->F32.  False: F32->F16 */
 767             HReg dst;
 768             HReg src;
 769          } VCvtHS;
 770          /* Convert between 16-bit and 64-bit FP values (both ways). (FCVT) */
 771          struct {
 772             Bool hToD; /* True: F16->F64.  False: F64->F16 */
 773             HReg dst;
 774             HReg src;
 775          } VCvtHD;
 776          /* 64-bit FP unary */
 777          struct {
 778             ARM64FpUnaryOp op;
 779             HReg           dst;
 780             HReg           src;
 781          } VUnaryD;
 782          /* 32-bit FP unary */
 783          struct {
 784             ARM64FpUnaryOp op;
 785             HReg           dst;
 786             HReg           src;
 787          } VUnaryS;
 788          /* 64-bit FP binary arithmetic */
 789          struct {
 790             ARM64FpBinOp op;
 791             HReg         dst;
 792             HReg         argL;
 793             HReg         argR;
 794          } VBinD;
 795          /* 32-bit FP binary arithmetic */
 796          struct {
 797             ARM64FpBinOp op;
 798             HReg         dst;
 799             HReg         argL;
 800             HReg         argR;
 801          } VBinS;
 802          /* 64-bit FP compare */
 803          struct {
 804             HReg argL;
 805             HReg argR;
 806          } VCmpD;
 807          /* 32-bit FP compare */
 808          struct {
 809             HReg argL;
 810             HReg argR;
 811          } VCmpS;
 812          /* 32- or 64-bit FP conditional select */
 813          struct {
 814             HReg          dst;
 815             HReg          argL;
 816             HReg          argR;
 817             ARM64CondCode cond;
 818             Bool          isD;
 819          }
 820          VFCSel;
 821          /* Move a 32-bit value to/from the FPCR */
 822          struct {
 823             Bool toFPCR;
 824             HReg iReg;
 825          } FPCR;
 826          /* Move a 32-bit value to/from the FPSR */
 827          struct {
 828             Bool toFPSR;
 829             HReg iReg;
 830          } FPSR;
 831          /* binary vector operation on vector registers */
 832          struct {
 833             ARM64VecBinOp op;
 834             HReg          dst;
 835             HReg          argL;
 836             HReg          argR;
 837          } VBinV;
 838          /* binary vector operation on vector registers.
 839             Dst reg is also a src. */
 840          struct {
 841             ARM64VecModifyOp op;
 842             HReg             mod;
 843             HReg             arg;
 844          } VModifyV;
 845          /* unary vector operation on vector registers */
 846          struct {
 847             ARM64VecUnaryOp op;
 848             HReg            dst;
 849             HReg            arg;
 850          } VUnaryV;
 851          /* vector narrowing, Q -> Q.  Result goes in the bottom half
 852             of dst and the top half is zeroed out.  Iow one of the
 853             XTN family. */
 854         struct {
 855            ARM64VecNarrowOp op;
 856            UInt             dszBlg2; // 0: 16to8_x8  1: 32to16_x4  2: 64to32_x2
 857            HReg             dst;     // Q reg
 858            HReg             src;     // Q reg
 859         } VNarrowV;
 860         /* Vector shift by immediate.  For left shifts, |amt| must be
 861            >= 0 and < implied lane size of |op|.  For right shifts,
 862            |amt| must be > 0 and <= implied lane size of |op|.  Shifts
 863            beyond these ranges are not allowed. */
 864         struct {
 865            ARM64VecShiftImmOp op;
 866            HReg               dst;
 867            HReg               src;
 868            UInt               amt;
 869         } VShiftImmV;
 870         struct {
 871            HReg dst;
 872            HReg srcLo;
 873            HReg srcHi;
 874            UInt amtB;
 875         } VExtV;
 876          struct {
 877             HReg   rQ;
 878             UShort imm; /* Same 1-bit-per-byte encoding as IR */
 879          } VImmQ;
 880          struct {
 881             HReg rD;
 882             HReg rX;
 883          } VDfromX;
 884          struct {
 885             HReg rQ;
 886             HReg rXlo;
 887          } VQfromX;
 888          struct {
 889             HReg rQ;
 890             HReg rXhi;
 891             HReg rXlo;
 892          } VQfromXX;
 893          struct {
 894             HReg rX;
 895             HReg rQ;
 896             UInt laneNo; /* either 0 or 1 */
 897          } VXfromQ;
 898          struct {
 899             HReg rX;
 900             HReg rDorS;
 901             Bool fromD;
 902          } VXfromDorS;
 903          /* MOV dst, src -- reg-reg move for vector registers */
 904          struct {
 905             UInt szB; // 16=mov qD,qS;  8=mov dD,dS;  4=mov sD,sS
 906             HReg dst;
 907             HReg src;
 908          } VMov;
 909          struct {
 910             ARM64AMode* amCounter;
 911             ARM64AMode* amFailAddr;
 912          } EvCheck;
 913          struct {
 914             /* No fields.  The address of the counter to inc is
 915                installed later, post-translation, by patching it in,
 916                as it is not known at translation time. */
 917          } ProfInc;
 918       } ARM64in;
 919    }
 920    ARM64Instr;
 921
 922
 923 extern ARM64Instr* ARM64Instr_Arith   ( HReg, HReg, ARM64RIA*, Bool isAdd );
 924 extern ARM64Instr* ARM64Instr_Cmp     ( HReg, ARM64RIA*, Bool is64 );
 925 extern ARM64Instr* ARM64Instr_Logic   ( HReg, HReg, ARM64RIL*, ARM64LogicOp );
 926 extern ARM64Instr* ARM64Instr_Test    ( HReg, ARM64RIL* );
 927 extern ARM64Instr* ARM64Instr_Shift   ( HReg, HReg, ARM64RI6*, ARM64ShiftOp );
 928 extern ARM64Instr* ARM64Instr_Unary   ( HReg, HReg, ARM64UnaryOp );
 929 extern ARM64Instr* ARM64Instr_Set64   ( HReg, ARM64CondCode );
 930 extern ARM64Instr* ARM64Instr_MovI    ( HReg, HReg );
 931 extern ARM64Instr* ARM64Instr_Imm64   ( HReg, ULong );
 932 extern ARM64Instr* ARM64Instr_LdSt64  ( Bool isLoad, HReg, ARM64AMode* );
 933 extern ARM64Instr* ARM64Instr_LdSt32  ( Bool isLoad, HReg, ARM64AMode* );
 934 extern ARM64Instr* ARM64Instr_LdSt16  ( Bool isLoad, HReg, ARM64AMode* );
 935 extern ARM64Instr* ARM64Instr_LdSt8   ( Bool isLoad, HReg, ARM64AMode* );
 936 extern ARM64Instr* ARM64Instr_XDirect ( Addr64 dstGA, ARM64AMode* amPC,
 937                                         ARM64CondCode cond, Bool toFastEP );
 938 extern ARM64Instr* ARM64Instr_XIndir  ( HReg dstGA, ARM64AMode* amPC,
 939                                         ARM64CondCode cond );
 940 extern ARM64Instr* ARM64Instr_XAssisted ( HReg dstGA, ARM64AMode* amPC,
 941                                           ARM64CondCode cond, IRJumpKind jk );
 942 extern ARM64Instr* ARM64Instr_CSel    ( HReg dst, HReg argL, HReg argR,
 943                                         ARM64CondCode cond );
 944 extern ARM64Instr* ARM64Instr_Call    ( ARM64CondCode, Addr64, Int nArgRegs,
 945                                         RetLoc rloc );
 946 extern ARM64Instr* ARM64Instr_AddToSP ( Int simm );
 947 extern ARM64Instr* ARM64Instr_FromSP  ( HReg dst );
 948 extern ARM64Instr* ARM64Instr_Mul     ( HReg dst, HReg argL, HReg argR,
 949                                         ARM64MulOp op );
 950 extern ARM64Instr* ARM64Instr_LdrEX   ( Int szB );
 951 extern ARM64Instr* ARM64Instr_StrEX   ( Int szB );
 952 extern ARM64Instr* ARM64Instr_CAS     ( Int szB );
 953 extern ARM64Instr* ARM64Instr_CASP    ( Int szB );
 954 extern ARM64Instr* ARM64Instr_MFence  ( void );
 955 extern ARM64Instr* ARM64Instr_ClrEX   ( void );
 956 extern ARM64Instr* ARM64Instr_VLdStH  ( Bool isLoad, HReg sD, HReg rN,
 957                                         UInt uimm12 /* 0 .. 8190, 0 % 2 */ );
 958 extern ARM64Instr* ARM64Instr_VLdStS  ( Bool isLoad, HReg sD, HReg rN,
 959                                         UInt uimm12 /* 0 .. 16380, 0 % 4 */ );
 960 extern ARM64Instr* ARM64Instr_VLdStD  ( Bool isLoad, HReg dD, HReg rN,
 961                                         UInt uimm12 /* 0 .. 32760, 0 % 8 */ );
 962 extern ARM64Instr* ARM64Instr_VLdStQ  ( Bool isLoad, HReg rQ, HReg rN );
 963 extern ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS );
 964 extern ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS,
 965                                         UChar armRM );
 966 extern ARM64Instr* ARM64Instr_VCvtSD  ( Bool sToD, HReg dst, HReg src );
 967 extern ARM64Instr* ARM64Instr_VCvtHS  ( Bool hToS, HReg dst, HReg src );
 968 extern ARM64Instr* ARM64Instr_VCvtHD  ( Bool hToD, HReg dst, HReg src );
 969 extern ARM64Instr* ARM64Instr_VUnaryD ( ARM64FpUnaryOp op, HReg dst, HReg src );
 970 extern ARM64Instr* ARM64Instr_VUnaryS ( ARM64FpUnaryOp op, HReg dst, HReg src );
 971 extern ARM64Instr* ARM64Instr_VBinD   ( ARM64FpBinOp op, HReg, HReg, HReg );
 972 extern ARM64Instr* ARM64Instr_VBinS   ( ARM64FpBinOp op, HReg, HReg, HReg );
 973 extern ARM64Instr* ARM64Instr_VCmpD   ( HReg argL, HReg argR );
 974 extern ARM64Instr* ARM64Instr_VCmpS   ( HReg argL, HReg argR );
 975 extern ARM64Instr* ARM64Instr_VFCSel  ( HReg dst, HReg argL, HReg argR,
 976                                         ARM64CondCode cond, Bool isD );
 977 extern ARM64Instr* ARM64Instr_FPCR    ( Bool toFPCR, HReg iReg );
 978 extern ARM64Instr* ARM64Instr_FPSR    ( Bool toFPSR, HReg iReg );
 979 extern ARM64Instr* ARM64Instr_VBinV   ( ARM64VecBinOp op, HReg, HReg, HReg );
 980 extern ARM64Instr* ARM64Instr_VModifyV ( ARM64VecModifyOp, HReg, HReg );
 981 extern ARM64Instr* ARM64Instr_VUnaryV ( ARM64VecUnaryOp op, HReg, HReg );
 982 extern ARM64Instr* ARM64Instr_VNarrowV ( ARM64VecNarrowOp op, UInt dszBlg2,
 983                                          HReg dst, HReg src );
 984 extern ARM64Instr* ARM64Instr_VShiftImmV ( ARM64VecShiftImmOp op,
 985                                            HReg dst, HReg src, UInt amt );
 986 extern ARM64Instr* ARM64Instr_VExtV   ( HReg dst,
 987                                         HReg srcLo, HReg srcHi, UInt amtB );
 988 extern ARM64Instr* ARM64Instr_VImmQ   ( HReg, UShort );
 989 extern ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX );
 990 extern ARM64Instr* ARM64Instr_VQfromX ( HReg rQ, HReg rXlo );
 991 extern ARM64Instr* ARM64Instr_VQfromXX( HReg rQ, HReg rXhi, HReg rXlo );
 992 extern ARM64Instr* ARM64Instr_VXfromQ ( HReg rX, HReg rQ, UInt laneNo );
 993 extern ARM64Instr* ARM64Instr_VXfromDorS ( HReg rX, HReg rDorS, Bool fromD );
 994 extern ARM64Instr* ARM64Instr_VMov    ( UInt szB, HReg dst, HReg src );
 995
 996 extern ARM64Instr* ARM64Instr_EvCheck ( ARM64AMode* amCounter,
 997                                         ARM64AMode* amFailAddr );
 998 extern ARM64Instr* ARM64Instr_ProfInc ( void );
 999
1000 extern void ppARM64Instr ( const ARM64Instr* );
1001
1002
1003 /* Some functions that insulate the register allocator from details
1004    of the underlying instruction set. */
1005 extern void getRegUsage_ARM64Instr ( HRegUsage*, const ARM64Instr*, Bool );
1006 extern void mapRegs_ARM64Instr     ( HRegRemap*, ARM64Instr*, Bool );
1007 extern Int  emit_ARM64Instr        ( /*MB_MOD*/Bool* is_profInc,
1008                                      UChar* buf, Int nbuf, const ARM64Instr* i,
1009                                      Bool mode64,
1010                                      VexEndness endness_host,
1011                                      const void* disp_cp_chain_me_to_slowEP,
1012                                      const void* disp_cp_chain_me_to_fastEP,
1013                                      const void* disp_cp_xindir,
1014                                      const void* disp_cp_xassisted );
1015
1016 extern void genSpill_ARM64  ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1017                               HReg rreg, Int offset, Bool );
1018 extern void genReload_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
1019                               HReg rreg, Int offset, Bool );
1020 extern ARM64Instr* genMove_ARM64(HReg from, HReg to, Bool);
1021
1022 extern const RRegUniverse* getRRegUniverse_ARM64 ( void );
1023
1024 extern HInstrArray* iselSB_ARM64 ( const IRSB*,
1025                                    VexArch,
1026                                    const VexArchInfo*,
1027                                    const VexAbiInfo*,
1028                                    Int offs_Host_EvC_Counter,
1029                                    Int offs_Host_EvC_FailAddr,
1030                                    Bool chainingAllowed,
1031                                    Bool addProfInc,
1032                                    Addr max_ga );
1033
1034 /* How big is an event check?  This is kind of a kludge because it
1035    depends on the offsets of host_EvC_FAILADDR and
1036    host_EvC_COUNTER. */
1037 extern Int evCheckSzB_ARM64 (void);
1038
1039 /* Perform a chaining and unchaining of an XDirect jump. */
1040 extern VexInvalRange chainXDirect_ARM64 ( VexEndness endness_host,
1041                                           void* place_to_chain,
1042                                           const void* disp_cp_chain_me_EXPECTED,
1043                                           const void* place_to_jump_to );
1044
1045 extern VexInvalRange unchainXDirect_ARM64 ( VexEndness endness_host,
1046                                             void* place_to_unchain,
1047                                             const void* place_to_jump_to_EXPECTED,
1048                                             const void* disp_cp_chain_me );
1049
1050 /* Patch the counter location into an existing ProfInc point. */
1051 extern VexInvalRange patchProfInc_ARM64 ( VexEndness endness_host,
1052                                           void*  place_to_patch,
1053                                           const ULong* location_of_counter );
1054
1055
1056 #endif /* ndef __VEX_HOST_ARM64_DEFS_H */
1057
1058 /*---------------------------------------------------------------*/
1059 /*--- end                                   host_arm64_defs.h ---*/
1060 /*---------------------------------------------------------------*/