VEX/priv/guest_amd64_defs.h

   1
   2 /*---------------------------------------------------------------*/
   3 /*--- begin                                guest_amd64_defs.h ---*/
   4 /*---------------------------------------------------------------*/
   5
   6 /*
   7    This file is part of Valgrind, a dynamic binary instrumentation
   8    framework.
   9
  10    Copyright (C) 2004-2017 OpenWorks LLP
  11       info@open-works.net
  12
  13    This program is free software; you can redistribute it and/or
  14    modify it under the terms of the GNU General Public License as
  15    published by the Free Software Foundation; either version 2 of the
  16    License, or (at your option) any later version.
  17
  18    This program is distributed in the hope that it will be useful, but
  19    WITHOUT ANY WARRANTY; without even the implied warranty of
  20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21    General Public License for more details.
  22
  23    You should have received a copy of the GNU General Public License
  24    along with this program; if not, see <http://www.gnu.org/licenses/>.
  25
  26    The GNU General Public License is contained in the file COPYING.
  27
  28    Neither the names of the U.S. Department of Energy nor the
  29    University of California nor the names of its contributors may be
  30    used to endorse or promote products derived from this software
  31    without prior written permission.
  32 */
  33
  34 /* Only to be used within the guest-amd64 directory. */
  35
  36 #ifndef __VEX_GUEST_AMD64_DEFS_H
  37 #define __VEX_GUEST_AMD64_DEFS_H
  38
  39 #include "libvex_basictypes.h"
  40 #include "libvex_emnote.h"              // VexEmNote
  41 #include "libvex_guest_amd64.h"         // VexGuestAMD64State
  42 #include "guest_generic_bb_to_IR.h"     // DisResult
  43
  44 /*---------------------------------------------------------*/
  45 /*--- amd64 to IR conversion                            ---*/
  46 /*---------------------------------------------------------*/
  47
  48 /* Convert one amd64 insn to IR.  See the type DisOneInstrFn in
  49    guest_generic_bb_to_IR.h. */
  50 extern
  51 DisResult disInstr_AMD64 ( IRSB*        irbb,
  52                            const UChar* guest_code,
  53                            Long         delta,
  54                            Addr         guest_IP,
  55                            VexArch      guest_arch,
  56                            const VexArchInfo* archinfo,
  57                            const VexAbiInfo*  abiinfo,
  58                            VexEndness   host_endness,
  59                            Bool         sigill_diag );
  60
  61 /* Used by the optimiser to specialise calls to helpers. */
  62 extern
  63 IRExpr* guest_amd64_spechelper ( const HChar* function_name,
  64                                  IRExpr** args,
  65                                  IRStmt** precedingStmts,
  66                                  Int      n_precedingStmts );
  67
  68 /* Describes to the optimiser which part of the guest state require
  69    precise memory exceptions.  This is logically part of the guest
  70    state description. */
  71 extern
  72 Bool guest_amd64_state_requires_precise_mem_exns ( Int, Int,
  73                                                    VexRegisterUpdates );
  74
  75 extern
  76 VexGuestLayout amd64guest_layout;
  77
  78
  79 /*---------------------------------------------------------*/
  80 /*--- amd64 guest helpers                               ---*/
  81 /*---------------------------------------------------------*/
  82
  83 /* --- CLEAN HELPERS --- */
  84
  85 extern ULong amd64g_calculate_rflags_all (
  86                 ULong cc_op,
  87                 ULong cc_dep1, ULong cc_dep2, ULong cc_ndep
  88              );
  89
  90 extern ULong amd64g_calculate_rflags_c (
  91                 ULong cc_op,
  92                 ULong cc_dep1, ULong cc_dep2, ULong cc_ndep
  93              );
  94
  95 extern ULong amd64g_calculate_condition (
  96                 ULong/*AMD64Condcode*/ cond,
  97                 ULong cc_op,
  98                 ULong cc_dep1, ULong cc_dep2, ULong cc_ndep
  99              );
 100
 101 extern ULong amd64g_calculate_FXAM ( ULong tag, ULong dbl );
 102
 103 extern ULong amd64g_calculate_RCR  (
 104                 ULong arg, ULong rot_amt, ULong rflags_in, Long sz
 105              );
 106
 107 extern ULong amd64g_calculate_RCL  (
 108                 ULong arg, ULong rot_amt, ULong rflags_in, Long sz
 109              );
 110
 111 extern ULong amd64g_calculate_pclmul(ULong s1, ULong s2, ULong which);
 112
 113 extern ULong amd64g_check_fldcw ( ULong fpucw );
 114
 115 extern ULong amd64g_create_fpucw ( ULong fpround );
 116
 117 extern ULong amd64g_check_ldmxcsr ( ULong mxcsr );
 118
 119 extern ULong amd64g_create_mxcsr ( ULong sseround );
 120
 121 extern VexEmNote amd64g_dirtyhelper_FLDENV  ( VexGuestAMD64State*, HWord );
 122 extern VexEmNote amd64g_dirtyhelper_FRSTOR  ( VexGuestAMD64State*, HWord );
 123 extern VexEmNote amd64g_dirtyhelper_FRSTORS ( VexGuestAMD64State*, HWord );
 124
 125 extern void amd64g_dirtyhelper_FSTENV  ( VexGuestAMD64State*, HWord );
 126 extern void amd64g_dirtyhelper_FNSAVE  ( VexGuestAMD64State*, HWord );
 127 extern void amd64g_dirtyhelper_FNSAVES ( VexGuestAMD64State*, HWord );
 128
 129 /* Translate a guest virtual_addr into a guest linear address by
 130    consulting the supplied LDT/GDT structures.  Their representation
 131    must be as specified in pub/libvex_guest_amd64.h.  To indicate a
 132    translation failure, 1<<32 is returned.  On success, the lower 32
 133    bits of the returned result indicate the linear address.
 134 */
 135 //extern
 136 //ULong amd64g_use_seg_selector ( HWord ldt, HWord gdt,
 137 //                              UInt seg_selector, UInt virtual_addr );
 138
 139 extern ULong amd64g_calculate_mmx_pmaddwd  ( ULong, ULong );
 140 extern ULong amd64g_calculate_mmx_psadbw   ( ULong, ULong );
 141
 142 extern ULong amd64g_calculate_sse_phminposuw ( ULong sLo, ULong sHi );
 143
 144 extern ULong amd64g_calc_crc32b ( ULong crcIn, ULong b );
 145 extern ULong amd64g_calc_crc32w ( ULong crcIn, ULong w );
 146 extern ULong amd64g_calc_crc32l ( ULong crcIn, ULong l );
 147 extern ULong amd64g_calc_crc32q ( ULong crcIn, ULong q );
 148
 149 extern ULong amd64g_calc_mpsadbw ( ULong sHi, ULong sLo,
 150                                    ULong dHi, ULong dLo,
 151                                    ULong imm_and_return_control_bit );
 152
 153 extern ULong amd64g_calculate_pext  ( ULong, ULong );
 154 extern ULong amd64g_calculate_pdep  ( ULong, ULong );
 155
 156 /* --- DIRTY HELPERS --- */
 157
 158 extern ULong amd64g_dirtyhelper_loadF80le  ( Addr/*addr*/ );
 159
 160 extern void  amd64g_dirtyhelper_storeF80le ( Addr/*addr*/, ULong/*data*/ );
 161
 162 extern void  amd64g_dirtyhelper_CPUID_baseline ( VexGuestAMD64State* st );
 163 extern void  amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st );
 164 extern void  amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st );
 165 extern void  amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st,
 166                                                      ULong hasF16C,
 167                                                      ULong hasRDRAND );
 168 extern void  amd64g_dirtyhelper_CPUID_avx2 ( VexGuestAMD64State* st,
 169                                              ULong hasF16C, ULong hasRDRAND );
 170
 171 extern void  amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* );
 172
 173 extern void amd64g_dirtyhelper_XSAVE_COMPONENT_0
 174                ( VexGuestAMD64State* gst, HWord addr );
 175 extern void amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGS
 176                ( VexGuestAMD64State* gst, HWord addr );
 177
 178 extern VexEmNote amd64g_dirtyhelper_XRSTOR_COMPONENT_0
 179                     ( VexGuestAMD64State* gst, HWord addr );
 180 extern VexEmNote amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS
 181                     ( VexGuestAMD64State* gst, HWord addr );
 182
 183 extern ULong amd64g_dirtyhelper_RDTSC ( void );
 184 extern void  amd64g_dirtyhelper_RDTSCP ( VexGuestAMD64State* st );
 185
 186 extern ULong amd64g_dirtyhelper_IN  ( ULong portno, ULong sz/*1,2 or 4*/ );
 187 extern void  amd64g_dirtyhelper_OUT ( ULong portno, ULong data,
 188                                       ULong sz/*1,2 or 4*/ );
 189
 190 extern void amd64g_dirtyhelper_SxDT ( void* address,
 191                                       ULong op /* 0 or 1 */ );
 192
 193 // This returns a 32-bit value from the host's RDRAND in bits 31:0, and the
 194 // resulting C flag value in bit 32.
 195 extern ULong amd64g_dirtyhelper_RDRAND ( void );
 196
 197
 198 /* Helps with PCMP{I,E}STR{I,M}.
 199
 200    CALLED FROM GENERATED CODE: DIRTY HELPER(s).  (But not really,
 201    actually it could be a clean helper, but for the fact that we can't
 202    pass by value 2 x V128 to a clean helper, nor have one returned.)
 203    Reads guest state, writes to guest state for the xSTRM cases, no
 204    accesses of memory, is a pure function.
 205
 206    opc_and_imm contains (4th byte of opcode << 8) | the-imm8-byte so
 207    the callee knows which I/E and I/M variant it is dealing with and
 208    what the specific operation is.  4th byte of opcode is in the range
 209    0x60 to 0x63:
 210        istri  66 0F 3A 63
 211        istrm  66 0F 3A 62
 212        estri  66 0F 3A 61
 213        estrm  66 0F 3A 60
 214
 215    gstOffL and gstOffR are the guest state offsets for the two XMM
 216    register inputs.  We never have to deal with the memory case since
 217    that is handled by pre-loading the relevant value into the fake
 218    XMM16 register.
 219
 220    For ESTRx variants, edxIN and eaxIN hold the values of those two
 221    registers.
 222
 223    In all cases, the bottom 16 bits of the result contain the new
 224    OSZACP %rflags values.  For xSTRI variants, bits[31:16] of the
 225    result hold the new %ecx value.  For xSTRM variants, the helper
 226    writes the result directly to the guest XMM0.
 227
 228    Declarable side effects: in all cases, reads guest state at
 229    [gstOffL, +16) and [gstOffR, +16).  For xSTRM variants, also writes
 230    guest_XMM0.
 231
 232    Is expected to be called with opc_and_imm combinations which have
 233    actually been validated, and will assert if otherwise.  The front
 234    end should ensure we're only called with verified values.
 235 */
 236 extern ULong amd64g_dirtyhelper_PCMPxSTRx (
 237           VexGuestAMD64State*,
 238           HWord opc4_and_imm,
 239           HWord gstOffL, HWord gstOffR,
 240           HWord edxIN, HWord eaxIN
 241        );
 242
 243 /* Implementation of intel AES instructions as described in
 244    Intel  Advanced Vector Extensions
 245           Programming Reference
 246           MARCH 2008
 247           319433-002.
 248
 249    CALLED FROM GENERATED CODE: DIRTY HELPER(s).  (But not really,
 250    actually it could be a clean helper, but for the fact that we can't
 251    pass by value 2 x V128 to a clean helper, nor have one returned.)
 252    Reads guest state, writes to guest state, no
 253    accesses of memory, is a pure function.
 254
 255    opc4 contains the 4th byte of opcode. Front-end should only
 256    give opcode corresponding to AESENC/AESENCLAST/AESDEC/AESDECLAST/AESIMC.
 257    (will assert otherwise).
 258
 259    gstOffL and gstOffR are the guest state offsets for the two XMM
 260    register inputs, gstOffD is the guest state offset for the XMM register
 261    output.  We never have to deal with the memory case since that is handled
 262    by pre-loading the relevant value into the fake XMM16 register.
 263
 264 */
 265 extern void amd64g_dirtyhelper_AES (
 266           VexGuestAMD64State* gst,
 267           HWord opc4, HWord gstOffD,
 268           HWord gstOffL, HWord gstOffR
 269        );
 270
 271 /* Implementation of AESKEYGENASSIST.
 272
 273    CALLED FROM GENERATED CODE: DIRTY HELPER(s).  (But not really,
 274    actually it could be a clean helper, but for the fact that we can't
 275    pass by value 1 x V128 to a clean helper, nor have one returned.)
 276    Reads guest state, writes to guest state, no
 277    accesses of memory, is a pure function.
 278
 279    imm8 is the Round Key constant.
 280
 281    gstOffL and gstOffR are the guest state offsets for the two XMM
 282    register input and output.  We never have to deal with the memory case since
 283    that is handled by pre-loading the relevant value into the fake
 284    XMM16 register.
 285
 286 */
 287 extern void amd64g_dirtyhelper_AESKEYGENASSIST (
 288           VexGuestAMD64State* gst,
 289           HWord imm8,
 290           HWord gstOffL, HWord gstOffR
 291        );
 292
 293 //extern void  amd64g_dirtyhelper_CPUID_sse0 ( VexGuestAMD64State* );
 294 //extern void  amd64g_dirtyhelper_CPUID_sse1 ( VexGuestAMD64State* );
 295 //extern void  amd64g_dirtyhelper_CPUID_sse2 ( VexGuestAMD64State* );
 296
 297 //extern void  amd64g_dirtyhelper_FSAVE ( VexGuestAMD64State*, HWord );
 298
 299 //extern VexEmNote
 300 //            amd64g_dirtyhelper_FRSTOR ( VexGuestAMD64State*, HWord );
 301
 302 //extern void amd64g_dirtyhelper_FSTENV ( VexGuestAMD64State*, HWord );
 303
 304 //extern VexEmNote
 305 //            amd64g_dirtyhelper_FLDENV ( VexGuestAMD64State*, HWord );
 306
 307
 308
 309 /*---------------------------------------------------------*/
 310 /*--- Condition code stuff                              ---*/
 311 /*---------------------------------------------------------*/
 312
 313 /* rflags masks */
 314 #define AMD64G_CC_SHIFT_O   11
 315 #define AMD64G_CC_SHIFT_S   7
 316 #define AMD64G_CC_SHIFT_Z   6
 317 #define AMD64G_CC_SHIFT_A   4
 318 #define AMD64G_CC_SHIFT_C   0
 319 #define AMD64G_CC_SHIFT_P   2
 320
 321 #define AMD64G_CC_MASK_O    (1ULL << AMD64G_CC_SHIFT_O)
 322 #define AMD64G_CC_MASK_S    (1ULL << AMD64G_CC_SHIFT_S)
 323 #define AMD64G_CC_MASK_Z    (1ULL << AMD64G_CC_SHIFT_Z)
 324 #define AMD64G_CC_MASK_A    (1ULL << AMD64G_CC_SHIFT_A)
 325 #define AMD64G_CC_MASK_C    (1ULL << AMD64G_CC_SHIFT_C)
 326 #define AMD64G_CC_MASK_P    (1ULL << AMD64G_CC_SHIFT_P)
 327
 328 /* additional rflags masks */
 329 #define AMD64G_CC_SHIFT_ID  21
 330 #define AMD64G_CC_SHIFT_AC  18
 331 #define AMD64G_CC_SHIFT_D   10
 332
 333 #define AMD64G_CC_MASK_ID   (1ULL << AMD64G_CC_SHIFT_ID)
 334 #define AMD64G_CC_MASK_AC   (1ULL << AMD64G_CC_SHIFT_AC)
 335 #define AMD64G_CC_MASK_D    (1ULL << AMD64G_CC_SHIFT_D)
 336
 337 /* FPU flag masks */
 338 #define AMD64G_FC_SHIFT_C3   14
 339 #define AMD64G_FC_SHIFT_C2   10
 340 #define AMD64G_FC_SHIFT_C1   9
 341 #define AMD64G_FC_SHIFT_C0   8
 342
 343 #define AMD64G_FC_MASK_C3    (1ULL << AMD64G_FC_SHIFT_C3)
 344 #define AMD64G_FC_MASK_C2    (1ULL << AMD64G_FC_SHIFT_C2)
 345 #define AMD64G_FC_MASK_C1    (1ULL << AMD64G_FC_SHIFT_C1)
 346 #define AMD64G_FC_MASK_C0    (1ULL << AMD64G_FC_SHIFT_C0)
 347
 348
 349 /* %RFLAGS thunk descriptors.  A four-word thunk is used to record
 350    details of the most recent flag-setting operation, so the flags can
 351    be computed later if needed.  It is possible to do this a little
 352    more efficiently using a 3-word thunk, but that makes it impossible
 353    to describe the flag data dependencies sufficiently accurately for
 354    Memcheck.  Hence 4 words are used, with minimal loss of efficiency.
 355
 356    The four words are:
 357
 358       CC_OP, which describes the operation.
 359
 360       CC_DEP1 and CC_DEP2.  These are arguments to the operation.
 361          We want Memcheck to believe that the resulting flags are
 362          data-dependent on both CC_DEP1 and CC_DEP2, hence the
 363          name DEP.
 364
 365       CC_NDEP.  This is a 3rd argument to the operation which is
 366          sometimes needed.  We arrange things so that Memcheck does
 367          not believe the resulting flags are data-dependent on CC_NDEP
 368          ("not dependent").
 369
 370    To make Memcheck believe that (the definedness of) the encoded
 371    flags depends only on (the definedness of) CC_DEP1 and CC_DEP2
 372    requires two things:
 373
 374    (1) In the guest state layout info (amd64guest_layout), CC_OP and
 375        CC_NDEP are marked as always defined.
 376
 377    (2) When passing the thunk components to an evaluation function
 378        (calculate_condition, calculate_eflags, calculate_eflags_c) the
 379        IRCallee's mcx_mask must be set so as to exclude from
 380        consideration all passed args except CC_DEP1 and CC_DEP2.
 381
 382    Strictly speaking only (2) is necessary for correctness.  However,
 383    (1) helps efficiency in that since (2) means we never ask about the
 384    definedness of CC_OP or CC_NDEP, we may as well not even bother to
 385    track their definedness.
 386
 387    When building the thunk, it is always necessary to write words into
 388    CC_DEP1 and CC_DEP2, even if those args are not used given the
 389    CC_OP field (eg, CC_DEP2 is not used if CC_OP is CC_LOGIC1/2/4).
 390    This is important because otherwise Memcheck could give false
 391    positives as it does not understand the relationship between the
 392    CC_OP field and CC_DEP1 and CC_DEP2, and so believes that the
 393    definedness of the stored flags always depends on both CC_DEP1 and
 394    CC_DEP2.
 395
 396    However, it is only necessary to set CC_NDEP when the CC_OP value
 397    requires it, because Memcheck ignores CC_NDEP, and the evaluation
 398    functions do understand the CC_OP fields and will only examine
 399    CC_NDEP for suitable values of CC_OP.
 400
 401    A summary of the field usages is:
 402
 403    Operation          DEP1               DEP2               NDEP
 404    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 405
 406    add/sub/mul        first arg          second arg         unused
 407
 408    adc/sbb            first arg          (second arg)
 409                                          XOR old_carry      old_carry
 410
 411    and/or/xor         result             zero               unused
 412
 413    inc/dec            result             zero               old_carry
 414
 415    shl/shr/sar        result             subshifted-        unused
 416                                          result
 417
 418    rol/ror            result             zero               old_flags
 419
 420    copy               old_flags          zero               unused.
 421
 422
 423    Therefore Memcheck will believe the following:
 424
 425    * add/sub/mul -- definedness of result flags depends on definedness
 426      of both args.
 427
 428    * adc/sbb -- definedness of result flags depends on definedness of
 429      both args and definedness of the old C flag.  Because only two
 430      DEP fields are available, the old C flag is XOR'd into the second
 431      arg so that Memcheck sees the data dependency on it.  That means
 432      the NDEP field must contain a second copy of the old C flag
 433      so that the evaluation functions can correctly recover the second
 434      arg.
 435
 436    * and/or/xor are straightforward -- definedness of result flags
 437      depends on definedness of result value.
 438
 439    * inc/dec -- definedness of result flags depends only on
 440      definedness of result.  This isn't really true -- it also depends
 441      on the old C flag.  However, we don't want Memcheck to see that,
 442      and so the old C flag must be passed in NDEP and not in DEP2.
 443      It's inconceivable that a compiler would generate code that puts
 444      the C flag in an undefined state, then does an inc/dec, which
 445      leaves C unchanged, and then makes a conditional jump/move based
 446      on C.  So our fiction seems a good approximation.
 447
 448    * shl/shr/sar -- straightforward, again, definedness of result
 449      flags depends on definedness of result value.  The subshifted
 450      value (value shifted one less) is also needed, but its
 451      definedness is the same as the definedness of the shifted value.
 452
 453    * rol/ror -- these only set O and C, and leave A Z C P alone.
 454      However it seems prudent (as per inc/dec) to say the definedness
 455      of all resulting flags depends on the definedness of the result,
 456      hence the old flags must go in as NDEP and not DEP2.
 457
 458    * rcl/rcr are too difficult to do in-line, and so are done by a
 459      helper function.  They are not part of this scheme.  The helper
 460      function takes the value to be rotated, the rotate amount and the
 461      old flags, and returns the new flags and the rotated value.
 462      Since the helper's mcx_mask does not have any set bits, Memcheck
 463      will lazily propagate undefinedness from any of the 3 args into
 464      both results (flags and actual value).
 465 */
 466 enum {
 467     AMD64G_CC_OP_COPY=0,  /* DEP1 = current flags, DEP2 = 0, NDEP = unused */
 468                           /* just copy DEP1 to output */
 469
 470     AMD64G_CC_OP_ADDB,    /* 1 */
 471     AMD64G_CC_OP_ADDW,    /* 2 DEP1 = argL, DEP2 = argR, NDEP = unused */
 472     AMD64G_CC_OP_ADDL,    /* 3 */
 473     AMD64G_CC_OP_ADDQ,    /* 4 */
 474
 475     AMD64G_CC_OP_SUBB,    /* 5 */
 476     AMD64G_CC_OP_SUBW,    /* 6 DEP1 = argL, DEP2 = argR, NDEP = unused */
 477     AMD64G_CC_OP_SUBL,    /* 7 */
 478     AMD64G_CC_OP_SUBQ,    /* 8 */
 479
 480     AMD64G_CC_OP_ADCB,    /* 9 */
 481     AMD64G_CC_OP_ADCW,    /* 10 DEP1 = argL, DEP2 = argR ^ oldCarry, NDEP = oldCarry */
 482     AMD64G_CC_OP_ADCL,    /* 11 */
 483     AMD64G_CC_OP_ADCQ,    /* 12 */
 484
 485     AMD64G_CC_OP_SBBB,    /* 13 */
 486     AMD64G_CC_OP_SBBW,    /* 14 DEP1 = argL, DEP2 = argR ^ oldCarry, NDEP = oldCarry */
 487     AMD64G_CC_OP_SBBL,    /* 15 */
 488     AMD64G_CC_OP_SBBQ,    /* 16 */
 489
 490     AMD64G_CC_OP_LOGICB,  /* 17 */
 491     AMD64G_CC_OP_LOGICW,  /* 18 DEP1 = result, DEP2 = 0, NDEP = unused */
 492     AMD64G_CC_OP_LOGICL,  /* 19 */
 493     AMD64G_CC_OP_LOGICQ,  /* 20 */
 494
 495     AMD64G_CC_OP_INCB,    /* 21 */
 496     AMD64G_CC_OP_INCW,    /* 22 DEP1 = result, DEP2 = 0, NDEP = oldCarry (0 or 1) */
 497     AMD64G_CC_OP_INCL,    /* 23 */
 498     AMD64G_CC_OP_INCQ,    /* 24 */
 499
 500     AMD64G_CC_OP_DECB,    /* 25 */
 501     AMD64G_CC_OP_DECW,    /* 26 DEP1 = result, DEP2 = 0, NDEP = oldCarry (0 or 1) */
 502     AMD64G_CC_OP_DECL,    /* 27 */
 503     AMD64G_CC_OP_DECQ,    /* 28 */
 504
 505     AMD64G_CC_OP_SHLB,    /* 29 DEP1 = res, DEP2 = res', NDEP = unused */
 506     AMD64G_CC_OP_SHLW,    /* 30 where res' is like res but shifted one bit less */
 507     AMD64G_CC_OP_SHLL,    /* 31 */
 508     AMD64G_CC_OP_SHLQ,    /* 32 */
 509
 510     AMD64G_CC_OP_SHRB,    /* 33 DEP1 = res, DEP2 = res', NDEP = unused */
 511     AMD64G_CC_OP_SHRW,    /* 34 where res' is like res but shifted one bit less */
 512     AMD64G_CC_OP_SHRL,    /* 35 */
 513     AMD64G_CC_OP_SHRQ,    /* 36 */
 514
 515     AMD64G_CC_OP_ROLB,    /* 37 */
 516     AMD64G_CC_OP_ROLW,    /* 38 DEP1 = res, DEP2 = 0, NDEP = old flags */
 517     AMD64G_CC_OP_ROLL,    /* 39 */
 518     AMD64G_CC_OP_ROLQ,    /* 40 */
 519
 520     AMD64G_CC_OP_RORB,    /* 41 */
 521     AMD64G_CC_OP_RORW,    /* 42 DEP1 = res, DEP2 = 0, NDEP = old flags */
 522     AMD64G_CC_OP_RORL,    /* 43 */
 523     AMD64G_CC_OP_RORQ,    /* 44 */
 524
 525     AMD64G_CC_OP_UMULB,   /* 45 */
 526     AMD64G_CC_OP_UMULW,   /* 46 DEP1 = argL, DEP2 = argR, NDEP = unused */
 527     AMD64G_CC_OP_UMULL,   /* 47 */
 528     AMD64G_CC_OP_UMULQ,   /* 48 */
 529
 530     AMD64G_CC_OP_SMULB,   /* 49 */
 531     AMD64G_CC_OP_SMULW,   /* 50 DEP1 = argL, DEP2 = argR, NDEP = unused */
 532     AMD64G_CC_OP_SMULL,   /* 51 */
 533     AMD64G_CC_OP_SMULQ,   /* 52 */
 534
 535     AMD64G_CC_OP_ANDN32,  /* 53 */
 536     AMD64G_CC_OP_ANDN64,  /* 54 DEP1 = res, DEP2 = 0, NDEP = unused */
 537
 538     AMD64G_CC_OP_BLSI32,  /* 55 */
 539     AMD64G_CC_OP_BLSI64,  /* 56 DEP1 = res, DEP2 = arg, NDEP = unused */
 540
 541     AMD64G_CC_OP_BLSMSK32,/* 57 */
 542     AMD64G_CC_OP_BLSMSK64,/* 58 DEP1 = res, DEP2 = arg, NDEP = unused */
 543
 544     AMD64G_CC_OP_BLSR32,  /* 59 */
 545     AMD64G_CC_OP_BLSR64,  /* 60 DEP1 = res, DEP2 = arg, NDEP = unused */
 546
 547     AMD64G_CC_OP_ADCX32,  /* 61 DEP1 = argL, DEP2 = argR ^ oldCarry, .. */
 548     AMD64G_CC_OP_ADCX64,  /* 62 .. NDEP = old flags */
 549
 550     AMD64G_CC_OP_ADOX32,  /* 63 DEP1 = argL, DEP2 = argR ^ oldOverflow, .. */
 551     AMD64G_CC_OP_ADOX64,  /* 64 .. NDEP = old flags */
 552
 553     AMD64G_CC_OP_NUMBER
 554 };
 555
 556 typedef
 557    enum {
 558       AMD64CondO      = 0,  /* overflow           */
 559       AMD64CondNO     = 1,  /* no overflow        */
 560
 561       AMD64CondB      = 2,  /* below              */
 562       AMD64CondNB     = 3,  /* not below          */
 563
 564       AMD64CondZ      = 4,  /* zero               */
 565       AMD64CondNZ     = 5,  /* not zero           */
 566
 567       AMD64CondBE     = 6,  /* below or equal     */
 568       AMD64CondNBE    = 7,  /* not below or equal */
 569
 570       AMD64CondS      = 8,  /* negative           */
 571       AMD64CondNS     = 9,  /* not negative       */
 572
 573       AMD64CondP      = 10, /* parity even        */
 574       AMD64CondNP     = 11, /* not parity even    */
 575
 576       AMD64CondL      = 12, /* less               */
 577       AMD64CondNL     = 13, /* not less           */
 578
 579       AMD64CondLE     = 14, /* less or equal      */
 580       AMD64CondNLE    = 15, /* not less or equal  */
 581
 582       AMD64CondAlways = 16  /* HACK */
 583    }
 584    AMD64Condcode;
 585
 586 #endif /* ndef __VEX_GUEST_AMD64_DEFS_H */
 587
 588 /*---------------------------------------------------------------*/
 589 /*--- end                                  guest_amd64_defs.h ---*/
 590 /*---------------------------------------------------------------*/