none/tests/mips64/load_store.c

   1 #include <stdio.h>
   2 #include "pub_core_basics.h"
   3 #include "macro_load_store.h"
   4
   5 int main()
   6 {
   7    int i;
   8    int s1 = sizeof(int);
   9    int s2 = sizeof(unsigned long long);
  10    init_reg_val2();
  11    /**********************************************************************/
  12    /*-------------------------------LOAD---------------------------------*/
  13    /**********************************************************************/
  14    /* lb */
  15    for (i = 0; i < N*s1; i++)
  16       TEST1("lb", i, reg_val1);
  17
  18    for (i = 0; i < N*s2; i++)
  19       TEST1("lb", i, reg_val2);
  20
  21    /* lbu */
  22    for (i = 0; i < N*s1; i++)
  23       TEST1("lbu", i, reg_val1);
  24
  25    for (i = 0; i < N*s2; i++)
  26       TEST1("lbu", i, reg_val2);
  27
  28    /* ld */
  29    for (i = 0; i < N*s1; i = i+8)
  30       TEST1("ld", i, reg_val1);
  31
  32    for (i = 0; i < N*s2; i = i+8)
  33       TEST1("ld", i, reg_val2);
  34
  35 #if (__mips_isa_rev < 6)
  36    /* ldl */
  37    for (i = 0; i < N*s1; i++)
  38       TEST1("ldl", i, reg_val1);
  39
  40    for (i = 0; i < N*s2; i++)
  41       TEST1("ldl", i, reg_val2);
  42
  43    /* ldr */
  44    for (i = 0; i < N*s1; i++)
  45       TEST1("ldr", i, reg_val1);
  46
  47    for (i = 0; i < N*s2; i++)
  48       TEST1("ldr", i, reg_val2);
  49 #endif
  50
  51    /* lh */
  52    for (i = 0; i < N*s1; i = i+2)
  53       TEST1("lh", i, reg_val1);
  54
  55    for (i = 0; i < N*s2; i = i+2)
  56       TEST1("lh", i, reg_val2);
  57
  58    /* lhu */
  59    for (i = 0; i < N*s1; i = i+2)
  60       TEST1("lhu", i, reg_val1);
  61
  62    for (i = 0; i < N*s2; i = i+2)
  63       TEST1("lhu", i, reg_val2);
  64
  65    /* lw */
  66    for (i = 0; i < N*s1; i = i+4)
  67       TEST1("lw", i, reg_val1);
  68
  69    for (i = 0; i < N*s2; i = i+4)
  70       TEST1("lw", i, reg_val2);
  71
  72 #if (__mips_isa_rev < 6)
  73    /* lwl */
  74    for (i = 0; i < N*s1; i++)
  75       TEST1("lwl", i, reg_val1);
  76
  77    for (i = 0; i < N*s2; i++)
  78       TEST1("lwl", i, reg_val2);
  79
  80    /* lwr */
  81    for (i = 0; i < N*s1; i++)
  82       TEST1("lwr", i, reg_val1);
  83
  84    for (i = 0; i < N*s2; i++)
  85       TEST1("lwr", i, reg_val2);
  86 #endif
  87    /* lwu */
  88    for (i = 0; i < N*s1; i = i+4)
  89       TEST1("lwu", i, reg_val1);
  90
  91    for (i = 0; i < N*s2; i = i+4)
  92       TEST1("lwu", i, reg_val2);
  93
  94    /**********************************************************************/
  95    /*-------------------------------STORE--------------------------------*/
  96    /**********************************************************************/
  97    init_reg_val_zero();
  98    /* sb */
  99    for (i = 0; i < (N-1)*s2; i++)
 100       TEST2("sb", i);
 101
 102    init_reg_val_zero();
 103    /* sd */
 104    for (i = 0; i < (N-1)*s2; i = i+8)
 105       TEST2("sd", i);
 106
 107 #if (__mips_isa_rev < 6)
 108    init_reg_val_zero();
 109    /* sdl */
 110    for (i = 0; i < (N-1)*s2; i++)
 111       TEST2("sdl", i);
 112
 113    init_reg_val_zero();
 114    /* sdr */
 115    for (i = 8; i < (N-1)*s2; i++)
 116       TEST2("sdr", i);
 117 #endif
 118    init_reg_val_zero();
 119    /* sh */
 120    for (i = 0; i < (N-1)*s2; i = i+2)
 121       TEST2("sh", i);
 122
 123    init_reg_val_zero();
 124    /* sw */
 125    for (i = 0; i < (N-1)*s2; i = i+4)
 126       TEST2("sw", i);
 127
 128    init_reg_val_zero();
 129
 130 #if (__mips_isa_rev < 6)
 131    /* swl */
 132    for (i = 4; i < (N-1)*s2; i++)
 133       TEST2("swl", i);
 134
 135    init_reg_val_zero();
 136    /* swr */
 137    for (i = 4; i < (N-1)*s2; i++)
 138       TEST2("swr", i);
 139 #endif
 140    return 0;
 141 }