none/tests/mips64/cvm_ins.c

   1 #include <stdio.h>
   2 #include "pub_core_basics.h"
   3 const int reg_val[256] = {
   4
   5    0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L,
   6    0x130476dcL, 0x17c56b6bL, 0x1a864db2L, 0x1e475005L,
   7    0x2608edb8L, 0x22c9f00fL, 0x2f8ad6d6L, 0x2b4bcb61L,
   8    0x350c9b64L, 0x31cd86d3L, 0x3c8ea00aL, 0x384fbdbdL,
   9    0x4c11db70L, 0x48d0c6c7L, 0x4593e01eL, 0x4152fda9L,
  10    0x5f15adacL, 0x5bd4b01bL, 0x569796c2L, 0x52568b75L,
  11    0x6a1936c8L, 0x6ed82b7fL, 0x639b0da6L, 0x675a1011L,
  12    0x791d4014L, 0x7ddc5da3L, 0x709f7b7aL, 0x745e66cdL,
  13    0x9823b6e0L, 0x9ce2ab57L, 0x91a18d8eL, 0x95609039L,
  14    0x8b27c03cL, 0x8fe6dd8bL, 0x82a5fb52L, 0x8664e6e5L,
  15    0xbe2b5b58L, 0xbaea46efL, 0xb7a96036L, 0xb3687d81L,
  16    0xad2f2d84L, 0xa9ee3033L, 0xa4ad16eaL, 0xa06c0b5dL,
  17    0xd4326d90L, 0xd0f37027L, 0xddb056feL, 0xd9714b49L,
  18    0xc7361b4cL, 0xc3f706fbL, 0xceb42022L, 0xca753d95L,
  19    0xf23a8028L, 0xf6fb9d9fL, 0xfbb8bb46L, 0xff79a6f1L,
  20    0xe13ef6f4L, 0xe5ffeb43L, 0xe8bccd9aL, 0xec7dd02dL,
  21    0x34867077L, 0x30476dc0L, 0x3d044b19L, 0x39c556aeL,
  22    0x278206abL, 0x23431b1cL, 0x2e003dc5L, 0x2ac12072L,
  23    0x128e9dcfL, 0x164f8078L, 0x1b0ca6a1L, 0x1fcdbb16L,
  24    0x018aeb13L, 0x054bf6a4L, 0x0808d07dL, 0x0cc9cdcaL,
  25    0x7897ab07L, 0x7c56b6b0L, 0x71159069L, 0x75d48ddeL,
  26    0x6b93dddbL, 0x6f52c06cL, 0x6211e6b5L, 0x66d0fb02L,
  27    0x5e9f46bfL, 0x5a5e5b08L, 0x571d7dd1L, 0x53dc6066L,
  28    0x4d9b3063L, 0x495a2dd4L, 0x44190b0dL, 0x40d816baL,
  29    0xaca5c697L, 0xa864db20L, 0xa527fdf9L, 0xa1e6e04eL,
  30    0xbfa1b04bL, 0xbb60adfcL, 0xb6238b25L, 0xb2e29692L,
  31    0x8aad2b2fL, 0x8e6c3698L, 0x832f1041L, 0x87ee0df6L,
  32    0x99a95df3L, 0x9d684044L, 0x902b669dL, 0x94ea7b2aL,
  33    0xe0b41de7L, 0xe4750050L, 0xe9362689L, 0xedf73b3eL,
  34    0xf3b06b3bL, 0xf771768cL, 0xfa325055L, 0xfef34de2L,
  35    0xc6bcf05fL, 0xc27dede8L, 0xcf3ecb31L, 0xcbffd686L,
  36    0xd5b88683L, 0xd1799b34L, 0xdc3abdedL, 0xd8fba05aL,
  37    0x690ce0eeL, 0x6dcdfd59L, 0x608edb80L, 0x644fc637L,
  38    0x7a089632L, 0x7ec98b85L, 0x738aad5cL, 0x774bb0ebL,
  39    0x4f040d56L, 0x4bc510e1L, 0x46863638L, 0x42472b8fL,
  40    0x5c007b8aL, 0x58c1663dL, 0x558240e4L, 0x51435d53L,
  41    0x251d3b9eL, 0x21dc2629L, 0x2c9f00f0L, 0x285e1d47L,
  42    0x36194d42L, 0x32d850f5L, 0x3f9b762cL, 0x3b5a6b9bL,
  43    0x0315d626L, 0x07d4cb91L, 0x0a97ed48L, 0x0e56f0ffL,
  44    0x1011a0faL, 0x14d0bd4dL, 0x19939b94L, 0x1d528623L,
  45    0xf12f560eL, 0xf5ee4bb9L, 0xf8ad6d60L, 0xfc6c70d7L,
  46    0xe22b20d2L, 0xe6ea3d65L, 0xeba91bbcL, 0xef68060bL,
  47    0xd727bbb6L, 0xd3e6a601L, 0xdea580d8L, 0xda649d6fL,
  48    0xc423cd6aL, 0xc0e2d0ddL, 0xcda1f604L, 0xc960ebb3L,
  49    0xbd3e8d7eL, 0xb9ff90c9L, 0xb4bcb610L, 0xb07daba7L,
  50    0xae3afba2L, 0xaafbe615L, 0xa7b8c0ccL, 0xa379dd7bL,
  51    0x9b3660c6L, 0x9ff77d71L, 0x92b45ba8L, 0x9675461fL,
  52    0x8832161aL, 0x8cf30badL, 0x81b02d74L, 0x857130c3L,
  53    0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L,
  54    0x4e8ee645L, 0x4a4ffbf2L, 0x470cdd2bL, 0x43cdc09cL,
  55    0x7b827d21L, 0x7f436096L, 0x7200464fL, 0x76c15bf8L,
  56    0x68860bfdL, 0x6c47164aL, 0x61043093L, 0x65c52d24L,
  57    0x119b4be9L, 0x155a565eL, 0x18197087L, 0x1cd86d30L,
  58    0x029f3d35L, 0x065e2082L, 0x0b1d065bL, 0x0fdc1becL,
  59    0x3793a651L, 0x3352bbe6L, 0x3e119d3fL, 0x3ad08088L,
  60    0x2497d08dL, 0x2056cd3aL, 0x2d15ebe3L, 0x29d4f654L,
  61    0xc5a92679L, 0xc1683bceL, 0xcc2b1d17L, 0xc8ea00a0L,
  62    0xd6ad50a5L, 0xd26c4d12L, 0xdf2f6bcbL, 0xdbee767cL,
  63    0xe3a1cbc1L, 0xe760d676L, 0xea23f0afL, 0xeee2ed18L,
  64    0xf0a5bd1dL, 0xf464a0aaL, 0xf9278673L, 0xfde69bc4L,
  65    0x89b8fd09L, 0x8d79e0beL, 0x803ac667L, 0x84fbdbd0L,
  66    0x9abc8bd5L, 0x9e7d9662L, 0x933eb0bbL, 0x97ffad0cL,
  67    0xafb010b1L, 0xab710d06L, 0xa6322bdfL, 0xa2f33668L,
  68    0xbcb4666dL, 0xb8757bdaL, 0xb5365d03L, 0xb1f740b4L
  69 };
  70
  71 #define TESTINST1(instruction, RSVal, RT, RS, p, lenm1)             \
  72 {                                                                   \
  73    RegWord out;                                                     \
  74    __asm__ volatile(                                                \
  75       "li   $" #RT ", 0"   "\n\t"                                   \
  76       "move $" #RS ", %1"  "\n\t"                                   \
  77       instruction          "\n\t"                                   \
  78       "move %0, $" #RT     "\n\t"                                   \
  79       : "=&r" (out)                                                 \
  80       : "r" (RSVal)                                                 \
  81       : #RS, #RT, "cc", "memory"                                    \
  82         );                                                          \
  83    printf("%s :: rt 0x%" FMT_REGWORD "x rs 0x%x, p 0x%08x, "        \
  84           "lenm1 0x%08x\n", instruction, out, RSVal, p, lenm1);     \
  85 }
  86 #define TESTINST2(instruction, RSVal, RTval, RD, RS, RT)  \
  87 {                                                         \
  88    RegWord out;                                           \
  89    __asm__ volatile(                                      \
  90       "li   $" #RD ", 0"   "\n\t"                         \
  91       "move $" #RS ", %1"  "\n\t"                         \
  92       "move $" #RT ", %2"  "\n\t"                         \
  93       instruction          "\n\t"                         \
  94       "move %0, $" #RD     "\n\t"                         \
  95       : "=&r" (out)                                       \
  96       : "r" (RSVal), "r" (RTval)                          \
  97       : #RD, #RS, #RT, "cc", "memory"                     \
  98         );                                                \
  99    printf("%s :: rd 0x%" FMT_REGWORD "x rs 0x%x, "        \
 100           "rt 0x%x\n", instruction, out, RSVal, RTval);   \
 101 }
 102 #define TESTINST3(instruction, RSVal, RT, RS, imm)     \
 103 {                                                      \
 104    RegWord out;                                        \
 105    __asm__ volatile(                                   \
 106       "li   $" #RT ", 0"   "\n\t"                      \
 107       "move $" #RS ", %1"  "\n\t"                      \
 108       instruction          "\n\t"                      \
 109       "move %0, $" #RT     "\n\t"                      \
 110       : "=&r" (out)                                    \
 111       : "r" (RSVal)                                    \
 112       : #RS, #RT, "cc", "memory"                       \
 113         );                                             \
 114    printf("%s :: rt 0x%" FMT_REGWORD "x rs 0x%x,imm "  \
 115           "0x%08x\n", instruction, out, RSVal, imm);   \
 116 }
 117
 118 typedef enum {
 119    EXTS=0, EXTS32, CINS, CINS32, SNEI, SNE, SEQI, DMUL, SEQ
 120 } cvm_op;
 121
 122 int main()
 123 {
 124 #if (_MIPS_ARCH_OCTEON)
 125    int i, j;
 126    cvm_op op;
 127    for (op = EXTS; op <= SEQ; op++) {
 128       switch(op) {
 129          case EXTS: {  /* To extract and sign-extend a bit field that starts
 130                           from the lower 32 bits of a register. */
 131             for (i = 0; i <= 255; i+=4)
 132                TESTINST1("exts $t1, $t2, 1, 7", reg_val[i], t1, t2, 1, 7);
 133             break;
 134          }
 135
 136          case EXTS32: { /* To extract and sign-extend a bit field that starts
 137                            from the upper 32 bits of a register. */
 138             for (i = 0; i <= 255; i+=4)
 139                TESTINST1("exts32 $t1, $t2, 1 , 7",  reg_val[i], t1, t2, 1, 7);
 140             break;
 141          }
 142
 143          case CINS:{  /* To insert a bit field that starts in the lower 32 bits
 144                          of a register. */
 145             for (i = 0; i <= 255; i+=4)
 146                TESTINST1("cins $t1, $t2, 2 , 9",  reg_val[i], t1, t2, 2, 9);
 147             break;
 148          }
 149
 150          case CINS32: { /* To insert a bit field that starts in the upper
 151                            32 bits of a register. */
 152             for (i =0; i <= 255; i+=4)
 153                TESTINST1("cins32 $t1, $t2, 2 , 9", reg_val[i], t1, t2, 2, 9);
 154             break;
 155          }
 156
 157          case SEQ: {  /* To record the result of an equals comparison. */
 158             for (i = 0; i <= 255; i+=4)
 159                for (j = 0; j <= 255; j+=4)
 160                   TESTINST2("seq $t1, $t2 ,$t3 ", reg_val[i], reg_val[j],
 161                                                   t1, t2, t3);
 162             break;
 163          }
 164
 165          case SEQI: {  /* To record the result of an equals comparison
 166                           with a constant. */
 167             /* First, make sure at least one testcase has source value (rs)
 168                that equals the immediate value to validate the true case. */
 169             const int immvalue = 9;
 170             TESTINST3("seqi $t1, $t2 ,9 ", immvalue, t1, t2, immvalue);
 171             for (i = 0; i <= 255; i+=4)
 172                TESTINST3("seqi $t1, $t2 ,9 ",  reg_val[i], t1, t2, 9);
 173             break;
 174          }
 175
 176          case SNE: {  /* To record the result of a not equals comparison. */
 177             for (i = 0; i <= 255; i+=4)
 178                for (j = 0; j<= 255; j+=4)
 179                   TESTINST2("sne $t1, $t2 ,$t3 ", reg_val[i], reg_val[j],
 180                                                   t1, t2, t3);
 181             break;
 182          }
 183
 184          case SNEI: {  /* To record the result of a not equals comparison
 185                           with a constant. */
 186             /* First, make sure at least one testcase has source value (rs)
 187                that equals the immediate value to validate the false case. */
 188             const int immvalue = 9;
 189             TESTINST3("snei $t1, $t2 ,9 ", immvalue, t1, t2, immvalue);
 190             for (i = 0; i <= 255; i+=1)
 191                TESTINST3("snei $t1, $t2 ,9 ", reg_val[i], t1, t2, 9);
 192             break;
 193          }
 194
 195          case DMUL: {  /* To multiply 64-bit signed integers and
 196                           write the result to a GPR. */
 197             for (i = 0; i <= 255; i+=4)
 198                for (j = 0; j <= 255; j+=8)
 199                   TESTINST2("dmul $t1, $t2 ,$t3 ", reg_val[i], reg_val[j],
 200                                                    t1, t2, t3);
 201             break;
 202          }
 203       }
 204    }
 205 #endif
 206    return 0;
 207 }