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2 This file records register use conventions and info for the 4
3 supported platforms (since it is ABI dependent). This is so as to
4 avoid having to endlessly re-look up this info in ABI documents.
6 -----------------------
8 x86-linux
9 ~~~~~~~~~
11 Reg Callee Arg
12 Name Saves? Reg? Comment Vex-uses?
13 --------------------------------------------------------------
14 eax n n int[31:0] retreg y
15 ebx y n y
16 ecx n n y
17 edx n n int[63:32] retreg y
18 esi y n y
19 edi y n y
20 ebp y n & guest state
21 esp reserved n/a n/a
22 eflags n n/a y
23 st0 n ? n fp retreg y
24 st1-7 n ? n y
25 xmm0-7 n ? n y
26 gs Thread ptr
28 In the case where arguments are passed in registers, the arg1,2,3
29 registers are EAX, EDX, and ECX respectively.
31 amd64-linux
32 ~~~~~~~~~~~
34 Reg Callee Arg
35 Name Saves? Reg? Comment Vex-uses?
36 -------------------------------------------------------------------
37 rax n n int[63:0] retreg
38 rbx y n y
39 rcx n int#4
40 rdx n int#3 int[127:64] retreg
41 rsi n int#2 y
42 rdi n int#1 y
43 rbp y n & guest state
44 rsp reserved n/a n/a
45 r8 n int#5 y
46 r9 n int#6 y
47 r10 n ?
48 r11 n jmp temporary
49 r12-15 y y
50 eflags n n/a y
51 st0-7 n n long double retreg y
52 xmm0 n fp#1 fp retreg
53 xmm1 n fp#2 fp-high retreg
54 xmm2-7 n fp#3-8 y (3-7)
55 xmm8-15 n y (8-12)
56 fs thread ptr
58 ppc32-linux
59 ~~~~~~~~~~~
61 Reg Callee Arg
62 Name Saves? Reg? Comment Vex-uses?
63 -------------------------------------------------------------------
64 r0 n n sometimes RAZ
65 r1 y n stack pointer
66 r2 n n thread ptr
67 r3 n int#1 int[31:0] retreg y
68 r4 n int#2 also int retreg y
69 r5 n int#3 y
70 r6 n int#4 y
71 r7 n int#5 y
72 r8 n int#6 y
73 r9 n int#7 y
74 r10 n int#8 y
75 r11 n y
76 r12 n y
77 r13 ?
78 r14-28 y y
79 r29 y reserved for dispatcher
80 r30 y altivec spill temporary
81 r31 y & guest state
82 f0 n
83 f1 n fp#1 fp retreg
84 f2-8 n fp#2-8
85 f9-13 n
86 f14-31 y y (14-21)
87 v0-v19 ?
88 v20-31 y y (20-27,29)
89 cr0-7
90 lr y return address
91 ctr n
92 xer n
93 fpscr
96 ppc64-linux
97 ~~~~~~~~~~~
98 Reg Callee Arg
99 Name Saves? Reg? Comment Vex-uses?
100 -------------------------------------------------------------------
101 r13 n n thread ptr
102 TBD
105 arm-linux
106 ~~~~~~~~~
108 Reg Callee Arg
109 Name Saves? Reg? Comment Vex-uses?
110 --------------------------------------------------------------
111 r0 int#1 int[31:0] retreg? avail
112 r1 int#2 int[63:32] retreg? avail
113 r2 int#3 avail
114 r3 int#4 avail
115 r4 y avail
116 r5 y avail
117 r6 y avail
118 r7 y avail
119 r8 y GSP
120 r9 y (but only on Linux; not in general) avail
121 r10 y avail
122 r11 y avail
123 r12 possibly used by linker? unavail
124 r13(sp) unavail
125 r14(lr) unavail
126 r15(pc) unavail
127 cp15/c3/r2 thread ptr (see libvex_guest_arm.h, guest_TPIDRURO)
129 VFP: d8-d15 are callee-saved
130 r12 (IP) is probably available for use as a caller-saved
131 register; but instead we use it as an intermediate for
132 holding the address for F32/F64 spills, since the VFP load/store
133 insns have reg+offset forms for offsets only up to 1020, which
134 often isn't enough.
137 arm64-linux
138 ~~~~~~~~~~~
140 Reg Callee Arg
141 Name Saves? Reg? Comment Vex-uses?
142 ---------------------------------------------------------------
143 r0 int#0 ret#0 (??)
144 r1 int#1 ret#1 (??)
145 r2-7 int#2..7
146 r8 "Indirect res loc reg" ProfInc scratch
147 r9 "Temporary regs" chaining scratch
148 r10-15 "Temporary regs" avail
149 r16(IP0)
150 r17(IP1)
151 r18 "Platform reg"
152 r19-20 "Temporary regs"
153 r21 y "Callee saved" GSP
154 r22-28 y "Callee saved"
155 r29(FP) y
156 r30(LR) y
158 NZCV "Status register"
160 Is there a TLS register?
162 x21 is the GSP. x9 is a scratch chaining/spill temp. Neither
163 are available to the register allocator.
165 Q registers:
166 It's a little awkward. Basically, D registers are the same as ARM,
167 so d0-d7 and d16-d31 are caller-saved, but d8-d15 are callee-saved.
169 Q registers are the same, except that the upper 64 bits of q8-q15
170 are caller-saved.
172 The idea is that you only need to preserve D registers, not Q
173 registers.
177 s390x-linux
178 ~~~~~~~~~~~
180 Reg Callee Arg
181 Name Saves? Reg? Comment Vex-uses?
182 --------------------------------------------------------------
183 r0 n see below unavail
184 r1 n avail
185 r2 n int#1 return value avail
186 r3 n int#2 avail
187 r4 n int#3 avail
188 r5 n int#4 avail
189 r6 y int#5 avail
190 r7 y avail
191 r8 y avail
192 r9 y avail
193 r10 y see below avail
194 r11 y see below avail
195 r12 y unavail VG_(dispatch_ctr)
196 r13 y unavail gsp
197 r14(lr) n unavail lr
198 r15(sp) y unavail sp
200 f0 n return value avail
201 f1-f7 n avail
202 f8-f11 y avail
203 f12-f15 y see below avail
204 a0 n thread ptr high word
205 a1 n thread ptr low word
207 When r0 is used as a base or index register its contents is
208 ignored and the value 0 is used instead. This is the reason
209 why VEX cannot use it.
211 r10, r11 as well as f12-f15 are used as real regs during insn
212 selection when register pairs are required.
214 ppc32-aix5
215 ~~~~~~~~~~
217 Reg Callee Arg
218 Name Saves? Reg? Comment Vex-uses?
219 -------------------------------------------------------------------
220 r0 n n sometimes RAZ
221 r1 y n stack pointer
222 r2 n n TOC pointer
223 r3 n int#1 int[31:0] retreg y
224 r4 n int#2 also int retreg y
225 r5 n int#3 y
226 r6 n int#4 y
227 r7 n int#5 y
228 r8 n int#6 y
229 r9 n int#7 y
230 r10 n int#8 y
231 r11 n "env pointer?!" y
232 r12 n "exn handling" y
233 r13 ? "reserved in 64-bit env"
234 r14-28 y y
235 r29 y reserved for dispatcher
236 r30 y altivec spill temporary
237 r31 y & guest state
238 f0 n
239 f1 n fp#1 fp retreg
240 f2-13 n fp#2-13
241 f14-31 y y (14-21)
242 v0-v19 ?
243 v20-31 y y (20-27,29)
244 cr0-7
245 lr y return address
246 ctr n
247 xer n
248 fpscr