arch/mips/kernel/irq_cpu.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  * Copyright (C) 2001 Ralf Baechle
   6  * Copyright (C) 2005  MIPS Technologies, Inc.  All rights reserved.
   7  *      Author: Maciej W. Rozycki <macro@mips.com>
   8  *
   9  * This file define the irq handler for MIPS CPU interrupts.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 /*
  18  * Almost all MIPS CPUs define 8 interrupt sources.  They are typically
  19  * level triggered (i.e., cannot be cleared from CPU; must be cleared from
  20  * device).  The first two are software interrupts which we don't really
  21  * use or support.  The last one is usually the CPU timer interrupt if
  22  * counter register is present or, for CPUs with an external FPU, by
  23  * convention it's the FPU exception interrupt.
  24  *
  25  * Don't even think about using this on SMP.  You have been warned.
  26  *
  27  * This file exports one global function:
  28  *      void mips_cpu_irq_init(int irq_base);
  29  */
  30 #include <linux/init.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/kernel.h>
  33
  34 #include <asm/irq_cpu.h>
  35 #include <asm/mipsregs.h>
  36 #include <asm/mipsmtregs.h>
  37 #include <asm/system.h>
  38
  39 static int mips_cpu_irq_base;
  40
  41 static inline void unmask_mips_irq(unsigned int irq)
  42 {
  43         set_c0_status(0x100 << (irq - mips_cpu_irq_base));
  44         irq_enable_hazard();
  45 }
  46
  47 static inline void mask_mips_irq(unsigned int irq)
  48 {
  49         clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
  50         irq_disable_hazard();
  51 }
  52
  53 static void mips_cpu_irq_end(unsigned int irq)
  54 {
  55         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  56                 unmask_mips_irq(irq);
  57 }
  58
  59 static struct irq_chip mips_cpu_irq_controller = {
  60         .typename       = "MIPS",
  61         .ack            = mask_mips_irq,
  62         .mask           = mask_mips_irq,
  63         .mask_ack       = mask_mips_irq,
  64         .unmask         = unmask_mips_irq,
  65         .eoi            = unmask_mips_irq,
  66         .end            = mips_cpu_irq_end,
  67 };
  68
  69 /*
  70  * Basically the same as above but taking care of all the MT stuff
  71  */
  72
  73 #define unmask_mips_mt_irq      unmask_mips_irq
  74 #define mask_mips_mt_irq        mask_mips_irq
  75
  76 static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
  77 {
  78         unsigned int vpflags = dvpe();
  79
  80         clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
  81         evpe(vpflags);
  82         unmask_mips_mt_irq(irq);
  83
  84         return 0;
  85 }
  86
  87 /*
  88  * While we ack the interrupt interrupts are disabled and thus we don't need
  89  * to deal with concurrency issues.  Same for mips_cpu_irq_end.
  90  */
  91 static void mips_mt_cpu_irq_ack(unsigned int irq)
  92 {
  93         unsigned int vpflags = dvpe();
  94         clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
  95         evpe(vpflags);
  96         mask_mips_mt_irq(irq);
  97 }
  98
  99 #define mips_mt_cpu_irq_end mips_cpu_irq_end
 100
 101 static struct irq_chip mips_mt_cpu_irq_controller = {
 102         .typename       = "MIPS",
 103         .startup        = mips_mt_cpu_irq_startup,
 104         .ack            = mips_mt_cpu_irq_ack,
 105         .mask           = mask_mips_mt_irq,
 106         .mask_ack       = mips_mt_cpu_irq_ack,
 107         .unmask         = unmask_mips_mt_irq,
 108         .eoi            = unmask_mips_mt_irq,
 109         .end            = mips_mt_cpu_irq_end,
 110 };
 111
 112 void __init mips_cpu_irq_init(int irq_base)
 113 {
 114         int i;
 115
 116         /* Mask interrupts. */
 117         clear_c0_status(ST0_IM);
 118         clear_c0_cause(CAUSEF_IP);
 119
 120         /*
 121          * Only MT is using the software interrupts currently, so we just
 122          * leave them uninitialized for other processors.
 123          */
 124         if (cpu_has_mipsmt)
 125                 for (i = irq_base; i < irq_base + 2; i++)
 126                         set_irq_chip(i, &mips_mt_cpu_irq_controller);
 127
 128         for (i = irq_base + 2; i < irq_base + 8; i++)
 129                 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
 130                                          handle_level_irq);
 131
 132         mips_cpu_irq_base = irq_base;
 133 }