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[RFKILL]: fix net/rfkill/rfkill-input.c bug on 64-bit systems
[usb.git] / drivers / serial / ip22zilog.c
blobc3abfb39f31650c207b16fe17d6ed778f5932bc9
1 /*
2 * Driver for Zilog serial chips found on SGI workstations and
3 * servers. This driver could actually be made more generic.
4 *
5 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
6 * old drivers/sgi/char/sgiserial.c code which itself is based of the original
7 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over
8 * directly from there but much has been rewritten. Credits therefore go out
9 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
10 * for their work there.
11 *
12 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
14 */
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #include <linux/init.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35 #include <asm/sgialib.h>
36 #include <asm/sgi/ioc.h>
37 #include <asm/sgi/hpc3.h>
38 #include <asm/sgi/ip22.h>
39
40 #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
41 #define SUPPORT_SYSRQ
42 #endif
43
44 #include <linux/serial_core.h>
45
46 #include "ip22zilog.h"
47
48 void ip22_do_break(void);
49
50 /*
51 * On IP22 we need to delay after register accesses but we do not need to
52 * flush writes.
53 */
54 #define ZSDELAY() udelay(5)
55 #define ZSDELAY_LONG() udelay(20)
56 #define ZS_WSYNC(channel) do { } while (0)
57
58 #define NUM_IP22ZILOG 1
59 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
60
61 #define ZS_CLOCK 3672000 /* Zilog input clock rate. */
62 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
63
64 /*
65 * We wrap our port structure around the generic uart_port.
66 */
67 struct uart_ip22zilog_port {
68 struct uart_port port;
69
70 /* IRQ servicing chain. */
71 struct uart_ip22zilog_port *next;
72
73 /* Current values of Zilog write registers. */
74 unsigned char curregs[NUM_ZSREGS];
75
76 unsigned int flags;
77 #define IP22ZILOG_FLAG_IS_CONS 0x00000004
78 #define IP22ZILOG_FLAG_IS_KGDB 0x00000008
79 #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010
80 #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020
81 #define IP22ZILOG_FLAG_REGS_HELD 0x00000040
82 #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080
83 #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100
84
85 unsigned int cflag;
86
87 /* L1-A keyboard break state. */
88 int kbd_id;
89 int l1_down;
90
91 unsigned char parity_mask;
92 unsigned char prev_status;
93 };
94
95 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
96 #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
97 #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
98 (UART_ZILOG(PORT)->curregs[REGNUM])
99 #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
100 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
101 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
102 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
103 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
104 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
105 #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
106 #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
107 #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
108
109 /* Reading and writing Zilog8530 registers. The delays are to make this
110 * driver work on the IP22 which needs a settling delay after each chip
111 * register access, other machines handle this in hardware via auxiliary
112 * flip-flops which implement the settle time we do in software.
113 *
114 * The port lock must be held and local IRQs must be disabled
115 * when {read,write}_zsreg is invoked.
116 */
117 static unsigned char read_zsreg(struct zilog_channel *channel,
118 unsigned char reg)
119 {
120 unsigned char retval;
121
122 writeb(reg, &channel->control);
123 ZSDELAY();
124 retval = readb(&channel->control);
125 ZSDELAY();
126
127 return retval;
128 }
129
130 static void write_zsreg(struct zilog_channel *channel,
131 unsigned char reg, unsigned char value)
132 {
133 writeb(reg, &channel->control);
134 ZSDELAY();
135 writeb(value, &channel->control);
136 ZSDELAY();
137 }
138
139 static void ip22zilog_clear_fifo(struct zilog_channel *channel)
140 {
141 int i;
142
143 for (i = 0; i < 32; i++) {
144 unsigned char regval;
145
146 regval = readb(&channel->control);
147 ZSDELAY();
148 if (regval & Rx_CH_AV)
149 break;
150
151 regval = read_zsreg(channel, R1);
152 readb(&channel->data);
153 ZSDELAY();
154
155 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
156 writeb(ERR_RES, &channel->control);
157 ZSDELAY();
158 ZS_WSYNC(channel);
159 }
160 }
161 }
162
163 /* This function must only be called when the TX is not busy. The UART
164 * port lock must be held and local interrupts disabled.
165 */
166 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
167 {
168 int i;
169
170 /* Let pending transmits finish. */
171 for (i = 0; i < 1000; i++) {
172 unsigned char stat = read_zsreg(channel, R1);
173 if (stat & ALL_SNT)
174 break;
175 udelay(100);
176 }
177
178 writeb(ERR_RES, &channel->control);
179 ZSDELAY();
180 ZS_WSYNC(channel);
181
182 ip22zilog_clear_fifo(channel);
183
184 /* Disable all interrupts. */
185 write_zsreg(channel, R1,
186 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
187
188 /* Set parity, sync config, stop bits, and clock divisor. */
189 write_zsreg(channel, R4, regs[R4]);
190
191 /* Set misc. TX/RX control bits. */
192 write_zsreg(channel, R10, regs[R10]);
193
194 /* Set TX/RX controls sans the enable bits. */
195 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
196 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
197
198 /* Synchronous mode config. */
199 write_zsreg(channel, R6, regs[R6]);
200 write_zsreg(channel, R7, regs[R7]);
201
202 /* Don't mess with the interrupt vector (R2, unused by us) and
203 * master interrupt control (R9). We make sure this is setup
204 * properly at probe time then never touch it again.
205 */
206
207 /* Disable baud generator. */
208 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
209
210 /* Clock mode control. */
211 write_zsreg(channel, R11, regs[R11]);
212
213 /* Lower and upper byte of baud rate generator divisor. */
214 write_zsreg(channel, R12, regs[R12]);
215 write_zsreg(channel, R13, regs[R13]);
216
217 /* Now rewrite R14, with BRENAB (if set). */
218 write_zsreg(channel, R14, regs[R14]);
219
220 /* External status interrupt control. */
221 write_zsreg(channel, R15, regs[R15]);
222
223 /* Reset external status interrupts. */
224 write_zsreg(channel, R0, RES_EXT_INT);
225 write_zsreg(channel, R0, RES_EXT_INT);
226
227 /* Rewrite R3/R5, this time without enables masked. */
228 write_zsreg(channel, R3, regs[R3]);
229 write_zsreg(channel, R5, regs[R5]);
230
231 /* Rewrite R1, this time without IRQ enabled masked. */
232 write_zsreg(channel, R1, regs[R1]);
233 }
234
235 /* Reprogram the Zilog channel HW registers with the copies found in the
236 * software state struct. If the transmitter is busy, we defer this update
237 * until the next TX complete interrupt. Else, we do it right now.
238 *
239 * The UART port lock must be held and local interrupts disabled.
240 */
241 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
242 struct zilog_channel *channel)
243 {
244 if (!ZS_REGS_HELD(up)) {
245 if (ZS_TX_ACTIVE(up)) {
246 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
247 } else {
248 __load_zsregs(channel, up->curregs);
249 }
250 }
251 }
252
253 static void ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
254 struct zilog_channel *channel)
255 {
256 struct tty_struct *tty = up->port.info->tty; /* XXX info==NULL? */
257
258 while (1) {
259 unsigned char ch, r1, flag;
260
261 r1 = read_zsreg(channel, R1);
262 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
263 writeb(ERR_RES, &channel->control);
264 ZSDELAY();
265 ZS_WSYNC(channel);
266 }
267
268 ch = readb(&channel->control);
269 ZSDELAY();
270
271 /* This funny hack depends upon BRK_ABRT not interfering
272 * with the other bits we care about in R1.
273 */
274 if (ch & BRK_ABRT)
275 r1 |= BRK_ABRT;
276
277 ch = readb(&channel->data);
278 ZSDELAY();
279
280 ch &= up->parity_mask;
281
282 if (ZS_IS_CONS(up) && (r1 & BRK_ABRT)) {
283 /* Wait for BREAK to deassert to avoid potentially
284 * confusing the PROM.
285 */
286 while (1) {
287 ch = readb(&channel->control);
288 ZSDELAY();
289 if (!(ch & BRK_ABRT))
290 break;
291 }
292 ip22_do_break();
293 return;
294 }
295
296 /* A real serial line, record the character and status. */
297 flag = TTY_NORMAL;
298 up->port.icount.rx++;
299 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
300 if (r1 & BRK_ABRT) {
301 r1 &= ~(PAR_ERR | CRC_ERR);
302 up->port.icount.brk++;
303 if (uart_handle_break(&up->port))
304 goto next_char;
305 }
306 else if (r1 & PAR_ERR)
307 up->port.icount.parity++;
308 else if (r1 & CRC_ERR)
309 up->port.icount.frame++;
310 if (r1 & Rx_OVR)
311 up->port.icount.overrun++;
312 r1 &= up->port.read_status_mask;
313 if (r1 & BRK_ABRT)
314 flag = TTY_BREAK;
315 else if (r1 & PAR_ERR)
316 flag = TTY_PARITY;
317 else if (r1 & CRC_ERR)
318 flag = TTY_FRAME;
319 }
320 if (uart_handle_sysrq_char(&up->port, ch))
321 goto next_char;
322
323 if (up->port.ignore_status_mask == 0xff ||
324 (r1 & up->port.ignore_status_mask) == 0)
325 tty_insert_flip_char(tty, ch, flag);
326
327 if (r1 & Rx_OVR)
328 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
329 next_char:
330 ch = readb(&channel->control);
331 ZSDELAY();
332 if (!(ch & Rx_CH_AV))
333 break;
334 }
335
336 tty_flip_buffer_push(tty);
337 }
338
339 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
340 struct zilog_channel *channel)
341 {
342 unsigned char status;
343
344 status = readb(&channel->control);
345 ZSDELAY();
346
347 writeb(RES_EXT_INT, &channel->control);
348 ZSDELAY();
349 ZS_WSYNC(channel);
350
351 if (ZS_WANTS_MODEM_STATUS(up)) {
352 if (status & SYNC)
353 up->port.icount.dsr++;
354
355 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
356 * But it does not tell us which bit has changed, we have to keep
357 * track of this ourselves.
358 */
359 if ((status & DCD) ^ up->prev_status)
360 uart_handle_dcd_change(&up->port,
361 (status & DCD));
362 if ((status & CTS) ^ up->prev_status)
363 uart_handle_cts_change(&up->port,
364 (status & CTS));
365
366 wake_up_interruptible(&up->port.info->delta_msr_wait);
367 }
368
369 up->prev_status = status;
370 }
371
372 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
373 struct zilog_channel *channel)
374 {
375 struct circ_buf *xmit;
376
377 if (ZS_IS_CONS(up)) {
378 unsigned char status = readb(&channel->control);
379 ZSDELAY();
380
381 /* TX still busy? Just wait for the next TX done interrupt.
382 *
383 * It can occur because of how we do serial console writes. It would
384 * be nice to transmit console writes just like we normally would for
385 * a TTY line. (ie. buffered and TX interrupt driven). That is not
386 * easy because console writes cannot sleep. One solution might be
387 * to poll on enough port->xmit space becomming free. -DaveM
388 */
389 if (!(status & Tx_BUF_EMP))
390 return;
391 }
392
393 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
394
395 if (ZS_REGS_HELD(up)) {
396 __load_zsregs(channel, up->curregs);
397 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
398 }
399
400 if (ZS_TX_STOPPED(up)) {
401 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
402 goto ack_tx_int;
403 }
404
405 if (up->port.x_char) {
406 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
407 writeb(up->port.x_char, &channel->data);
408 ZSDELAY();
409 ZS_WSYNC(channel);
410
411 up->port.icount.tx++;
412 up->port.x_char = 0;
413 return;
414 }
415
416 if (up->port.info == NULL)
417 goto ack_tx_int;
418 xmit = &up->port.info->xmit;
419 if (uart_circ_empty(xmit))
420 goto ack_tx_int;
421 if (uart_tx_stopped(&up->port))
422 goto ack_tx_int;
423
424 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
425 writeb(xmit->buf[xmit->tail], &channel->data);
426 ZSDELAY();
427 ZS_WSYNC(channel);
428
429 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
430 up->port.icount.tx++;
431
432 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
433 uart_write_wakeup(&up->port);
434
435 return;
436
437 ack_tx_int:
438 writeb(RES_Tx_P, &channel->control);
439 ZSDELAY();
440 ZS_WSYNC(channel);
441 }
442
443 static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
444 {
445 struct uart_ip22zilog_port *up = dev_id;
446
447 while (up) {
448 struct zilog_channel *channel
449 = ZILOG_CHANNEL_FROM_PORT(&up->port);
450 unsigned char r3;
451
452 spin_lock(&up->port.lock);
453 r3 = read_zsreg(channel, R3);
454
455 /* Channel A */
456 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
457 writeb(RES_H_IUS, &channel->control);
458 ZSDELAY();
459 ZS_WSYNC(channel);
460
461 if (r3 & CHARxIP)
462 ip22zilog_receive_chars(up, channel);
463 if (r3 & CHAEXT)
464 ip22zilog_status_handle(up, channel);
465 if (r3 & CHATxIP)
466 ip22zilog_transmit_chars(up, channel);
467 }
468 spin_unlock(&up->port.lock);
469
470 /* Channel B */
471 up = up->next;
472 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
473
474 spin_lock(&up->port.lock);
475 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
476 writeb(RES_H_IUS, &channel->control);
477 ZSDELAY();
478 ZS_WSYNC(channel);
479
480 if (r3 & CHBRxIP)
481 ip22zilog_receive_chars(up, channel);
482 if (r3 & CHBEXT)
483 ip22zilog_status_handle(up, channel);
484 if (r3 & CHBTxIP)
485 ip22zilog_transmit_chars(up, channel);
486 }
487 spin_unlock(&up->port.lock);
488
489 up = up->next;
490 }
491
492 return IRQ_HANDLED;
493 }
494
495 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
496 * port lock, it is acquired here.
497 */
498 static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
499 {
500 struct zilog_channel *channel;
501 unsigned char status;
502
503 channel = ZILOG_CHANNEL_FROM_PORT(port);
504 status = readb(&channel->control);
505 ZSDELAY();
506
507 return status;
508 }
509
510 /* The port lock is not held. */
511 static unsigned int ip22zilog_tx_empty(struct uart_port *port)
512 {
513 unsigned long flags;
514 unsigned char status;
515 unsigned int ret;
516
517 spin_lock_irqsave(&port->lock, flags);
518
519 status = ip22zilog_read_channel_status(port);
520
521 spin_unlock_irqrestore(&port->lock, flags);
522
523 if (status & Tx_BUF_EMP)
524 ret = TIOCSER_TEMT;
525 else
526 ret = 0;
527
528 return ret;
529 }
530
531 /* The port lock is held and interrupts are disabled. */
532 static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
533 {
534 unsigned char status;
535 unsigned int ret;
536
537 status = ip22zilog_read_channel_status(port);
538
539 ret = 0;
540 if (status & DCD)
541 ret |= TIOCM_CAR;
542 if (status & SYNC)
543 ret |= TIOCM_DSR;
544 if (status & CTS)
545 ret |= TIOCM_CTS;
546
547 return ret;
548 }
549
550 /* The port lock is held and interrupts are disabled. */
551 static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
552 {
553 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
554 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
555 unsigned char set_bits, clear_bits;
556
557 set_bits = clear_bits = 0;
558
559 if (mctrl & TIOCM_RTS)
560 set_bits |= RTS;
561 else
562 clear_bits |= RTS;
563 if (mctrl & TIOCM_DTR)
564 set_bits |= DTR;
565 else
566 clear_bits |= DTR;
567
568 /* NOTE: Not subject to 'transmitter active' rule. */
569 up->curregs[R5] |= set_bits;
570 up->curregs[R5] &= ~clear_bits;
571 write_zsreg(channel, R5, up->curregs[R5]);
572 }
573
574 /* The port lock is held and interrupts are disabled. */
575 static void ip22zilog_stop_tx(struct uart_port *port)
576 {
577 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
578
579 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
580 }
581
582 /* The port lock is held and interrupts are disabled. */
583 static void ip22zilog_start_tx(struct uart_port *port)
584 {
585 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
586 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
587 unsigned char status;
588
589 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
590 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
591
592 status = readb(&channel->control);
593 ZSDELAY();
594
595 /* TX busy? Just wait for the TX done interrupt. */
596 if (!(status & Tx_BUF_EMP))
597 return;
598
599 /* Send the first character to jump-start the TX done
600 * IRQ sending engine.
601 */
602 if (port->x_char) {
603 writeb(port->x_char, &channel->data);
604 ZSDELAY();
605 ZS_WSYNC(channel);
606
607 port->icount.tx++;
608 port->x_char = 0;
609 } else {
610 struct circ_buf *xmit = &port->info->xmit;
611
612 writeb(xmit->buf[xmit->tail], &channel->data);
613 ZSDELAY();
614 ZS_WSYNC(channel);
615
616 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
617 port->icount.tx++;
618
619 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
620 uart_write_wakeup(&up->port);
621 }
622 }
623
624 /* The port lock is held and interrupts are disabled. */
625 static void ip22zilog_stop_rx(struct uart_port *port)
626 {
627 struct uart_ip22zilog_port *up = UART_ZILOG(port);
628 struct zilog_channel *channel;
629
630 if (ZS_IS_CONS(up))
631 return;
632
633 channel = ZILOG_CHANNEL_FROM_PORT(port);
634
635 /* Disable all RX interrupts. */
636 up->curregs[R1] &= ~RxINT_MASK;
637 ip22zilog_maybe_update_regs(up, channel);
638 }
639
640 /* The port lock is held. */
641 static void ip22zilog_enable_ms(struct uart_port *port)
642 {
643 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
644 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
645 unsigned char new_reg;
646
647 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
648 if (new_reg != up->curregs[R15]) {
649 up->curregs[R15] = new_reg;
650
651 /* NOTE: Not subject to 'transmitter active' rule. */
652 write_zsreg(channel, R15, up->curregs[R15]);
653 }
654 }
655
656 /* The port lock is not held. */
657 static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
658 {
659 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
660 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
661 unsigned char set_bits, clear_bits, new_reg;
662 unsigned long flags;
663
664 set_bits = clear_bits = 0;
665
666 if (break_state)
667 set_bits |= SND_BRK;
668 else
669 clear_bits |= SND_BRK;
670
671 spin_lock_irqsave(&port->lock, flags);
672
673 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
674 if (new_reg != up->curregs[R5]) {
675 up->curregs[R5] = new_reg;
676
677 /* NOTE: Not subject to 'transmitter active' rule. */
678 write_zsreg(channel, R5, up->curregs[R5]);
679 }
680
681 spin_unlock_irqrestore(&port->lock, flags);
682 }
683
684 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
685 {
686 struct zilog_channel *channel;
687
688 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
689 up->prev_status = readb(&channel->control);
690
691 /* Enable receiver and transmitter. */
692 up->curregs[R3] |= RxENAB;
693 up->curregs[R5] |= TxENAB;
694
695 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
696 ip22zilog_maybe_update_regs(up, channel);
697 }
698
699 static int ip22zilog_startup(struct uart_port *port)
700 {
701 struct uart_ip22zilog_port *up = UART_ZILOG(port);
702 unsigned long flags;
703
704 if (ZS_IS_CONS(up))
705 return 0;
706
707 spin_lock_irqsave(&port->lock, flags);
708 __ip22zilog_startup(up);
709 spin_unlock_irqrestore(&port->lock, flags);
710 return 0;
711 }
712
713 /*
714 * The test for ZS_IS_CONS is explained by the following e-mail:
715 *****
716 * From: Russell King <rmk@arm.linux.org.uk>
717 * Date: Sun, 8 Dec 2002 10:18:38 +0000
718 *
719 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
720 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
721 * > and I noticed that something is not right with reference
722 * > counting in this case. It seems that when the console
723 * > is open by kernel initially, this is not accounted
724 * > as an open, and uart_startup is not called.
725 *
726 * That is correct. We are unable to call uart_startup when the serial
727 * console is initialised because it may need to allocate memory (as
728 * request_irq does) and the memory allocators may not have been
729 * initialised.
730 *
731 * 1. initialise the port into a state where it can send characters in the
732 * console write method.
733 *
734 * 2. don't do the actual hardware shutdown in your shutdown() method (but
735 * do the normal software shutdown - ie, free irqs etc)
736 *****
737 */
738 static void ip22zilog_shutdown(struct uart_port *port)
739 {
740 struct uart_ip22zilog_port *up = UART_ZILOG(port);
741 struct zilog_channel *channel;
742 unsigned long flags;
743
744 if (ZS_IS_CONS(up))
745 return;
746
747 spin_lock_irqsave(&port->lock, flags);
748
749 channel = ZILOG_CHANNEL_FROM_PORT(port);
750
751 /* Disable receiver and transmitter. */
752 up->curregs[R3] &= ~RxENAB;
753 up->curregs[R5] &= ~TxENAB;
754
755 /* Disable all interrupts and BRK assertion. */
756 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
757 up->curregs[R5] &= ~SND_BRK;
758 ip22zilog_maybe_update_regs(up, channel);
759
760 spin_unlock_irqrestore(&port->lock, flags);
761 }
762
763 /* Shared by TTY driver and serial console setup. The port lock is held
764 * and local interrupts are disabled.
765 */
766 static void
767 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
768 unsigned int iflag, int brg)
769 {
770
771 up->curregs[R10] = NRZ;
772 up->curregs[R11] = TCBR | RCBR;
773
774 /* Program BAUD and clock source. */
775 up->curregs[R4] &= ~XCLK_MASK;
776 up->curregs[R4] |= X16CLK;
777 up->curregs[R12] = brg & 0xff;
778 up->curregs[R13] = (brg >> 8) & 0xff;
779 up->curregs[R14] = BRENAB;
780
781 /* Character size, stop bits, and parity. */
782 up->curregs[3] &= ~RxN_MASK;
783 up->curregs[5] &= ~TxN_MASK;
784 switch (cflag & CSIZE) {
785 case CS5:
786 up->curregs[3] |= Rx5;
787 up->curregs[5] |= Tx5;
788 up->parity_mask = 0x1f;
789 break;
790 case CS6:
791 up->curregs[3] |= Rx6;
792 up->curregs[5] |= Tx6;
793 up->parity_mask = 0x3f;
794 break;
795 case CS7:
796 up->curregs[3] |= Rx7;
797 up->curregs[5] |= Tx7;
798 up->parity_mask = 0x7f;
799 break;
800 case CS8:
801 default:
802 up->curregs[3] |= Rx8;
803 up->curregs[5] |= Tx8;
804 up->parity_mask = 0xff;
805 break;
806 };
807 up->curregs[4] &= ~0x0c;
808 if (cflag & CSTOPB)
809 up->curregs[4] |= SB2;
810 else
811 up->curregs[4] |= SB1;
812 if (cflag & PARENB)
813 up->curregs[4] |= PAR_ENAB;
814 else
815 up->curregs[4] &= ~PAR_ENAB;
816 if (!(cflag & PARODD))
817 up->curregs[4] |= PAR_EVEN;
818 else
819 up->curregs[4] &= ~PAR_EVEN;
820
821 up->port.read_status_mask = Rx_OVR;
822 if (iflag & INPCK)
823 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
824 if (iflag & (BRKINT | PARMRK))
825 up->port.read_status_mask |= BRK_ABRT;
826
827 up->port.ignore_status_mask = 0;
828 if (iflag & IGNPAR)
829 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
830 if (iflag & IGNBRK) {
831 up->port.ignore_status_mask |= BRK_ABRT;
832 if (iflag & IGNPAR)
833 up->port.ignore_status_mask |= Rx_OVR;
834 }
835
836 if ((cflag & CREAD) == 0)
837 up->port.ignore_status_mask = 0xff;
838 }
839
840 /* The port lock is not held. */
841 static void
842 ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,
843 struct ktermios *old)
844 {
845 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
846 unsigned long flags;
847 int baud, brg;
848
849 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
850
851 spin_lock_irqsave(&up->port.lock, flags);
852
853 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
854
855 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
856
857 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
858 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
859 else
860 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
861
862 up->cflag = termios->c_cflag;
863
864 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
865
866 spin_unlock_irqrestore(&up->port.lock, flags);
867 }
868
869 static const char *ip22zilog_type(struct uart_port *port)
870 {
871 return "IP22-Zilog";
872 }
873
874 /* We do not request/release mappings of the registers here, this
875 * happens at early serial probe time.
876 */
877 static void ip22zilog_release_port(struct uart_port *port)
878 {
879 }
880
881 static int ip22zilog_request_port(struct uart_port *port)
882 {
883 return 0;
884 }
885
886 /* These do not need to do anything interesting either. */
887 static void ip22zilog_config_port(struct uart_port *port, int flags)
888 {
889 }
890
891 /* We do not support letting the user mess with the divisor, IRQ, etc. */
892 static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
893 {
894 return -EINVAL;
895 }
896
897 static struct uart_ops ip22zilog_pops = {
898 .tx_empty = ip22zilog_tx_empty,
899 .set_mctrl = ip22zilog_set_mctrl,
900 .get_mctrl = ip22zilog_get_mctrl,
901 .stop_tx = ip22zilog_stop_tx,
902 .start_tx = ip22zilog_start_tx,
903 .stop_rx = ip22zilog_stop_rx,
904 .enable_ms = ip22zilog_enable_ms,
905 .break_ctl = ip22zilog_break_ctl,
906 .startup = ip22zilog_startup,
907 .shutdown = ip22zilog_shutdown,
908 .set_termios = ip22zilog_set_termios,
909 .type = ip22zilog_type,
910 .release_port = ip22zilog_release_port,
911 .request_port = ip22zilog_request_port,
912 .config_port = ip22zilog_config_port,
913 .verify_port = ip22zilog_verify_port,
914 };
915
916 static struct uart_ip22zilog_port *ip22zilog_port_table;
917 static struct zilog_layout **ip22zilog_chip_regs;
918
919 static struct uart_ip22zilog_port *ip22zilog_irq_chain;
920 static int zilog_irq = -1;
921
922 static void * __init alloc_one_table(unsigned long size)
923 {
924 return kzalloc(size, GFP_KERNEL);
925 }
926
927 static void __init ip22zilog_alloc_tables(void)
928 {
929 ip22zilog_port_table = (struct uart_ip22zilog_port *)
930 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));
931 ip22zilog_chip_regs = (struct zilog_layout **)
932 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));
933
934 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {
935 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");
936 }
937 }
938
939 /* Get the address of the registers for IP22-Zilog instance CHIP. */
940 static struct zilog_layout * __init get_zs(int chip)
941 {
942 unsigned long base;
943
944 if (chip < 0 || chip >= NUM_IP22ZILOG) {
945 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);
946 }
947
948 /* Not probe-able, hard code it. */
949 base = (unsigned long) &sgioc->uart;
950
951 zilog_irq = SGI_SERIAL_IRQ;
952 request_mem_region(base, 8, "IP22-Zilog");
953
954 return (struct zilog_layout *) base;
955 }
956
957 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
958
959 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
960 static void ip22zilog_put_char(struct uart_port *port, int ch)
961 {
962 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
963 int loops = ZS_PUT_CHAR_MAX_DELAY;
964
965 /* This is a timed polling loop so do not switch the explicit
966 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
967 */
968 do {
969 unsigned char val = readb(&channel->control);
970 if (val & Tx_BUF_EMP) {
971 ZSDELAY();
972 break;
973 }
974 udelay(5);
975 } while (--loops);
976
977 writeb(ch, &channel->data);
978 ZSDELAY();
979 ZS_WSYNC(channel);
980 }
981
982 static void
983 ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
984 {
985 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
986 unsigned long flags;
987
988 spin_lock_irqsave(&up->port.lock, flags);
989 uart_console_write(&up->port, s, count, ip22zilog_put_char);
990 udelay(2);
991 spin_unlock_irqrestore(&up->port.lock, flags);
992 }
993
994 void
995 ip22serial_console_termios(struct console *con, char *options)
996 {
997 int baud = 9600, bits = 8, cflag;
998 int parity = 'n';
999 int flow = 'n';
1000
1001 if (options)
1002 uart_parse_options(options, &baud, &parity, &bits, &flow);
1003
1004 cflag = CREAD | HUPCL | CLOCAL;
1005
1006 switch (baud) {
1007 case 150: cflag |= B150; break;
1008 case 300: cflag |= B300; break;
1009 case 600: cflag |= B600; break;
1010 case 1200: cflag |= B1200; break;
1011 case 2400: cflag |= B2400; break;
1012 case 4800: cflag |= B4800; break;
1013 case 9600: cflag |= B9600; break;
1014 case 19200: cflag |= B19200; break;
1015 case 38400: cflag |= B38400; break;
1016 default: baud = 9600; cflag |= B9600; break;
1017 }
1018
1019 con->cflag = cflag | CS8; /* 8N1 */
1020 }
1021
1022 static int __init ip22zilog_console_setup(struct console *con, char *options)
1023 {
1024 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1025 unsigned long flags;
1026 int baud, brg;
1027
1028 printk("Console: ttyS%d (IP22-Zilog)\n", con->index);
1029
1030 /* Get firmware console settings. */
1031 ip22serial_console_termios(con, options);
1032
1033 /* Firmware console speed is limited to 150-->38400 baud so
1034 * this hackish cflag thing is OK.
1035 */
1036 switch (con->cflag & CBAUD) {
1037 case B150: baud = 150; break;
1038 case B300: baud = 300; break;
1039 case B600: baud = 600; break;
1040 case B1200: baud = 1200; break;
1041 case B2400: baud = 2400; break;
1042 case B4800: baud = 4800; break;
1043 default: case B9600: baud = 9600; break;
1044 case B19200: baud = 19200; break;
1045 case B38400: baud = 38400; break;
1046 };
1047
1048 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1049
1050 spin_lock_irqsave(&up->port.lock, flags);
1051
1052 up->curregs[R15] = BRKIE;
1053 ip22zilog_convert_to_zs(up, con->cflag, 0, brg);
1054
1055 __ip22zilog_startup(up);
1056
1057 spin_unlock_irqrestore(&up->port.lock, flags);
1058
1059 return 0;
1060 }
1061
1062 static struct uart_driver ip22zilog_reg;
1063
1064 static struct console ip22zilog_console = {
1065 .name = "ttyS",
1066 .write = ip22zilog_console_write,
1067 .device = uart_console_device,
1068 .setup = ip22zilog_console_setup,
1069 .flags = CON_PRINTBUFFER,
1070 .index = -1,
1071 .data = &ip22zilog_reg,
1072 };
1073 #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */
1074
1075 static struct uart_driver ip22zilog_reg = {
1076 .owner = THIS_MODULE,
1077 .driver_name = "serial",
1078 .dev_name = "ttyS",
1079 .major = TTY_MAJOR,
1080 .minor = 64,
1081 .nr = NUM_CHANNELS,
1082 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1083 .cons = &ip22zilog_console,
1084 #endif
1085 };
1086
1087 static void __init ip22zilog_prepare(void)
1088 {
1089 struct uart_ip22zilog_port *up;
1090 struct zilog_layout *rp;
1091 int channel, chip;
1092
1093 /*
1094 * Temporary fix.
1095 */
1096 for (channel = 0; channel < NUM_CHANNELS; channel++)
1097 spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1098
1099 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];
1100 up = &ip22zilog_port_table[0];
1101 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1102 up[channel].next = &up[channel - 1];
1103 up[channel].next = NULL;
1104
1105 for (chip = 0; chip < NUM_IP22ZILOG; chip++) {
1106 if (!ip22zilog_chip_regs[chip]) {
1107 ip22zilog_chip_regs[chip] = rp = get_zs(chip);
1108
1109 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1110 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1111
1112 /* In theory mapbase is the physical address ... */
1113 up[(chip * 2) + 0].port.mapbase =
1114 (unsigned long) ioremap((unsigned long) &rp->channelB, 8);
1115 up[(chip * 2) + 1].port.mapbase =
1116 (unsigned long) ioremap((unsigned long) &rp->channelA, 8);
1117 }
1118
1119 /* Channel A */
1120 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1121 up[(chip * 2) + 0].port.irq = zilog_irq;
1122 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1123 up[(chip * 2) + 0].port.fifosize = 1;
1124 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1125 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1126 up[(chip * 2) + 0].port.flags = 0;
1127 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1128 up[(chip * 2) + 0].flags = 0;
1129
1130 /* Channel B */
1131 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1132 up[(chip * 2) + 1].port.irq = zilog_irq;
1133 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1134 up[(chip * 2) + 1].port.fifosize = 1;
1135 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1136 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1137 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1138 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1139 }
1140 }
1141
1142 static void __init ip22zilog_init_hw(void)
1143 {
1144 int i;
1145
1146 for (i = 0; i < NUM_CHANNELS; i++) {
1147 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1148 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1149 unsigned long flags;
1150 int baud, brg;
1151
1152 spin_lock_irqsave(&up->port.lock, flags);
1153
1154 if (ZS_IS_CHANNEL_A(up)) {
1155 write_zsreg(channel, R9, FHWRES);
1156 ZSDELAY_LONG();
1157 (void) read_zsreg(channel, R0);
1158 }
1159
1160 /* Normal serial TTY. */
1161 up->parity_mask = 0xff;
1162 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1163 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1164 up->curregs[R3] = RxENAB | Rx8;
1165 up->curregs[R5] = TxENAB | Tx8;
1166 up->curregs[R9] = NV | MIE;
1167 up->curregs[R10] = NRZ;
1168 up->curregs[R11] = TCBR | RCBR;
1169 baud = 9600;
1170 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1171 up->curregs[R12] = (brg & 0xff);
1172 up->curregs[R13] = (brg >> 8) & 0xff;
1173 up->curregs[R14] = BRENAB;
1174 __load_zsregs(channel, up->curregs);
1175 /* set master interrupt enable */
1176 write_zsreg(channel, R9, up->curregs[R9]);
1177
1178 spin_unlock_irqrestore(&up->port.lock, flags);
1179 }
1180 }
1181
1182 static int __init ip22zilog_ports_init(void)
1183 {
1184 int ret;
1185
1186 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1187
1188 ip22zilog_prepare();
1189
1190 if (request_irq(zilog_irq, ip22zilog_interrupt, 0,
1191 "IP22-Zilog", ip22zilog_irq_chain)) {
1192 panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1193 }
1194
1195 ip22zilog_init_hw();
1196
1197 ret = uart_register_driver(&ip22zilog_reg);
1198 if (ret == 0) {
1199 int i;
1200
1201 for (i = 0; i < NUM_CHANNELS; i++) {
1202 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1203
1204 uart_add_one_port(&ip22zilog_reg, &up->port);
1205 }
1206 }
1207
1208 return ret;
1209 }
1210
1211 static int __init ip22zilog_init(void)
1212 {
1213 /* IP22 Zilog setup is hard coded, no probing to do. */
1214 ip22zilog_alloc_tables();
1215 ip22zilog_ports_init();
1216
1217 return 0;
1218 }
1219
1220 static void __exit ip22zilog_exit(void)
1221 {
1222 int i;
1223 struct uart_ip22zilog_port *up;
1224
1225 for (i = 0; i < NUM_CHANNELS; i++) {
1226 up = &ip22zilog_port_table[i];
1227
1228 uart_remove_one_port(&ip22zilog_reg, &up->port);
1229 }
1230
1231 /* Free IO mem */
1232 up = &ip22zilog_port_table[0];
1233 for (i = 0; i < NUM_IP22ZILOG; i++) {
1234 if (up[(i * 2) + 0].port.mapbase) {
1235 iounmap((void*)up[(i * 2) + 0].port.mapbase);
1236 up[(i * 2) + 0].port.mapbase = 0;
1237 }
1238 if (up[(i * 2) + 1].port.mapbase) {
1239 iounmap((void*)up[(i * 2) + 1].port.mapbase);
1240 up[(i * 2) + 1].port.mapbase = 0;
1241 }
1242 }
1243
1244 uart_unregister_driver(&ip22zilog_reg);
1245 }
1246
1247 module_init(ip22zilog_init);
1248 module_exit(ip22zilog_exit);
1249
1250 /* David wrote it but I'm to blame for the bugs ... */
1251 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1252 MODULE_DESCRIPTION("SGI Zilog serial port driver");
1253 MODULE_LICENSE("GPL");
USB Experimental Work