2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/mii.h>
45 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46 #define SKY2_VLAN_TAG_USED 1
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.11.1"
53 #define PFX DRV_NAME " "
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81 static const u32 default_msg
=
82 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
83 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
86 static int debug
= -1; /* defaults above */
87 module_param(debug
, int, 0);
88 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
90 static int copybreak __read_mostly
= 128;
91 module_param(copybreak
, int, 0);
92 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
94 static int disable_msi
= 0;
95 module_param(disable_msi
, int, 0);
96 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
98 static int idle_timeout
= 0;
99 module_param(idle_timeout
, int, 0);
100 MODULE_PARM_DESC(idle_timeout
, "Watchdog timer for lost interrupts (ms)");
102 static const struct pci_device_id sky2_id_table
[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
132 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
134 /* Avoid conditionals by using array */
135 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
136 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
137 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
139 /* This driver supports yukon2 chipset only */
140 static const char *yukon2_name
[] = {
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
148 /* Access to external PHY */
149 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
153 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
154 gma_write16(hw
, port
, GM_SMI_CTRL
,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
157 for (i
= 0; i
< PHY_RETRIES
; i
++) {
158 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
163 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
167 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
171 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
172 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
174 for (i
= 0; i
< PHY_RETRIES
; i
++) {
175 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
176 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
186 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
190 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
191 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
196 static void sky2_power_on(struct sky2_hw
*hw
)
198 /* switch power to VCC (WA for VAUX problem) */
199 sky2_write8(hw
, B0_POWER_CTRL
,
200 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
202 /* disable Core Clock Division, */
203 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
205 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
206 /* enable bits are inverted */
207 sky2_write8(hw
, B2_Y2_CLK_GATE
,
208 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
209 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
210 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
212 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
214 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
217 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
218 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
219 reg1
&= P_ASPM_CONTROL_MSK
;
220 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
221 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
225 static void sky2_power_aux(struct sky2_hw
*hw
)
227 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
228 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
230 /* enable bits are inverted */
231 sky2_write8(hw
, B2_Y2_CLK_GATE
,
232 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
233 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
234 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
236 /* switch power to VAUX */
237 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
238 sky2_write8(hw
, B0_POWER_CTRL
,
239 (PC_VAUX_ENA
| PC_VCC_ENA
|
240 PC_VAUX_ON
| PC_VCC_OFF
));
243 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
247 /* disable all GMAC IRQ's */
248 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
249 /* disable PHY IRQs */
250 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
252 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
253 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
254 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
255 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
257 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
258 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
259 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
262 /* flow control to advertise bits */
263 static const u16 copper_fc_adv
[] = {
265 [FC_TX
] = PHY_M_AN_ASP
,
266 [FC_RX
] = PHY_M_AN_PC
,
267 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
270 /* flow control to advertise bits when using 1000BaseX */
271 static const u16 fiber_fc_adv
[] = {
272 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
273 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
274 [FC_RX
] = PHY_M_P_SYM_MD_X
,
275 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
278 /* flow control to GMA disable bits */
279 static const u16 gm_fc_disable
[] = {
280 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
281 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
282 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
287 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
289 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
290 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
292 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
293 !(hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
294 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
296 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
298 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
300 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
301 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
303 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
305 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
308 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
309 if (sky2_is_copper(hw
)) {
310 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
311 /* enable automatic crossover */
312 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
314 /* disable energy detect */
315 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
317 /* enable automatic crossover */
318 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
320 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
321 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
322 ctrl
&= ~PHY_M_PC_DSC_MSK
;
323 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
327 /* workaround for deviation #4.88 (CRC errors) */
328 /* disable Automatic Crossover */
330 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
333 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
335 /* special setup for PHY 88E1112 Fiber */
336 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
337 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
341 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
342 ctrl
&= ~PHY_M_MAC_MD_MSK
;
343 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
344 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
346 if (hw
->pmd_type
== 'P') {
347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
350 /* for SFP-module set SIGDET polarity to low */
351 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
352 ctrl
|= PHY_M_FIB_SIGD_POL
;
353 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
356 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
364 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
365 if (sky2_is_copper(hw
)) {
366 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
367 ct1000
|= PHY_M_1000C_AFD
;
368 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
369 ct1000
|= PHY_M_1000C_AHD
;
370 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
371 adv
|= PHY_M_AN_100_FD
;
372 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
373 adv
|= PHY_M_AN_100_HD
;
374 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
375 adv
|= PHY_M_AN_10_FD
;
376 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
377 adv
|= PHY_M_AN_10_HD
;
379 adv
|= copper_fc_adv
[sky2
->flow_mode
];
380 } else { /* special defines for FIBER (88E1040S only) */
381 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
382 adv
|= PHY_M_AN_1000X_AFD
;
383 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
384 adv
|= PHY_M_AN_1000X_AHD
;
386 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
389 /* Restart Auto-negotiation */
390 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
392 /* forced speed/duplex settings */
393 ct1000
= PHY_M_1000C_MSE
;
395 /* Disable auto update for duplex flow control and speed */
396 reg
|= GM_GPCR_AU_ALL_DIS
;
398 switch (sky2
->speed
) {
400 ctrl
|= PHY_CT_SP1000
;
401 reg
|= GM_GPCR_SPEED_1000
;
404 ctrl
|= PHY_CT_SP100
;
405 reg
|= GM_GPCR_SPEED_100
;
409 if (sky2
->duplex
== DUPLEX_FULL
) {
410 reg
|= GM_GPCR_DUP_FULL
;
411 ctrl
|= PHY_CT_DUP_MD
;
412 } else if (sky2
->speed
< SPEED_1000
)
413 sky2
->flow_mode
= FC_NONE
;
416 reg
|= gm_fc_disable
[sky2
->flow_mode
];
418 /* Forward pause packets to GMAC? */
419 if (sky2
->flow_mode
& FC_RX
)
420 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
422 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
425 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
427 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
428 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
430 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
431 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
433 /* Setup Phy LED's */
434 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
437 switch (hw
->chip_id
) {
438 case CHIP_ID_YUKON_FE
:
439 /* on 88E3082 these bits are at 11..9 (shifted left) */
440 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
442 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
444 /* delete ACT LED control bits */
445 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
446 /* change ACT LED control to blink mode */
447 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
448 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
451 case CHIP_ID_YUKON_XL
:
452 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
454 /* select page 3 to access LED control register */
455 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
457 /* set LED Function Control register */
458 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
459 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
460 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
461 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
462 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
464 /* set Polarity Control register */
465 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
466 (PHY_M_POLC_LS1_P_MIX(4) |
467 PHY_M_POLC_IS0_P_MIX(4) |
468 PHY_M_POLC_LOS_CTRL(2) |
469 PHY_M_POLC_INIT_CTRL(2) |
470 PHY_M_POLC_STA1_CTRL(2) |
471 PHY_M_POLC_STA0_CTRL(2)));
473 /* restore page register */
474 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
476 case CHIP_ID_YUKON_EC_U
:
477 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
482 /* set LED Function Control register */
483 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
489 /* set Blink Rate in LED Timer Control Register */
490 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
491 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
492 /* restore page register */
493 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
497 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
498 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
499 /* turn off the Rx LED (LED_RX) */
500 ledover
&= ~PHY_M_LED_MO_RX
;
503 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
504 /* apply fixes in PHY AFE */
505 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
506 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
508 /* increase differential signal amplitude in 10BASE-T */
509 gm_phy_write(hw
, port
, 0x18, 0xaa99);
510 gm_phy_write(hw
, port
, 0x17, 0x2011);
512 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
513 gm_phy_write(hw
, port
, 0x18, 0xa204);
514 gm_phy_write(hw
, port
, 0x17, 0x2002);
516 /* set page register to 0 */
517 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
519 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
521 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
522 /* turn on 100 Mbps LED (LED_LINK100) */
523 ledover
|= PHY_M_LED_MO_100
;
527 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
531 /* Enable phy interrupt on auto-negotiation complete (or link up) */
532 if (sky2
->autoneg
== AUTONEG_ENABLE
)
533 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
535 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
538 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
541 static const u32 phy_power
[]
542 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
544 /* looks like this XL is back asswards .. */
545 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
548 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
549 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
551 /* Turn off phy power saving */
552 reg1
&= ~phy_power
[port
];
554 reg1
|= phy_power
[port
];
556 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
557 sky2_pci_read32(hw
, PCI_DEV_REG1
);
558 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
562 /* Force a renegotiation */
563 static void sky2_phy_reinit(struct sky2_port
*sky2
)
565 spin_lock_bh(&sky2
->phy_lock
);
566 sky2_phy_init(sky2
->hw
, sky2
->port
);
567 spin_unlock_bh(&sky2
->phy_lock
);
570 /* Put device in state to listen for Wake On Lan */
571 static void sky2_wol_init(struct sky2_port
*sky2
)
573 struct sky2_hw
*hw
= sky2
->hw
;
574 unsigned port
= sky2
->port
;
575 enum flow_control save_mode
;
579 /* Bring hardware out of reset */
580 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
581 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
583 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
584 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
587 * sky2_reset will re-enable on resume
589 save_mode
= sky2
->flow_mode
;
590 ctrl
= sky2
->advertising
;
592 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
593 sky2
->flow_mode
= FC_NONE
;
594 sky2_phy_power(hw
, port
, 1);
595 sky2_phy_reinit(sky2
);
597 sky2
->flow_mode
= save_mode
;
598 sky2
->advertising
= ctrl
;
600 /* Set GMAC to no flow control and auto update for speed/duplex */
601 gma_write16(hw
, port
, GM_GP_CTRL
,
602 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
603 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
605 /* Set WOL address */
606 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
607 sky2
->netdev
->dev_addr
, ETH_ALEN
);
609 /* Turn on appropriate WOL control bits */
610 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
612 if (sky2
->wol
& WAKE_PHY
)
613 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
615 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
617 if (sky2
->wol
& WAKE_MAGIC
)
618 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
620 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
622 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
623 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
625 /* Turn on legacy PCI-Express PME mode */
626 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
627 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
628 reg1
|= PCI_Y2_PME_LEGACY
;
629 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
630 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
633 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
637 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
639 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
642 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
644 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
645 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
647 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
649 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
650 /* WA DEV_472 -- looks like crossed wires on port 2 */
651 /* clear GMAC 1 Control reset */
652 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
654 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
655 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
656 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
657 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
658 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
661 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
663 /* Enable Transmit FIFO Underrun */
664 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
666 spin_lock_bh(&sky2
->phy_lock
);
667 sky2_phy_init(hw
, port
);
668 spin_unlock_bh(&sky2
->phy_lock
);
671 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
672 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
674 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
675 gma_read16(hw
, port
, i
);
676 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
678 /* transmit control */
679 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
681 /* receive control reg: unicast + multicast + no FCS */
682 gma_write16(hw
, port
, GM_RX_CTRL
,
683 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
685 /* transmit flow control */
686 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
688 /* transmit parameter */
689 gma_write16(hw
, port
, GM_TX_PARAM
,
690 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
691 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
692 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
693 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
695 /* serial mode register */
696 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
697 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
699 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
700 reg
|= GM_SMOD_JUMBO_ENA
;
702 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
704 /* virtual address for data */
705 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
707 /* physical address: used for pause frames */
708 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
710 /* ignore counter overflows */
711 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
712 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
713 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
715 /* Configure Rx MAC FIFO */
716 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
717 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
718 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
720 /* Flush Rx MAC FIFO on any flow control or error */
721 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
723 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
724 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
726 /* Configure Tx MAC FIFO */
727 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
728 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
730 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
731 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
732 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
733 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
734 /* set Tx GMAC FIFO Almost Empty Threshold */
735 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
736 /* Disable Store & Forward mode for TX */
737 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
743 /* Assign Ram Buffer allocation to queue */
744 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
748 /* convert from K bytes to qwords used for hw register */
751 end
= start
+ space
- 1;
753 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
754 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
755 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
756 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
757 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
759 if (q
== Q_R1
|| q
== Q_R2
) {
760 u32 tp
= space
- space
/4;
762 /* On receive queue's set the thresholds
763 * give receiver priority when > 3/4 full
764 * send pause when down to 2K
766 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
767 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
770 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
771 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
773 /* Enable store & forward on Tx queue's because
774 * Tx FIFO is only 1K on Yukon
776 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
779 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
780 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
783 /* Setup Bus Memory Interface */
784 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
786 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
787 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
788 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
789 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
792 /* Setup prefetch unit registers. This is the interface between
793 * hardware and driver list elements
795 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
798 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
799 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
800 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
801 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
802 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
803 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
805 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
808 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
810 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
812 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
817 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
818 struct sky2_tx_le
*le
)
820 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
823 /* Update chip's next pointer */
824 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
826 q
= Y2_QADDR(q
, PREF_UNIT_PUT_IDX
);
828 sky2_write16(hw
, q
, idx
);
833 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
835 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
836 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
841 /* Return high part of DMA address (could be 32 or 64 bit) */
842 static inline u32
high32(dma_addr_t a
)
844 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
847 /* Build description to hardware for one receive segment */
848 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
849 dma_addr_t map
, unsigned len
)
851 struct sky2_rx_le
*le
;
852 u32 hi
= high32(map
);
854 if (sky2
->rx_addr64
!= hi
) {
855 le
= sky2_next_rx(sky2
);
856 le
->addr
= cpu_to_le32(hi
);
857 le
->opcode
= OP_ADDR64
| HW_OWNER
;
858 sky2
->rx_addr64
= high32(map
+ len
);
861 le
= sky2_next_rx(sky2
);
862 le
->addr
= cpu_to_le32((u32
) map
);
863 le
->length
= cpu_to_le16(len
);
864 le
->opcode
= op
| HW_OWNER
;
867 /* Build description to hardware for one possibly fragmented skb */
868 static void sky2_rx_submit(struct sky2_port
*sky2
,
869 const struct rx_ring_info
*re
)
873 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
875 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
876 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
880 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
883 struct sk_buff
*skb
= re
->skb
;
886 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
887 pci_unmap_len_set(re
, data_size
, size
);
889 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
890 re
->frag_addr
[i
] = pci_map_page(pdev
,
891 skb_shinfo(skb
)->frags
[i
].page
,
892 skb_shinfo(skb
)->frags
[i
].page_offset
,
893 skb_shinfo(skb
)->frags
[i
].size
,
897 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
899 struct sk_buff
*skb
= re
->skb
;
902 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
905 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
906 pci_unmap_page(pdev
, re
->frag_addr
[i
],
907 skb_shinfo(skb
)->frags
[i
].size
,
911 /* Tell chip where to start receive checksum.
912 * Actually has two checksums, but set both same to avoid possible byte
915 static void rx_set_checksum(struct sky2_port
*sky2
)
917 struct sky2_rx_le
*le
;
919 le
= sky2_next_rx(sky2
);
920 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
922 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
924 sky2_write32(sky2
->hw
,
925 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
926 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
931 * The RX Stop command will not work for Yukon-2 if the BMU does not
932 * reach the end of packet and since we can't make sure that we have
933 * incoming data, we must reset the BMU while it is not doing a DMA
934 * transfer. Since it is possible that the RX path is still active,
935 * the RX RAM buffer will be stopped first, so any possible incoming
936 * data will not trigger a DMA. After the RAM buffer is stopped, the
937 * BMU is polled until any DMA in progress is ended and only then it
940 static void sky2_rx_stop(struct sky2_port
*sky2
)
942 struct sky2_hw
*hw
= sky2
->hw
;
943 unsigned rxq
= rxqaddr
[sky2
->port
];
946 /* disable the RAM Buffer receive queue */
947 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
949 for (i
= 0; i
< 0xffff; i
++)
950 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
951 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
954 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
957 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
959 /* reset the Rx prefetch unit */
960 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
963 /* Clean out receive buffer area, assumes receiver hardware stopped */
964 static void sky2_rx_clean(struct sky2_port
*sky2
)
968 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
969 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
970 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
973 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
980 /* Basic MII support */
981 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
983 struct mii_ioctl_data
*data
= if_mii(ifr
);
984 struct sky2_port
*sky2
= netdev_priv(dev
);
985 struct sky2_hw
*hw
= sky2
->hw
;
986 int err
= -EOPNOTSUPP
;
988 if (!netif_running(dev
))
989 return -ENODEV
; /* Phy still in reset */
993 data
->phy_id
= PHY_ADDR_MARV
;
999 spin_lock_bh(&sky2
->phy_lock
);
1000 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1001 spin_unlock_bh(&sky2
->phy_lock
);
1003 data
->val_out
= val
;
1008 if (!capable(CAP_NET_ADMIN
))
1011 spin_lock_bh(&sky2
->phy_lock
);
1012 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1014 spin_unlock_bh(&sky2
->phy_lock
);
1020 #ifdef SKY2_VLAN_TAG_USED
1021 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1023 struct sky2_port
*sky2
= netdev_priv(dev
);
1024 struct sky2_hw
*hw
= sky2
->hw
;
1025 u16 port
= sky2
->port
;
1027 netif_tx_lock_bh(dev
);
1029 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
1030 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
1033 netif_tx_unlock_bh(dev
);
1036 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
1038 struct sky2_port
*sky2
= netdev_priv(dev
);
1039 struct sky2_hw
*hw
= sky2
->hw
;
1040 u16 port
= sky2
->port
;
1042 netif_tx_lock_bh(dev
);
1044 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
1045 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
1047 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
1049 netif_tx_unlock_bh(dev
);
1054 * Allocate an skb for receiving. If the MTU is large enough
1055 * make the skb non-linear with a fragment list of pages.
1057 * It appears the hardware has a bug in the FIFO logic that
1058 * cause it to hang if the FIFO gets overrun and the receive buffer
1059 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1060 * aligned except if slab debugging is enabled.
1062 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1064 struct sk_buff
*skb
;
1068 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1072 p
= (unsigned long) skb
->data
;
1073 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1075 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1076 struct page
*page
= alloc_page(GFP_ATOMIC
);
1080 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1091 * Allocate and setup receiver buffer pool.
1092 * Normal case this ends up creating one list element for skb
1093 * in the receive ring. Worst case if using large MTU and each
1094 * allocation falls on a different 64 bit region, that results
1095 * in 6 list elements per ring entry.
1096 * One element is used for checksum enable/disable, and one
1097 * extra to avoid wrap.
1099 static int sky2_rx_start(struct sky2_port
*sky2
)
1101 struct sky2_hw
*hw
= sky2
->hw
;
1102 struct rx_ring_info
*re
;
1103 unsigned rxq
= rxqaddr
[sky2
->port
];
1104 unsigned i
, size
, space
, thresh
;
1106 sky2
->rx_put
= sky2
->rx_next
= 0;
1109 /* On PCI express lowering the watermark gives better performance */
1110 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1111 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1113 /* These chips have no ram buffer?
1114 * MAC Rx RAM Read is controlled by hardware */
1115 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1116 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1117 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1118 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
1120 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1122 rx_set_checksum(sky2
);
1124 /* Space needed for frame data + headers rounded up */
1125 size
= ALIGN(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8)
1128 /* Stopping point for hardware truncation */
1129 thresh
= (size
- 8) / sizeof(u32
);
1131 /* Account for overhead of skb - to avoid order > 0 allocation */
1132 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1133 + sizeof(struct skb_shared_info
);
1135 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1136 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1138 if (sky2
->rx_nfrags
!= 0) {
1139 /* Compute residue after pages */
1140 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1147 /* Optimize to handle small packets and headers */
1148 if (size
< copybreak
)
1150 if (size
< ETH_HLEN
)
1153 sky2
->rx_data_size
= size
;
1156 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1157 re
= sky2
->rx_ring
+ i
;
1159 re
->skb
= sky2_rx_alloc(sky2
);
1163 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1164 sky2_rx_submit(sky2
, re
);
1168 * The receiver hangs if it receives frames larger than the
1169 * packet buffer. As a workaround, truncate oversize frames, but
1170 * the register is limited to 9 bits, so if you do frames > 2052
1171 * you better get the MTU right!
1174 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1176 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1177 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1180 /* Tell chip about available buffers */
1181 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1184 sky2_rx_clean(sky2
);
1188 /* Bring up network interface. */
1189 static int sky2_up(struct net_device
*dev
)
1191 struct sky2_port
*sky2
= netdev_priv(dev
);
1192 struct sky2_hw
*hw
= sky2
->hw
;
1193 unsigned port
= sky2
->port
;
1195 int cap
, err
= -ENOMEM
;
1196 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1199 * On dual port PCI-X card, there is an problem where status
1200 * can be received out of order due to split transactions
1202 if (otherdev
&& netif_running(otherdev
) &&
1203 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1204 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1207 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1208 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1209 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1215 if (netif_msg_ifup(sky2
))
1216 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1218 /* must be power of 2 */
1219 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1221 sizeof(struct sky2_tx_le
),
1226 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1230 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1232 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1236 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1238 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1243 sky2_phy_power(hw
, port
, 1);
1245 sky2_mac_init(hw
, port
);
1247 /* Register is number of 4K blocks on internal RAM buffer. */
1248 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1249 printk(KERN_INFO PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1255 rxspace
= ramsize
/ 2;
1257 rxspace
= 8 + (2*(ramsize
- 16))/3;
1259 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1260 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1262 /* Make sure SyncQ is disabled */
1263 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1267 sky2_qset(hw
, txqaddr
[port
]);
1269 /* Set almost empty threshold */
1270 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1271 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1272 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1274 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1277 err
= sky2_rx_start(sky2
);
1281 /* Enable interrupts from phy/mac for port */
1282 imask
= sky2_read32(hw
, B0_IMSK
);
1283 imask
|= portirq_msk
[port
];
1284 sky2_write32(hw
, B0_IMSK
, imask
);
1290 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1291 sky2
->rx_le
, sky2
->rx_le_map
);
1295 pci_free_consistent(hw
->pdev
,
1296 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1297 sky2
->tx_le
, sky2
->tx_le_map
);
1300 kfree(sky2
->tx_ring
);
1301 kfree(sky2
->rx_ring
);
1303 sky2
->tx_ring
= NULL
;
1304 sky2
->rx_ring
= NULL
;
1308 /* Modular subtraction in ring */
1309 static inline int tx_dist(unsigned tail
, unsigned head
)
1311 return (head
- tail
) & (TX_RING_SIZE
- 1);
1314 /* Number of list elements available for next tx */
1315 static inline int tx_avail(const struct sky2_port
*sky2
)
1317 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1320 /* Estimate of number of transmit list elements required */
1321 static unsigned tx_le_req(const struct sk_buff
*skb
)
1325 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1326 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1328 if (skb_is_gso(skb
))
1331 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1338 * Put one packet in ring for transmit.
1339 * A single packet can generate multiple list elements, and
1340 * the number of ring elements will probably be less than the number
1341 * of list elements used.
1343 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1345 struct sky2_port
*sky2
= netdev_priv(dev
);
1346 struct sky2_hw
*hw
= sky2
->hw
;
1347 struct sky2_tx_le
*le
= NULL
;
1348 struct tx_ring_info
*re
;
1355 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1356 return NETDEV_TX_BUSY
;
1358 if (unlikely(netif_msg_tx_queued(sky2
)))
1359 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1360 dev
->name
, sky2
->tx_prod
, skb
->len
);
1362 len
= skb_headlen(skb
);
1363 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1364 addr64
= high32(mapping
);
1366 /* Send high bits if changed or crosses boundary */
1367 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1368 le
= get_tx_le(sky2
);
1369 le
->addr
= cpu_to_le32(addr64
);
1370 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1371 sky2
->tx_addr64
= high32(mapping
+ len
);
1374 /* Check for TCP Segmentation Offload */
1375 mss
= skb_shinfo(skb
)->gso_size
;
1377 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1378 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1381 if (mss
!= sky2
->tx_last_mss
) {
1382 le
= get_tx_le(sky2
);
1383 le
->addr
= cpu_to_le32(mss
);
1384 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1385 sky2
->tx_last_mss
= mss
;
1390 #ifdef SKY2_VLAN_TAG_USED
1391 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1392 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1394 le
= get_tx_le(sky2
);
1396 le
->opcode
= OP_VLAN
|HW_OWNER
;
1398 le
->opcode
|= OP_VLAN
;
1399 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1404 /* Handle TCP checksum offload */
1405 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1406 unsigned offset
= skb
->h
.raw
- skb
->data
;
1409 tcpsum
= offset
<< 16; /* sum start */
1410 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1412 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1413 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1416 if (tcpsum
!= sky2
->tx_tcpsum
) {
1417 sky2
->tx_tcpsum
= tcpsum
;
1419 le
= get_tx_le(sky2
);
1420 le
->addr
= cpu_to_le32(tcpsum
);
1421 le
->length
= 0; /* initial checksum value */
1422 le
->ctrl
= 1; /* one packet */
1423 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1427 le
= get_tx_le(sky2
);
1428 le
->addr
= cpu_to_le32((u32
) mapping
);
1429 le
->length
= cpu_to_le16(len
);
1431 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1433 re
= tx_le_re(sky2
, le
);
1435 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1436 pci_unmap_len_set(re
, maplen
, len
);
1438 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1439 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1441 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1442 frag
->size
, PCI_DMA_TODEVICE
);
1443 addr64
= high32(mapping
);
1444 if (addr64
!= sky2
->tx_addr64
) {
1445 le
= get_tx_le(sky2
);
1446 le
->addr
= cpu_to_le32(addr64
);
1448 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1449 sky2
->tx_addr64
= addr64
;
1452 le
= get_tx_le(sky2
);
1453 le
->addr
= cpu_to_le32((u32
) mapping
);
1454 le
->length
= cpu_to_le16(frag
->size
);
1456 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1458 re
= tx_le_re(sky2
, le
);
1460 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1461 pci_unmap_len_set(re
, maplen
, frag
->size
);
1466 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1467 netif_stop_queue(dev
);
1469 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1471 dev
->trans_start
= jiffies
;
1472 return NETDEV_TX_OK
;
1476 * Free ring elements from starting at tx_cons until "done"
1478 * NB: the hardware will tell us about partial completion of multi-part
1479 * buffers so make sure not to free skb to early.
1481 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1483 struct net_device
*dev
= sky2
->netdev
;
1484 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1487 BUG_ON(done
>= TX_RING_SIZE
);
1489 for (idx
= sky2
->tx_cons
; idx
!= done
;
1490 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1491 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1492 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1494 switch(le
->opcode
& ~HW_OWNER
) {
1497 pci_unmap_single(pdev
,
1498 pci_unmap_addr(re
, mapaddr
),
1499 pci_unmap_len(re
, maplen
),
1503 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1504 pci_unmap_len(re
, maplen
),
1509 if (le
->ctrl
& EOP
) {
1510 if (unlikely(netif_msg_tx_done(sky2
)))
1511 printk(KERN_DEBUG
"%s: tx done %u\n",
1513 sky2
->net_stats
.tx_packets
++;
1514 sky2
->net_stats
.tx_bytes
+= re
->skb
->len
;
1516 dev_kfree_skb_any(re
->skb
);
1519 le
->opcode
= 0; /* paranoia */
1522 sky2
->tx_cons
= idx
;
1523 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1524 netif_wake_queue(dev
);
1527 /* Cleanup all untransmitted buffers, assume transmitter not running */
1528 static void sky2_tx_clean(struct net_device
*dev
)
1530 struct sky2_port
*sky2
= netdev_priv(dev
);
1532 netif_tx_lock_bh(dev
);
1533 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1534 netif_tx_unlock_bh(dev
);
1537 /* Network shutdown */
1538 static int sky2_down(struct net_device
*dev
)
1540 struct sky2_port
*sky2
= netdev_priv(dev
);
1541 struct sky2_hw
*hw
= sky2
->hw
;
1542 unsigned port
= sky2
->port
;
1546 /* Never really got started! */
1550 if (netif_msg_ifdown(sky2
))
1551 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1553 /* Stop more packets from being queued */
1554 netif_stop_queue(dev
);
1556 /* Disable port IRQ */
1557 imask
= sky2_read32(hw
, B0_IMSK
);
1558 imask
&= ~portirq_msk
[port
];
1559 sky2_write32(hw
, B0_IMSK
, imask
);
1562 * Both ports share the NAPI poll on port 0, so if necessary undo the
1563 * the disable that is done in dev_close.
1565 if (sky2
->port
== 0 && hw
->ports
> 1)
1566 netif_poll_enable(dev
);
1568 sky2_gmac_reset(hw
, port
);
1570 /* Stop transmitter */
1571 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1572 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1574 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1575 RB_RST_SET
| RB_DIS_OP_MD
);
1577 /* WA for dev. #4.209 */
1578 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1579 && (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
|| hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1580 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1581 sky2
->speed
!= SPEED_1000
?
1582 TX_STFW_ENA
: TX_STFW_DIS
);
1584 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1585 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1586 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1588 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1590 /* Workaround shared GMAC reset */
1591 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1592 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1593 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1595 /* Disable Force Sync bit and Enable Alloc bit */
1596 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1597 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1599 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1600 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1601 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1603 /* Reset the PCI FIFO of the async Tx queue */
1604 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1605 BMU_RST_SET
| BMU_FIFO_RST
);
1607 /* Reset the Tx prefetch units */
1608 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1611 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1615 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1616 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1618 sky2_phy_power(hw
, port
, 0);
1620 /* turn off LED's */
1621 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1623 synchronize_irq(hw
->pdev
->irq
);
1626 sky2_rx_clean(sky2
);
1628 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1629 sky2
->rx_le
, sky2
->rx_le_map
);
1630 kfree(sky2
->rx_ring
);
1632 pci_free_consistent(hw
->pdev
,
1633 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1634 sky2
->tx_le
, sky2
->tx_le_map
);
1635 kfree(sky2
->tx_ring
);
1640 sky2
->rx_ring
= NULL
;
1641 sky2
->tx_ring
= NULL
;
1646 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1648 if (!sky2_is_copper(hw
))
1651 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1652 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1654 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1655 case PHY_M_PS_SPEED_1000
:
1657 case PHY_M_PS_SPEED_100
:
1664 static void sky2_link_up(struct sky2_port
*sky2
)
1666 struct sky2_hw
*hw
= sky2
->hw
;
1667 unsigned port
= sky2
->port
;
1669 static const char *fc_name
[] = {
1677 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1678 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1679 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1681 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1683 netif_carrier_on(sky2
->netdev
);
1684 netif_wake_queue(sky2
->netdev
);
1686 /* Turn on link LED */
1687 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1688 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1690 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1691 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1692 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1694 switch(sky2
->speed
) {
1696 led
|= PHY_M_LEDC_INIT_CTRL(7);
1700 led
|= PHY_M_LEDC_STA1_CTRL(7);
1704 led
|= PHY_M_LEDC_STA0_CTRL(7);
1708 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1709 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1710 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1713 if (netif_msg_link(sky2
))
1714 printk(KERN_INFO PFX
1715 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1716 sky2
->netdev
->name
, sky2
->speed
,
1717 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1718 fc_name
[sky2
->flow_status
]);
1721 static void sky2_link_down(struct sky2_port
*sky2
)
1723 struct sky2_hw
*hw
= sky2
->hw
;
1724 unsigned port
= sky2
->port
;
1727 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1729 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1730 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1731 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1733 if (sky2
->flow_status
== FC_RX
) {
1734 /* restore Asymmetric Pause bit */
1735 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1736 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1740 netif_carrier_off(sky2
->netdev
);
1741 netif_stop_queue(sky2
->netdev
);
1743 /* Turn on link LED */
1744 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1746 if (netif_msg_link(sky2
))
1747 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1749 sky2_phy_init(hw
, port
);
1752 static enum flow_control
sky2_flow(int rx
, int tx
)
1755 return tx
? FC_BOTH
: FC_RX
;
1757 return tx
? FC_TX
: FC_NONE
;
1760 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1762 struct sky2_hw
*hw
= sky2
->hw
;
1763 unsigned port
= sky2
->port
;
1766 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1768 if (lpa
& PHY_M_AN_RF
) {
1769 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1773 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1774 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1775 sky2
->netdev
->name
);
1779 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1780 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1782 /* Pause bits are offset (9..8) */
1783 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1786 sky2
->flow_status
= sky2_flow(aux
& PHY_M_PS_RX_P_EN
,
1787 aux
& PHY_M_PS_TX_P_EN
);
1789 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1790 && hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
1791 sky2
->flow_status
= FC_NONE
;
1793 if (aux
& PHY_M_PS_RX_P_EN
)
1794 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1796 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1801 /* Interrupt from PHY */
1802 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1804 struct net_device
*dev
= hw
->dev
[port
];
1805 struct sky2_port
*sky2
= netdev_priv(dev
);
1806 u16 istatus
, phystat
;
1808 if (!netif_running(dev
))
1811 spin_lock(&sky2
->phy_lock
);
1812 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1813 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1815 if (netif_msg_intr(sky2
))
1816 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1817 sky2
->netdev
->name
, istatus
, phystat
);
1819 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1820 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1825 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1826 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1828 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1830 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1832 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1833 if (phystat
& PHY_M_PS_LINK_UP
)
1836 sky2_link_down(sky2
);
1839 spin_unlock(&sky2
->phy_lock
);
1843 /* Transmit timeout is only called if we are running, carries is up
1844 * and tx queue is full (stopped).
1846 static void sky2_tx_timeout(struct net_device
*dev
)
1848 struct sky2_port
*sky2
= netdev_priv(dev
);
1849 struct sky2_hw
*hw
= sky2
->hw
;
1850 unsigned txq
= txqaddr
[sky2
->port
];
1853 if (netif_msg_timer(sky2
))
1854 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1856 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1857 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1859 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1861 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1863 if (report
!= done
) {
1864 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1866 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1867 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1868 } else if (report
!= sky2
->tx_cons
) {
1869 printk(KERN_INFO PFX
"status report lost?\n");
1871 netif_tx_lock_bh(dev
);
1872 sky2_tx_complete(sky2
, report
);
1873 netif_tx_unlock_bh(dev
);
1875 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1877 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1878 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1883 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1887 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1889 struct sky2_port
*sky2
= netdev_priv(dev
);
1890 struct sky2_hw
*hw
= sky2
->hw
;
1895 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1898 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1901 if (!netif_running(dev
)) {
1906 imask
= sky2_read32(hw
, B0_IMSK
);
1907 sky2_write32(hw
, B0_IMSK
, 0);
1909 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1910 netif_stop_queue(dev
);
1911 netif_poll_disable(hw
->dev
[0]);
1913 synchronize_irq(hw
->pdev
->irq
);
1915 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1916 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1918 sky2_rx_clean(sky2
);
1922 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1923 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1925 if (dev
->mtu
> ETH_DATA_LEN
)
1926 mode
|= GM_SMOD_JUMBO_ENA
;
1928 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1930 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1932 err
= sky2_rx_start(sky2
);
1933 sky2_write32(hw
, B0_IMSK
, imask
);
1938 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1940 netif_poll_enable(hw
->dev
[0]);
1941 netif_wake_queue(dev
);
1947 /* For small just reuse existing skb for next receive */
1948 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
1949 const struct rx_ring_info
*re
,
1952 struct sk_buff
*skb
;
1954 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
1956 skb_reserve(skb
, 2);
1957 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
1958 length
, PCI_DMA_FROMDEVICE
);
1959 memcpy(skb
->data
, re
->skb
->data
, length
);
1960 skb
->ip_summed
= re
->skb
->ip_summed
;
1961 skb
->csum
= re
->skb
->csum
;
1962 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
1963 length
, PCI_DMA_FROMDEVICE
);
1964 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1965 skb_put(skb
, length
);
1970 /* Adjust length of skb with fragments to match received data */
1971 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
1972 unsigned int length
)
1977 /* put header into skb */
1978 size
= min(length
, hdr_space
);
1983 num_frags
= skb_shinfo(skb
)->nr_frags
;
1984 for (i
= 0; i
< num_frags
; i
++) {
1985 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1988 /* don't need this page */
1989 __free_page(frag
->page
);
1990 --skb_shinfo(skb
)->nr_frags
;
1992 size
= min(length
, (unsigned) PAGE_SIZE
);
1995 skb
->data_len
+= size
;
1996 skb
->truesize
+= size
;
2003 /* Normal packet - take skb from ring element and put in a new one */
2004 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2005 struct rx_ring_info
*re
,
2006 unsigned int length
)
2008 struct sk_buff
*skb
, *nskb
;
2009 unsigned hdr_space
= sky2
->rx_data_size
;
2011 pr_debug(PFX
"receive new length=%d\n", length
);
2013 /* Don't be tricky about reusing pages (yet) */
2014 nskb
= sky2_rx_alloc(sky2
);
2015 if (unlikely(!nskb
))
2019 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2021 prefetch(skb
->data
);
2023 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
2025 if (skb_shinfo(skb
)->nr_frags
)
2026 skb_put_frags(skb
, hdr_space
, length
);
2028 skb_put(skb
, length
);
2033 * Receive one packet.
2034 * For larger packets, get new buffer.
2036 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2037 u16 length
, u32 status
)
2039 struct sky2_port
*sky2
= netdev_priv(dev
);
2040 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2041 struct sk_buff
*skb
= NULL
;
2043 if (unlikely(netif_msg_rx_status(sky2
)))
2044 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2045 dev
->name
, sky2
->rx_next
, status
, length
);
2047 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2048 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2050 if (status
& GMR_FS_ANY_ERR
)
2053 if (!(status
& GMR_FS_RX_OK
))
2056 if (length
> dev
->mtu
+ ETH_HLEN
)
2059 if (length
< copybreak
)
2060 skb
= receive_copy(sky2
, re
, length
);
2062 skb
= receive_new(sky2
, re
, length
);
2064 sky2_rx_submit(sky2
, re
);
2069 ++sky2
->net_stats
.rx_over_errors
;
2073 ++sky2
->net_stats
.rx_errors
;
2074 if (status
& GMR_FS_RX_FF_OV
) {
2075 sky2
->net_stats
.rx_fifo_errors
++;
2079 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2080 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2081 dev
->name
, status
, length
);
2083 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2084 sky2
->net_stats
.rx_length_errors
++;
2085 if (status
& GMR_FS_FRAGMENT
)
2086 sky2
->net_stats
.rx_frame_errors
++;
2087 if (status
& GMR_FS_CRC_ERR
)
2088 sky2
->net_stats
.rx_crc_errors
++;
2093 /* Transmit complete */
2094 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2096 struct sky2_port
*sky2
= netdev_priv(dev
);
2098 if (netif_running(dev
)) {
2100 sky2_tx_complete(sky2
, last
);
2101 netif_tx_unlock(dev
);
2105 /* Process status response ring */
2106 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2108 struct sky2_port
*sky2
;
2110 unsigned buf_write
[2] = { 0, 0 };
2111 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2115 while (hw
->st_idx
!= hwidx
) {
2116 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2117 struct net_device
*dev
;
2118 struct sk_buff
*skb
;
2122 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2124 BUG_ON(le
->link
>= 2);
2125 dev
= hw
->dev
[le
->link
];
2127 sky2
= netdev_priv(dev
);
2128 length
= le16_to_cpu(le
->length
);
2129 status
= le32_to_cpu(le
->status
);
2131 switch (le
->opcode
& ~HW_OWNER
) {
2133 skb
= sky2_receive(dev
, length
, status
);
2137 skb
->protocol
= eth_type_trans(skb
, dev
);
2138 sky2
->net_stats
.rx_packets
++;
2139 sky2
->net_stats
.rx_bytes
+= skb
->len
;
2140 dev
->last_rx
= jiffies
;
2142 #ifdef SKY2_VLAN_TAG_USED
2143 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2144 vlan_hwaccel_receive_skb(skb
,
2146 be16_to_cpu(sky2
->rx_tag
));
2149 netif_receive_skb(skb
);
2151 /* Update receiver after 16 frames */
2152 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
2154 sky2_put_idx(hw
, rxqaddr
[le
->link
], sky2
->rx_put
);
2155 buf_write
[le
->link
] = 0;
2158 /* Stop after net poll weight */
2159 if (++work_done
>= to_do
)
2163 #ifdef SKY2_VLAN_TAG_USED
2165 sky2
->rx_tag
= length
;
2169 sky2
->rx_tag
= length
;
2173 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2174 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2175 skb
->csum
= status
& 0xffff;
2179 /* TX index reports status for both ports */
2180 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2181 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2183 sky2_tx_done(hw
->dev
[1],
2184 ((status
>> 24) & 0xff)
2185 | (u16
)(length
& 0xf) << 8);
2189 if (net_ratelimit())
2190 printk(KERN_WARNING PFX
2191 "unknown status opcode 0x%x\n", le
->opcode
);
2196 /* Fully processed status ring so clear irq */
2197 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2201 sky2
= netdev_priv(hw
->dev
[0]);
2202 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2206 sky2
= netdev_priv(hw
->dev
[1]);
2207 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2213 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2215 struct net_device
*dev
= hw
->dev
[port
];
2217 if (net_ratelimit())
2218 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2221 if (status
& Y2_IS_PAR_RD1
) {
2222 if (net_ratelimit())
2223 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2226 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2229 if (status
& Y2_IS_PAR_WR1
) {
2230 if (net_ratelimit())
2231 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2234 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2237 if (status
& Y2_IS_PAR_MAC1
) {
2238 if (net_ratelimit())
2239 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2240 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2243 if (status
& Y2_IS_PAR_RX1
) {
2244 if (net_ratelimit())
2245 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2246 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2249 if (status
& Y2_IS_TCP_TXA1
) {
2250 if (net_ratelimit())
2251 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2253 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2257 static void sky2_hw_intr(struct sky2_hw
*hw
)
2259 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2261 if (status
& Y2_IS_TIST_OV
)
2262 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2264 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2267 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2268 if (net_ratelimit())
2269 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2270 pci_name(hw
->pdev
), pci_err
);
2272 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2273 sky2_pci_write16(hw
, PCI_STATUS
,
2274 pci_err
| PCI_STATUS_ERROR_BITS
);
2275 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2278 if (status
& Y2_IS_PCI_EXP
) {
2279 /* PCI-Express uncorrectable Error occurred */
2282 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2284 if (net_ratelimit())
2285 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2286 pci_name(hw
->pdev
), pex_err
);
2288 /* clear the interrupt */
2289 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2290 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2292 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2294 if (pex_err
& PEX_FATAL_ERRORS
) {
2295 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2296 hwmsk
&= ~Y2_IS_PCI_EXP
;
2297 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2301 if (status
& Y2_HWE_L1_MASK
)
2302 sky2_hw_error(hw
, 0, status
);
2304 if (status
& Y2_HWE_L1_MASK
)
2305 sky2_hw_error(hw
, 1, status
);
2308 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2310 struct net_device
*dev
= hw
->dev
[port
];
2311 struct sky2_port
*sky2
= netdev_priv(dev
);
2312 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2314 if (netif_msg_intr(sky2
))
2315 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2318 if (status
& GM_IS_RX_FF_OR
) {
2319 ++sky2
->net_stats
.rx_fifo_errors
;
2320 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2323 if (status
& GM_IS_TX_FF_UR
) {
2324 ++sky2
->net_stats
.tx_fifo_errors
;
2325 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2329 /* This should never happen it is a fatal situation */
2330 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2331 const char *rxtx
, u32 mask
)
2333 struct net_device
*dev
= hw
->dev
[port
];
2334 struct sky2_port
*sky2
= netdev_priv(dev
);
2337 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2338 dev
? dev
->name
: "<not registered>", rxtx
);
2340 imask
= sky2_read32(hw
, B0_IMSK
);
2342 sky2_write32(hw
, B0_IMSK
, imask
);
2345 spin_lock(&sky2
->phy_lock
);
2346 sky2_link_down(sky2
);
2347 spin_unlock(&sky2
->phy_lock
);
2351 /* If idle then force a fake soft NAPI poll once a second
2352 * to work around cases where sharing an edge triggered interrupt.
2354 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2356 if (idle_timeout
> 0)
2357 mod_timer(&hw
->idle_timer
,
2358 jiffies
+ msecs_to_jiffies(idle_timeout
));
2361 static void sky2_idle(unsigned long arg
)
2363 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2364 struct net_device
*dev
= hw
->dev
[0];
2366 if (__netif_rx_schedule_prep(dev
))
2367 __netif_rx_schedule(dev
);
2369 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2373 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2375 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2376 int work_limit
= min(dev0
->quota
, *budget
);
2378 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2380 if (status
& Y2_IS_HW_ERR
)
2383 if (status
& Y2_IS_IRQ_PHY1
)
2384 sky2_phy_intr(hw
, 0);
2386 if (status
& Y2_IS_IRQ_PHY2
)
2387 sky2_phy_intr(hw
, 1);
2389 if (status
& Y2_IS_IRQ_MAC1
)
2390 sky2_mac_intr(hw
, 0);
2392 if (status
& Y2_IS_IRQ_MAC2
)
2393 sky2_mac_intr(hw
, 1);
2395 if (status
& Y2_IS_CHK_RX1
)
2396 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2398 if (status
& Y2_IS_CHK_RX2
)
2399 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2401 if (status
& Y2_IS_CHK_TXA1
)
2402 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2404 if (status
& Y2_IS_CHK_TXA2
)
2405 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2407 work_done
= sky2_status_intr(hw
, work_limit
);
2408 if (work_done
< work_limit
) {
2409 netif_rx_complete(dev0
);
2411 sky2_read32(hw
, B0_Y2_SP_LISR
);
2414 *budget
-= work_done
;
2415 dev0
->quota
-= work_done
;
2420 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2422 struct sky2_hw
*hw
= dev_id
;
2423 struct net_device
*dev0
= hw
->dev
[0];
2426 /* Reading this mask interrupts as side effect */
2427 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2428 if (status
== 0 || status
== ~0)
2431 prefetch(&hw
->st_le
[hw
->st_idx
]);
2432 if (likely(__netif_rx_schedule_prep(dev0
)))
2433 __netif_rx_schedule(dev0
);
2438 #ifdef CONFIG_NET_POLL_CONTROLLER
2439 static void sky2_netpoll(struct net_device
*dev
)
2441 struct sky2_port
*sky2
= netdev_priv(dev
);
2442 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2444 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2445 __netif_rx_schedule(dev0
);
2449 /* Chip internal frequency for clock calculations */
2450 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2452 switch (hw
->chip_id
) {
2453 case CHIP_ID_YUKON_EC
:
2454 case CHIP_ID_YUKON_EC_U
:
2455 return 125; /* 125 Mhz */
2456 case CHIP_ID_YUKON_FE
:
2457 return 100; /* 100 Mhz */
2458 default: /* YUKON_XL */
2459 return 156; /* 156 Mhz */
2463 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2465 return sky2_mhz(hw
) * us
;
2468 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2470 return clk
/ sky2_mhz(hw
);
2474 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2478 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2480 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2481 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2482 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2483 pci_name(hw
->pdev
), hw
->chip_id
);
2487 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2489 /* This rev is really old, and requires untested workarounds */
2490 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2491 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2492 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2493 hw
->chip_id
, hw
->chip_rev
);
2497 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2499 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2500 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2501 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2508 static void sky2_reset(struct sky2_hw
*hw
)
2514 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2515 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2516 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2520 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2521 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2523 /* clear PCI errors, if any */
2524 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2526 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2527 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2530 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2532 /* clear any PEX errors */
2533 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2534 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2539 for (i
= 0; i
< hw
->ports
; i
++) {
2540 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2541 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2544 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2546 /* Clear I2C IRQ noise */
2547 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2549 /* turn off hardware timer (unused) */
2550 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2551 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2553 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2555 /* Turn off descriptor polling */
2556 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2558 /* Turn off receive timestamp */
2559 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2560 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2562 /* enable the Tx Arbiters */
2563 for (i
= 0; i
< hw
->ports
; i
++)
2564 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2566 /* Initialize ram interface */
2567 for (i
= 0; i
< hw
->ports
; i
++) {
2568 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2570 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2571 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2572 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2573 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2574 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2575 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2576 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2577 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2578 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2579 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2580 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2581 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2584 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2586 for (i
= 0; i
< hw
->ports
; i
++)
2587 sky2_gmac_reset(hw
, i
);
2589 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2592 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2593 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2595 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2596 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2598 /* Set the list last index */
2599 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2601 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2602 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2604 /* set Status-FIFO ISR watermark */
2605 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2606 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2608 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2610 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2611 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2612 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2614 /* enable status unit */
2615 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2617 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2618 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2619 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2622 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
2624 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
2627 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2629 const struct sky2_port
*sky2
= netdev_priv(dev
);
2631 wol
->supported
= sky2_wol_supported(sky2
->hw
);
2632 wol
->wolopts
= sky2
->wol
;
2635 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2637 struct sky2_port
*sky2
= netdev_priv(dev
);
2638 struct sky2_hw
*hw
= sky2
->hw
;
2640 if (wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
2643 sky2
->wol
= wol
->wolopts
;
2645 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
2646 sky2_write32(hw
, B0_CTST
, sky2
->wol
2647 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
2649 if (!netif_running(dev
))
2650 sky2_wol_init(sky2
);
2654 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2656 if (sky2_is_copper(hw
)) {
2657 u32 modes
= SUPPORTED_10baseT_Half
2658 | SUPPORTED_10baseT_Full
2659 | SUPPORTED_100baseT_Half
2660 | SUPPORTED_100baseT_Full
2661 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2663 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2664 modes
|= SUPPORTED_1000baseT_Half
2665 | SUPPORTED_1000baseT_Full
;
2668 return SUPPORTED_1000baseT_Half
2669 | SUPPORTED_1000baseT_Full
2674 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2676 struct sky2_port
*sky2
= netdev_priv(dev
);
2677 struct sky2_hw
*hw
= sky2
->hw
;
2679 ecmd
->transceiver
= XCVR_INTERNAL
;
2680 ecmd
->supported
= sky2_supported_modes(hw
);
2681 ecmd
->phy_address
= PHY_ADDR_MARV
;
2682 if (sky2_is_copper(hw
)) {
2683 ecmd
->supported
= SUPPORTED_10baseT_Half
2684 | SUPPORTED_10baseT_Full
2685 | SUPPORTED_100baseT_Half
2686 | SUPPORTED_100baseT_Full
2687 | SUPPORTED_1000baseT_Half
2688 | SUPPORTED_1000baseT_Full
2689 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2690 ecmd
->port
= PORT_TP
;
2691 ecmd
->speed
= sky2
->speed
;
2693 ecmd
->speed
= SPEED_1000
;
2694 ecmd
->port
= PORT_FIBRE
;
2697 ecmd
->advertising
= sky2
->advertising
;
2698 ecmd
->autoneg
= sky2
->autoneg
;
2699 ecmd
->duplex
= sky2
->duplex
;
2703 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2705 struct sky2_port
*sky2
= netdev_priv(dev
);
2706 const struct sky2_hw
*hw
= sky2
->hw
;
2707 u32 supported
= sky2_supported_modes(hw
);
2709 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2710 ecmd
->advertising
= supported
;
2716 switch (ecmd
->speed
) {
2718 if (ecmd
->duplex
== DUPLEX_FULL
)
2719 setting
= SUPPORTED_1000baseT_Full
;
2720 else if (ecmd
->duplex
== DUPLEX_HALF
)
2721 setting
= SUPPORTED_1000baseT_Half
;
2726 if (ecmd
->duplex
== DUPLEX_FULL
)
2727 setting
= SUPPORTED_100baseT_Full
;
2728 else if (ecmd
->duplex
== DUPLEX_HALF
)
2729 setting
= SUPPORTED_100baseT_Half
;
2735 if (ecmd
->duplex
== DUPLEX_FULL
)
2736 setting
= SUPPORTED_10baseT_Full
;
2737 else if (ecmd
->duplex
== DUPLEX_HALF
)
2738 setting
= SUPPORTED_10baseT_Half
;
2746 if ((setting
& supported
) == 0)
2749 sky2
->speed
= ecmd
->speed
;
2750 sky2
->duplex
= ecmd
->duplex
;
2753 sky2
->autoneg
= ecmd
->autoneg
;
2754 sky2
->advertising
= ecmd
->advertising
;
2756 if (netif_running(dev
))
2757 sky2_phy_reinit(sky2
);
2762 static void sky2_get_drvinfo(struct net_device
*dev
,
2763 struct ethtool_drvinfo
*info
)
2765 struct sky2_port
*sky2
= netdev_priv(dev
);
2767 strcpy(info
->driver
, DRV_NAME
);
2768 strcpy(info
->version
, DRV_VERSION
);
2769 strcpy(info
->fw_version
, "N/A");
2770 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2773 static const struct sky2_stat
{
2774 char name
[ETH_GSTRING_LEN
];
2777 { "tx_bytes", GM_TXO_OK_HI
},
2778 { "rx_bytes", GM_RXO_OK_HI
},
2779 { "tx_broadcast", GM_TXF_BC_OK
},
2780 { "rx_broadcast", GM_RXF_BC_OK
},
2781 { "tx_multicast", GM_TXF_MC_OK
},
2782 { "rx_multicast", GM_RXF_MC_OK
},
2783 { "tx_unicast", GM_TXF_UC_OK
},
2784 { "rx_unicast", GM_RXF_UC_OK
},
2785 { "tx_mac_pause", GM_TXF_MPAUSE
},
2786 { "rx_mac_pause", GM_RXF_MPAUSE
},
2787 { "collisions", GM_TXF_COL
},
2788 { "late_collision",GM_TXF_LAT_COL
},
2789 { "aborted", GM_TXF_ABO_COL
},
2790 { "single_collisions", GM_TXF_SNG_COL
},
2791 { "multi_collisions", GM_TXF_MUL_COL
},
2793 { "rx_short", GM_RXF_SHT
},
2794 { "rx_runt", GM_RXE_FRAG
},
2795 { "rx_64_byte_packets", GM_RXF_64B
},
2796 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2797 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2798 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2799 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2800 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2801 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2802 { "rx_too_long", GM_RXF_LNG_ERR
},
2803 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2804 { "rx_jabber", GM_RXF_JAB_PKT
},
2805 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2807 { "tx_64_byte_packets", GM_TXF_64B
},
2808 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2809 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2810 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2811 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2812 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2813 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2814 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2817 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2819 struct sky2_port
*sky2
= netdev_priv(dev
);
2821 return sky2
->rx_csum
;
2824 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2826 struct sky2_port
*sky2
= netdev_priv(dev
);
2828 sky2
->rx_csum
= data
;
2830 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2831 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2836 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2838 struct sky2_port
*sky2
= netdev_priv(netdev
);
2839 return sky2
->msg_enable
;
2842 static int sky2_nway_reset(struct net_device
*dev
)
2844 struct sky2_port
*sky2
= netdev_priv(dev
);
2846 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
2849 sky2_phy_reinit(sky2
);
2854 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2856 struct sky2_hw
*hw
= sky2
->hw
;
2857 unsigned port
= sky2
->port
;
2860 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2861 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2862 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2863 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2865 for (i
= 2; i
< count
; i
++)
2866 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2869 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2871 struct sky2_port
*sky2
= netdev_priv(netdev
);
2872 sky2
->msg_enable
= value
;
2875 static int sky2_get_stats_count(struct net_device
*dev
)
2877 return ARRAY_SIZE(sky2_stats
);
2880 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2881 struct ethtool_stats
*stats
, u64
* data
)
2883 struct sky2_port
*sky2
= netdev_priv(dev
);
2885 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2888 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2892 switch (stringset
) {
2894 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2895 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2896 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2901 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2903 struct sky2_port
*sky2
= netdev_priv(dev
);
2904 return &sky2
->net_stats
;
2907 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2909 struct sky2_port
*sky2
= netdev_priv(dev
);
2910 struct sky2_hw
*hw
= sky2
->hw
;
2911 unsigned port
= sky2
->port
;
2912 const struct sockaddr
*addr
= p
;
2914 if (!is_valid_ether_addr(addr
->sa_data
))
2915 return -EADDRNOTAVAIL
;
2917 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2918 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2919 dev
->dev_addr
, ETH_ALEN
);
2920 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2921 dev
->dev_addr
, ETH_ALEN
);
2923 /* virtual address for data */
2924 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2926 /* physical address: used for pause frames */
2927 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2932 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
2936 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
2937 filter
[bit
>> 3] |= 1 << (bit
& 7);
2940 static void sky2_set_multicast(struct net_device
*dev
)
2942 struct sky2_port
*sky2
= netdev_priv(dev
);
2943 struct sky2_hw
*hw
= sky2
->hw
;
2944 unsigned port
= sky2
->port
;
2945 struct dev_mc_list
*list
= dev
->mc_list
;
2949 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2951 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
2952 memset(filter
, 0, sizeof(filter
));
2954 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2955 reg
|= GM_RXCR_UCF_ENA
;
2957 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2958 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2959 else if (dev
->flags
& IFF_ALLMULTI
)
2960 memset(filter
, 0xff, sizeof(filter
));
2961 else if (dev
->mc_count
== 0 && !rx_pause
)
2962 reg
&= ~GM_RXCR_MCF_ENA
;
2965 reg
|= GM_RXCR_MCF_ENA
;
2968 sky2_add_filter(filter
, pause_mc_addr
);
2970 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
2971 sky2_add_filter(filter
, list
->dmi_addr
);
2974 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2975 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2976 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2977 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2978 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2979 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2980 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2981 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2983 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2986 /* Can have one global because blinking is controlled by
2987 * ethtool and that is always under RTNL mutex
2989 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2993 switch (hw
->chip_id
) {
2994 case CHIP_ID_YUKON_XL
:
2995 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2996 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2997 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2998 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2999 PHY_M_LEDC_INIT_CTRL(7) |
3000 PHY_M_LEDC_STA1_CTRL(7) |
3001 PHY_M_LEDC_STA0_CTRL(7))
3004 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3008 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
3009 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3010 on
? PHY_M_LED_ALL
: 0);
3014 /* blink LED's for finding board */
3015 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3017 struct sky2_port
*sky2
= netdev_priv(dev
);
3018 struct sky2_hw
*hw
= sky2
->hw
;
3019 unsigned port
= sky2
->port
;
3020 u16 ledctrl
, ledover
= 0;
3025 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
3026 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
3030 /* save initial values */
3031 spin_lock_bh(&sky2
->phy_lock
);
3032 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3033 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3034 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3035 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
3036 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3038 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
3039 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
3043 while (!interrupted
&& ms
> 0) {
3044 sky2_led(hw
, port
, onoff
);
3047 spin_unlock_bh(&sky2
->phy_lock
);
3048 interrupted
= msleep_interruptible(250);
3049 spin_lock_bh(&sky2
->phy_lock
);
3054 /* resume regularly scheduled programming */
3055 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
3056 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3057 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3058 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
3059 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3061 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
3062 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
3064 spin_unlock_bh(&sky2
->phy_lock
);
3069 static void sky2_get_pauseparam(struct net_device
*dev
,
3070 struct ethtool_pauseparam
*ecmd
)
3072 struct sky2_port
*sky2
= netdev_priv(dev
);
3074 switch (sky2
->flow_mode
) {
3076 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3079 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3082 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3085 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3088 ecmd
->autoneg
= sky2
->autoneg
;
3091 static int sky2_set_pauseparam(struct net_device
*dev
,
3092 struct ethtool_pauseparam
*ecmd
)
3094 struct sky2_port
*sky2
= netdev_priv(dev
);
3096 sky2
->autoneg
= ecmd
->autoneg
;
3097 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3099 if (netif_running(dev
))
3100 sky2_phy_reinit(sky2
);
3105 static int sky2_get_coalesce(struct net_device
*dev
,
3106 struct ethtool_coalesce
*ecmd
)
3108 struct sky2_port
*sky2
= netdev_priv(dev
);
3109 struct sky2_hw
*hw
= sky2
->hw
;
3111 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3112 ecmd
->tx_coalesce_usecs
= 0;
3114 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3115 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3117 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3119 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3120 ecmd
->rx_coalesce_usecs
= 0;
3122 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3123 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3125 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3127 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3128 ecmd
->rx_coalesce_usecs_irq
= 0;
3130 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3131 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3134 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3139 /* Note: this affect both ports */
3140 static int sky2_set_coalesce(struct net_device
*dev
,
3141 struct ethtool_coalesce
*ecmd
)
3143 struct sky2_port
*sky2
= netdev_priv(dev
);
3144 struct sky2_hw
*hw
= sky2
->hw
;
3145 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3147 if (ecmd
->tx_coalesce_usecs
> tmax
||
3148 ecmd
->rx_coalesce_usecs
> tmax
||
3149 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3152 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3154 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3156 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3159 if (ecmd
->tx_coalesce_usecs
== 0)
3160 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3162 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3163 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3164 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3166 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3168 if (ecmd
->rx_coalesce_usecs
== 0)
3169 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3171 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3172 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3173 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3175 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3177 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3178 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3180 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3181 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3182 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3184 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3188 static void sky2_get_ringparam(struct net_device
*dev
,
3189 struct ethtool_ringparam
*ering
)
3191 struct sky2_port
*sky2
= netdev_priv(dev
);
3193 ering
->rx_max_pending
= RX_MAX_PENDING
;
3194 ering
->rx_mini_max_pending
= 0;
3195 ering
->rx_jumbo_max_pending
= 0;
3196 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3198 ering
->rx_pending
= sky2
->rx_pending
;
3199 ering
->rx_mini_pending
= 0;
3200 ering
->rx_jumbo_pending
= 0;
3201 ering
->tx_pending
= sky2
->tx_pending
;
3204 static int sky2_set_ringparam(struct net_device
*dev
,
3205 struct ethtool_ringparam
*ering
)
3207 struct sky2_port
*sky2
= netdev_priv(dev
);
3210 if (ering
->rx_pending
> RX_MAX_PENDING
||
3211 ering
->rx_pending
< 8 ||
3212 ering
->tx_pending
< MAX_SKB_TX_LE
||
3213 ering
->tx_pending
> TX_RING_SIZE
- 1)
3216 if (netif_running(dev
))
3219 sky2
->rx_pending
= ering
->rx_pending
;
3220 sky2
->tx_pending
= ering
->tx_pending
;
3222 if (netif_running(dev
)) {
3227 sky2_set_multicast(dev
);
3233 static int sky2_get_regs_len(struct net_device
*dev
)
3239 * Returns copy of control register region
3240 * Note: access to the RAM address register set will cause timeouts.
3242 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3245 const struct sky2_port
*sky2
= netdev_priv(dev
);
3246 const void __iomem
*io
= sky2
->hw
->regs
;
3248 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3250 memset(p
, 0, regs
->len
);
3252 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3254 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3256 regs
->len
- B3_RI_WTO_R1
);
3259 static const struct ethtool_ops sky2_ethtool_ops
= {
3260 .get_settings
= sky2_get_settings
,
3261 .set_settings
= sky2_set_settings
,
3262 .get_drvinfo
= sky2_get_drvinfo
,
3263 .get_wol
= sky2_get_wol
,
3264 .set_wol
= sky2_set_wol
,
3265 .get_msglevel
= sky2_get_msglevel
,
3266 .set_msglevel
= sky2_set_msglevel
,
3267 .nway_reset
= sky2_nway_reset
,
3268 .get_regs_len
= sky2_get_regs_len
,
3269 .get_regs
= sky2_get_regs
,
3270 .get_link
= ethtool_op_get_link
,
3271 .get_sg
= ethtool_op_get_sg
,
3272 .set_sg
= ethtool_op_set_sg
,
3273 .get_tx_csum
= ethtool_op_get_tx_csum
,
3274 .set_tx_csum
= ethtool_op_set_tx_csum
,
3275 .get_tso
= ethtool_op_get_tso
,
3276 .set_tso
= ethtool_op_set_tso
,
3277 .get_rx_csum
= sky2_get_rx_csum
,
3278 .set_rx_csum
= sky2_set_rx_csum
,
3279 .get_strings
= sky2_get_strings
,
3280 .get_coalesce
= sky2_get_coalesce
,
3281 .set_coalesce
= sky2_set_coalesce
,
3282 .get_ringparam
= sky2_get_ringparam
,
3283 .set_ringparam
= sky2_set_ringparam
,
3284 .get_pauseparam
= sky2_get_pauseparam
,
3285 .set_pauseparam
= sky2_set_pauseparam
,
3286 .phys_id
= sky2_phys_id
,
3287 .get_stats_count
= sky2_get_stats_count
,
3288 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3289 .get_perm_addr
= ethtool_op_get_perm_addr
,
3292 /* Initialize network device */
3293 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3295 int highmem
, int wol
)
3297 struct sky2_port
*sky2
;
3298 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3301 printk(KERN_ERR
"sky2 etherdev alloc failed");
3305 SET_MODULE_OWNER(dev
);
3306 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3307 dev
->irq
= hw
->pdev
->irq
;
3308 dev
->open
= sky2_up
;
3309 dev
->stop
= sky2_down
;
3310 dev
->do_ioctl
= sky2_ioctl
;
3311 dev
->hard_start_xmit
= sky2_xmit_frame
;
3312 dev
->get_stats
= sky2_get_stats
;
3313 dev
->set_multicast_list
= sky2_set_multicast
;
3314 dev
->set_mac_address
= sky2_set_mac_address
;
3315 dev
->change_mtu
= sky2_change_mtu
;
3316 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3317 dev
->tx_timeout
= sky2_tx_timeout
;
3318 dev
->watchdog_timeo
= TX_WATCHDOG
;
3320 dev
->poll
= sky2_poll
;
3321 dev
->weight
= NAPI_WEIGHT
;
3322 #ifdef CONFIG_NET_POLL_CONTROLLER
3323 /* Network console (only works on port 0)
3324 * because netpoll makes assumptions about NAPI
3327 dev
->poll_controller
= sky2_netpoll
;
3330 sky2
= netdev_priv(dev
);
3333 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3335 /* Auto speed and flow control */
3336 sky2
->autoneg
= AUTONEG_ENABLE
;
3337 sky2
->flow_mode
= FC_BOTH
;
3341 sky2
->advertising
= sky2_supported_modes(hw
);
3345 spin_lock_init(&sky2
->phy_lock
);
3346 sky2
->tx_pending
= TX_DEF_PENDING
;
3347 sky2
->rx_pending
= RX_DEF_PENDING
;
3349 hw
->dev
[port
] = dev
;
3353 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3354 dev
->features
|= NETIF_F_TSO
;
3356 dev
->features
|= NETIF_F_HIGHDMA
;
3357 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3359 #ifdef SKY2_VLAN_TAG_USED
3360 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3361 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3362 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3365 /* read the mac address */
3366 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3367 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3369 /* device is off until link detection */
3370 netif_carrier_off(dev
);
3371 netif_stop_queue(dev
);
3376 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3378 const struct sky2_port
*sky2
= netdev_priv(dev
);
3380 if (netif_msg_probe(sky2
))
3381 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3383 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3384 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3387 /* Handle software interrupt used during MSI test */
3388 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3390 struct sky2_hw
*hw
= dev_id
;
3391 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3396 if (status
& Y2_IS_IRQ_SW
) {
3398 wake_up(&hw
->msi_wait
);
3399 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3401 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3406 /* Test interrupt path by forcing a a software IRQ */
3407 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3409 struct pci_dev
*pdev
= hw
->pdev
;
3412 init_waitqueue_head (&hw
->msi_wait
);
3414 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3416 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
3418 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3419 pci_name(pdev
), pdev
->irq
);
3423 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3424 sky2_read8(hw
, B0_CTST
);
3426 wait_event_timeout(hw
->msi_wait
, hw
->msi
, HZ
/10);
3429 /* MSI test failed, go back to INTx mode */
3430 printk(KERN_INFO PFX
"%s: No interrupt generated using MSI, "
3431 "switching to INTx mode.\n",
3435 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3438 sky2_write32(hw
, B0_IMSK
, 0);
3439 sky2_read32(hw
, B0_IMSK
);
3441 free_irq(pdev
->irq
, hw
);
3446 static int __devinit
pci_wake_enabled(struct pci_dev
*dev
)
3448 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3453 if (pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
))
3455 return value
& PCI_PM_CTRL_PME_ENABLE
;
3458 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3459 const struct pci_device_id
*ent
)
3461 struct net_device
*dev
;
3463 int err
, using_dac
= 0, wol_default
;
3465 err
= pci_enable_device(pdev
);
3467 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3472 err
= pci_request_regions(pdev
, DRV_NAME
);
3474 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3479 pci_set_master(pdev
);
3481 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3482 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3484 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3486 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3487 "for consistent allocations\n", pci_name(pdev
));
3488 goto err_out_free_regions
;
3492 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3494 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3496 goto err_out_free_regions
;
3500 wol_default
= pci_wake_enabled(pdev
) ? WAKE_MAGIC
: 0;
3503 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3505 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3507 goto err_out_free_regions
;
3512 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3514 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3516 goto err_out_free_hw
;
3520 /* The sk98lin vendor driver uses hardware byte swapping but
3521 * this driver uses software swapping.
3525 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3526 reg
&= ~PCI_REV_DESC
;
3527 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3531 /* ring for status responses */
3532 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3535 goto err_out_iounmap
;
3537 err
= sky2_init(hw
);
3539 goto err_out_iounmap
;
3541 printk(KERN_INFO PFX
"v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3542 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3543 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3544 hw
->chip_id
, hw
->chip_rev
);
3548 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
3551 goto err_out_free_pci
;
3554 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3555 err
= sky2_test_msi(hw
);
3556 if (err
== -EOPNOTSUPP
)
3557 pci_disable_msi(pdev
);
3559 goto err_out_free_netdev
;
3562 err
= register_netdev(dev
);
3564 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3566 goto err_out_free_netdev
;
3569 err
= request_irq(pdev
->irq
, sky2_intr
, hw
->msi
? 0 : IRQF_SHARED
,
3572 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3573 pci_name(pdev
), pdev
->irq
);
3574 goto err_out_unregister
;
3576 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3578 sky2_show_addr(dev
);
3580 if (hw
->ports
> 1) {
3581 struct net_device
*dev1
;
3583 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
3585 printk(KERN_WARNING PFX
3586 "allocation of second port failed\n");
3588 else if (!(err
= register_netdev(dev1
)))
3589 sky2_show_addr(dev1
);
3591 printk(KERN_WARNING PFX
3592 "register of second port failed (%d)\n", err
);
3598 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3599 sky2_idle_start(hw
);
3601 pci_set_drvdata(pdev
, hw
);
3607 pci_disable_msi(pdev
);
3608 unregister_netdev(dev
);
3609 err_out_free_netdev
:
3612 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3613 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3618 err_out_free_regions
:
3619 pci_release_regions(pdev
);
3620 pci_disable_device(pdev
);
3625 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3627 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3628 struct net_device
*dev0
, *dev1
;
3633 del_timer_sync(&hw
->idle_timer
);
3635 sky2_write32(hw
, B0_IMSK
, 0);
3636 synchronize_irq(hw
->pdev
->irq
);
3641 unregister_netdev(dev1
);
3642 unregister_netdev(dev0
);
3646 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3647 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3648 sky2_read8(hw
, B0_CTST
);
3650 free_irq(pdev
->irq
, hw
);
3652 pci_disable_msi(pdev
);
3653 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3654 pci_release_regions(pdev
);
3655 pci_disable_device(pdev
);
3663 pci_set_drvdata(pdev
, NULL
);
3667 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3669 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3672 del_timer_sync(&hw
->idle_timer
);
3673 netif_poll_disable(hw
->dev
[0]);
3675 for (i
= 0; i
< hw
->ports
; i
++) {
3676 struct net_device
*dev
= hw
->dev
[i
];
3677 struct sky2_port
*sky2
= netdev_priv(dev
);
3679 if (netif_running(dev
))
3683 sky2_wol_init(sky2
);
3688 sky2_write32(hw
, B0_IMSK
, 0);
3691 pci_save_state(pdev
);
3692 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3693 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3698 static int sky2_resume(struct pci_dev
*pdev
)
3700 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3703 err
= pci_set_power_state(pdev
, PCI_D0
);
3707 err
= pci_restore_state(pdev
);
3711 pci_enable_wake(pdev
, PCI_D0
, 0);
3714 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3716 for (i
= 0; i
< hw
->ports
; i
++) {
3717 struct net_device
*dev
= hw
->dev
[i
];
3718 if (netif_running(dev
)) {
3721 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3729 netif_poll_enable(hw
->dev
[0]);
3730 sky2_idle_start(hw
);
3733 printk(KERN_ERR PFX
"%s: resume failed (%d)\n", pci_name(pdev
), err
);
3734 pci_disable_device(pdev
);
3739 static void sky2_shutdown(struct pci_dev
*pdev
)
3741 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3744 del_timer_sync(&hw
->idle_timer
);
3745 netif_poll_disable(hw
->dev
[0]);
3747 for (i
= 0; i
< hw
->ports
; i
++) {
3748 struct net_device
*dev
= hw
->dev
[i
];
3749 struct sky2_port
*sky2
= netdev_priv(dev
);
3753 sky2_wol_init(sky2
);
3760 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
3761 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
3763 pci_disable_device(pdev
);
3764 pci_set_power_state(pdev
, PCI_D3hot
);
3768 static struct pci_driver sky2_driver
= {
3770 .id_table
= sky2_id_table
,
3771 .probe
= sky2_probe
,
3772 .remove
= __devexit_p(sky2_remove
),
3774 .suspend
= sky2_suspend
,
3775 .resume
= sky2_resume
,
3777 .shutdown
= sky2_shutdown
,
3780 static int __init
sky2_init_module(void)
3782 return pci_register_driver(&sky2_driver
);
3785 static void __exit
sky2_cleanup_module(void)
3787 pci_unregister_driver(&sky2_driver
);
3790 module_init(sky2_init_module
);
3791 module_exit(sky2_cleanup_module
);
3793 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3794 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3795 MODULE_LICENSE("GPL");
3796 MODULE_VERSION(DRV_VERSION
);