drivers/scsi/qla4xxx/ql4_fw.h

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7
   8 #ifndef _QLA4X_FW_H
   9 #define _QLA4X_FW_H
  10
  11
  12 #define MAX_PRST_DEV_DB_ENTRIES         64
  13 #define MIN_DISC_DEV_DB_ENTRY           MAX_PRST_DEV_DB_ENTRIES
  14 #define MAX_DEV_DB_ENTRIES 512
  15
  16 /*************************************************************************
  17  *
  18  *              ISP 4010 I/O Register Set Structure and Definitions
  19  *
  20  *************************************************************************/
  21
  22 struct port_ctrl_stat_regs {
  23         __le32 ext_hw_conf;     /*  80 x50  R/W */
  24         __le32 intChipConfiguration; /*  84 x54 */
  25         __le32 port_ctrl;       /*  88 x58 */
  26         __le32 port_status;     /*  92 x5c */
  27         __le32 HostPrimMACHi;   /*  96 x60 */
  28         __le32 HostPrimMACLow;  /* 100 x64 */
  29         __le32 HostSecMACHi;    /* 104 x68 */
  30         __le32 HostSecMACLow;   /* 108 x6c */
  31         __le32 EPPrimMACHi;     /* 112 x70 */
  32         __le32 EPPrimMACLow;    /* 116 x74 */
  33         __le32 EPSecMACHi;      /* 120 x78 */
  34         __le32 EPSecMACLow;     /* 124 x7c */
  35         __le32 HostPrimIPHi;    /* 128 x80 */
  36         __le32 HostPrimIPMidHi; /* 132 x84 */
  37         __le32 HostPrimIPMidLow;        /* 136 x88 */
  38         __le32 HostPrimIPLow;   /* 140 x8c */
  39         __le32 HostSecIPHi;     /* 144 x90 */
  40         __le32 HostSecIPMidHi;  /* 148 x94 */
  41         __le32 HostSecIPMidLow; /* 152 x98 */
  42         __le32 HostSecIPLow;    /* 156 x9c */
  43         __le32 EPPrimIPHi;      /* 160 xa0 */
  44         __le32 EPPrimIPMidHi;   /* 164 xa4 */
  45         __le32 EPPrimIPMidLow;  /* 168 xa8 */
  46         __le32 EPPrimIPLow;     /* 172 xac */
  47         __le32 EPSecIPHi;       /* 176 xb0 */
  48         __le32 EPSecIPMidHi;    /* 180 xb4 */
  49         __le32 EPSecIPMidLow;   /* 184 xb8 */
  50         __le32 EPSecIPLow;      /* 188 xbc */
  51         __le32 IPReassemblyTimeout; /* 192 xc0 */
  52         __le32 EthMaxFramePayload; /* 196 xc4 */
  53         __le32 TCPMaxWindowSize; /* 200 xc8 */
  54         __le32 TCPCurrentTimestampHi; /* 204 xcc */
  55         __le32 TCPCurrentTimestampLow; /* 208 xd0 */
  56         __le32 LocalRAMAddress; /* 212 xd4 */
  57         __le32 LocalRAMData;    /* 216 xd8 */
  58         __le32 PCSReserved1;    /* 220 xdc */
  59         __le32 gp_out;          /* 224 xe0 */
  60         __le32 gp_in;           /* 228 xe4 */
  61         __le32 ProbeMuxAddr;    /* 232 xe8 */
  62         __le32 ProbeMuxData;    /* 236 xec */
  63         __le32 ERMQueueBaseAddr0; /* 240 xf0 */
  64         __le32 ERMQueueBaseAddr1; /* 244 xf4 */
  65         __le32 MACConfiguration; /* 248 xf8 */
  66         __le32 port_err_status; /* 252 xfc  COR */
  67 };
  68
  69 struct host_mem_cfg_regs {
  70         __le32 NetRequestQueueOut; /*  80 x50 */
  71         __le32 NetRequestQueueOutAddrHi; /*  84 x54 */
  72         __le32 NetRequestQueueOutAddrLow; /*  88 x58 */
  73         __le32 NetRequestQueueBaseAddrHi; /*  92 x5c */
  74         __le32 NetRequestQueueBaseAddrLow; /*  96 x60 */
  75         __le32 NetRequestQueueLength; /* 100 x64 */
  76         __le32 NetResponseQueueIn; /* 104 x68 */
  77         __le32 NetResponseQueueInAddrHi; /* 108 x6c */
  78         __le32 NetResponseQueueInAddrLow; /* 112 x70 */
  79         __le32 NetResponseQueueBaseAddrHi; /* 116 x74 */
  80         __le32 NetResponseQueueBaseAddrLow; /* 120 x78 */
  81         __le32 NetResponseQueueLength; /* 124 x7c */
  82         __le32 req_q_out;       /* 128 x80 */
  83         __le32 RequestQueueOutAddrHi; /* 132 x84 */
  84         __le32 RequestQueueOutAddrLow; /* 136 x88 */
  85         __le32 RequestQueueBaseAddrHi; /* 140 x8c */
  86         __le32 RequestQueueBaseAddrLow; /* 144 x90 */
  87         __le32 RequestQueueLength; /* 148 x94 */
  88         __le32 ResponseQueueIn; /* 152 x98 */
  89         __le32 ResponseQueueInAddrHi; /* 156 x9c */
  90         __le32 ResponseQueueInAddrLow; /* 160 xa0 */
  91         __le32 ResponseQueueBaseAddrHi; /* 164 xa4 */
  92         __le32 ResponseQueueBaseAddrLow; /* 168 xa8 */
  93         __le32 ResponseQueueLength; /* 172 xac */
  94         __le32 NetRxLargeBufferQueueOut; /* 176 xb0 */
  95         __le32 NetRxLargeBufferQueueBaseAddrHi; /* 180 xb4 */
  96         __le32 NetRxLargeBufferQueueBaseAddrLow; /* 184 xb8 */
  97         __le32 NetRxLargeBufferQueueLength; /* 188 xbc */
  98         __le32 NetRxLargeBufferLength; /* 192 xc0 */
  99         __le32 NetRxSmallBufferQueueOut; /* 196 xc4 */
 100         __le32 NetRxSmallBufferQueueBaseAddrHi; /* 200 xc8 */
 101         __le32 NetRxSmallBufferQueueBaseAddrLow; /* 204 xcc */
 102         __le32 NetRxSmallBufferQueueLength; /* 208 xd0 */
 103         __le32 NetRxSmallBufferLength; /* 212 xd4 */
 104         __le32 HMCReserved0[10]; /* 216 xd8 */
 105 };
 106
 107 struct local_ram_cfg_regs {
 108         __le32 BufletSize;      /*  80 x50 */
 109         __le32 BufletMaxCount;  /*  84 x54 */
 110         __le32 BufletCurrCount; /*  88 x58 */
 111         __le32 BufletPauseThresholdCount; /*  92 x5c */
 112         __le32 BufletTCPWinThresholdHi; /*  96 x60 */
 113         __le32 BufletTCPWinThresholdLow; /* 100 x64 */
 114         __le32 IPHashTableBaseAddr; /* 104 x68 */
 115         __le32 IPHashTableSize; /* 108 x6c */
 116         __le32 TCPHashTableBaseAddr; /* 112 x70 */
 117         __le32 TCPHashTableSize; /* 116 x74 */
 118         __le32 NCBAreaBaseAddr; /* 120 x78 */
 119         __le32 NCBMaxCount;     /* 124 x7c */
 120         __le32 NCBCurrCount;    /* 128 x80 */
 121         __le32 DRBAreaBaseAddr; /* 132 x84 */
 122         __le32 DRBMaxCount;     /* 136 x88 */
 123         __le32 DRBCurrCount;    /* 140 x8c */
 124         __le32 LRCReserved[28]; /* 144 x90 */
 125 };
 126
 127 struct prot_stat_regs {
 128         __le32 MACTxFrameCount; /*  80 x50   R */
 129         __le32 MACTxByteCount;  /*  84 x54   R */
 130         __le32 MACRxFrameCount; /*  88 x58   R */
 131         __le32 MACRxByteCount;  /*  92 x5c   R */
 132         __le32 MACCRCErrCount;  /*  96 x60   R */
 133         __le32 MACEncErrCount;  /* 100 x64   R */
 134         __le32 MACRxLengthErrCount; /* 104 x68   R */
 135         __le32 IPTxPacketCount; /* 108 x6c   R */
 136         __le32 IPTxByteCount;   /* 112 x70   R */
 137         __le32 IPTxFragmentCount; /* 116 x74   R */
 138         __le32 IPRxPacketCount; /* 120 x78   R */
 139         __le32 IPRxByteCount;   /* 124 x7c   R */
 140         __le32 IPRxFragmentCount; /* 128 x80   R */
 141         __le32 IPDatagramReassemblyCount; /* 132 x84   R */
 142         __le32 IPV6RxPacketCount; /* 136 x88   R */
 143         __le32 IPErrPacketCount; /* 140 x8c   R */
 144         __le32 IPReassemblyErrCount; /* 144 x90   R */
 145         __le32 TCPTxSegmentCount; /* 148 x94   R */
 146         __le32 TCPTxByteCount;  /* 152 x98   R */
 147         __le32 TCPRxSegmentCount; /* 156 x9c   R */
 148         __le32 TCPRxByteCount;  /* 160 xa0   R */
 149         __le32 TCPTimerExpCount; /* 164 xa4   R */
 150         __le32 TCPRxAckCount;   /* 168 xa8   R */
 151         __le32 TCPTxAckCount;   /* 172 xac   R */
 152         __le32 TCPRxErrOOOCount; /* 176 xb0   R */
 153         __le32 PSReserved0;     /* 180 xb4 */
 154         __le32 TCPRxWindowProbeUpdateCount; /* 184 xb8   R */
 155         __le32 ECCErrCorrectionCount; /* 188 xbc   R */
 156         __le32 PSReserved1[16]; /* 192 xc0 */
 157 };
 158
 159
 160 /*  remote register set (access via PCI memory read/write) */
 161 struct isp_reg {
 162 #define MBOX_REG_COUNT 8
 163         __le32 mailbox[MBOX_REG_COUNT];
 164
 165         __le32 flash_address;   /* 0x20 */
 166         __le32 flash_data;
 167         __le32 ctrl_status;
 168
 169         union {
 170                 struct {
 171                         __le32 nvram;
 172                         __le32 reserved1[2]; /* 0x30 */
 173                 } __attribute__ ((packed)) isp4010;
 174                 struct {
 175                         __le32 intr_mask;
 176                         __le32 nvram; /* 0x30 */
 177                         __le32 semaphore;
 178                 } __attribute__ ((packed)) isp4022;
 179         } u1;
 180
 181         __le32 req_q_in;    /* SCSI Request Queue Producer Index */
 182         __le32 rsp_q_out;   /* SCSI Completion Queue Consumer Index */
 183
 184         __le32 reserved2[4];    /* 0x40 */
 185
 186         union {
 187                 struct {
 188                         __le32 ext_hw_conf; /* 0x50 */
 189                         __le32 flow_ctrl;
 190                         __le32 port_ctrl;
 191                         __le32 port_status;
 192
 193                         __le32 reserved3[8]; /* 0x60 */
 194
 195                         __le32 req_q_out; /* 0x80 */
 196
 197                         __le32 reserved4[23]; /* 0x84 */
 198
 199                         __le32 gp_out; /* 0xe0 */
 200                         __le32 gp_in;
 201
 202                         __le32 reserved5[5];
 203
 204                         __le32 port_err_status; /* 0xfc */
 205                 } __attribute__ ((packed)) isp4010;
 206                 struct {
 207                         union {
 208                                 struct port_ctrl_stat_regs p0;
 209                                 struct host_mem_cfg_regs p1;
 210                                 struct local_ram_cfg_regs p2;
 211                                 struct prot_stat_regs p3;
 212                                 __le32 r_union[44];
 213                         };
 214
 215                 } __attribute__ ((packed)) isp4022;
 216         } u2;
 217 };                              /* 256 x100 */
 218
 219
 220 /* Semaphore Defines for 4010 */
 221 #define QL4010_DRVR_SEM_BITS    0x00000030
 222 #define QL4010_GPIO_SEM_BITS    0x000000c0
 223 #define QL4010_SDRAM_SEM_BITS   0x00000300
 224 #define QL4010_PHY_SEM_BITS     0x00000c00
 225 #define QL4010_NVRAM_SEM_BITS   0x00003000
 226 #define QL4010_FLASH_SEM_BITS   0x0000c000
 227
 228 #define QL4010_DRVR_SEM_MASK    0x00300000
 229 #define QL4010_GPIO_SEM_MASK    0x00c00000
 230 #define QL4010_SDRAM_SEM_MASK   0x03000000
 231 #define QL4010_PHY_SEM_MASK     0x0c000000
 232 #define QL4010_NVRAM_SEM_MASK   0x30000000
 233 #define QL4010_FLASH_SEM_MASK   0xc0000000
 234
 235 /* Semaphore Defines for 4022 */
 236 #define QL4022_RESOURCE_MASK_BASE_CODE 0x7
 237 #define QL4022_RESOURCE_BITS_BASE_CODE 0x4
 238
 239
 240 #define QL4022_DRVR_SEM_MASK    (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
 241 #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
 242 #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
 243 #define QL4022_NVRAM_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
 244 #define QL4022_FLASH_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
 245
 246
 247
 248 /* Page # defines for 4022 */
 249 #define PORT_CTRL_STAT_PAGE                     0       /* 4022 */
 250 #define HOST_MEM_CFG_PAGE                       1       /* 4022 */
 251 #define LOCAL_RAM_CFG_PAGE                      2       /* 4022 */
 252 #define PROT_STAT_PAGE                          3       /* 4022 */
 253
 254 /* Register Mask - sets corresponding mask bits in the upper word */
 255 static inline uint32_t set_rmask(uint32_t val)
 256 {
 257         return (val & 0xffff) | (val << 16);
 258 }
 259
 260
 261 static inline uint32_t clr_rmask(uint32_t val)
 262 {
 263         return 0 | (val << 16);
 264 }
 265
 266 /*  ctrl_status definitions */
 267 #define CSR_SCSI_PAGE_SELECT                    0x00000003
 268 #define CSR_SCSI_INTR_ENABLE                    0x00000004      /* 4010 */
 269 #define CSR_SCSI_RESET_INTR                     0x00000008
 270 #define CSR_SCSI_COMPLETION_INTR                0x00000010
 271 #define CSR_SCSI_PROCESSOR_INTR                 0x00000020
 272 #define CSR_INTR_RISC                           0x00000040
 273 #define CSR_BOOT_ENABLE                         0x00000080
 274 #define CSR_NET_PAGE_SELECT                     0x00000300      /* 4010 */
 275 #define CSR_FUNC_NUM                            0x00000700      /* 4022 */
 276 #define CSR_NET_RESET_INTR                      0x00000800      /* 4010 */
 277 #define CSR_FORCE_SOFT_RESET                    0x00002000      /* 4022 */
 278 #define CSR_FATAL_ERROR                         0x00004000
 279 #define CSR_SOFT_RESET                          0x00008000
 280 #define ISP_CONTROL_FN_MASK                     CSR_FUNC_NUM
 281 #define ISP_CONTROL_FN0_SCSI                    0x0500
 282 #define ISP_CONTROL_FN1_SCSI                    0x0700
 283
 284 #define INTR_PENDING                            (CSR_SCSI_COMPLETION_INTR |\
 285                                                  CSR_SCSI_PROCESSOR_INTR |\
 286                                                  CSR_SCSI_RESET_INTR)
 287
 288 /* ISP InterruptMask definitions */
 289 #define IMR_SCSI_INTR_ENABLE                    0x00000004      /* 4022 */
 290
 291 /* ISP 4022 nvram definitions */
 292 #define NVR_WRITE_ENABLE                        0x00000010      /* 4022 */
 293
 294 /*  ISP port_status definitions */
 295
 296 /*  ISP Semaphore definitions */
 297
 298 /*  ISP General Purpose Output definitions */
 299
 300 /*  shadow registers (DMA'd from HA to system memory.  read only) */
 301 struct shadow_regs {
 302         /* SCSI Request Queue Consumer Index */
 303         __le32 req_q_out;       /*  0 x0   R */
 304
 305         /* SCSI Completion Queue Producer Index */
 306         __le32 rsp_q_in;        /*  4 x4   R */
 307 };                /*  8 x8 */
 308
 309
 310 /*  External hardware configuration register */
 311 union external_hw_config_reg {
 312         struct {
 313                 /* FIXME: Do we even need this?  All values are
 314                  * referred to by 16 bit quantities.  Platform and
 315                  * endianess issues. */
 316                 __le32 bReserved0:1;
 317                 __le32 bSDRAMProtectionMethod:2;
 318                 __le32 bSDRAMBanks:1;
 319                 __le32 bSDRAMChipWidth:1;
 320                 __le32 bSDRAMChipSize:2;
 321                 __le32 bParityDisable:1;
 322                 __le32 bExternalMemoryType:1;
 323                 __le32 bFlashBIOSWriteEnable:1;
 324                 __le32 bFlashUpperBankSelect:1;
 325                 __le32 bWriteBurst:2;
 326                 __le32 bReserved1:3;
 327                 __le32 bMask:16;
 328         };
 329         uint32_t Asuint32_t;
 330 };
 331
 332 /*************************************************************************
 333  *
 334  *              Mailbox Commands Structures and Definitions
 335  *
 336  *************************************************************************/
 337
 338 /*  Mailbox command definitions */
 339 #define MBOX_CMD_ABOUT_FW                       0x0009
 340 #define MBOX_CMD_LUN_RESET                      0x0016
 341 #define MBOX_CMD_GET_MANAGEMENT_DATA            0x001E
 342 #define MBOX_CMD_GET_FW_STATUS                  0x001F
 343 #define MBOX_CMD_SET_ISNS_SERVICE               0x0021
 344 #define ISNS_DISABLE                            0
 345 #define ISNS_ENABLE                             1
 346 #define MBOX_CMD_COPY_FLASH                     0x0024
 347 #define MBOX_CMD_WRITE_FLASH                    0x0025
 348 #define MBOX_CMD_READ_FLASH                     0x0026
 349 #define MBOX_CMD_CLEAR_DATABASE_ENTRY           0x0031
 350 #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT         0x0056
 351 #define LOGOUT_OPTION_CLOSE_SESSION             0x01
 352 #define LOGOUT_OPTION_RELOGIN                   0x02
 353 #define MBOX_CMD_EXECUTE_IOCB_A64               0x005A
 354 #define MBOX_CMD_INITIALIZE_FIRMWARE            0x0060
 355 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK         0x0061
 356 #define MBOX_CMD_REQUEST_DATABASE_ENTRY         0x0062
 357 #define MBOX_CMD_SET_DATABASE_ENTRY             0x0063
 358 #define MBOX_CMD_GET_DATABASE_ENTRY             0x0064
 359 #define DDB_DS_UNASSIGNED                       0x00
 360 #define DDB_DS_NO_CONNECTION_ACTIVE             0x01
 361 #define DDB_DS_SESSION_ACTIVE                   0x04
 362 #define DDB_DS_SESSION_FAILED                   0x06
 363 #define DDB_DS_LOGIN_IN_PROCESS                 0x07
 364 #define MBOX_CMD_GET_FW_STATE                   0x0069
 365 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
 366 #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS       0x0087
 367
 368 /* Mailbox 1 */
 369 #define FW_STATE_READY                          0x0000
 370 #define FW_STATE_CONFIG_WAIT                    0x0001
 371 #define FW_STATE_WAIT_LOGIN                     0x0002
 372 #define FW_STATE_ERROR                          0x0004
 373 #define FW_STATE_DHCP_IN_PROGRESS               0x0008
 374
 375 /* Mailbox 3 */
 376 #define FW_ADDSTATE_OPTICAL_MEDIA               0x0001
 377 #define FW_ADDSTATE_DHCP_ENABLED                0x0002
 378 #define FW_ADDSTATE_LINK_UP                     0x0010
 379 #define FW_ADDSTATE_ISNS_SVC_ENABLED            0x0020
 380 #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS    0x006B
 381 #define MBOX_CMD_CONN_OPEN_SESS_LOGIN           0x0074
 382 #define MBOX_CMD_GET_CRASH_RECORD               0x0076  /* 4010 only */
 383 #define MBOX_CMD_GET_CONN_EVENT_LOG             0x0077
 384
 385 /*  Mailbox status definitions */
 386 #define MBOX_COMPLETION_STATUS                  4
 387 #define MBOX_STS_BUSY                           0x0007
 388 #define MBOX_STS_INTERMEDIATE_COMPLETION        0x1000
 389 #define MBOX_STS_COMMAND_COMPLETE               0x4000
 390 #define MBOX_STS_COMMAND_ERROR                  0x4005
 391
 392 #define MBOX_ASYNC_EVENT_STATUS                 8
 393 #define MBOX_ASTS_SYSTEM_ERROR                  0x8002
 394 #define MBOX_ASTS_REQUEST_TRANSFER_ERROR        0x8003
 395 #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR       0x8004
 396 #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM      0x8005
 397 #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED     0x8006
 398 #define MBOX_ASTS_LINK_UP                       0x8010
 399 #define MBOX_ASTS_LINK_DOWN                     0x8011
 400 #define MBOX_ASTS_DATABASE_CHANGED              0x8014
 401 #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED      0x8015
 402 #define MBOX_ASTS_SELF_TEST_FAILED              0x8016
 403 #define MBOX_ASTS_LOGIN_FAILED                  0x8017
 404 #define MBOX_ASTS_DNS                           0x8018
 405 #define MBOX_ASTS_HEARTBEAT                     0x8019
 406 #define MBOX_ASTS_NVRAM_INVALID                 0x801A
 407 #define MBOX_ASTS_MAC_ADDRESS_CHANGED           0x801B
 408 #define MBOX_ASTS_IP_ADDRESS_CHANGED            0x801C
 409 #define MBOX_ASTS_DHCP_LEASE_EXPIRED            0x801D
 410 #define MBOX_ASTS_DHCP_LEASE_ACQUIRED           0x801F
 411 #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
 412 #define ISNS_EVENT_DATA_RECEIVED                0x0000
 413 #define ISNS_EVENT_CONNECTION_OPENED            0x0001
 414 #define ISNS_EVENT_CONNECTION_FAILED            0x0002
 415 #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR      0x8022
 416 #define MBOX_ASTS_SUBNET_STATE_CHANGE           0x8027
 417
 418 /*************************************************************************/
 419
 420 /* Host Adapter Initialization Control Block (from host) */
 421 struct init_fw_ctrl_blk {
 422         uint8_t Version;        /* 00 */
 423         uint8_t Control;        /* 01 */
 424
 425         uint16_t FwOptions;     /* 02-03 */
 426 #define  FWOPT_HEARTBEAT_ENABLE           0x1000
 427 #define  FWOPT_SESSION_MODE               0x0040
 428 #define  FWOPT_INITIATOR_MODE             0x0020
 429 #define  FWOPT_TARGET_MODE                0x0010
 430
 431         uint16_t ExecThrottle;  /* 04-05 */
 432         uint8_t RetryCount;     /* 06 */
 433         uint8_t RetryDelay;     /* 07 */
 434         uint16_t MaxEthFrPayloadSize;   /* 08-09 */
 435         uint16_t AddFwOptions;  /* 0A-0B */
 436
 437         uint8_t HeartbeatInterval;      /* 0C */
 438         uint8_t InstanceNumber; /* 0D */
 439         uint16_t RES2;          /* 0E-0F */
 440         uint16_t ReqQConsumerIndex;     /* 10-11 */
 441         uint16_t ComplQProducerIndex;   /* 12-13 */
 442         uint16_t ReqQLen;       /* 14-15 */
 443         uint16_t ComplQLen;     /* 16-17 */
 444         uint32_t ReqQAddrLo;    /* 18-1B */
 445         uint32_t ReqQAddrHi;    /* 1C-1F */
 446         uint32_t ComplQAddrLo;  /* 20-23 */
 447         uint32_t ComplQAddrHi;  /* 24-27 */
 448         uint32_t ShadowRegBufAddrLo;    /* 28-2B */
 449         uint32_t ShadowRegBufAddrHi;    /* 2C-2F */
 450
 451         uint16_t iSCSIOptions;  /* 30-31 */
 452
 453         uint16_t TCPOptions;    /* 32-33 */
 454
 455         uint16_t IPOptions;     /* 34-35 */
 456
 457         uint16_t MaxPDUSize;    /* 36-37 */
 458         uint16_t RcvMarkerInt;  /* 38-39 */
 459         uint16_t SndMarkerInt;  /* 3A-3B */
 460         uint16_t InitMarkerlessInt;     /* 3C-3D */
 461         uint16_t FirstBurstSize;        /* 3E-3F */
 462         uint16_t DefaultTime2Wait;      /* 40-41 */
 463         uint16_t DefaultTime2Retain;    /* 42-43 */
 464         uint16_t MaxOutStndngR2T;       /* 44-45 */
 465         uint16_t KeepAliveTimeout;      /* 46-47 */
 466         uint16_t PortNumber;    /* 48-49 */
 467         uint16_t MaxBurstSize;  /* 4A-4B */
 468         uint32_t RES4;          /* 4C-4F */
 469         uint8_t IPAddr[4];      /* 50-53 */
 470         uint8_t RES5[12];       /* 54-5F */
 471         uint8_t SubnetMask[4];  /* 60-63 */
 472         uint8_t RES6[12];       /* 64-6F */
 473         uint8_t GatewayIPAddr[4];       /* 70-73 */
 474         uint8_t RES7[12];       /* 74-7F */
 475         uint8_t PriDNSIPAddr[4];        /* 80-83 */
 476         uint8_t SecDNSIPAddr[4];        /* 84-87 */
 477         uint8_t RES8[8];        /* 88-8F */
 478         uint8_t Alias[32];      /* 90-AF */
 479         uint8_t TargAddr[8];    /* B0-B7 *//* /FIXME: Remove?? */
 480         uint8_t CHAPNameSecretsTable[8];        /* B8-BF */
 481         uint8_t EthernetMACAddr[6];     /* C0-C5 */
 482         uint16_t TargetPortalGroup;     /* C6-C7 */
 483         uint8_t SendScale;      /* C8    */
 484         uint8_t RecvScale;      /* C9    */
 485         uint8_t TypeOfService;  /* CA    */
 486         uint8_t Time2Live;      /* CB    */
 487         uint16_t VLANPriority;  /* CC-CD */
 488         uint16_t Reserved8;     /* CE-CF */
 489         uint8_t SecIPAddr[4];   /* D0-D3 */
 490         uint8_t Reserved9[12];  /* D4-DF */
 491         uint8_t iSNSIPAddr[4];  /* E0-E3 */
 492         uint16_t iSNSServerPortNumber;  /* E4-E5 */
 493         uint8_t Reserved10[10]; /* E6-EF */
 494         uint8_t SLPDAIPAddr[4]; /* F0-F3 */
 495         uint8_t Reserved11[12]; /* F4-FF */
 496         uint8_t iSCSINameString[256];   /* 100-1FF */
 497 };
 498
 499 /*************************************************************************/
 500
 501 struct dev_db_entry {
 502         uint8_t options;        /* 00 */
 503 #define DDB_OPT_DISC_SESSION  0x10
 504 #define DDB_OPT_TARGET        0x02 /* device is a target */
 505
 506         uint8_t control;        /* 01 */
 507
 508         uint16_t exeThrottle;   /* 02-03 */
 509         uint16_t exeCount;      /* 04-05 */
 510         uint8_t retryCount;     /* 06    */
 511         uint8_t retryDelay;     /* 07    */
 512         uint16_t iSCSIOptions;  /* 08-09 */
 513
 514         uint16_t TCPOptions;    /* 0A-0B */
 515
 516         uint16_t IPOptions;     /* 0C-0D */
 517
 518         uint16_t maxPDUSize;    /* 0E-0F */
 519         uint16_t rcvMarkerInt;  /* 10-11 */
 520         uint16_t sndMarkerInt;  /* 12-13 */
 521         uint16_t iSCSIMaxSndDataSegLen; /* 14-15 */
 522         uint16_t firstBurstSize;        /* 16-17 */
 523         uint16_t minTime2Wait;  /* 18-19 : RA :default_time2wait */
 524         uint16_t maxTime2Retain;        /* 1A-1B */
 525         uint16_t maxOutstndngR2T;       /* 1C-1D */
 526         uint16_t keepAliveTimeout;      /* 1E-1F */
 527         uint8_t ISID[6];        /* 20-25 big-endian, must be converted
 528                                  * to little-endian */
 529         uint16_t TSID;          /* 26-27 */
 530         uint16_t portNumber;    /* 28-29 */
 531         uint16_t maxBurstSize;  /* 2A-2B */
 532         uint16_t taskMngmntTimeout;     /* 2C-2D */
 533         uint16_t reserved1;     /* 2E-2F */
 534         uint8_t ipAddr[0x10];   /* 30-3F */
 535         uint8_t iSCSIAlias[0x20];       /* 40-5F */
 536         uint8_t targetAddr[0x20];       /* 60-7F */
 537         uint8_t userID[0x20];   /* 80-9F */
 538         uint8_t password[0x20]; /* A0-BF */
 539         uint8_t iscsiName[0x100];       /* C0-1BF : xxzzy Make this a
 540                                          * pointer to a string so we
 541                                          * don't have to reserve soooo
 542                                          * much RAM */
 543         uint16_t ddbLink;       /* 1C0-1C1 */
 544         uint16_t CHAPTableIndex; /* 1C2-1C3 */
 545         uint16_t TargetPortalGroup; /* 1C4-1C5 */
 546         uint16_t reserved2[2];  /* 1C6-1C7 */
 547         uint32_t statSN;        /* 1C8-1CB */
 548         uint32_t expStatSN;     /* 1CC-1CF */
 549         uint16_t reserved3[0x2C]; /* 1D0-1FB */
 550         uint16_t ddbValidCookie; /* 1FC-1FD */
 551         uint16_t ddbValidSize;  /* 1FE-1FF */
 552 };
 553
 554 /*************************************************************************/
 555
 556 /* Flash definitions */
 557
 558 #define FLASH_OFFSET_SYS_INFO   0x02000000
 559 #define FLASH_DEFAULTBLOCKSIZE  0x20000
 560 #define FLASH_EOF_OFFSET        (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
 561                                                             * for EOF
 562                                                             * signature */
 563
 564 struct sys_info_phys_addr {
 565         uint8_t address[6];     /* 00-05 */
 566         uint8_t filler[2];      /* 06-07 */
 567 };
 568
 569 struct flash_sys_info {
 570         uint32_t cookie;        /* 00-03 */
 571         uint32_t physAddrCount; /* 04-07 */
 572         struct sys_info_phys_addr physAddr[4]; /* 08-27 */
 573         uint8_t vendorId[128];  /* 28-A7 */
 574         uint8_t productId[128]; /* A8-127 */
 575         uint32_t serialNumber;  /* 128-12B */
 576
 577         /*  PCI Configuration values */
 578         uint32_t pciDeviceVendor;       /* 12C-12F */
 579         uint32_t pciDeviceId;   /* 130-133 */
 580         uint32_t pciSubsysVendor;       /* 134-137 */
 581         uint32_t pciSubsysId;   /* 138-13B */
 582
 583         /*  This validates version 1. */
 584         uint32_t crumbs;        /* 13C-13F */
 585
 586         uint32_t enterpriseNumber;      /* 140-143 */
 587
 588         uint32_t mtu;           /* 144-147 */
 589         uint32_t reserved0;     /* 148-14b */
 590         uint32_t crumbs2;       /* 14c-14f */
 591         uint8_t acSerialNumber[16];     /* 150-15f */
 592         uint32_t crumbs3;       /* 160-16f */
 593
 594         /* Leave this last in the struct so it is declared invalid if
 595          * any new items are added.
 596          */
 597         uint32_t reserved1[39]; /* 170-1ff */
 598 };      /* 200 */
 599
 600 struct crash_record {
 601         uint16_t fw_major_version;      /* 00 - 01 */
 602         uint16_t fw_minor_version;      /* 02 - 03 */
 603         uint16_t fw_patch_version;      /* 04 - 05 */
 604         uint16_t fw_build_version;      /* 06 - 07 */
 605
 606         uint8_t build_date[16]; /* 08 - 17 */
 607         uint8_t build_time[16]; /* 18 - 27 */
 608         uint8_t build_user[16]; /* 28 - 37 */
 609         uint8_t card_serial_num[16];    /* 38 - 47 */
 610
 611         uint32_t time_of_crash_in_secs; /* 48 - 4B */
 612         uint32_t time_of_crash_in_ms;   /* 4C - 4F */
 613
 614         uint16_t out_RISC_sd_num_frames;        /* 50 - 51 */
 615         uint16_t OAP_sd_num_words;      /* 52 - 53 */
 616         uint16_t IAP_sd_num_frames;     /* 54 - 55 */
 617         uint16_t in_RISC_sd_num_words;  /* 56 - 57 */
 618
 619         uint8_t reserved1[28];  /* 58 - 7F */
 620
 621         uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
 622         uint8_t in_RISC_reg_dump[256];  /*180 -27F */
 623         uint8_t in_out_RISC_stack_dump[0];      /*280 - ??? */
 624 };
 625
 626 struct conn_event_log_entry {
 627 #define MAX_CONN_EVENT_LOG_ENTRIES      100
 628         uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
 629         uint32_t timestamp_ms;  /* 04 - 07 milliseconds since boot */
 630         uint16_t device_index;  /* 08 - 09  */
 631         uint16_t fw_conn_state; /* 0A - 0B  */
 632         uint8_t event_type;     /* 0C - 0C  */
 633         uint8_t error_code;     /* 0D - 0D  */
 634         uint16_t error_code_detail;     /* 0E - 0F  */
 635         uint8_t num_consecutive_events; /* 10 - 10  */
 636         uint8_t rsvd[3];        /* 11 - 13  */
 637 };
 638
 639 /*************************************************************************
 640  *
 641  *                              IOCB Commands Structures and Definitions
 642  *
 643  *************************************************************************/
 644 #define IOCB_MAX_CDB_LEN            16  /* Bytes in a CBD */
 645 #define IOCB_MAX_SENSEDATA_LEN      32  /* Bytes of sense data */
 646
 647 /* IOCB header structure */
 648 struct qla4_header {
 649         uint8_t entryType;
 650 #define ET_STATUS                0x03
 651 #define ET_MARKER                0x04
 652 #define ET_CONT_T1               0x0A
 653 #define ET_STATUS_CONTINUATION   0x10
 654 #define ET_CMND_T3               0x19
 655 #define ET_PASSTHRU0             0x3A
 656 #define ET_PASSTHRU_STATUS       0x3C
 657
 658         uint8_t entryStatus;
 659         uint8_t systemDefined;
 660         uint8_t entryCount;
 661
 662         /* SyetemDefined definition */
 663 };
 664
 665 /* Generic queue entry structure*/
 666 struct queue_entry {
 667         uint8_t data[60];
 668         uint32_t signature;
 669
 670 };
 671
 672 /* 64 bit addressing segment counts*/
 673
 674 #define COMMAND_SEG_A64   1
 675 #define CONTINUE_SEG_A64  5
 676
 677 /* 64 bit addressing segment definition*/
 678
 679 struct data_seg_a64 {
 680         struct {
 681                 uint32_t addrLow;
 682                 uint32_t addrHigh;
 683
 684         } base;
 685
 686         uint32_t count;
 687
 688 };
 689
 690 /* Command Type 3 entry structure*/
 691
 692 struct command_t3_entry {
 693         struct qla4_header hdr; /* 00-03 */
 694
 695         uint32_t handle;        /* 04-07 */
 696         uint16_t target;        /* 08-09 */
 697         uint16_t connection_id; /* 0A-0B */
 698
 699         uint8_t control_flags;  /* 0C */
 700
 701         /* data direction  (bits 5-6) */
 702 #define CF_WRITE                0x20
 703 #define CF_READ                 0x40
 704 #define CF_NO_DATA              0x00
 705
 706         /* task attributes (bits 2-0) */
 707 #define CF_HEAD_TAG             0x03
 708 #define CF_ORDERED_TAG          0x02
 709 #define CF_SIMPLE_TAG           0x01
 710
 711         /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
 712          * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
 713          * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
 714          * PROPERLY.
 715          */
 716         uint8_t state_flags;    /* 0D */
 717         uint8_t cmdRefNum;      /* 0E */
 718         uint8_t reserved1;      /* 0F */
 719         uint8_t cdb[IOCB_MAX_CDB_LEN];  /* 10-1F */
 720         struct scsi_lun lun;    /* FCP LUN (BE). */
 721         uint32_t cmdSeqNum;     /* 28-2B */
 722         uint16_t timeout;       /* 2C-2D */
 723         uint16_t dataSegCnt;    /* 2E-2F */
 724         uint32_t ttlByteCnt;    /* 30-33 */
 725         struct data_seg_a64 dataseg[COMMAND_SEG_A64];   /* 34-3F */
 726
 727 };
 728
 729
 730 /* Continuation Type 1 entry structure*/
 731 struct continuation_t1_entry {
 732         struct qla4_header hdr;
 733
 734         struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
 735
 736 };
 737
 738 /* Parameterize for 64 or 32 bits */
 739 #define COMMAND_SEG     COMMAND_SEG_A64
 740 #define CONTINUE_SEG    CONTINUE_SEG_A64
 741
 742 #define ET_COMMAND      ET_CMND_T3
 743 #define ET_CONTINUE     ET_CONT_T1
 744
 745 /* Marker entry structure*/
 746 struct marker_entry {
 747         struct qla4_header hdr; /* 00-03 */
 748
 749         uint32_t system_defined; /* 04-07 */
 750         uint16_t target;        /* 08-09 */
 751         uint16_t modifier;      /* 0A-0B */
 752 #define MM_LUN_RESET         0
 753
 754         uint16_t flags;         /* 0C-0D */
 755         uint16_t reserved1;     /* 0E-0F */
 756         struct scsi_lun lun;    /* FCP LUN (BE). */
 757         uint64_t reserved2;     /* 18-1F */
 758         uint64_t reserved3;     /* 20-27 */
 759         uint64_t reserved4;     /* 28-2F */
 760         uint64_t reserved5;     /* 30-37 */
 761         uint64_t reserved6;     /* 38-3F */
 762 };
 763
 764 /* Status entry structure*/
 765 struct status_entry {
 766         struct qla4_header hdr; /* 00-03 */
 767
 768         uint32_t handle;        /* 04-07 */
 769
 770         uint8_t scsiStatus;     /* 08 */
 771 #define SCSI_CHECK_CONDITION              0x02
 772
 773         uint8_t iscsiFlags;     /* 09 */
 774 #define ISCSI_FLAG_RESIDUAL_UNDER         0x02
 775 #define ISCSI_FLAG_RESIDUAL_OVER          0x04
 776
 777         uint8_t iscsiResponse;  /* 0A */
 778
 779         uint8_t completionStatus;       /* 0B */
 780 #define SCS_COMPLETE                      0x00
 781 #define SCS_INCOMPLETE                    0x01
 782 #define SCS_RESET_OCCURRED                0x04
 783 #define SCS_ABORTED                       0x05
 784 #define SCS_TIMEOUT                       0x06
 785 #define SCS_DATA_OVERRUN                  0x07
 786 #define SCS_DATA_UNDERRUN                 0x15
 787 #define SCS_QUEUE_FULL                    0x1C
 788 #define SCS_DEVICE_UNAVAILABLE            0x28
 789 #define SCS_DEVICE_LOGGED_OUT             0x29
 790
 791         uint8_t reserved1;      /* 0C */
 792
 793         /* state_flags MUST be at the same location as state_flags in
 794          * the Command_T3/4_Entry */
 795         uint8_t state_flags;    /* 0D */
 796
 797         uint16_t senseDataByteCnt;      /* 0E-0F */
 798         uint32_t residualByteCnt;       /* 10-13 */
 799         uint32_t bidiResidualByteCnt;   /* 14-17 */
 800         uint32_t expSeqNum;     /* 18-1B */
 801         uint32_t maxCmdSeqNum;  /* 1C-1F */
 802         uint8_t senseData[IOCB_MAX_SENSEDATA_LEN];      /* 20-3F */
 803
 804 };
 805
 806 struct passthru0 {
 807         struct qla4_header hdr;                /* 00-03 */
 808         uint32_t handle;        /* 04-07 */
 809         uint16_t target;        /* 08-09 */
 810         uint16_t connectionID;  /* 0A-0B */
 811 #define ISNS_DEFAULT_SERVER_CONN_ID     ((uint16_t)0x8000)
 812
 813         uint16_t controlFlags;  /* 0C-0D */
 814 #define PT_FLAG_ETHERNET_FRAME          0x8000
 815 #define PT_FLAG_ISNS_PDU                0x8000
 816 #define PT_FLAG_SEND_BUFFER             0x0200
 817 #define PT_FLAG_WAIT_4_RESPONSE         0x0100
 818
 819         uint16_t timeout;       /* 0E-0F */
 820 #define PT_DEFAULT_TIMEOUT              30 /* seconds */
 821
 822         struct data_seg_a64 outDataSeg64;       /* 10-1B */
 823         uint32_t res1;          /* 1C-1F */
 824         struct data_seg_a64 inDataSeg64;        /* 20-2B */
 825         uint8_t res2[20];       /* 2C-3F */
 826 };
 827
 828 struct passthru_status {
 829         struct qla4_header hdr;                /* 00-03 */
 830         uint32_t handle;        /* 04-07 */
 831         uint16_t target;        /* 08-09 */
 832         uint16_t connectionID;  /* 0A-0B */
 833
 834         uint8_t completionStatus;       /* 0C */
 835 #define PASSTHRU_STATUS_COMPLETE                0x01
 836
 837         uint8_t residualFlags;  /* 0D */
 838
 839         uint16_t timeout;       /* 0E-0F */
 840         uint16_t portNumber;    /* 10-11 */
 841         uint8_t res1[10];       /* 12-1B */
 842         uint32_t outResidual;   /* 1C-1F */
 843         uint8_t res2[12];       /* 20-2B */
 844         uint32_t inResidual;    /* 2C-2F */
 845         uint8_t res4[16];       /* 30-3F */
 846 };
 847
 848 #endif /*  _QLA4X_FW_H */