drivers/scsi/esp.h

   1 /* $Id: esp.h,v 1.29 2001/12/11 04:55:47 davem Exp $
   2  * esp.h:  Defines and structures for the Sparc ESP (Enhanced SCSI
   3  *         Processor) driver under Linux.
   4  *
   5  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   6  */
   7
   8 #ifndef _SPARC_ESP_H
   9 #define _SPARC_ESP_H
  10
  11 /* For dvma controller register definitions. */
  12 #include <asm/dma.h>
  13
  14 /* The ESP SCSI controllers have their register sets in three
  15  * "classes":
  16  *
  17  * 1) Registers which are both read and write.
  18  * 2) Registers which are read only.
  19  * 3) Registers which are write only.
  20  *
  21  * Yet, they all live within the same IO space.
  22  */
  23
  24 /* All the ESP registers are one byte each and are accessed longwords
  25  * apart with a big-endian ordering to the bytes.
  26  */
  27                                         /* Access    Description              Offset */
  28 #define ESP_TCLOW       0x00UL          /* rw  Low bits of the transfer count 0x00   */
  29 #define ESP_TCMED       0x04UL          /* rw  Mid bits of the transfer count 0x04   */
  30 #define ESP_FDATA       0x08UL          /* rw  FIFO data bits                 0x08   */
  31 #define ESP_CMD         0x0cUL          /* rw  SCSI command bits              0x0c   */
  32 #define ESP_STATUS      0x10UL          /* ro  ESP status register            0x10   */
  33 #define ESP_BUSID       ESP_STATUS      /* wo  Bus ID for select/reselect     0x10   */
  34 #define ESP_INTRPT      0x14UL          /* ro  Kind of interrupt              0x14   */
  35 #define ESP_TIMEO       ESP_INTRPT      /* wo  Timeout value for select/resel 0x14   */
  36 #define ESP_SSTEP       0x18UL          /* ro  Sequence step register         0x18   */
  37 #define ESP_STP         ESP_SSTEP       /* wo  Transfer period per sync       0x18   */
  38 #define ESP_FFLAGS      0x1cUL          /* ro  Bits of current FIFO info      0x1c   */
  39 #define ESP_SOFF        ESP_FFLAGS      /* wo  Sync offset                    0x1c   */
  40 #define ESP_CFG1        0x20UL          /* rw  First configuration register   0x20   */
  41 #define ESP_CFACT       0x24UL          /* wo  Clock conversion factor        0x24   */
  42 #define ESP_STATUS2     ESP_CFACT       /* ro  HME status2 register           0x24   */
  43 #define ESP_CTEST       0x28UL          /* wo  Chip test register             0x28   */
  44 #define ESP_CFG2        0x2cUL          /* rw  Second configuration register  0x2c   */
  45 #define ESP_CFG3        0x30UL          /* rw  Third configuration register   0x30   */
  46 #define ESP_TCHI        0x38UL          /* rw  High bits of transfer count    0x38   */
  47 #define ESP_UID         ESP_TCHI        /* ro  Unique ID code                 0x38   */
  48 #define FAS_RLO         ESP_TCHI        /* rw  HME extended counter           0x38   */
  49 #define ESP_FGRND       0x3cUL          /* rw  Data base for fifo             0x3c   */
  50 #define FAS_RHI         ESP_FGRND       /* rw  HME extended counter           0x3c   */
  51 #define ESP_REG_SIZE    0x40UL
  52
  53 /* Various revisions of the ESP board. */
  54 enum esp_rev {
  55         esp100     = 0x00,  /* NCR53C90 - very broken */
  56         esp100a    = 0x01,  /* NCR53C90A */
  57         esp236     = 0x02,
  58         fas236     = 0x03,
  59         fas100a    = 0x04,
  60         fast       = 0x05,
  61         fashme     = 0x06,
  62         espunknown = 0x07
  63 };
  64
  65 /* We allocate one of these for each scsi device and attach it to
  66  * SDptr->hostdata for use in the driver
  67  */
  68 struct esp_device {
  69   unsigned char sync_min_period;
  70   unsigned char sync_max_offset;
  71   unsigned sync:1;
  72   unsigned wide:1;
  73   unsigned disconnect:1;
  74 };
  75
  76 struct scsi_cmnd;
  77
  78 /* We get one of these for each ESP probed. */
  79 struct esp {
  80         void __iomem            *eregs;         /* ESP controller registers */
  81         void __iomem            *dregs;         /* DMA controller registers */
  82         struct sbus_dma         *dma;           /* DMA controller sw state */
  83         struct Scsi_Host        *ehost;         /* Backpointer to SCSI Host */
  84         struct sbus_dev         *sdev;          /* Pointer to SBus entry */
  85
  86         /* ESP Configuration Registers */
  87         u8                      config1;        /* Copy of the 1st config register */
  88         u8                      config2;        /* Copy of the 2nd config register */
  89         u8                      config3[16];    /* Copy of the 3rd config register */
  90
  91         /* The current command we are sending to the ESP chip.  This esp_command
  92          * ptr needs to be mapped in DVMA area so we can send commands and read
  93          * from the ESP fifo without burning precious CPU cycles.  Programmed I/O
  94          * sucks when we have the DVMA to do it for us.  The ESP is stupid and will
  95          * only send out 6, 10, and 12 byte SCSI commands, others we need to send
  96          * one byte at a time.  esp_slowcmd being set says that we are doing one
  97          * of the command types ESP doesn't understand, esp_scmdp keeps track of
  98          * which byte we are sending, esp_scmdleft says how many bytes to go.
  99          */
 100         volatile u8             *esp_command;    /* Location of command (CPU view)  */
 101         __u32                   esp_command_dvma;/* Location of command (DVMA view) */
 102         unsigned char           esp_clen;        /* Length of this command */
 103         unsigned char           esp_slowcmd;
 104         unsigned char           *esp_scmdp;
 105         unsigned char           esp_scmdleft;
 106
 107         /* The following are used to determine the cause of an IRQ. Upon every
 108          * IRQ entry we synchronize these with the hardware registers.
 109          */
 110         u8                      ireg;           /* Copy of ESP interrupt register */
 111         u8                      sreg;           /* Copy of ESP status register */
 112         u8                      seqreg;         /* Copy of ESP sequence step register */
 113         u8                      sreg2;          /* Copy of HME status2 register */
 114
 115         /* To save register writes to the ESP, which can be expensive, we
 116          * keep track of the previous value that various registers had for
 117          * the last target we connected to.  If they are the same for the
 118          * current target, we skip the register writes as they are not needed.
 119          */
 120         u8                      prev_soff, prev_stp;
 121         u8                      prev_cfg3, __cache_pad;
 122
 123         /* We also keep a cache of the previous FAS/HME DMA CSR register value.  */
 124         u32                     prev_hme_dmacsr;
 125
 126         /* The HME is the biggest piece of shit I have ever seen. */
 127         u8                      hme_fifo_workaround_buffer[16 * 2];
 128         u8                      hme_fifo_workaround_count;
 129
 130         /* For each target we keep track of save/restore data
 131          * pointer information.  This needs to be updated majorly
 132          * when we add support for tagged queueing.  -DaveM
 133          */
 134         struct esp_pointers {
 135                 char                    *saved_ptr;
 136                 struct scatterlist      *saved_buffer;
 137                 int                     saved_this_residual;
 138                 int                     saved_buffers_residual;
 139         } data_pointers[16] /*XXX [MAX_TAGS_PER_TARGET]*/;
 140
 141         /* Clock periods, frequencies, synchronization, etc. */
 142         unsigned int            cfreq;          /* Clock frequency in HZ */
 143         unsigned int            cfact;          /* Clock conversion factor */
 144         unsigned int            raw_cfact;      /* Raw copy from probing */
 145         unsigned int            ccycle;         /* One ESP clock cycle */
 146         unsigned int            ctick;          /* One ESP clock time */
 147         unsigned int            radelay;        /* FAST chip req/ack delay */
 148         unsigned int            neg_defp;       /* Default negotiation period */
 149         unsigned int            sync_defp;      /* Default sync transfer period */
 150         unsigned int            max_period;     /* longest our period can be */
 151         unsigned int            min_period;     /* shortest period we can withstand */
 152
 153         struct esp              *next;          /* Next ESP we probed or NULL */
 154         char                    prom_name[64];  /* Name of ESP device from prom */
 155         int                     prom_node;      /* Prom node where ESP found */
 156         int                     esp_id;         /* Unique per-ESP ID number */
 157
 158         /* For slow to medium speed input clock rates we shoot for 5mb/s,
 159          * but for high input clock rates we try to do 10mb/s although I
 160          * don't think a transfer can even run that fast with an ESP even
 161          * with DMA2 scatter gather pipelining.
 162          */
 163 #define SYNC_DEFP_SLOW            0x32   /* 5mb/s  */
 164 #define SYNC_DEFP_FAST            0x19   /* 10mb/s */
 165
 166         unsigned int            snip;           /* Sync. negotiation in progress */
 167         unsigned int            wnip;           /* WIDE negotiation in progress */
 168         unsigned int            targets_present;/* targets spoken to before */
 169
 170         int             current_transfer_size;  /* Set at beginning of data dma */
 171
 172         u8                      espcmdlog[32];  /* Log of current esp cmds sent. */
 173         u8                      espcmdent;      /* Current entry in esp cmd log. */
 174
 175         /* Misc. info about this ESP */
 176         enum esp_rev            erev;           /* ESP revision */
 177         int                     irq;            /* SBus IRQ for this ESP */
 178         int                     scsi_id;        /* Who am I as initiator? */
 179         int                     scsi_id_mask;   /* Bitmask of 'me'. */
 180         int                     diff;           /* Differential SCSI bus? */
 181         int                     bursts;         /* Burst sizes our DVMA supports */
 182
 183         /* Our command queues, only one cmd lives in the current_SC queue. */
 184         struct scsi_cmnd        *issue_SC;      /* Commands to be issued */
 185         struct scsi_cmnd        *current_SC;    /* Who is currently working the bus */
 186         struct scsi_cmnd        *disconnected_SC;/* Commands disconnected from the bus */
 187
 188         /* Message goo */
 189         u8                      cur_msgout[16];
 190         u8                      cur_msgin[16];
 191         u8                      prevmsgout, prevmsgin;
 192         u8                      msgout_len, msgin_len;
 193         u8                      msgout_ctr, msgin_ctr;
 194
 195         /* States that we cannot keep in the per cmd structure because they
 196          * cannot be assosciated with any specific command.
 197          */
 198         u8                      resetting_bus;
 199         wait_queue_head_t       reset_queue;
 200 };
 201
 202 /* Bitfield meanings for the above registers. */
 203
 204 /* ESP config reg 1, read-write, found on all ESP chips */
 205 #define ESP_CONFIG1_ID        0x07             /* My BUS ID bits */
 206 #define ESP_CONFIG1_CHTEST    0x08             /* Enable ESP chip tests */
 207 #define ESP_CONFIG1_PENABLE   0x10             /* Enable parity checks */
 208 #define ESP_CONFIG1_PARTEST   0x20             /* Parity test mode enabled? */
 209 #define ESP_CONFIG1_SRRDISAB  0x40             /* Disable SCSI reset reports */
 210 #define ESP_CONFIG1_SLCABLE   0x80             /* Enable slow cable mode */
 211
 212 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
 213 #define ESP_CONFIG2_DMAPARITY 0x01             /* enable DMA Parity (200,236) */
 214 #define ESP_CONFIG2_REGPARITY 0x02             /* enable reg Parity (200,236) */
 215 #define ESP_CONFIG2_BADPARITY 0x04             /* Bad parity target abort  */
 216 #define ESP_CONFIG2_SCSI2ENAB 0x08             /* Enable SCSI-2 features (tmode only) */
 217 #define ESP_CONFIG2_HI        0x10             /* High Impedance DREQ ???  */
 218 #define ESP_CONFIG2_HMEFENAB  0x10             /* HME features enable */
 219 #define ESP_CONFIG2_BCM       0x20             /* Enable byte-ctrl (236)   */
 220 #define ESP_CONFIG2_DISPINT   0x20             /* Disable pause irq (hme) */
 221 #define ESP_CONFIG2_FENAB     0x40             /* Enable features (fas100,esp216)      */
 222 #define ESP_CONFIG2_SPL       0x40             /* Enable status-phase latch (esp236)   */
 223 #define ESP_CONFIG2_MKDONE    0x40             /* HME magic feature */
 224 #define ESP_CONFIG2_HME32     0x80             /* HME 32 extended */
 225 #define ESP_CONFIG2_MAGIC     0xe0             /* Invalid bits... */
 226
 227 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
 228 #define ESP_CONFIG3_FCLOCK    0x01             /* FAST SCSI clock rate (esp100a/hme) */
 229 #define ESP_CONFIG3_TEM       0x01             /* Enable thresh-8 mode (esp/fas236)  */
 230 #define ESP_CONFIG3_FAST      0x02             /* Enable FAST SCSI     (esp100a/hme) */
 231 #define ESP_CONFIG3_ADMA      0x02             /* Enable alternate-dma (esp/fas236)  */
 232 #define ESP_CONFIG3_TENB      0x04             /* group2 SCSI2 support (esp100a/hme) */
 233 #define ESP_CONFIG3_SRB       0x04             /* Save residual byte   (esp/fas236)  */
 234 #define ESP_CONFIG3_TMS       0x08             /* Three-byte msg's ok  (esp100a/hme) */
 235 #define ESP_CONFIG3_FCLK      0x08             /* Fast SCSI clock rate (esp/fas236)  */
 236 #define ESP_CONFIG3_IDMSG     0x10             /* ID message checking  (esp100a/hme) */
 237 #define ESP_CONFIG3_FSCSI     0x10             /* Enable FAST SCSI     (esp/fas236)  */
 238 #define ESP_CONFIG3_GTM       0x20             /* group2 SCSI2 support (esp/fas236)  */
 239 #define ESP_CONFIG3_IDBIT3    0x20             /* Bit 3 of HME SCSI-ID (hme)         */
 240 #define ESP_CONFIG3_TBMS      0x40             /* Three-byte msg's ok  (esp/fas236)  */
 241 #define ESP_CONFIG3_EWIDE     0x40             /* Enable Wide-SCSI     (hme)         */
 242 #define ESP_CONFIG3_IMS       0x80             /* ID msg chk'ng        (esp/fas236)  */
 243 #define ESP_CONFIG3_OBPUSH    0x80             /* Push odd-byte to dma (hme)         */
 244
 245 /* ESP command register read-write */
 246 /* Group 1 commands:  These may be sent at any point in time to the ESP
 247  *                    chip.  None of them can generate interrupts 'cept
 248  *                    the "SCSI bus reset" command if you have not disabled
 249  *                    SCSI reset interrupts in the config1 ESP register.
 250  */
 251 #define ESP_CMD_NULL          0x00             /* Null command, ie. a nop */
 252 #define ESP_CMD_FLUSH         0x01             /* FIFO Flush */
 253 #define ESP_CMD_RC            0x02             /* Chip reset */
 254 #define ESP_CMD_RS            0x03             /* SCSI bus reset */
 255
 256 /* Group 2 commands:  ESP must be an initiator and connected to a target
 257  *                    for these commands to work.
 258  */
 259 #define ESP_CMD_TI            0x10             /* Transfer Information */
 260 #define ESP_CMD_ICCSEQ        0x11             /* Initiator cmd complete sequence */
 261 #define ESP_CMD_MOK           0x12             /* Message okie-dokie */
 262 #define ESP_CMD_TPAD          0x18             /* Transfer Pad */
 263 #define ESP_CMD_SATN          0x1a             /* Set ATN */
 264 #define ESP_CMD_RATN          0x1b             /* De-assert ATN */
 265
 266 /* Group 3 commands:  ESP must be in the MSGOUT or MSGIN state and be connected
 267  *                    to a target as the initiator for these commands to work.
 268  */
 269 #define ESP_CMD_SMSG          0x20             /* Send message */
 270 #define ESP_CMD_SSTAT         0x21             /* Send status */
 271 #define ESP_CMD_SDATA         0x22             /* Send data */
 272 #define ESP_CMD_DSEQ          0x23             /* Discontinue Sequence */
 273 #define ESP_CMD_TSEQ          0x24             /* Terminate Sequence */
 274 #define ESP_CMD_TCCSEQ        0x25             /* Target cmd cmplt sequence */
 275 #define ESP_CMD_DCNCT         0x27             /* Disconnect */
 276 #define ESP_CMD_RMSG          0x28             /* Receive Message */
 277 #define ESP_CMD_RCMD          0x29             /* Receive Command */
 278 #define ESP_CMD_RDATA         0x2a             /* Receive Data */
 279 #define ESP_CMD_RCSEQ         0x2b             /* Receive cmd sequence */
 280
 281 /* Group 4 commands:  The ESP must be in the disconnected state and must
 282  *                    not be connected to any targets as initiator for
 283  *                    these commands to work.
 284  */
 285 #define ESP_CMD_RSEL          0x40             /* Reselect */
 286 #define ESP_CMD_SEL           0x41             /* Select w/o ATN */
 287 #define ESP_CMD_SELA          0x42             /* Select w/ATN */
 288 #define ESP_CMD_SELAS         0x43             /* Select w/ATN & STOP */
 289 #define ESP_CMD_ESEL          0x44             /* Enable selection */
 290 #define ESP_CMD_DSEL          0x45             /* Disable selections */
 291 #define ESP_CMD_SA3           0x46             /* Select w/ATN3 */
 292 #define ESP_CMD_RSEL3         0x47             /* Reselect3 */
 293
 294 /* This bit enables the ESP's DMA on the SBus */
 295 #define ESP_CMD_DMA           0x80             /* Do DMA? */
 296
 297
 298 /* ESP status register read-only */
 299 #define ESP_STAT_PIO          0x01             /* IO phase bit */
 300 #define ESP_STAT_PCD          0x02             /* CD phase bit */
 301 #define ESP_STAT_PMSG         0x04             /* MSG phase bit */
 302 #define ESP_STAT_PMASK        0x07             /* Mask of phase bits */
 303 #define ESP_STAT_TDONE        0x08             /* Transfer Completed */
 304 #define ESP_STAT_TCNT         0x10             /* Transfer Counter Is Zero */
 305 #define ESP_STAT_PERR         0x20             /* Parity error */
 306 #define ESP_STAT_SPAM         0x40             /* Real bad error */
 307 /* This indicates the 'interrupt pending' condition on esp236, it is a reserved
 308  * bit on other revs of the ESP.
 309  */
 310 #define ESP_STAT_INTR         0x80             /* Interrupt */
 311
 312 /* HME only: status 2 register */
 313 #define ESP_STAT2_SCHBIT      0x01 /* Upper bits 3-7 of sstep enabled */
 314 #define ESP_STAT2_FFLAGS      0x02 /* The fifo flags are now latched */
 315 #define ESP_STAT2_XCNT        0x04 /* The transfer counter is latched */
 316 #define ESP_STAT2_CREGA       0x08 /* The command reg is active now */
 317 #define ESP_STAT2_WIDE        0x10 /* Interface on this adapter is wide */
 318 #define ESP_STAT2_F1BYTE      0x20 /* There is one byte at top of fifo */
 319 #define ESP_STAT2_FMSB        0x40 /* Next byte in fifo is most significant */
 320 #define ESP_STAT2_FEMPTY      0x80 /* FIFO is empty */
 321
 322 /* The status register can be masked with ESP_STAT_PMASK and compared
 323  * with the following values to determine the current phase the ESP
 324  * (at least thinks it) is in.  For our purposes we also add our own
 325  * software 'done' bit for our phase management engine.
 326  */
 327 #define ESP_DOP   (0)                                       /* Data Out  */
 328 #define ESP_DIP   (ESP_STAT_PIO)                            /* Data In   */
 329 #define ESP_CMDP  (ESP_STAT_PCD)                            /* Command   */
 330 #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO)               /* Status    */
 331 #define ESP_MOP   (ESP_STAT_PMSG|ESP_STAT_PCD)              /* Message Out */
 332 #define ESP_MIP   (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
 333
 334 /* ESP interrupt register read-only */
 335 #define ESP_INTR_S            0x01             /* Select w/o ATN */
 336 #define ESP_INTR_SATN         0x02             /* Select w/ATN */
 337 #define ESP_INTR_RSEL         0x04             /* Reselected */
 338 #define ESP_INTR_FDONE        0x08             /* Function done */
 339 #define ESP_INTR_BSERV        0x10             /* Bus service */
 340 #define ESP_INTR_DC           0x20             /* Disconnect */
 341 #define ESP_INTR_IC           0x40             /* Illegal command given */
 342 #define ESP_INTR_SR           0x80             /* SCSI bus reset detected */
 343
 344 /* Interrupt status macros */
 345 #define ESP_SRESET_IRQ(esp)  ((esp)->intreg & (ESP_INTR_SR))
 346 #define ESP_ILLCMD_IRQ(esp)  ((esp)->intreg & (ESP_INTR_IC))
 347 #define ESP_SELECT_WITH_ATN_IRQ(esp)     ((esp)->intreg & (ESP_INTR_SATN))
 348 #define ESP_SELECT_WITHOUT_ATN_IRQ(esp)  ((esp)->intreg & (ESP_INTR_S))
 349 #define ESP_SELECTION_IRQ(esp)  ((ESP_SELECT_WITH_ATN_IRQ(esp)) ||         \
 350                                  (ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
 351 #define ESP_RESELECTION_IRQ(esp)         ((esp)->intreg & (ESP_INTR_RSEL))
 352
 353 /* ESP sequence step register read-only */
 354 #define ESP_STEP_VBITS        0x07             /* Valid bits */
 355 #define ESP_STEP_ASEL         0x00             /* Selection&Arbitrate cmplt */
 356 #define ESP_STEP_SID          0x01             /* One msg byte sent */
 357 #define ESP_STEP_NCMD         0x02             /* Was not in command phase */
 358 #define ESP_STEP_PPC          0x03             /* Early phase chg caused cmnd
 359                                                 * bytes to be lost
 360                                                 */
 361 #define ESP_STEP_FINI4        0x04             /* Command was sent ok */
 362
 363 /* Ho hum, some ESP's set the step register to this as well... */
 364 #define ESP_STEP_FINI5        0x05
 365 #define ESP_STEP_FINI6        0x06
 366 #define ESP_STEP_FINI7        0x07
 367
 368 /* ESP chip-test register read-write */
 369 #define ESP_TEST_TARG         0x01             /* Target test mode */
 370 #define ESP_TEST_INI          0x02             /* Initiator test mode */
 371 #define ESP_TEST_TS           0x04             /* Tristate test mode */
 372
 373 /* ESP unique ID register read-only, found on fas236+fas100a only */
 374 #define ESP_UID_F100A         0x00             /* ESP FAS100A  */
 375 #define ESP_UID_F236          0x02             /* ESP FAS236   */
 376 #define ESP_UID_REV           0x07             /* ESP revision */
 377 #define ESP_UID_FAM           0xf8             /* ESP family   */
 378
 379 /* ESP fifo flags register read-only */
 380 /* Note that the following implies a 16 byte FIFO on the ESP. */
 381 #define ESP_FF_FBYTES         0x1f             /* Num bytes in FIFO */
 382 #define ESP_FF_ONOTZERO       0x20             /* offset ctr not zero (esp100) */
 383 #define ESP_FF_SSTEP          0xe0             /* Sequence step */
 384
 385 /* ESP clock conversion factor register write-only */
 386 #define ESP_CCF_F0            0x00             /* 35.01MHz - 40MHz */
 387 #define ESP_CCF_NEVER         0x01             /* Set it to this and die */
 388 #define ESP_CCF_F2            0x02             /* 10MHz */
 389 #define ESP_CCF_F3            0x03             /* 10.01MHz - 15MHz */
 390 #define ESP_CCF_F4            0x04             /* 15.01MHz - 20MHz */
 391 #define ESP_CCF_F5            0x05             /* 20.01MHz - 25MHz */
 392 #define ESP_CCF_F6            0x06             /* 25.01MHz - 30MHz */
 393 #define ESP_CCF_F7            0x07             /* 30.01MHz - 35MHz */
 394
 395 /* HME only... */
 396 #define ESP_BUSID_RESELID     0x10
 397 #define ESP_BUSID_CTR32BIT    0x40
 398
 399 #define ESP_BUS_TIMEOUT        275             /* In milli-seconds */
 400 #define ESP_TIMEO_CONST       8192
 401 #define ESP_NEG_DEFP(mhz, cfact) \
 402         ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
 403 #define ESP_MHZ_TO_CYCLE(mhertz)  ((1000000000) / ((mhertz) / 1000))
 404 #define ESP_TICK(ccf, cycle)  ((7682 * (ccf) * (cycle) / 1000))
 405
 406 #endif /* !(_SPARC_ESP_H) */