drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /* statistics can be kept for for tuning/monitoring */
  25 struct ehci_stats {
  26         /* irq usage */
  27         unsigned long           normal;
  28         unsigned long           error;
  29         unsigned long           reclaim;
  30         unsigned long           lost_iaa;
  31
  32         /* termination of urbs from core */
  33         unsigned long           complete;
  34         unsigned long           unlink;
  35 };
  36
  37 /* ehci_hcd->lock guards shared data against other CPUs:
  38  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  39  *   usb_host_endpoint: hcpriv
  40  *   ehci_qh:   qh_next, qtd_list
  41  *   ehci_qtd:  qtd_list
  42  *
  43  * Also, hold this lock when talking to HC registers or
  44  * when updating hw_* fields in shared qh/qtd/... structures.
  45  */
  46
  47 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  48
  49 struct ehci_hcd {                       /* one per controller */
  50         /* glue to PCI and HCD framework */
  51         struct ehci_caps __iomem *caps;
  52         struct ehci_regs __iomem *regs;
  53         struct ehci_dbg_port __iomem *debug;
  54
  55         __u32                   hcs_params;     /* cached register copy */
  56         spinlock_t              lock;
  57
  58         /* async schedule support */
  59         struct ehci_qh          *async;
  60         struct ehci_qh          *reclaim;
  61         unsigned                reclaim_ready : 1;
  62         unsigned                scanning : 1;
  63
  64         /* periodic schedule support */
  65 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  66         unsigned                periodic_size;
  67         __le32                  *periodic;      /* hw periodic table */
  68         dma_addr_t              periodic_dma;
  69         unsigned                i_thresh;       /* uframes HC might cache */
  70
  71         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  72         int                     next_uframe;    /* scan periodic, start here */
  73         unsigned                periodic_sched; /* periodic activity count */
  74
  75         /* per root hub port */
  76         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  77         unsigned long           bus_suspended;
  78
  79         /* per-HC memory pools (could be per-bus, but ...) */
  80         struct dma_pool         *qh_pool;       /* qh per active urb */
  81         struct dma_pool         *qtd_pool;      /* one or more per qh */
  82         struct dma_pool         *itd_pool;      /* itd per iso urb */
  83         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
  84
  85         struct timer_list       watchdog;
  86         unsigned long           actions;
  87         unsigned                stamp;
  88         unsigned long           next_statechange;
  89         u32                     command;
  90
  91         /* SILICON QUIRKS */
  92         unsigned                is_tdi_rh_tt:1; /* TDI roothub with TT */
  93         unsigned                no_selective_suspend:1;
  94         unsigned                has_fsl_port_bug:1; /* FreeScale */
  95         unsigned                big_endian_mmio:1;
  96
  97         u8                      sbrn;           /* packed release number */
  98
  99         /* irq statistics */
 100 #ifdef EHCI_STATS
 101         struct ehci_stats       stats;
 102 #       define COUNT(x) do { (x)++; } while (0)
 103 #else
 104 #       define COUNT(x) do {} while (0)
 105 #endif
 106 };
 107
 108 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 109 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 110 {
 111         return (struct ehci_hcd *) (hcd->hcd_priv);
 112 }
 113 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 114 {
 115         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 116 }
 117
 118
 119 enum ehci_timer_action {
 120         TIMER_IO_WATCHDOG,
 121         TIMER_IAA_WATCHDOG,
 122         TIMER_ASYNC_SHRINK,
 123         TIMER_ASYNC_OFF,
 124 };
 125
 126 static inline void
 127 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 128 {
 129         clear_bit (action, &ehci->actions);
 130 }
 131
 132 static inline void
 133 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
 134 {
 135         if (!test_and_set_bit (action, &ehci->actions)) {
 136                 unsigned long t;
 137
 138                 switch (action) {
 139                 case TIMER_IAA_WATCHDOG:
 140                         t = EHCI_IAA_JIFFIES;
 141                         break;
 142                 case TIMER_IO_WATCHDOG:
 143                         t = EHCI_IO_JIFFIES;
 144                         break;
 145                 case TIMER_ASYNC_OFF:
 146                         t = EHCI_ASYNC_JIFFIES;
 147                         break;
 148                 // case TIMER_ASYNC_SHRINK:
 149                 default:
 150                         t = EHCI_SHRINK_JIFFIES;
 151                         break;
 152                 }
 153                 t += jiffies;
 154                 // all timings except IAA watchdog can be overridden.
 155                 // async queue SHRINK often precedes IAA.  while it's ready
 156                 // to go OFF neither can matter, and afterwards the IO
 157                 // watchdog stops unless there's still periodic traffic.
 158                 if (action != TIMER_IAA_WATCHDOG
 159                                 && t > ehci->watchdog.expires
 160                                 && timer_pending (&ehci->watchdog))
 161                         return;
 162                 mod_timer (&ehci->watchdog, t);
 163         }
 164 }
 165
 166 /*-------------------------------------------------------------------------*/
 167
 168 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 169
 170 /* Section 2.2 Host Controller Capability Registers */
 171 struct ehci_caps {
 172         /* these fields are specified as 8 and 16 bit registers,
 173          * but some hosts can't perform 8 or 16 bit PCI accesses.
 174          */
 175         u32             hc_capbase;
 176 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 177 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 178         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 179 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 180 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 181 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 182 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 183 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 184 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 185 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 186
 187         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 188 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 189 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 190 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 191 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 192 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 193 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 194         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 195 } __attribute__ ((packed));
 196
 197
 198 /* Section 2.3 Host Controller Operational Registers */
 199 struct ehci_regs {
 200
 201         /* USBCMD: offset 0x00 */
 202         u32             command;
 203 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 204 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 205 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 206 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 207 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 208 #define CMD_ASE         (1<<5)          /* async schedule enable */
 209 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 210 /* 3:2 is periodic frame list size */
 211 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 212 #define CMD_RUN         (1<<0)          /* start/stop HC */
 213
 214         /* USBSTS: offset 0x04 */
 215         u32             status;
 216 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 217 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 218 #define STS_RECL        (1<<13)         /* Reclamation */
 219 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 220 /* some bits reserved */
 221         /* these STS_* flags are also intr_enable bits (USBINTR) */
 222 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 223 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 224 #define STS_FLR         (1<<3)          /* frame list rolled over */
 225 #define STS_PCD         (1<<2)          /* port change detect */
 226 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 227 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 228
 229         /* USBINTR: offset 0x08 */
 230         u32             intr_enable;
 231
 232         /* FRINDEX: offset 0x0C */
 233         u32             frame_index;    /* current microframe number */
 234         /* CTRLDSSEGMENT: offset 0x10 */
 235         u32             segment;        /* address bits 63:32 if needed */
 236         /* PERIODICLISTBASE: offset 0x14 */
 237         u32             frame_list;     /* points to periodic list */
 238         /* ASYNCLISTADDR: offset 0x18 */
 239         u32             async_next;     /* address of next async queue head */
 240
 241         u32             reserved [9];
 242
 243         /* CONFIGFLAG: offset 0x40 */
 244         u32             configured_flag;
 245 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 246
 247         /* PORTSC: offset 0x44 */
 248         u32             port_status [0];        /* up to N_PORTS */
 249 /* 31:23 reserved */
 250 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 251 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 252 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 253 /* 19:16 for port testing */
 254 #define PORT_LED_OFF    (0<<14)
 255 #define PORT_LED_AMBER  (1<<14)
 256 #define PORT_LED_GREEN  (2<<14)
 257 #define PORT_LED_MASK   (3<<14)
 258 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 259 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 260 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 261 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 262 /* 9 reserved */
 263 #define PORT_RESET      (1<<8)          /* reset port */
 264 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 265 #define PORT_RESUME     (1<<6)          /* resume it */
 266 #define PORT_OCC        (1<<5)          /* over current change */
 267 #define PORT_OC         (1<<4)          /* over current active */
 268 #define PORT_PEC        (1<<3)          /* port enable change */
 269 #define PORT_PE         (1<<2)          /* port enable */
 270 #define PORT_CSC        (1<<1)          /* connect status change */
 271 #define PORT_CONNECT    (1<<0)          /* device connected */
 272 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
 273 } __attribute__ ((packed));
 274
 275 /* Appendix C, Debug port ... intended for use with special "debug devices"
 276  * that can help if there's no serial console.  (nonstandard enumeration.)
 277  */
 278 struct ehci_dbg_port {
 279         u32     control;
 280 #define DBGP_OWNER      (1<<30)
 281 #define DBGP_ENABLED    (1<<28)
 282 #define DBGP_DONE       (1<<16)
 283 #define DBGP_INUSE      (1<<10)
 284 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 285 #       define DBGP_ERR_BAD     1
 286 #       define DBGP_ERR_SIGNAL  2
 287 #define DBGP_ERROR      (1<<6)
 288 #define DBGP_GO         (1<<5)
 289 #define DBGP_OUT        (1<<4)
 290 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 291         u32     pids;
 292 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 293 #define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
 294         u32     data03;
 295         u32     data47;
 296         u32     address;
 297 #define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
 298 } __attribute__ ((packed));
 299
 300 /*-------------------------------------------------------------------------*/
 301
 302 #define QTD_NEXT(dma)   cpu_to_le32((u32)dma)
 303
 304 /*
 305  * EHCI Specification 0.95 Section 3.5
 306  * QTD: describe data transfer components (buffer, direction, ...)
 307  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 308  *
 309  * These are associated only with "QH" (Queue Head) structures,
 310  * used with control, bulk, and interrupt transfers.
 311  */
 312 struct ehci_qtd {
 313         /* first part defined by EHCI spec */
 314         __le32                  hw_next;          /* see EHCI 3.5.1 */
 315         __le32                  hw_alt_next;      /* see EHCI 3.5.2 */
 316         __le32                  hw_token;         /* see EHCI 3.5.3 */
 317 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 318 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 319 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 320 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 321 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 322 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 323 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 324 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 325 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 326 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 327 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 328 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 329 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 330         __le32                  hw_buf [5];        /* see EHCI 3.5.4 */
 331         __le32                  hw_buf_hi [5];        /* Appendix B */
 332
 333         /* the rest is HCD-private */
 334         dma_addr_t              qtd_dma;                /* qtd address */
 335         struct list_head        qtd_list;               /* sw qtd list */
 336         struct urb              *urb;                   /* qtd's urb */
 337         size_t                  length;                 /* length of buffer */
 338 } __attribute__ ((aligned (32)));
 339
 340 /* mask NakCnt+T in qh->hw_alt_next */
 341 #define QTD_MASK __constant_cpu_to_le32 (~0x1f)
 342
 343 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 344
 345 /*-------------------------------------------------------------------------*/
 346
 347 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 348 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
 349
 350 /* values for that type tag */
 351 #define Q_TYPE_ITD      __constant_cpu_to_le32 (0 << 1)
 352 #define Q_TYPE_QH       __constant_cpu_to_le32 (1 << 1)
 353 #define Q_TYPE_SITD     __constant_cpu_to_le32 (2 << 1)
 354 #define Q_TYPE_FSTN     __constant_cpu_to_le32 (3 << 1)
 355
 356 /* next async queue entry, or pointer to interrupt/periodic QH */
 357 #define QH_NEXT(dma)    (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
 358
 359 /* for periodic/async schedules and qtd lists, mark end of list */
 360 #define EHCI_LIST_END   __constant_cpu_to_le32(1) /* "null pointer" to hw */
 361
 362 /*
 363  * Entries in periodic shadow table are pointers to one of four kinds
 364  * of data structure.  That's dictated by the hardware; a type tag is
 365  * encoded in the low bits of the hardware's periodic schedule.  Use
 366  * Q_NEXT_TYPE to get the tag.
 367  *
 368  * For entries in the async schedule, the type tag always says "qh".
 369  */
 370 union ehci_shadow {
 371         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 372         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 373         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 374         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 375         __le32                  *hw_next;       /* (all types) */
 376         void                    *ptr;
 377 };
 378
 379 /*-------------------------------------------------------------------------*/
 380
 381 /*
 382  * EHCI Specification 0.95 Section 3.6
 383  * QH: describes control/bulk/interrupt endpoints
 384  * See Fig 3-7 "Queue Head Structure Layout".
 385  *
 386  * These appear in both the async and (for interrupt) periodic schedules.
 387  */
 388
 389 struct ehci_qh {
 390         /* first part defined by EHCI spec */
 391         __le32                  hw_next;         /* see EHCI 3.6.1 */
 392         __le32                  hw_info1;        /* see EHCI 3.6.2 */
 393 #define QH_HEAD         0x00008000
 394         __le32                  hw_info2;        /* see EHCI 3.6.2 */
 395 #define QH_SMASK        0x000000ff
 396 #define QH_CMASK        0x0000ff00
 397 #define QH_HUBADDR      0x007f0000
 398 #define QH_HUBPORT      0x3f800000
 399 #define QH_MULT         0xc0000000
 400         __le32                  hw_current;      /* qtd list - see EHCI 3.6.4 */
 401
 402         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 403         __le32                  hw_qtd_next;
 404         __le32                  hw_alt_next;
 405         __le32                  hw_token;
 406         __le32                  hw_buf [5];
 407         __le32                  hw_buf_hi [5];
 408
 409         /* the rest is HCD-private */
 410         dma_addr_t              qh_dma;         /* address of qh */
 411         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 412         struct list_head        qtd_list;       /* sw qtd list */
 413         struct ehci_qtd         *dummy;
 414         struct ehci_qh          *reclaim;       /* next to reclaim */
 415
 416         struct ehci_hcd         *ehci;
 417         struct kref             kref;
 418         unsigned                stamp;
 419
 420         u8                      qh_state;
 421 #define QH_STATE_LINKED         1               /* HC sees this */
 422 #define QH_STATE_UNLINK         2               /* HC may still see this */
 423 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 424 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 425 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 426
 427         /* periodic schedule info */
 428         u8                      usecs;          /* intr bandwidth */
 429         u8                      gap_uf;         /* uframes split/csplit gap */
 430         u8                      c_usecs;        /* ... split completion bw */
 431         u16                     tt_usecs;       /* tt downstream bandwidth */
 432         unsigned short          period;         /* polling interval */
 433         unsigned short          start;          /* where polling starts */
 434 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 435         struct usb_device       *dev;           /* access to TT */
 436 } __attribute__ ((aligned (32)));
 437
 438 /*-------------------------------------------------------------------------*/
 439
 440 /* description of one iso transaction (up to 3 KB data if highspeed) */
 441 struct ehci_iso_packet {
 442         /* These will be copied to iTD when scheduling */
 443         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 444         __le32                  transaction;    /* itd->hw_transaction[i] |= */
 445         u8                      cross;          /* buf crosses pages */
 446         /* for full speed OUT splits */
 447         u32                     buf1;
 448 };
 449
 450 /* temporary schedule data for packets from iso urbs (both speeds)
 451  * each packet is one logical usb transaction to the device (not TT),
 452  * beginning at stream->next_uframe
 453  */
 454 struct ehci_iso_sched {
 455         struct list_head        td_list;
 456         unsigned                span;
 457         struct ehci_iso_packet  packet [0];
 458 };
 459
 460 /*
 461  * ehci_iso_stream - groups all (s)itds for this endpoint.
 462  * acts like a qh would, if EHCI had them for ISO.
 463  */
 464 struct ehci_iso_stream {
 465         /* first two fields match QH, but info1 == 0 */
 466         __le32                  hw_next;
 467         __le32                  hw_info1;
 468
 469         u32                     refcount;
 470         u8                      bEndpointAddress;
 471         u8                      highspeed;
 472         u16                     depth;          /* depth in uframes */
 473         struct list_head        td_list;        /* queued itds/sitds */
 474         struct list_head        free_list;      /* list of unused itds/sitds */
 475         struct usb_device       *udev;
 476         struct usb_host_endpoint *ep;
 477
 478         /* output of (re)scheduling */
 479         unsigned long           start;          /* jiffies */
 480         unsigned long           rescheduled;
 481         int                     next_uframe;
 482         __le32                  splits;
 483
 484         /* the rest is derived from the endpoint descriptor,
 485          * trusting urb->interval == f(epdesc->bInterval) and
 486          * including the extra info for hw_bufp[0..2]
 487          */
 488         u8                      interval;
 489         u8                      usecs, c_usecs;
 490         u16                     tt_usecs;
 491         u16                     maxp;
 492         u16                     raw_mask;
 493         unsigned                bandwidth;
 494
 495         /* This is used to initialize iTD's hw_bufp fields */
 496         __le32                  buf0;
 497         __le32                  buf1;
 498         __le32                  buf2;
 499
 500         /* this is used to initialize sITD's tt info */
 501         __le32                  address;
 502 };
 503
 504 /*-------------------------------------------------------------------------*/
 505
 506 /*
 507  * EHCI Specification 0.95 Section 3.3
 508  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 509  *
 510  * Schedule records for high speed iso xfers
 511  */
 512 struct ehci_itd {
 513         /* first part defined by EHCI spec */
 514         __le32                  hw_next;           /* see EHCI 3.3.1 */
 515         __le32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 516 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 517 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 518 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 519 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 520 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 521 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 522
 523 #define ITD_ACTIVE      __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
 524
 525         __le32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 526         __le32                  hw_bufp_hi [7]; /* Appendix B */
 527
 528         /* the rest is HCD-private */
 529         dma_addr_t              itd_dma;        /* for this itd */
 530         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 531
 532         struct urb              *urb;
 533         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 534         struct list_head        itd_list;       /* list of stream's itds */
 535
 536         /* any/all hw_transactions here may be used by that urb */
 537         unsigned                frame;          /* where scheduled */
 538         unsigned                pg;
 539         unsigned                index[8];       /* in urb->iso_frame_desc */
 540         u8                      usecs[8];
 541 } __attribute__ ((aligned (32)));
 542
 543 /*-------------------------------------------------------------------------*/
 544
 545 /*
 546  * EHCI Specification 0.95 Section 3.4
 547  * siTD, aka split-transaction isochronous Transfer Descriptor
 548  *       ... describe full speed iso xfers through TT in hubs
 549  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 550  */
 551 struct ehci_sitd {
 552         /* first part defined by EHCI spec */
 553         __le32                  hw_next;
 554 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 555         __le32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 556         __le32                  hw_uframe;              /* EHCI table 3-10 */
 557         __le32                  hw_results;             /* EHCI table 3-11 */
 558 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 559 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 560 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 561 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 562 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 563 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 564 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 565 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 566 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 567 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 568
 569 #define SITD_ACTIVE     __constant_cpu_to_le32(SITD_STS_ACTIVE)
 570
 571         __le32                  hw_buf [2];             /* EHCI table 3-12 */
 572         __le32                  hw_backpointer;         /* EHCI table 3-13 */
 573         __le32                  hw_buf_hi [2];          /* Appendix B */
 574
 575         /* the rest is HCD-private */
 576         dma_addr_t              sitd_dma;
 577         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 578
 579         struct urb              *urb;
 580         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 581         struct list_head        sitd_list;      /* list of stream's sitds */
 582         unsigned                frame;
 583         unsigned                index;
 584 } __attribute__ ((aligned (32)));
 585
 586 /*-------------------------------------------------------------------------*/
 587
 588 /*
 589  * EHCI Specification 0.96 Section 3.7
 590  * Periodic Frame Span Traversal Node (FSTN)
 591  *
 592  * Manages split interrupt transactions (using TT) that span frame boundaries
 593  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 594  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 595  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 596  */
 597 struct ehci_fstn {
 598         __le32                  hw_next;        /* any periodic q entry */
 599         __le32                  hw_prev;        /* qh or EHCI_LIST_END */
 600
 601         /* the rest is HCD-private */
 602         dma_addr_t              fstn_dma;
 603         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 604 } __attribute__ ((aligned (32)));
 605
 606 /*-------------------------------------------------------------------------*/
 607
 608 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 609
 610 /*
 611  * Some EHCI controllers have a Transaction Translator built into the
 612  * root hub. This is a non-standard feature.  Each controller will need
 613  * to add code to the following inline functions, and call them as
 614  * needed (mostly in root hub code).
 615  */
 616
 617 #define ehci_is_TDI(e)                  ((e)->is_tdi_rh_tt)
 618
 619 /* Returns the speed of a device attached to a port on the root hub. */
 620 static inline unsigned int
 621 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 622 {
 623         if (ehci_is_TDI(ehci)) {
 624                 switch ((portsc>>26)&3) {
 625                 case 0:
 626                         return 0;
 627                 case 1:
 628                         return (1<<USB_PORT_FEAT_LOWSPEED);
 629                 case 2:
 630                 default:
 631                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 632                 }
 633         }
 634         return (1<<USB_PORT_FEAT_HIGHSPEED);
 635 }
 636
 637 #else
 638
 639 #define ehci_is_TDI(e)                  (0)
 640
 641 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 642 #endif
 643
 644 /*-------------------------------------------------------------------------*/
 645
 646 #ifdef CONFIG_PPC_83xx
 647 /* Some Freescale processors have an erratum in which the TT
 648  * port number in the queue head was 0..N-1 instead of 1..N.
 649  */
 650 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 651 #else
 652 #define ehci_has_fsl_portno_bug(e)              (0)
 653 #endif
 654
 655 /*
 656  * While most USB host controllers implement their registers in
 657  * little-endian format, a minority (celleb companion chip) implement
 658  * them in big endian format.
 659  *
 660  * This attempts to support either format at compile time without a
 661  * runtime penalty, or both formats with the additional overhead
 662  * of checking a flag bit.
 663  */
 664
 665 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 666 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 667 #else
 668 #define ehci_big_endian_mmio(e)         0
 669 #endif
 670
 671 static inline unsigned int ehci_readl (const struct ehci_hcd *ehci,
 672                                        __u32 __iomem * regs)
 673 {
 674 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 675         return ehci_big_endian_mmio(ehci) ?
 676                 readl_be((__force u32 *)regs) :
 677                 readl((__force u32 *)regs);
 678 #else
 679         return readl((__force u32 *)regs);
 680 #endif
 681 }
 682
 683 static inline void ehci_writel (const struct ehci_hcd *ehci,
 684                                 const unsigned int val, __u32 __iomem *regs)
 685 {
 686 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 687         ehci_big_endian_mmio(ehci) ?
 688                 writel_be(val, (__force u32 *)regs) :
 689                 writel(val, (__force u32 *)regs);
 690 #else
 691         writel(val, (__force u32 *)regs);
 692 #endif
 693 }
 694
 695 /*-------------------------------------------------------------------------*/
 696
 697 #ifndef DEBUG
 698 #define STUB_DEBUG_FILES
 699 #endif  /* DEBUG */
 700
 701 /*-------------------------------------------------------------------------*/
 702
 703 #endif /* __LINUX_EHCI_HCD_H */