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[PATCH] Move valid_dma_direction() from x86_64 to generic code
[usb.git] / sound / oss / maestro3.c
blob5548e3cff7ceb4476cd75263ab54cccc01f637f9
1 /*****************************************************************************
2 *
3 * ESS Maestro3/Allegro driver for Linux 2.4.x
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * (c) Copyright 2000 Zach Brown <zab@zabbo.net>
20 *
21 * I need to thank many people for helping make this driver happen.
22 * As always, Eric Brombaugh was a hacking machine and killed many bugs
23 * that I was too dumb to notice. Howard Kim at ESS provided reference boards
24 * and as much docs as he could. Todd and Mick at Dell tested snapshots on
25 * an army of laptops. msw and deviant at Red Hat also humoured me by hanging
26 * their laptops every few hours in the name of science.
27 *
28 * Shouts go out to Mike "DJ XPCom" Ang.
29 *
30 * History
31 * v1.23 - Jun 5 2002 - Michael Olson <olson@cs.odu.edu>
32 * added a module option to allow selection of GPIO pin number
33 * for external amp
34 * v1.22 - Feb 28 2001 - Zach Brown <zab@zabbo.net>
35 * allocate mem at insmod/setup, rather than open
36 * limit pci dma addresses to 28bit, thanks guys.
37 * v1.21 - Feb 04 2001 - Zach Brown <zab@zabbo.net>
38 * fix up really dumb notifier -> suspend oops
39 * v1.20 - Jan 30 2001 - Zach Brown <zab@zabbo.net>
40 * get rid of pm callback and use pci_dev suspend/resume instead
41 * m3_probe cleanups, including pm oops think-o
42 * v1.10 - Jan 6 2001 - Zach Brown <zab@zabbo.net>
43 * revert to lame remap_page_range mmap() just to make it work
44 * record mmap fixed.
45 * fix up incredibly broken open/release resource management
46 * duh. fix record format setting.
47 * add SMP locking and cleanup formatting here and there
48 * v1.00 - Dec 16 2000 - Zach Brown <zab@zabbo.net>
49 * port to sexy 2.4 interfaces
50 * properly align instance allocations so recording works
51 * clean up function namespace a little :/
52 * update PCI IDs based on mail from ESS
53 * arbitrarily bump version number to show its 2.4 now,
54 * 2.2 will stay 0., oss_audio port gets 2.
55 * v0.03 - Nov 05 2000 - Zach Brown <zab@zabbo.net>
56 * disable recording but allow dsp to be opened read
57 * pull out most silly compat defines
58 * v0.02 - Nov 04 2000 - Zach Brown <zab@zabbo.net>
59 * changed clocking setup for m3, slowdown fixed.
60 * codec reset is hopefully reliable now
61 * rudimentary apm/power management makes suspend/resume work
62 * v0.01 - Oct 31 2000 - Zach Brown <zab@zabbo.net>
63 * first release
64 * v0.00 - Sep 09 2000 - Zach Brown <zab@zabbo.net>
65 * first pass derivation from maestro.c
66 *
67 * TODO
68 * in/out allocated contiguously so fullduplex mmap will work?
69 * no beep on init (mute)
70 * resetup msrc data memory if freq changes?
71 *
72 * --
73 *
74 * Allow me to ramble a bit about the m3 architecture. The core of the
75 * chip is the 'assp', the custom ESS dsp that runs the show. It has
76 * a small amount of code and data ram. ESS drops binary dsp code images
77 * on our heads, but we don't get to see specs on the dsp.
78 *
79 * The constant piece of code on the dsp is the 'kernel'. It also has a
80 * chunk of the dsp memory that is statically set aside for its control
81 * info. This is the KDATA defines in maestro3.h. Part of its core
82 * data is a list of code addresses that point to the pieces of DSP code
83 * that it should walk through in its loop. These other pieces of code
84 * do the real work. The kernel presumably jumps into each of them in turn.
85 * These code images tend to have their own data area, and one can have
86 * multiple data areas representing different states for each of the 'client
87 * instance' code portions. There is generally a list in the kernel data
88 * that points to the data instances for a given piece of code.
89 *
90 * We've only been given the binary image for the 'minisrc', mini sample
91 * rate converter. This is rather annoying because it limits the work
92 * we can do on the dsp, but it also greatly simplifies the job of managing
93 * dsp data memory for the code and data for our playing streams :). We
94 * statically allocate the minisrc code into a region we 'know' to be free
95 * based on the map of the binary kernel image we're loading. We also
96 * statically allocate the data areas for the maximum number of pcm streams
97 * we can be dealing with. This max is set by the length of the static list
98 * in the kernel data that records the number of minisrc data regions we
99 * can have. Thats right, all software dsp mixing with static code list
100 * limits. Rock.
101 *
102 * How sound goes in and out is still a relative mystery. It appears
103 * that the dsp has the ability to get input and output through various
104 * 'connections'. To do IO from or to a connection, you put the address
105 * of the minisrc client area in the static kernel data lists for that
106 * input or output. so for pcm -> dsp -> mixer, we put the minisrc data
107 * instance in the DMA list and also in the list for the mixer. I guess
108 * it Just Knows which is in/out, and we give some dma control info that
109 * helps. There are all sorts of cool inputs/outputs that it seems we can't
110 * use without dsp code images that know how to use them.
111 *
112 * So at init time we preload all the memory allocation stuff and set some
113 * system wide parameters. When we really get a sound to play we build
114 * up its minisrc header (stream parameters, buffer addresses, input/output
115 * settings). Then we throw its header on the various lists. We also
116 * tickle some KDATA settings that ask the assp to raise clock interrupts
117 * and do some amount of software mixing before handing data to the ac97.
118 *
119 * Sorry for the vague details. Feel free to ask Eric or myself if you
120 * happen to be trying to use this driver elsewhere. Please accept my
121 * apologies for the quality of the OSS support code, its passed through
122 * too many hands now and desperately wants to be rethought.
123 */
124
125 /*****************************************************************************/
126
127 #include <linux/config.h>
128 #include <linux/module.h>
129 #include <linux/kernel.h>
130 #include <linux/string.h>
131 #include <linux/ctype.h>
132 #include <linux/ioport.h>
133 #include <linux/sched.h>
134 #include <linux/delay.h>
135 #include <linux/sound.h>
136 #include <linux/slab.h>
137 #include <linux/soundcard.h>
138 #include <linux/pci.h>
139 #include <linux/vmalloc.h>
140 #include <linux/init.h>
141 #include <linux/interrupt.h>
142 #include <linux/poll.h>
143 #include <linux/reboot.h>
144 #include <linux/spinlock.h>
145 #include <linux/ac97_codec.h>
146 #include <linux/wait.h>
147 #include <linux/mutex.h>
148
149
150 #include <asm/io.h>
151 #include <asm/dma.h>
152 #include <asm/uaccess.h>
153
154 #include "maestro3.h"
155
156 #define M_DEBUG 1
157
158 #define DRIVER_VERSION "1.23"
159 #define M3_MODULE_NAME "maestro3"
160 #define PFX M3_MODULE_NAME ": "
161
162 #define M3_STATE_MAGIC 0x734d724d
163 #define M3_CARD_MAGIC 0x646e6f50
164
165 #define ESS_FMT_STEREO 0x01
166 #define ESS_FMT_16BIT 0x02
167 #define ESS_FMT_MASK 0x03
168 #define ESS_DAC_SHIFT 0
169 #define ESS_ADC_SHIFT 4
170
171 #define DAC_RUNNING 1
172 #define ADC_RUNNING 2
173
174 #define SND_DEV_DSP16 5
175
176 #ifdef M_DEBUG
177 static int debug;
178 #define DPMOD 1 /* per module load */
179 #define DPSTR 2 /* per 'stream' */
180 #define DPSYS 3 /* per syscall */
181 #define DPCRAP 4 /* stuff the user shouldn't see unless they're really debuggin */
182 #define DPINT 5 /* per interrupt, LOTS */
183 #define DPRINTK(DP, args...) {if (debug >= (DP)) printk(KERN_DEBUG PFX args);}
184 #else
185 #define DPRINTK(x)
186 #endif
187
188 struct m3_list {
189 int curlen;
190 u16 mem_addr;
191 int max;
192 };
193
194 static int external_amp = 1;
195 static int gpio_pin = -1;
196
197 struct m3_state {
198 unsigned int magic;
199 struct m3_card *card;
200 unsigned char fmt, enable;
201
202 int index;
203
204 /* this locks around the oss state in the driver */
205 /* no, this lock is removed - only use card->lock */
206 /* otherwise: against what are you protecting on SMP
207 when irqhandler uses s->lock
208 and m3_assp_read uses card->lock ?
209 */
210 struct mutex open_mutex;
211 wait_queue_head_t open_wait;
212 mode_t open_mode;
213
214 int dev_audio;
215
216 struct assp_instance {
217 u16 code, data;
218 } dac_inst, adc_inst;
219
220 /* should be in dmabuf */
221 unsigned int rateadc, ratedac;
222
223 struct dmabuf {
224 void *rawbuf;
225 unsigned buforder;
226 unsigned numfrag;
227 unsigned fragshift;
228 unsigned hwptr, swptr;
229 unsigned total_bytes;
230 int count;
231 unsigned error; /* over/underrun */
232 wait_queue_head_t wait;
233 /* redundant, but makes calculations easier */
234 unsigned fragsize;
235 unsigned dmasize;
236 unsigned fragsamples;
237 /* OSS stuff */
238 unsigned mapped:1;
239 unsigned ready:1;
240 unsigned endcleared:1;
241 unsigned ossfragshift;
242 int ossmaxfrags;
243 unsigned subdivision;
244 /* new in m3 */
245 int mixer_index, dma_index, msrc_index, adc1_index;
246 int in_lists;
247 /* 2.4.. */
248 dma_addr_t handle;
249
250 } dma_dac, dma_adc;
251 };
252
253 struct m3_card {
254 unsigned int magic;
255
256 struct m3_card *next;
257
258 struct ac97_codec *ac97;
259 spinlock_t ac97_lock;
260
261 int card_type;
262
263 #define NR_DSPS 1
264 #define MAX_DSPS NR_DSPS
265 struct m3_state channels[MAX_DSPS];
266
267 /* this locks around the physical registers on the card */
268 spinlock_t lock;
269
270 /* hardware resources */
271 struct pci_dev *pcidev;
272 u32 iobase;
273 u32 irq;
274
275 int dacs_active;
276
277 int timer_users;
278
279 struct m3_list msrc_list,
280 mixer_list,
281 adc1_list,
282 dma_list;
283
284 /* for storing reset state..*/
285 u8 reset_state;
286
287 u16 *suspend_mem;
288 int in_suspend;
289 wait_queue_head_t suspend_queue;
290 };
291
292 /*
293 * an arbitrary volume we set the internal
294 * volume settings to so that the ac97 volume
295 * range is a little less insane. 0x7fff is
296 * max.
297 */
298 #define ARB_VOLUME ( 0x6800 )
299
300 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
301
302 enum {
303 ESS_ALLEGRO,
304 ESS_MAESTRO3,
305 /*
306 * a maestro3 with 'hardware strapping', only
307 * found inside ESS?
308 */
309 ESS_MAESTRO3HW,
310 };
311
312 static char *card_names[] = {
313 [ESS_ALLEGRO] = "Allegro",
314 [ESS_MAESTRO3] = "Maestro3(i)",
315 [ESS_MAESTRO3HW] = "Maestro3(i)hw"
316 };
317
318 #ifndef PCI_VENDOR_ESS
319 #define PCI_VENDOR_ESS 0x125D
320 #endif
321
322 #define M3_DEVICE(DEV, TYPE) \
323 { \
324 .vendor = PCI_VENDOR_ESS, \
325 .device = DEV, \
326 .subvendor = PCI_ANY_ID, \
327 .subdevice = PCI_ANY_ID, \
328 .class = PCI_CLASS_MULTIMEDIA_AUDIO << 8, \
329 .class_mask = 0xffff << 8, \
330 .driver_data = TYPE, \
331 }
332
333 static struct pci_device_id m3_id_table[] = {
334 M3_DEVICE(0x1988, ESS_ALLEGRO),
335 M3_DEVICE(0x1998, ESS_MAESTRO3),
336 M3_DEVICE(0x199a, ESS_MAESTRO3HW),
337 {0,}
338 };
339
340 MODULE_DEVICE_TABLE (pci, m3_id_table);
341
342 /*
343 * reports seem to indicate that the m3 is limited
344 * to 28bit bus addresses. aaaargggh...
345 */
346 #define M3_PCI_DMA_MASK 0x0fffffff
347
348 static unsigned
349 ld2(unsigned int x)
350 {
351 unsigned r = 0;
352
353 if (x >= 0x10000) {
354 x >>= 16;
355 r += 16;
356 }
357 if (x >= 0x100) {
358 x >>= 8;
359 r += 8;
360 }
361 if (x >= 0x10) {
362 x >>= 4;
363 r += 4;
364 }
365 if (x >= 4) {
366 x >>= 2;
367 r += 2;
368 }
369 if (x >= 2)
370 r++;
371 return r;
372 }
373
374 static struct m3_card *devs;
375
376 /*
377 * I'm not very good at laying out functions in a file :)
378 */
379 static int m3_notifier(struct notifier_block *nb, unsigned long event, void *buf);
380 static int m3_suspend(struct pci_dev *pci_dev, pm_message_t state);
381 static void check_suspend(struct m3_card *card);
382
383 static struct notifier_block m3_reboot_nb = {
384 .notifier_call = m3_notifier,
385 };
386
387 static void m3_outw(struct m3_card *card,
388 u16 value, unsigned long reg)
389 {
390 check_suspend(card);
391 outw(value, card->iobase + reg);
392 }
393
394 static u16 m3_inw(struct m3_card *card, unsigned long reg)
395 {
396 check_suspend(card);
397 return inw(card->iobase + reg);
398 }
399 static void m3_outb(struct m3_card *card,
400 u8 value, unsigned long reg)
401 {
402 check_suspend(card);
403 outb(value, card->iobase + reg);
404 }
405 static u8 m3_inb(struct m3_card *card, unsigned long reg)
406 {
407 check_suspend(card);
408 return inb(card->iobase + reg);
409 }
410
411 /*
412 * access 16bit words to the code or data regions of the dsp's memory.
413 * index addresses 16bit words.
414 */
415 static u16 __m3_assp_read(struct m3_card *card, u16 region, u16 index)
416 {
417 m3_outw(card, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
418 m3_outw(card, index, DSP_PORT_MEMORY_INDEX);
419 return m3_inw(card, DSP_PORT_MEMORY_DATA);
420 }
421 static u16 m3_assp_read(struct m3_card *card, u16 region, u16 index)
422 {
423 unsigned long flags;
424 u16 ret;
425
426 spin_lock_irqsave(&(card->lock), flags);
427 ret = __m3_assp_read(card, region, index);
428 spin_unlock_irqrestore(&(card->lock), flags);
429
430 return ret;
431 }
432
433 static void __m3_assp_write(struct m3_card *card,
434 u16 region, u16 index, u16 data)
435 {
436 m3_outw(card, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
437 m3_outw(card, index, DSP_PORT_MEMORY_INDEX);
438 m3_outw(card, data, DSP_PORT_MEMORY_DATA);
439 }
440 static void m3_assp_write(struct m3_card *card,
441 u16 region, u16 index, u16 data)
442 {
443 unsigned long flags;
444
445 spin_lock_irqsave(&(card->lock), flags);
446 __m3_assp_write(card, region, index, data);
447 spin_unlock_irqrestore(&(card->lock), flags);
448 }
449
450 static void m3_assp_halt(struct m3_card *card)
451 {
452 card->reset_state = m3_inb(card, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
453 mdelay(10);
454 m3_outb(card, card->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
455 }
456
457 static void m3_assp_continue(struct m3_card *card)
458 {
459 m3_outb(card, card->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
460 }
461
462 /*
463 * This makes me sad. the maestro3 has lists
464 * internally that must be packed.. 0 terminates,
465 * apparently, or maybe all unused entries have
466 * to be 0, the lists have static lengths set
467 * by the binary code images.
468 */
469
470 static int m3_add_list(struct m3_card *card,
471 struct m3_list *list, u16 val)
472 {
473 DPRINTK(DPSTR, "adding val 0x%x to list 0x%p at pos %d\n",
474 val, list, list->curlen);
475
476 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
477 list->mem_addr + list->curlen,
478 val);
479
480 return list->curlen++;
481
482 }
483
484 static void m3_remove_list(struct m3_card *card,
485 struct m3_list *list, int index)
486 {
487 u16 val;
488 int lastindex = list->curlen - 1;
489
490 DPRINTK(DPSTR, "removing ind %d from list 0x%p\n",
491 index, list);
492
493 if(index != lastindex) {
494 val = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
495 list->mem_addr + lastindex);
496 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
497 list->mem_addr + index,
498 val);
499 }
500
501 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
502 list->mem_addr + lastindex,
503 0);
504
505 list->curlen--;
506 }
507
508 static void set_fmt(struct m3_state *s, unsigned char mask, unsigned char data)
509 {
510 int tmp;
511
512 s->fmt = (s->fmt & mask) | data;
513
514 tmp = (s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK;
515
516 /* write to 'mono' word */
517 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
518 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 1,
519 (tmp & ESS_FMT_STEREO) ? 0 : 1);
520 /* write to '8bit' word */
521 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
522 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 2,
523 (tmp & ESS_FMT_16BIT) ? 0 : 1);
524
525 tmp = (s->fmt >> ESS_ADC_SHIFT) & ESS_FMT_MASK;
526
527 /* write to 'mono' word */
528 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
529 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 1,
530 (tmp & ESS_FMT_STEREO) ? 0 : 1);
531 /* write to '8bit' word */
532 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
533 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 2,
534 (tmp & ESS_FMT_16BIT) ? 0 : 1);
535 }
536
537 static void set_dac_rate(struct m3_state *s, unsigned int rate)
538 {
539 u32 freq;
540
541 if (rate > 48000)
542 rate = 48000;
543 if (rate < 8000)
544 rate = 8000;
545
546 s->ratedac = rate;
547
548 freq = ((rate << 15) + 24000 ) / 48000;
549 if(freq)
550 freq--;
551
552 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
553 s->dac_inst.data + CDATA_FREQUENCY,
554 freq);
555 }
556
557 static void set_adc_rate(struct m3_state *s, unsigned int rate)
558 {
559 u32 freq;
560
561 if (rate > 48000)
562 rate = 48000;
563 if (rate < 8000)
564 rate = 8000;
565
566 s->rateadc = rate;
567
568 freq = ((rate << 15) + 24000 ) / 48000;
569 if(freq)
570 freq--;
571
572 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
573 s->adc_inst.data + CDATA_FREQUENCY,
574 freq);
575 }
576
577 static void inc_timer_users(struct m3_card *card)
578 {
579 unsigned long flags;
580
581 spin_lock_irqsave(&card->lock, flags);
582
583 card->timer_users++;
584 DPRINTK(DPSYS, "inc timer users now %d\n",
585 card->timer_users);
586 if(card->timer_users != 1)
587 goto out;
588
589 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
590 KDATA_TIMER_COUNT_RELOAD,
591 240 ) ;
592
593 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
594 KDATA_TIMER_COUNT_CURRENT,
595 240 ) ;
596
597 m3_outw(card,
598 m3_inw(card, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
599 HOST_INT_CTRL);
600 out:
601 spin_unlock_irqrestore(&card->lock, flags);
602 }
603
604 static void dec_timer_users(struct m3_card *card)
605 {
606 unsigned long flags;
607
608 spin_lock_irqsave(&card->lock, flags);
609
610 card->timer_users--;
611 DPRINTK(DPSYS, "dec timer users now %d\n",
612 card->timer_users);
613 if(card->timer_users > 0 )
614 goto out;
615
616 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
617 KDATA_TIMER_COUNT_RELOAD,
618 0 ) ;
619
620 __m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
621 KDATA_TIMER_COUNT_CURRENT,
622 0 ) ;
623
624 m3_outw(card, m3_inw(card, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
625 HOST_INT_CTRL);
626 out:
627 spin_unlock_irqrestore(&card->lock, flags);
628 }
629
630 /*
631 * {start,stop}_{adc,dac} should be called
632 * while holding the 'state' lock and they
633 * will try to grab the 'card' lock..
634 */
635 static void stop_adc(struct m3_state *s)
636 {
637 if (! (s->enable & ADC_RUNNING))
638 return;
639
640 s->enable &= ~ADC_RUNNING;
641 dec_timer_users(s->card);
642
643 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
644 s->adc_inst.data + CDATA_INSTANCE_READY, 0);
645
646 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
647 KDATA_ADC1_REQUEST, 0);
648 }
649
650 static void stop_dac(struct m3_state *s)
651 {
652 if (! (s->enable & DAC_RUNNING))
653 return;
654
655 DPRINTK(DPSYS, "stop_dac()\n");
656
657 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
658 s->dac_inst.data + CDATA_INSTANCE_READY, 0);
659
660 s->enable &= ~DAC_RUNNING;
661 s->card->dacs_active--;
662 dec_timer_users(s->card);
663
664 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
665 KDATA_MIXER_TASK_NUMBER,
666 s->card->dacs_active ) ;
667 }
668
669 static void start_dac(struct m3_state *s)
670 {
671 if( (!s->dma_dac.mapped && s->dma_dac.count < 1) ||
672 !s->dma_dac.ready ||
673 (s->enable & DAC_RUNNING))
674 return;
675
676 DPRINTK(DPSYS, "start_dac()\n");
677
678 s->enable |= DAC_RUNNING;
679 s->card->dacs_active++;
680 inc_timer_users(s->card);
681
682 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
683 s->dac_inst.data + CDATA_INSTANCE_READY, 1);
684
685 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
686 KDATA_MIXER_TASK_NUMBER,
687 s->card->dacs_active ) ;
688 }
689
690 static void start_adc(struct m3_state *s)
691 {
692 if ((! s->dma_adc.mapped &&
693 s->dma_adc.count >= (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
694 || !s->dma_adc.ready
695 || (s->enable & ADC_RUNNING) )
696 return;
697
698 DPRINTK(DPSYS, "start_adc()\n");
699
700 s->enable |= ADC_RUNNING;
701 inc_timer_users(s->card);
702
703 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
704 KDATA_ADC1_REQUEST, 1);
705
706 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
707 s->adc_inst.data + CDATA_INSTANCE_READY, 1);
708 }
709
710 static struct play_vals {
711 u16 addr, val;
712 } pv[] = {
713 {CDATA_LEFT_VOLUME, ARB_VOLUME},
714 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
715 {SRC3_DIRECTION_OFFSET, 0} ,
716 /* +1, +2 are stereo/16 bit */
717 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
718 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
719 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
720 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
721 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
722 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
723 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
724 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
725 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
726 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
727 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
728 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
729 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
730 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
731 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
732 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
733 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
734 };
735
736
737 /* the mode passed should be already shifted and masked */
738 static void m3_play_setup(struct m3_state *s, int mode, u32 rate, void *buffer, int size)
739 {
740 int dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
741 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
742 int dsp_in_buffer = s->dac_inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
743 int dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
744 struct dmabuf *db = &s->dma_dac;
745 int i;
746
747 DPRINTK(DPSTR, "mode=%d rate=%d buf=%p len=%d.\n",
748 mode, rate, buffer, size);
749
750 #define LO(x) ((x) & 0xffff)
751 #define HI(x) LO((x) >> 16)
752
753 /* host dma buffer pointers */
754
755 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
756 s->dac_inst.data + CDATA_HOST_SRC_ADDRL,
757 LO(virt_to_bus(buffer)));
758
759 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
760 s->dac_inst.data + CDATA_HOST_SRC_ADDRH,
761 HI(virt_to_bus(buffer)));
762
763 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
764 s->dac_inst.data + CDATA_HOST_SRC_END_PLUS_1L,
765 LO(virt_to_bus(buffer) + size));
766
767 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
768 s->dac_inst.data + CDATA_HOST_SRC_END_PLUS_1H,
769 HI(virt_to_bus(buffer) + size));
770
771 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
772 s->dac_inst.data + CDATA_HOST_SRC_CURRENTL,
773 LO(virt_to_bus(buffer)));
774
775 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
776 s->dac_inst.data + CDATA_HOST_SRC_CURRENTH,
777 HI(virt_to_bus(buffer)));
778 #undef LO
779 #undef HI
780
781 /* dsp buffers */
782
783 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
784 s->dac_inst.data + CDATA_IN_BUF_BEGIN,
785 dsp_in_buffer);
786
787 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
788 s->dac_inst.data + CDATA_IN_BUF_END_PLUS_1,
789 dsp_in_buffer + (dsp_in_size / 2));
790
791 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
792 s->dac_inst.data + CDATA_IN_BUF_HEAD,
793 dsp_in_buffer);
794
795 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
796 s->dac_inst.data + CDATA_IN_BUF_TAIL,
797 dsp_in_buffer);
798
799 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
800 s->dac_inst.data + CDATA_OUT_BUF_BEGIN,
801 dsp_out_buffer);
802
803 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
804 s->dac_inst.data + CDATA_OUT_BUF_END_PLUS_1,
805 dsp_out_buffer + (dsp_out_size / 2));
806
807 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
808 s->dac_inst.data + CDATA_OUT_BUF_HEAD,
809 dsp_out_buffer);
810
811 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
812 s->dac_inst.data + CDATA_OUT_BUF_TAIL,
813 dsp_out_buffer);
814
815 /*
816 * some per client initializers
817 */
818
819 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
820 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 12,
821 s->dac_inst.data + 40 + 8);
822
823 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
824 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 19,
825 s->dac_inst.code + MINISRC_COEF_LOC);
826
827 /* enable or disable low pass filter? */
828 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
829 s->dac_inst.data + SRC3_DIRECTION_OFFSET + 22,
830 s->ratedac > 45000 ? 0xff : 0 );
831
832 /* tell it which way dma is going? */
833 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
834 s->dac_inst.data + CDATA_DMA_CONTROL,
835 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
836
837 /*
838 * set an armload of static initializers
839 */
840 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++)
841 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
842 s->dac_inst.data + pv[i].addr, pv[i].val);
843
844 /*
845 * put us in the lists if we're not already there
846 */
847
848 if(db->in_lists == 0) {
849
850 db->msrc_index = m3_add_list(s->card, &s->card->msrc_list,
851 s->dac_inst.data >> DP_SHIFT_COUNT);
852
853 db->dma_index = m3_add_list(s->card, &s->card->dma_list,
854 s->dac_inst.data >> DP_SHIFT_COUNT);
855
856 db->mixer_index = m3_add_list(s->card, &s->card->mixer_list,
857 s->dac_inst.data >> DP_SHIFT_COUNT);
858
859 db->in_lists = 1;
860 }
861
862 set_dac_rate(s,rate);
863 start_dac(s);
864 }
865
866 /*
867 * Native record driver
868 */
869 static struct rec_vals {
870 u16 addr, val;
871 } rv[] = {
872 {CDATA_LEFT_VOLUME, ARB_VOLUME},
873 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
874 {SRC3_DIRECTION_OFFSET, 1} ,
875 /* +1, +2 are stereo/16 bit */
876 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
877 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
878 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
879 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
880 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
881 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
882 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
883 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
884 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
885 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
886 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
887 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
888 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
889 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
890 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
891 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
892 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
893 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
894 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
895 };
896
897 /* again, passed mode is alrady shifted/masked */
898 static void m3_rec_setup(struct m3_state *s, int mode, u32 rate, void *buffer, int size)
899 {
900 int dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
901 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
902 int dsp_in_buffer = s->adc_inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
903 int dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
904 struct dmabuf *db = &s->dma_adc;
905 int i;
906
907 DPRINTK(DPSTR, "rec_setup mode=%d rate=%d buf=%p len=%d.\n",
908 mode, rate, buffer, size);
909
910 #define LO(x) ((x) & 0xffff)
911 #define HI(x) LO((x) >> 16)
912
913 /* host dma buffer pointers */
914
915 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
916 s->adc_inst.data + CDATA_HOST_SRC_ADDRL,
917 LO(virt_to_bus(buffer)));
918
919 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
920 s->adc_inst.data + CDATA_HOST_SRC_ADDRH,
921 HI(virt_to_bus(buffer)));
922
923 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
924 s->adc_inst.data + CDATA_HOST_SRC_END_PLUS_1L,
925 LO(virt_to_bus(buffer) + size));
926
927 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
928 s->adc_inst.data + CDATA_HOST_SRC_END_PLUS_1H,
929 HI(virt_to_bus(buffer) + size));
930
931 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
932 s->adc_inst.data + CDATA_HOST_SRC_CURRENTL,
933 LO(virt_to_bus(buffer)));
934
935 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
936 s->adc_inst.data + CDATA_HOST_SRC_CURRENTH,
937 HI(virt_to_bus(buffer)));
938 #undef LO
939 #undef HI
940
941 /* dsp buffers */
942
943 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
944 s->adc_inst.data + CDATA_IN_BUF_BEGIN,
945 dsp_in_buffer);
946
947 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
948 s->adc_inst.data + CDATA_IN_BUF_END_PLUS_1,
949 dsp_in_buffer + (dsp_in_size / 2));
950
951 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
952 s->adc_inst.data + CDATA_IN_BUF_HEAD,
953 dsp_in_buffer);
954
955 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
956 s->adc_inst.data + CDATA_IN_BUF_TAIL,
957 dsp_in_buffer);
958
959 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
960 s->adc_inst.data + CDATA_OUT_BUF_BEGIN,
961 dsp_out_buffer);
962
963 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
964 s->adc_inst.data + CDATA_OUT_BUF_END_PLUS_1,
965 dsp_out_buffer + (dsp_out_size / 2));
966
967 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
968 s->adc_inst.data + CDATA_OUT_BUF_HEAD,
969 dsp_out_buffer);
970
971 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
972 s->adc_inst.data + CDATA_OUT_BUF_TAIL,
973 dsp_out_buffer);
974
975 /*
976 * some per client initializers
977 */
978
979 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
980 s->adc_inst.data + SRC3_DIRECTION_OFFSET + 12,
981 s->adc_inst.data + 40 + 8);
982
983 /* tell it which way dma is going? */
984 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
985 s->adc_inst.data + CDATA_DMA_CONTROL,
986 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
987 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
988
989 /*
990 * set an armload of static initializers
991 */
992 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++)
993 m3_assp_write(s->card, MEMTYPE_INTERNAL_DATA,
994 s->adc_inst.data + rv[i].addr, rv[i].val);
995
996 /*
997 * put us in the lists if we're not already there
998 */
999
1000 if(db->in_lists == 0) {
1001
1002 db->adc1_index = m3_add_list(s->card, &s->card->adc1_list,
1003 s->adc_inst.data >> DP_SHIFT_COUNT);
1004
1005 db->dma_index = m3_add_list(s->card, &s->card->dma_list,
1006 s->adc_inst.data >> DP_SHIFT_COUNT);
1007
1008 db->msrc_index = m3_add_list(s->card, &s->card->msrc_list,
1009 s->adc_inst.data >> DP_SHIFT_COUNT);
1010
1011 db->in_lists = 1;
1012 }
1013
1014 set_adc_rate(s,rate);
1015 start_adc(s);
1016 }
1017 /* --------------------------------------------------------------------- */
1018
1019 static void set_dmaa(struct m3_state *s, unsigned int addr, unsigned int count)
1020 {
1021 DPRINTK(DPINT,"set_dmaa??\n");
1022 }
1023
1024 static void set_dmac(struct m3_state *s, unsigned int addr, unsigned int count)
1025 {
1026 DPRINTK(DPINT,"set_dmac??\n");
1027 }
1028
1029 static u32 get_dma_pos(struct m3_card *card,
1030 int instance_addr)
1031 {
1032 u16 hi = 0, lo = 0;
1033 int retry = 10;
1034
1035 /*
1036 * try and get a valid answer
1037 */
1038 while(retry--) {
1039 hi = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1040 instance_addr + CDATA_HOST_SRC_CURRENTH);
1041
1042 lo = m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1043 instance_addr + CDATA_HOST_SRC_CURRENTL);
1044
1045 if(hi == m3_assp_read(card, MEMTYPE_INTERNAL_DATA,
1046 instance_addr + CDATA_HOST_SRC_CURRENTH))
1047 break;
1048 }
1049 return lo | (hi<<16);
1050 }
1051
1052 static u32 get_dmaa(struct m3_state *s)
1053 {
1054 u32 offset;
1055
1056 offset = get_dma_pos(s->card, s->dac_inst.data) -
1057 virt_to_bus(s->dma_dac.rawbuf);
1058
1059 DPRINTK(DPINT,"get_dmaa: 0x%08x\n",offset);
1060
1061 return offset;
1062 }
1063
1064 static u32 get_dmac(struct m3_state *s)
1065 {
1066 u32 offset;
1067
1068 offset = get_dma_pos(s->card, s->adc_inst.data) -
1069 virt_to_bus(s->dma_adc.rawbuf);
1070
1071 DPRINTK(DPINT,"get_dmac: 0x%08x\n",offset);
1072
1073 return offset;
1074
1075 }
1076
1077 static int
1078 prog_dmabuf(struct m3_state *s, unsigned rec)
1079 {
1080 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1081 unsigned rate = rec ? s->rateadc : s->ratedac;
1082 unsigned bytepersec;
1083 unsigned bufs;
1084 unsigned char fmt;
1085 unsigned long flags;
1086
1087 spin_lock_irqsave(&s->card->lock, flags);
1088
1089 fmt = s->fmt;
1090 if (rec) {
1091 stop_adc(s);
1092 fmt >>= ESS_ADC_SHIFT;
1093 } else {
1094 stop_dac(s);
1095 fmt >>= ESS_DAC_SHIFT;
1096 }
1097 fmt &= ESS_FMT_MASK;
1098
1099 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1100
1101 bytepersec = rate << sample_shift[fmt];
1102 bufs = PAGE_SIZE << db->buforder;
1103 if (db->ossfragshift) {
1104 if ((1000 << db->ossfragshift) < bytepersec)
1105 db->fragshift = ld2(bytepersec/1000);
1106 else
1107 db->fragshift = db->ossfragshift;
1108 } else {
1109 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1110 if (db->fragshift < 3)
1111 db->fragshift = 3;
1112 }
1113 db->numfrag = bufs >> db->fragshift;
1114 while (db->numfrag < 4 && db->fragshift > 3) {
1115 db->fragshift--;
1116 db->numfrag = bufs >> db->fragshift;
1117 }
1118 db->fragsize = 1 << db->fragshift;
1119 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1120 db->numfrag = db->ossmaxfrags;
1121 db->fragsamples = db->fragsize >> sample_shift[fmt];
1122 db->dmasize = db->numfrag << db->fragshift;
1123
1124 DPRINTK(DPSTR,"prog_dmabuf: numfrag: %d fragsize: %d dmasize: %d\n",db->numfrag,db->fragsize,db->dmasize);
1125
1126 memset(db->rawbuf, (fmt & ESS_FMT_16BIT) ? 0 : 0x80, db->dmasize);
1127
1128 if (rec)
1129 m3_rec_setup(s, fmt, s->rateadc, db->rawbuf, db->dmasize);
1130 else
1131 m3_play_setup(s, fmt, s->ratedac, db->rawbuf, db->dmasize);
1132
1133 db->ready = 1;
1134
1135 spin_unlock_irqrestore(&s->card->lock, flags);
1136
1137 return 0;
1138 }
1139
1140 static void clear_advance(struct m3_state *s)
1141 {
1142 unsigned char c = ((s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_16BIT) ? 0 : 0x80;
1143
1144 unsigned char *buf = s->dma_dac.rawbuf;
1145 unsigned bsize = s->dma_dac.dmasize;
1146 unsigned bptr = s->dma_dac.swptr;
1147 unsigned len = s->dma_dac.fragsize;
1148
1149 if (bptr + len > bsize) {
1150 unsigned x = bsize - bptr;
1151 memset(buf + bptr, c, x);
1152 /* account for wrapping? */
1153 bptr = 0;
1154 len -= x;
1155 }
1156 memset(buf + bptr, c, len);
1157 }
1158
1159 /* call with spinlock held! */
1160 static void m3_update_ptr(struct m3_state *s)
1161 {
1162 unsigned hwptr;
1163 int diff;
1164
1165 /* update ADC pointer */
1166 if (s->dma_adc.ready) {
1167 hwptr = get_dmac(s) % s->dma_adc.dmasize;
1168 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1169 s->dma_adc.hwptr = hwptr;
1170 s->dma_adc.total_bytes += diff;
1171 s->dma_adc.count += diff;
1172 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1173 wake_up(&s->dma_adc.wait);
1174 if (!s->dma_adc.mapped) {
1175 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1176 stop_adc(s);
1177 /* brute force everyone back in sync, sigh */
1178 s->dma_adc.count = 0;
1179 s->dma_adc.swptr = 0;
1180 s->dma_adc.hwptr = 0;
1181 s->dma_adc.error++;
1182 }
1183 }
1184 }
1185 /* update DAC pointer */
1186 if (s->dma_dac.ready) {
1187 hwptr = get_dmaa(s) % s->dma_dac.dmasize;
1188 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1189
1190 DPRINTK(DPINT,"updating dac: hwptr: %6d diff: %6d count: %6d\n",
1191 hwptr,diff,s->dma_dac.count);
1192
1193 s->dma_dac.hwptr = hwptr;
1194 s->dma_dac.total_bytes += diff;
1195
1196 if (s->dma_dac.mapped) {
1197
1198 s->dma_dac.count += diff;
1199 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize) {
1200 wake_up(&s->dma_dac.wait);
1201 }
1202 } else {
1203
1204 s->dma_dac.count -= diff;
1205
1206 if (s->dma_dac.count <= 0) {
1207 DPRINTK(DPCRAP,"underflow! diff: %d (0x%x) count: %d (0x%x) hw: %d (0x%x) sw: %d (0x%x)\n",
1208 diff, diff,
1209 s->dma_dac.count,
1210 s->dma_dac.count,
1211 hwptr, hwptr,
1212 s->dma_dac.swptr,
1213 s->dma_dac.swptr);
1214 stop_dac(s);
1215 /* brute force everyone back in sync, sigh */
1216 s->dma_dac.count = 0;
1217 s->dma_dac.swptr = hwptr;
1218 s->dma_dac.error++;
1219 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1220 clear_advance(s);
1221 s->dma_dac.endcleared = 1;
1222 }
1223 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize) {
1224 wake_up(&s->dma_dac.wait);
1225 DPRINTK(DPINT,"waking up DAC count: %d sw: %d hw: %d\n",
1226 s->dma_dac.count, s->dma_dac.swptr, hwptr);
1227 }
1228 }
1229 }
1230 }
1231
1232 static irqreturn_t m3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1233 {
1234 struct m3_card *c = (struct m3_card *)dev_id;
1235 struct m3_state *s = &c->channels[0];
1236 u8 status;
1237
1238 status = inb(c->iobase+0x1A);
1239
1240 if(status == 0xff)
1241 return IRQ_NONE;
1242
1243 /* presumably acking the ints? */
1244 outw(status, c->iobase+0x1A);
1245
1246 if(c->in_suspend)
1247 return IRQ_HANDLED;
1248
1249 /*
1250 * ack an assp int if its running
1251 * and has an int pending
1252 */
1253 if( status & ASSP_INT_PENDING) {
1254 u8 ctl = inb(c->iobase + ASSP_CONTROL_B);
1255 if( !(ctl & STOP_ASSP_CLOCK)) {
1256 ctl = inb(c->iobase + ASSP_HOST_INT_STATUS );
1257 if(ctl & DSP2HOST_REQ_TIMER) {
1258 outb( DSP2HOST_REQ_TIMER, c->iobase + ASSP_HOST_INT_STATUS);
1259 /* update adc/dac info if it was a timer int */
1260 spin_lock(&c->lock);
1261 m3_update_ptr(s);
1262 spin_unlock(&c->lock);
1263 }
1264 }
1265 }
1266
1267 /* XXX is this needed? */
1268 if(status & 0x40)
1269 outb(0x40, c->iobase+0x1A);
1270 return IRQ_HANDLED;
1271 }
1272
1273
1274 /* --------------------------------------------------------------------- */
1275
1276 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value in %s\n";
1277
1278 #define VALIDATE_MAGIC(FOO,MAG) \
1279 ({ \
1280 if (!(FOO) || (FOO)->magic != MAG) { \
1281 printk(invalid_magic,__FUNCTION__); \
1282 return -ENXIO; \
1283 } \
1284 })
1285
1286 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,M3_STATE_MAGIC)
1287 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,M3_CARD_MAGIC)
1288
1289 /* --------------------------------------------------------------------- */
1290
1291 static int drain_dac(struct m3_state *s, int nonblock)
1292 {
1293 DECLARE_WAITQUEUE(wait,current);
1294 unsigned long flags;
1295 int count;
1296 signed long tmo;
1297
1298 if (s->dma_dac.mapped || !s->dma_dac.ready)
1299 return 0;
1300 set_current_state(TASK_INTERRUPTIBLE);
1301 add_wait_queue(&s->dma_dac.wait, &wait);
1302 for (;;) {
1303 spin_lock_irqsave(&s->card->lock, flags);
1304 count = s->dma_dac.count;
1305 spin_unlock_irqrestore(&s->card->lock, flags);
1306 if (count <= 0)
1307 break;
1308 if (signal_pending(current))
1309 break;
1310 if (nonblock) {
1311 remove_wait_queue(&s->dma_dac.wait, &wait);
1312 set_current_state(TASK_RUNNING);
1313 return -EBUSY;
1314 }
1315 tmo = (count * HZ) / s->ratedac;
1316 tmo >>= sample_shift[(s->fmt >> ESS_DAC_SHIFT) & ESS_FMT_MASK];
1317 /* XXX this is just broken. someone is waking us up alot, or schedule_timeout is broken.
1318 or something. who cares. - zach */
1319 if (!schedule_timeout(tmo ? tmo : 1) && tmo)
1320 DPRINTK(DPCRAP,"dma timed out?? %ld\n",jiffies);
1321 }
1322 remove_wait_queue(&s->dma_dac.wait, &wait);
1323 set_current_state(TASK_RUNNING);
1324 if (signal_pending(current))
1325 return -ERESTARTSYS;
1326 return 0;
1327 }
1328
1329 static ssize_t m3_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1330 {
1331 struct m3_state *s = (struct m3_state *)file->private_data;
1332 ssize_t ret;
1333 unsigned long flags;
1334 unsigned swptr;
1335 int cnt;
1336
1337 VALIDATE_STATE(s);
1338 if (s->dma_adc.mapped)
1339 return -ENXIO;
1340 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1341 return ret;
1342 if (!access_ok(VERIFY_WRITE, buffer, count))
1343 return -EFAULT;
1344 ret = 0;
1345
1346 spin_lock_irqsave(&s->card->lock, flags);
1347
1348 while (count > 0) {
1349 int timed_out;
1350
1351 swptr = s->dma_adc.swptr;
1352 cnt = s->dma_adc.dmasize-swptr;
1353 if (s->dma_adc.count < cnt)
1354 cnt = s->dma_adc.count;
1355
1356 if (cnt > count)
1357 cnt = count;
1358
1359 if (cnt <= 0) {
1360 start_adc(s);
1361 if (file->f_flags & O_NONBLOCK)
1362 {
1363 ret = ret ? ret : -EAGAIN;
1364 goto out;
1365 }
1366
1367 spin_unlock_irqrestore(&s->card->lock, flags);
1368 timed_out = interruptible_sleep_on_timeout(&s->dma_adc.wait, HZ) == 0;
1369 spin_lock_irqsave(&s->card->lock, flags);
1370
1371 if(timed_out) {
1372 printk("read: chip lockup? dmasz %u fragsz %u count %u hwptr %u swptr %u\n",
1373 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1374 s->dma_adc.hwptr, s->dma_adc.swptr);
1375 stop_adc(s);
1376 set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
1377 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1378 }
1379 if (signal_pending(current))
1380 {
1381 ret = ret ? ret : -ERESTARTSYS;
1382 goto out;
1383 }
1384 continue;
1385 }
1386
1387 spin_unlock_irqrestore(&s->card->lock, flags);
1388 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1389 ret = ret ? ret : -EFAULT;
1390 return ret;
1391 }
1392 spin_lock_irqsave(&s->card->lock, flags);
1393
1394 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1395 s->dma_adc.swptr = swptr;
1396 s->dma_adc.count -= cnt;
1397 count -= cnt;
1398 buffer += cnt;
1399 ret += cnt;
1400 start_adc(s);
1401 }
1402
1403 out:
1404 spin_unlock_irqrestore(&s->card->lock, flags);
1405 return ret;
1406 }
1407
1408 static ssize_t m3_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1409 {
1410 struct m3_state *s = (struct m3_state *)file->private_data;
1411 ssize_t ret;
1412 unsigned long flags;
1413 unsigned swptr;
1414 int cnt;
1415
1416 VALIDATE_STATE(s);
1417 if (s->dma_dac.mapped)
1418 return -ENXIO;
1419 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1420 return ret;
1421 if (!access_ok(VERIFY_READ, buffer, count))
1422 return -EFAULT;
1423 ret = 0;
1424
1425 spin_lock_irqsave(&s->card->lock, flags);
1426
1427 while (count > 0) {
1428 int timed_out;
1429
1430 if (s->dma_dac.count < 0) {
1431 s->dma_dac.count = 0;
1432 s->dma_dac.swptr = s->dma_dac.hwptr;
1433 }
1434 swptr = s->dma_dac.swptr;
1435
1436 cnt = s->dma_dac.dmasize-swptr;
1437
1438 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1439 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1440
1441
1442 if (cnt > count)
1443 cnt = count;
1444
1445 if (cnt <= 0) {
1446 start_dac(s);
1447 if (file->f_flags & O_NONBLOCK) {
1448 if(!ret) ret = -EAGAIN;
1449 goto out;
1450 }
1451 spin_unlock_irqrestore(&s->card->lock, flags);
1452 timed_out = interruptible_sleep_on_timeout(&s->dma_dac.wait, HZ) == 0;
1453 spin_lock_irqsave(&s->card->lock, flags);
1454 if(timed_out) {
1455 DPRINTK(DPCRAP,"write: chip lockup? dmasz %u fragsz %u count %u hwptr %u swptr %u\n",
1456 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
1457 s->dma_dac.hwptr, s->dma_dac.swptr);
1458 stop_dac(s);
1459 set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
1460 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
1461 }
1462 if (signal_pending(current)) {
1463 if (!ret) ret = -ERESTARTSYS;
1464 goto out;
1465 }
1466 continue;
1467 }
1468 spin_unlock_irqrestore(&s->card->lock, flags);
1469 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1470 if (!ret) ret = -EFAULT;
1471 return ret;
1472 }
1473 spin_lock_irqsave(&s->card->lock, flags);
1474
1475 DPRINTK(DPSYS,"wrote %6d bytes at sw: %6d cnt: %6d while hw: %6d\n",
1476 cnt, swptr, s->dma_dac.count, s->dma_dac.hwptr);
1477
1478 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1479
1480 s->dma_dac.swptr = swptr;
1481 s->dma_dac.count += cnt;
1482 s->dma_dac.endcleared = 0;
1483 count -= cnt;
1484 buffer += cnt;
1485 ret += cnt;
1486 start_dac(s);
1487 }
1488 out:
1489 spin_unlock_irqrestore(&s->card->lock, flags);
1490 return ret;
1491 }
1492
1493 static unsigned int m3_poll(struct file *file, struct poll_table_struct *wait)
1494 {
1495 struct m3_state *s = (struct m3_state *)file->private_data;
1496 unsigned long flags;
1497 unsigned int mask = 0;
1498
1499 VALIDATE_STATE(s);
1500 if (file->f_mode & FMODE_WRITE)
1501 poll_wait(file, &s->dma_dac.wait, wait);
1502 if (file->f_mode & FMODE_READ)
1503 poll_wait(file, &s->dma_adc.wait, wait);
1504
1505 spin_lock_irqsave(&s->card->lock, flags);
1506 m3_update_ptr(s);
1507
1508 if (file->f_mode & FMODE_READ) {
1509 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1510 mask |= POLLIN | POLLRDNORM;
1511 }
1512 if (file->f_mode & FMODE_WRITE) {
1513 if (s->dma_dac.mapped) {
1514 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1515 mask |= POLLOUT | POLLWRNORM;
1516 } else {
1517 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
1518 mask |= POLLOUT | POLLWRNORM;
1519 }
1520 }
1521
1522 spin_unlock_irqrestore(&s->card->lock, flags);
1523 return mask;
1524 }
1525
1526 static int m3_mmap(struct file *file, struct vm_area_struct *vma)
1527 {
1528 struct m3_state *s = (struct m3_state *)file->private_data;
1529 unsigned long max_size, size, start, offset;
1530 struct dmabuf *db;
1531 int ret = -EINVAL;
1532
1533 VALIDATE_STATE(s);
1534 if (vma->vm_flags & VM_WRITE) {
1535 if ((ret = prog_dmabuf(s, 0)) != 0)
1536 return ret;
1537 db = &s->dma_dac;
1538 } else
1539 if (vma->vm_flags & VM_READ) {
1540 if ((ret = prog_dmabuf(s, 1)) != 0)
1541 return ret;
1542 db = &s->dma_adc;
1543 } else
1544 return -EINVAL;
1545
1546 max_size = db->dmasize;
1547
1548 start = vma->vm_start;
1549 offset = (vma->vm_pgoff << PAGE_SHIFT);
1550 size = vma->vm_end - vma->vm_start;
1551
1552 if(size > max_size)
1553 goto out;
1554 if(offset > max_size - size)
1555 goto out;
1556
1557 /*
1558 * this will be ->nopage() once I can
1559 * ask Jeff what the hell I'm doing wrong.
1560 */
1561 ret = -EAGAIN;
1562 if (remap_pfn_range(vma, vma->vm_start,
1563 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1564 size, vma->vm_page_prot))
1565 goto out;
1566
1567 db->mapped = 1;
1568 ret = 0;
1569
1570 out:
1571 return ret;
1572 }
1573
1574 /*
1575 * this function is a disaster..
1576 */
1577 #define get_user_ret(x, ptr, ret) ({ if(get_user(x, ptr)) return ret; })
1578 static int m3_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1579 {
1580 struct m3_state *s = (struct m3_state *)file->private_data;
1581 struct m3_card *card=s->card;
1582 unsigned long flags;
1583 audio_buf_info abinfo;
1584 count_info cinfo;
1585 int val, mapped, ret;
1586 unsigned char fmtm, fmtd;
1587 void __user *argp = (void __user *)arg;
1588 int __user *p = argp;
1589
1590 VALIDATE_STATE(s);
1591
1592 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1593 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1594
1595 DPRINTK(DPSYS,"m3_ioctl: cmd %d\n", cmd);
1596
1597 switch (cmd) {
1598 case OSS_GETVERSION:
1599 return put_user(SOUND_VERSION, p);
1600
1601 case SNDCTL_DSP_SYNC:
1602 if (file->f_mode & FMODE_WRITE)
1603 return drain_dac(s, file->f_flags & O_NONBLOCK);
1604 return 0;
1605
1606 case SNDCTL_DSP_SETDUPLEX:
1607 /* XXX fix */
1608 return 0;
1609
1610 case SNDCTL_DSP_GETCAPS:
1611 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1612
1613 case SNDCTL_DSP_RESET:
1614 spin_lock_irqsave(&card->lock, flags);
1615 if (file->f_mode & FMODE_WRITE) {
1616 stop_dac(s);
1617 synchronize_irq(s->card->pcidev->irq);
1618 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1619 }
1620 if (file->f_mode & FMODE_READ) {
1621 stop_adc(s);
1622 synchronize_irq(s->card->pcidev->irq);
1623 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1624 }
1625 spin_unlock_irqrestore(&card->lock, flags);
1626 return 0;
1627
1628 case SNDCTL_DSP_SPEED:
1629 get_user_ret(val, p, -EFAULT);
1630 spin_lock_irqsave(&card->lock, flags);
1631 if (val >= 0) {
1632 if (file->f_mode & FMODE_READ) {
1633 stop_adc(s);
1634 s->dma_adc.ready = 0;
1635 set_adc_rate(s, val);
1636 }
1637 if (file->f_mode & FMODE_WRITE) {
1638 stop_dac(s);
1639 s->dma_dac.ready = 0;
1640 set_dac_rate(s, val);
1641 }
1642 }
1643 spin_unlock_irqrestore(&card->lock, flags);
1644 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1645
1646 case SNDCTL_DSP_STEREO:
1647 get_user_ret(val, p, -EFAULT);
1648 spin_lock_irqsave(&card->lock, flags);
1649 fmtd = 0;
1650 fmtm = ~0;
1651 if (file->f_mode & FMODE_READ) {
1652 stop_adc(s);
1653 s->dma_adc.ready = 0;
1654 if (val)
1655 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
1656 else
1657 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
1658 }
1659 if (file->f_mode & FMODE_WRITE) {
1660 stop_dac(s);
1661 s->dma_dac.ready = 0;
1662 if (val)
1663 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
1664 else
1665 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
1666 }
1667 set_fmt(s, fmtm, fmtd);
1668 spin_unlock_irqrestore(&card->lock, flags);
1669 return 0;
1670
1671 case SNDCTL_DSP_CHANNELS:
1672 get_user_ret(val, p, -EFAULT);
1673 spin_lock_irqsave(&card->lock, flags);
1674 if (val != 0) {
1675 fmtd = 0;
1676 fmtm = ~0;
1677 if (file->f_mode & FMODE_READ) {
1678 stop_adc(s);
1679 s->dma_adc.ready = 0;
1680 if (val >= 2)
1681 fmtd |= ESS_FMT_STEREO << ESS_ADC_SHIFT;
1682 else
1683 fmtm &= ~(ESS_FMT_STEREO << ESS_ADC_SHIFT);
1684 }
1685 if (file->f_mode & FMODE_WRITE) {
1686 stop_dac(s);
1687 s->dma_dac.ready = 0;
1688 if (val >= 2)
1689 fmtd |= ESS_FMT_STEREO << ESS_DAC_SHIFT;
1690 else
1691 fmtm &= ~(ESS_FMT_STEREO << ESS_DAC_SHIFT);
1692 }
1693 set_fmt(s, fmtm, fmtd);
1694 }
1695 spin_unlock_irqrestore(&card->lock, flags);
1696 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
1697 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, p);
1698
1699 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1700 return put_user(AFMT_U8|AFMT_S16_LE, p);
1701
1702 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1703 get_user_ret(val, p, -EFAULT);
1704 spin_lock_irqsave(&card->lock, flags);
1705 if (val != AFMT_QUERY) {
1706 fmtd = 0;
1707 fmtm = ~0;
1708 if (file->f_mode & FMODE_READ) {
1709 stop_adc(s);
1710 s->dma_adc.ready = 0;
1711 if (val == AFMT_S16_LE)
1712 fmtd |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
1713 else
1714 fmtm &= ~(ESS_FMT_16BIT << ESS_ADC_SHIFT);
1715 }
1716 if (file->f_mode & FMODE_WRITE) {
1717 stop_dac(s);
1718 s->dma_dac.ready = 0;
1719 if (val == AFMT_S16_LE)
1720 fmtd |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
1721 else
1722 fmtm &= ~(ESS_FMT_16BIT << ESS_DAC_SHIFT);
1723 }
1724 set_fmt(s, fmtm, fmtd);
1725 }
1726 spin_unlock_irqrestore(&card->lock, flags);
1727 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ?
1728 (ESS_FMT_16BIT << ESS_ADC_SHIFT)
1729 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ?
1730 AFMT_S16_LE :
1731 AFMT_U8,
1732 p);
1733
1734 case SNDCTL_DSP_POST:
1735 return 0;
1736
1737 case SNDCTL_DSP_GETTRIGGER:
1738 val = 0;
1739 if ((file->f_mode & FMODE_READ) && (s->enable & ADC_RUNNING))
1740 val |= PCM_ENABLE_INPUT;
1741 if ((file->f_mode & FMODE_WRITE) && (s->enable & DAC_RUNNING))
1742 val |= PCM_ENABLE_OUTPUT;
1743 return put_user(val, p);
1744
1745 case SNDCTL_DSP_SETTRIGGER:
1746 get_user_ret(val, p, -EFAULT);
1747 if (file->f_mode & FMODE_READ) {
1748 if (val & PCM_ENABLE_INPUT) {
1749 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1750 return ret;
1751 start_adc(s);
1752 } else
1753 stop_adc(s);
1754 }
1755 if (file->f_mode & FMODE_WRITE) {
1756 if (val & PCM_ENABLE_OUTPUT) {
1757 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1758 return ret;
1759 start_dac(s);
1760 } else
1761 stop_dac(s);
1762 }
1763 return 0;
1764
1765 case SNDCTL_DSP_GETOSPACE:
1766 if (!(file->f_mode & FMODE_WRITE))
1767 return -EINVAL;
1768 if (!(s->enable & DAC_RUNNING) && (val = prog_dmabuf(s, 0)) != 0)
1769 return val;
1770 spin_lock_irqsave(&card->lock, flags);
1771 m3_update_ptr(s);
1772 abinfo.fragsize = s->dma_dac.fragsize;
1773 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
1774 abinfo.fragstotal = s->dma_dac.numfrag;
1775 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1776 spin_unlock_irqrestore(&card->lock, flags);
1777 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1778
1779 case SNDCTL_DSP_GETISPACE:
1780 if (!(file->f_mode & FMODE_READ))
1781 return -EINVAL;
1782 if (!(s->enable & ADC_RUNNING) && (val = prog_dmabuf(s, 1)) != 0)
1783 return val;
1784 spin_lock_irqsave(&card->lock, flags);
1785 m3_update_ptr(s);
1786 abinfo.fragsize = s->dma_adc.fragsize;
1787 abinfo.bytes = s->dma_adc.count;
1788 abinfo.fragstotal = s->dma_adc.numfrag;
1789 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1790 spin_unlock_irqrestore(&card->lock, flags);
1791 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1792
1793 case SNDCTL_DSP_NONBLOCK:
1794 file->f_flags |= O_NONBLOCK;
1795 return 0;
1796
1797 case SNDCTL_DSP_GETODELAY:
1798 if (!(file->f_mode & FMODE_WRITE))
1799 return -EINVAL;
1800 spin_lock_irqsave(&card->lock, flags);
1801 m3_update_ptr(s);
1802 val = s->dma_dac.count;
1803 spin_unlock_irqrestore(&card->lock, flags);
1804 return put_user(val, p);
1805
1806 case SNDCTL_DSP_GETIPTR:
1807 if (!(file->f_mode & FMODE_READ))
1808 return -EINVAL;
1809 spin_lock_irqsave(&card->lock, flags);
1810 m3_update_ptr(s);
1811 cinfo.bytes = s->dma_adc.total_bytes;
1812 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
1813 cinfo.ptr = s->dma_adc.hwptr;
1814 if (s->dma_adc.mapped)
1815 s->dma_adc.count &= s->dma_adc.fragsize-1;
1816 spin_unlock_irqrestore(&card->lock, flags);
1817 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1818 return -EFAULT;
1819 return 0;
1820
1821 case SNDCTL_DSP_GETOPTR:
1822 if (!(file->f_mode & FMODE_WRITE))
1823 return -EINVAL;
1824 spin_lock_irqsave(&card->lock, flags);
1825 m3_update_ptr(s);
1826 cinfo.bytes = s->dma_dac.total_bytes;
1827 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
1828 cinfo.ptr = s->dma_dac.hwptr;
1829 if (s->dma_dac.mapped)
1830 s->dma_dac.count &= s->dma_dac.fragsize-1;
1831 spin_unlock_irqrestore(&card->lock, flags);
1832 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1833 return -EFAULT;
1834 return 0;
1835
1836 case SNDCTL_DSP_GETBLKSIZE:
1837 if (file->f_mode & FMODE_WRITE) {
1838 if ((val = prog_dmabuf(s, 0)))
1839 return val;
1840 return put_user(s->dma_dac.fragsize, p);
1841 }
1842 if ((val = prog_dmabuf(s, 1)))
1843 return val;
1844 return put_user(s->dma_adc.fragsize, p);
1845
1846 case SNDCTL_DSP_SETFRAGMENT:
1847 get_user_ret(val, p, -EFAULT);
1848 spin_lock_irqsave(&card->lock, flags);
1849 if (file->f_mode & FMODE_READ) {
1850 s->dma_adc.ossfragshift = val & 0xffff;
1851 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1852 if (s->dma_adc.ossfragshift < 4)
1853 s->dma_adc.ossfragshift = 4;
1854 if (s->dma_adc.ossfragshift > 15)
1855 s->dma_adc.ossfragshift = 15;
1856 if (s->dma_adc.ossmaxfrags < 4)
1857 s->dma_adc.ossmaxfrags = 4;
1858 }
1859 if (file->f_mode & FMODE_WRITE) {
1860 s->dma_dac.ossfragshift = val & 0xffff;
1861 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1862 if (s->dma_dac.ossfragshift < 4)
1863 s->dma_dac.ossfragshift = 4;
1864 if (s->dma_dac.ossfragshift > 15)
1865 s->dma_dac.ossfragshift = 15;
1866 if (s->dma_dac.ossmaxfrags < 4)
1867 s->dma_dac.ossmaxfrags = 4;
1868 }
1869 spin_unlock_irqrestore(&card->lock, flags);
1870 return 0;
1871
1872 case SNDCTL_DSP_SUBDIVIDE:
1873 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1874 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1875 return -EINVAL;
1876 get_user_ret(val, p, -EFAULT);
1877 if (val != 1 && val != 2 && val != 4)
1878 return -EINVAL;
1879 if (file->f_mode & FMODE_READ)
1880 s->dma_adc.subdivision = val;
1881 if (file->f_mode & FMODE_WRITE)
1882 s->dma_dac.subdivision = val;
1883 return 0;
1884
1885 case SOUND_PCM_READ_RATE:
1886 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1887
1888 case SOUND_PCM_READ_CHANNELS:
1889 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_STEREO << ESS_ADC_SHIFT)
1890 : (ESS_FMT_STEREO << ESS_DAC_SHIFT))) ? 2 : 1, p);
1891
1892 case SOUND_PCM_READ_BITS:
1893 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_FMT_16BIT << ESS_ADC_SHIFT)
1894 : (ESS_FMT_16BIT << ESS_DAC_SHIFT))) ? 16 : 8, p);
1895
1896 case SOUND_PCM_WRITE_FILTER:
1897 case SNDCTL_DSP_SETSYNCRO:
1898 case SOUND_PCM_READ_FILTER:
1899 return -EINVAL;
1900
1901 }
1902 return -EINVAL;
1903 }
1904
1905 static int
1906 allocate_dmabuf(struct pci_dev *pci_dev, struct dmabuf *db)
1907 {
1908 int order;
1909
1910 DPRINTK(DPSTR,"allocating for dmabuf %p\n", db);
1911
1912 /*
1913 * alloc as big a chunk as we can, start with
1914 * 64k 'cause we're insane. based on order cause
1915 * the amazingly complicated prog_dmabuf wants it.
1916 *
1917 * pci_alloc_sonsistent guarantees that it won't cross a natural
1918 * boundary; the m3 hardware can't have dma cross a 64k bus
1919 * address boundary.
1920 */
1921 for (order = 16-PAGE_SHIFT; order >= 1; order--) {
1922 db->rawbuf = pci_alloc_consistent(pci_dev, PAGE_SIZE << order,
1923 &(db->handle));
1924 if(db->rawbuf)
1925 break;
1926 }
1927
1928 if (!db->rawbuf)
1929 return 1;
1930
1931 DPRINTK(DPSTR,"allocated %ld (%d) bytes at %p\n",
1932 PAGE_SIZE<<order, order, db->rawbuf);
1933
1934 {
1935 struct page *page, *pend;
1936
1937 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << order) - 1);
1938 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
1939 SetPageReserved(page);
1940 }
1941
1942
1943 db->buforder = order;
1944 db->ready = 0;
1945 db->mapped = 0;
1946
1947 return 0;
1948 }
1949
1950 static void
1951 nuke_lists(struct m3_card *card, struct dmabuf *db)
1952 {
1953 m3_remove_list(card, &(card->dma_list), db->dma_index);
1954 m3_remove_list(card, &(card->msrc_list), db->msrc_index);
1955 db->in_lists = 0;
1956 }
1957
1958 static void
1959 free_dmabuf(struct pci_dev *pci_dev, struct dmabuf *db)
1960 {
1961 if(db->rawbuf == NULL)
1962 return;
1963
1964 DPRINTK(DPSTR,"freeing %p from dmabuf %p\n",db->rawbuf, db);
1965
1966 {
1967 struct page *page, *pend;
1968 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1969 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
1970 ClearPageReserved(page);
1971 }
1972
1973
1974 pci_free_consistent(pci_dev, PAGE_SIZE << db->buforder,
1975 db->rawbuf, db->handle);
1976
1977 db->rawbuf = NULL;
1978 db->buforder = 0;
1979 db->mapped = 0;
1980 db->ready = 0;
1981 }
1982
1983 static int m3_open(struct inode *inode, struct file *file)
1984 {
1985 unsigned int minor = iminor(inode);
1986 struct m3_card *c;
1987 struct m3_state *s = NULL;
1988 int i;
1989 unsigned char fmtm = ~0, fmts = 0;
1990 unsigned long flags;
1991
1992 /*
1993 * Scan the cards and find the channel. We only
1994 * do this at open time so it is ok
1995 */
1996 for(c = devs ; c != NULL ; c = c->next) {
1997
1998 for(i=0;i<NR_DSPS;i++) {
1999
2000 if(c->channels[i].dev_audio < 0)
2001 continue;
2002 if((c->channels[i].dev_audio ^ minor) & ~0xf)
2003 continue;
2004
2005 s = &c->channels[i];
2006 break;
2007 }
2008 }
2009
2010 if (!s)
2011 return -ENODEV;
2012
2013 VALIDATE_STATE(s);
2014
2015 file->private_data = s;
2016
2017 /* wait for device to become free */
2018 mutex_lock(&s->open_mutex);
2019 while (s->open_mode & file->f_mode) {
2020 if (file->f_flags & O_NONBLOCK) {
2021 mutex_unlock(&s->open_mutex);
2022 return -EWOULDBLOCK;
2023 }
2024 mutex_unlock(&s->open_mutex);
2025 interruptible_sleep_on(&s->open_wait);
2026 if (signal_pending(current))
2027 return -ERESTARTSYS;
2028 mutex_lock(&s->open_mutex);
2029 }
2030
2031 spin_lock_irqsave(&c->lock, flags);
2032
2033 if (file->f_mode & FMODE_READ) {
2034 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_ADC_SHIFT);
2035 if ((minor & 0xf) == SND_DEV_DSP16)
2036 fmts |= ESS_FMT_16BIT << ESS_ADC_SHIFT;
2037
2038 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2039 set_adc_rate(s, 8000);
2040 }
2041 if (file->f_mode & FMODE_WRITE) {
2042 fmtm &= ~((ESS_FMT_STEREO | ESS_FMT_16BIT) << ESS_DAC_SHIFT);
2043 if ((minor & 0xf) == SND_DEV_DSP16)
2044 fmts |= ESS_FMT_16BIT << ESS_DAC_SHIFT;
2045
2046 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2047 set_dac_rate(s, 8000);
2048 }
2049 set_fmt(s, fmtm, fmts);
2050 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2051
2052 mutex_unlock(&s->open_mutex);
2053 spin_unlock_irqrestore(&c->lock, flags);
2054 return nonseekable_open(inode, file);
2055 }
2056
2057 static int m3_release(struct inode *inode, struct file *file)
2058 {
2059 struct m3_state *s = (struct m3_state *)file->private_data;
2060 struct m3_card *card=s->card;
2061 unsigned long flags;
2062
2063 VALIDATE_STATE(s);
2064 if (file->f_mode & FMODE_WRITE)
2065 drain_dac(s, file->f_flags & O_NONBLOCK);
2066
2067 mutex_lock(&s->open_mutex);
2068 spin_lock_irqsave(&card->lock, flags);
2069
2070 if (file->f_mode & FMODE_WRITE) {
2071 stop_dac(s);
2072 if(s->dma_dac.in_lists) {
2073 m3_remove_list(s->card, &(s->card->mixer_list), s->dma_dac.mixer_index);
2074 nuke_lists(s->card, &(s->dma_dac));
2075 }
2076 }
2077 if (file->f_mode & FMODE_READ) {
2078 stop_adc(s);
2079 if(s->dma_adc.in_lists) {
2080 m3_remove_list(s->card, &(s->card->adc1_list), s->dma_adc.adc1_index);
2081 nuke_lists(s->card, &(s->dma_adc));
2082 }
2083 }
2084
2085 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
2086
2087 spin_unlock_irqrestore(&card->lock, flags);
2088 mutex_unlock(&s->open_mutex);
2089 wake_up(&s->open_wait);
2090
2091 return 0;
2092 }
2093
2094 /*
2095 * Wait for the ac97 serial bus to be free.
2096 * return nonzero if the bus is still busy.
2097 */
2098 static int m3_ac97_wait(struct m3_card *card)
2099 {
2100 int i = 10000;
2101
2102 while( (m3_inb(card, 0x30) & 1) && i--) ;
2103
2104 return i == 0;
2105 }
2106
2107 static u16 m3_ac97_read(struct ac97_codec *codec, u8 reg)
2108 {
2109 u16 ret = 0;
2110 struct m3_card *card = codec->private_data;
2111
2112 spin_lock(&card->ac97_lock);
2113
2114 if(m3_ac97_wait(card)) {
2115 printk(KERN_ERR PFX "serial bus busy reading reg 0x%x\n",reg);
2116 goto out;
2117 }
2118
2119 m3_outb(card, 0x80 | (reg & 0x7f), 0x30);
2120
2121 if(m3_ac97_wait(card)) {
2122 printk(KERN_ERR PFX "serial bus busy finishing read reg 0x%x\n",reg);
2123 goto out;
2124 }
2125
2126 ret = m3_inw(card, 0x32);
2127 DPRINTK(DPCRAP,"reading 0x%04x from 0x%02x\n",ret, reg);
2128
2129 out:
2130 spin_unlock(&card->ac97_lock);
2131 return ret;
2132 }
2133
2134 static void m3_ac97_write(struct ac97_codec *codec, u8 reg, u16 val)
2135 {
2136 struct m3_card *card = codec->private_data;
2137
2138 spin_lock(&card->ac97_lock);
2139
2140 if(m3_ac97_wait(card)) {
2141 printk(KERN_ERR PFX "serial bus busy writing 0x%x to 0x%x\n",val, reg);
2142 goto out;
2143 }
2144 DPRINTK(DPCRAP,"writing 0x%04x to 0x%02x\n", val, reg);
2145
2146 m3_outw(card, val, 0x32);
2147 m3_outb(card, reg & 0x7f, 0x30);
2148 out:
2149 spin_unlock(&card->ac97_lock);
2150 }
2151 /* OSS /dev/mixer file operation methods */
2152 static int m3_open_mixdev(struct inode *inode, struct file *file)
2153 {
2154 unsigned int minor = iminor(inode);
2155 struct m3_card *card = devs;
2156
2157 for (card = devs; card != NULL; card = card->next) {
2158 if((card->ac97 != NULL) && (card->ac97->dev_mixer == minor))
2159 break;
2160 }
2161
2162 if (!card) {
2163 return -ENODEV;
2164 }
2165
2166 file->private_data = card->ac97;
2167
2168 return nonseekable_open(inode, file);
2169 }
2170
2171 static int m3_release_mixdev(struct inode *inode, struct file *file)
2172 {
2173 return 0;
2174 }
2175
2176 static int m3_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd,
2177 unsigned long arg)
2178 {
2179 struct ac97_codec *codec = (struct ac97_codec *)file->private_data;
2180
2181 return codec->mixer_ioctl(codec, cmd, arg);
2182 }
2183
2184 static struct file_operations m3_mixer_fops = {
2185 .owner = THIS_MODULE,
2186 .llseek = no_llseek,
2187 .ioctl = m3_ioctl_mixdev,
2188 .open = m3_open_mixdev,
2189 .release = m3_release_mixdev,
2190 };
2191
2192 static void remote_codec_config(int io, int isremote)
2193 {
2194 isremote = isremote ? 1 : 0;
2195
2196 outw( (inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2197 io + RING_BUS_CTRL_B);
2198 outw( (inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2199 io + SDO_OUT_DEST_CTRL);
2200 outw( (inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2201 io + SDO_IN_DEST_CTRL);
2202 }
2203
2204 /*
2205 * hack, returns non zero on err
2206 */
2207 static int try_read_vendor(struct m3_card *card)
2208 {
2209 u16 ret;
2210
2211 if(m3_ac97_wait(card))
2212 return 1;
2213
2214 m3_outb(card, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2215
2216 if(m3_ac97_wait(card))
2217 return 1;
2218
2219 ret = m3_inw(card, 0x32);
2220
2221 return (ret == 0) || (ret == 0xffff);
2222 }
2223
2224 static void m3_codec_reset(struct m3_card *card, int busywait)
2225 {
2226 u16 dir;
2227 int delay1 = 0, delay2 = 0, i;
2228 int io = card->iobase;
2229
2230 switch (card->card_type) {
2231 /*
2232 * the onboard codec on the allegro seems
2233 * to want to wait a very long time before
2234 * coming back to life
2235 */
2236 case ESS_ALLEGRO:
2237 delay1 = 50;
2238 delay2 = 800;
2239 break;
2240 case ESS_MAESTRO3:
2241 case ESS_MAESTRO3HW:
2242 delay1 = 20;
2243 delay2 = 500;
2244 break;
2245 }
2246
2247 for(i = 0; i < 5; i ++) {
2248 dir = inw(io + GPIO_DIRECTION);
2249 dir |= 0x10; /* assuming pci bus master? */
2250
2251 remote_codec_config(io, 0);
2252
2253 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2254 udelay(20);
2255
2256 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2257 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2258 outw(0, io + GPIO_DATA);
2259 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2260
2261 if(busywait) {
2262 mdelay(delay1);
2263 } else {
2264 set_current_state(TASK_UNINTERRUPTIBLE);
2265 schedule_timeout((delay1 * HZ) / 1000);
2266 }
2267
2268 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2269 udelay(5);
2270 /* ok, bring back the ac-link */
2271 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2272 outw(~0, io + GPIO_MASK);
2273
2274 if(busywait) {
2275 mdelay(delay2);
2276 } else {
2277 set_current_state(TASK_UNINTERRUPTIBLE);
2278 schedule_timeout((delay2 * HZ) / 1000);
2279 }
2280 if(! try_read_vendor(card))
2281 break;
2282
2283 delay1 += 10;
2284 delay2 += 100;
2285
2286 DPRINTK(DPMOD, "retrying codec reset with delays of %d and %d ms\n",
2287 delay1, delay2);
2288 }
2289
2290 #if 0
2291 /* more gung-ho reset that doesn't
2292 * seem to work anywhere :)
2293 */
2294 tmp = inw(io + RING_BUS_CTRL_A);
2295 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2296 mdelay(20);
2297 outw(tmp, io + RING_BUS_CTRL_A);
2298 mdelay(50);
2299 #endif
2300 }
2301
2302 static int __devinit m3_codec_install(struct m3_card *card)
2303 {
2304 struct ac97_codec *codec;
2305
2306 if ((codec = ac97_alloc_codec()) == NULL)
2307 return -ENOMEM;
2308
2309 codec->private_data = card;
2310 codec->codec_read = m3_ac97_read;
2311 codec->codec_write = m3_ac97_write;
2312 /* someday we should support secondary codecs.. */
2313 codec->id = 0;
2314
2315 if (ac97_probe_codec(codec) == 0) {
2316 printk(KERN_ERR PFX "codec probe failed\n");
2317 ac97_release_codec(codec);
2318 return -1;
2319 }
2320
2321 if ((codec->dev_mixer = register_sound_mixer(&m3_mixer_fops, -1)) < 0) {
2322 printk(KERN_ERR PFX "couldn't register mixer!\n");
2323 ac97_release_codec(codec);
2324 return -1;
2325 }
2326
2327 card->ac97 = codec;
2328
2329 return 0;
2330 }
2331
2332
2333 #define MINISRC_LPF_LEN 10
2334 static u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2335 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2336 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2337 };
2338 static void m3_assp_init(struct m3_card *card)
2339 {
2340 int i;
2341
2342 /* zero kernel data */
2343 for(i = 0 ; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2344 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2345 KDATA_BASE_ADDR + i, 0);
2346
2347 /* zero mixer data? */
2348 for(i = 0 ; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2349 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2350 KDATA_BASE_ADDR2 + i, 0);
2351
2352 /* init dma pointer */
2353 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2354 KDATA_CURRENT_DMA,
2355 KDATA_DMA_XFER0);
2356
2357 /* write kernel into code memory.. */
2358 for(i = 0 ; i < sizeof(assp_kernel_image) / 2; i++) {
2359 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2360 REV_B_CODE_MEMORY_BEGIN + i,
2361 assp_kernel_image[i]);
2362 }
2363
2364 /*
2365 * We only have this one client and we know that 0x400
2366 * is free in our kernel's mem map, so lets just
2367 * drop it there. It seems that the minisrc doesn't
2368 * need vectors, so we won't bother with them..
2369 */
2370 for(i = 0 ; i < sizeof(assp_minisrc_image) / 2; i++) {
2371 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2372 0x400 + i,
2373 assp_minisrc_image[i]);
2374 }
2375
2376 /*
2377 * write the coefficients for the low pass filter?
2378 */
2379 for(i = 0; i < MINISRC_LPF_LEN ; i++) {
2380 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2381 0x400 + MINISRC_COEF_LOC + i,
2382 minisrc_lpf[i]);
2383 }
2384
2385 m3_assp_write(card, MEMTYPE_INTERNAL_CODE,
2386 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2387 0x8000);
2388
2389 /*
2390 * the minisrc is the only thing on
2391 * our task list..
2392 */
2393 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2394 KDATA_TASK0,
2395 0x400);
2396
2397 /*
2398 * init the mixer number..
2399 */
2400
2401 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2402 KDATA_MIXER_TASK_NUMBER,0);
2403
2404 /*
2405 * EXTREME KERNEL MASTER VOLUME
2406 */
2407 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2408 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2409 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2410 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2411
2412 card->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2413 card->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2414 card->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2415 card->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2416 card->dma_list.mem_addr = KDATA_DMA_XFER0;
2417 card->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2418 card->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2419 card->msrc_list.max = MAX_INSTANCE_MINISRC;
2420 }
2421
2422 static int setup_msrc(struct m3_card *card,
2423 struct assp_instance *inst, int index)
2424 {
2425 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2426 MINISRC_IN_BUFFER_SIZE / 2 +
2427 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2428 int address, i;
2429
2430 /*
2431 * the revb memory map has 0x1100 through 0x1c00
2432 * free.
2433 */
2434
2435 /*
2436 * align instance address to 256 bytes so that it's
2437 * shifted list address is aligned.
2438 * list address = (mem address >> 1) >> 7;
2439 */
2440 data_bytes = (data_bytes + 255) & ~255;
2441 address = 0x1100 + ((data_bytes/2) * index);
2442
2443 if((address + (data_bytes/2)) >= 0x1c00) {
2444 printk(KERN_ERR PFX "no memory for %d bytes at ind %d (addr 0x%x)\n",
2445 data_bytes, index, address);
2446 return -1;
2447 }
2448
2449 for(i = 0; i < data_bytes/2 ; i++)
2450 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2451 address + i, 0);
2452
2453 inst->code = 0x400;
2454 inst->data = address;
2455
2456 return 0;
2457 }
2458
2459 static int m3_assp_client_init(struct m3_state *s)
2460 {
2461 setup_msrc(s->card, &(s->dac_inst), s->index * 2);
2462 setup_msrc(s->card, &(s->adc_inst), (s->index * 2) + 1);
2463
2464 return 0;
2465 }
2466
2467 static void m3_amp_enable(struct m3_card *card, int enable)
2468 {
2469 /*
2470 * this works for the reference board, have to find
2471 * out about others
2472 *
2473 * this needs more magic for 4 speaker, but..
2474 */
2475 int io = card->iobase;
2476 u16 gpo, polarity_port, polarity;
2477
2478 if(!external_amp)
2479 return;
2480
2481 if (gpio_pin >= 0 && gpio_pin <= 15) {
2482 polarity_port = 0x1000 + (0x100 * gpio_pin);
2483 } else {
2484 switch (card->card_type) {
2485 case ESS_ALLEGRO:
2486 polarity_port = 0x1800;
2487 break;
2488 default:
2489 polarity_port = 0x1100;
2490 /* Panasonic toughbook CF72 has to be different... */
2491 if(card->pcidev->subsystem_vendor == 0x10F7 && card->pcidev->subsystem_device == 0x833D)
2492 polarity_port = 0x1D00;
2493 break;
2494 }
2495 }
2496
2497 gpo = (polarity_port >> 8) & 0x0F;
2498 polarity = polarity_port >> 12;
2499 if ( enable )
2500 polarity = !polarity;
2501 polarity = polarity << gpo;
2502 gpo = 1 << gpo;
2503
2504 outw(~gpo , io + GPIO_MASK);
2505
2506 outw( inw(io + GPIO_DIRECTION) | gpo ,
2507 io + GPIO_DIRECTION);
2508
2509 outw( (GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity) ,
2510 io + GPIO_DATA);
2511
2512 outw(0xffff , io + GPIO_MASK);
2513 }
2514
2515 static int
2516 maestro_config(struct m3_card *card)
2517 {
2518 struct pci_dev *pcidev = card->pcidev;
2519 u32 n;
2520 u8 t; /* makes as much sense as 'n', no? */
2521
2522 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2523 n &= REDUCED_DEBOUNCE;
2524 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2525 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2526
2527 outb(RESET_ASSP, card->iobase + ASSP_CONTROL_B);
2528 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2529 n &= ~INT_CLK_SELECT;
2530 if(card->card_type >= ESS_MAESTRO3) {
2531 n &= ~INT_CLK_MULT_ENABLE;
2532 n |= INT_CLK_SRC_NOT_PCI;
2533 }
2534 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2535 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2536
2537 if(card->card_type <= ESS_ALLEGRO) {
2538 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2539 n |= IN_CLK_12MHZ_SELECT;
2540 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2541 }
2542
2543 t = inb(card->iobase + ASSP_CONTROL_A);
2544 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2545 t |= ASSP_CLK_49MHZ_SELECT;
2546 t |= ASSP_0_WS_ENABLE;
2547 outb(t, card->iobase + ASSP_CONTROL_A);
2548
2549 outb(RUN_ASSP, card->iobase + ASSP_CONTROL_B);
2550
2551 return 0;
2552 }
2553
2554 static void m3_enable_ints(struct m3_card *card)
2555 {
2556 unsigned long io = card->iobase;
2557
2558 outw(ASSP_INT_ENABLE, io + HOST_INT_CTRL);
2559 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2560 io + ASSP_CONTROL_C);
2561 }
2562
2563 static struct file_operations m3_audio_fops = {
2564 .owner = THIS_MODULE,
2565 .llseek = no_llseek,
2566 .read = m3_read,
2567 .write = m3_write,
2568 .poll = m3_poll,
2569 .ioctl = m3_ioctl,
2570 .mmap = m3_mmap,
2571 .open = m3_open,
2572 .release = m3_release,
2573 };
2574
2575 #ifdef CONFIG_PM
2576 static int alloc_dsp_suspendmem(struct m3_card *card)
2577 {
2578 int len = sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH);
2579
2580 if( (card->suspend_mem = vmalloc(len)) == NULL)
2581 return 1;
2582
2583 return 0;
2584 }
2585
2586 #else
2587 #define alloc_dsp_suspendmem(args...) 0
2588 #endif
2589
2590 /*
2591 * great day! this function is ugly as hell.
2592 */
2593 static int __devinit m3_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_id)
2594 {
2595 u32 n;
2596 int i;
2597 struct m3_card *card = NULL;
2598 int ret = 0;
2599 int card_type = pci_id->driver_data;
2600
2601 DPRINTK(DPMOD, "in maestro_install\n");
2602
2603 if (pci_enable_device(pci_dev))
2604 return -EIO;
2605
2606 if (pci_set_dma_mask(pci_dev, M3_PCI_DMA_MASK)) {
2607 printk(KERN_ERR PFX "architecture does not support limiting to 28bit PCI bus addresses\n");
2608 return -ENODEV;
2609 }
2610
2611 pci_set_master(pci_dev);
2612
2613 if( (card = kmalloc(sizeof(struct m3_card), GFP_KERNEL)) == NULL) {
2614 printk(KERN_WARNING PFX "out of memory\n");
2615 return -ENOMEM;
2616 }
2617 memset(card, 0, sizeof(struct m3_card));
2618 card->pcidev = pci_dev;
2619 init_waitqueue_head(&card->suspend_queue);
2620
2621 if ( ! request_region(pci_resource_start(pci_dev, 0),
2622 pci_resource_len (pci_dev, 0), M3_MODULE_NAME)) {
2623
2624 printk(KERN_WARNING PFX "unable to reserve I/O space.\n");
2625 ret = -EBUSY;
2626 goto out;
2627 }
2628
2629 card->iobase = pci_resource_start(pci_dev, 0);
2630
2631 if(alloc_dsp_suspendmem(card)) {
2632 printk(KERN_WARNING PFX "couldn't alloc %d bytes for saving dsp state on suspend\n",
2633 REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH);
2634 ret = -ENOMEM;
2635 goto out;
2636 }
2637
2638 card->card_type = card_type;
2639 card->irq = pci_dev->irq;
2640 card->next = devs;
2641 card->magic = M3_CARD_MAGIC;
2642 spin_lock_init(&card->lock);
2643 spin_lock_init(&card->ac97_lock);
2644 devs = card;
2645 for(i = 0; i<NR_DSPS; i++) {
2646 struct m3_state *s = &(card->channels[i]);
2647 s->dev_audio = -1;
2648 }
2649
2650 printk(KERN_INFO PFX "Configuring ESS %s found at IO 0x%04X IRQ %d\n",
2651 card_names[card->card_type], card->iobase, card->irq);
2652
2653 pci_read_config_dword(pci_dev, PCI_SUBSYSTEM_VENDOR_ID, &n);
2654 printk(KERN_INFO PFX " subvendor id: 0x%08x\n",n);
2655
2656 maestro_config(card);
2657 m3_assp_halt(card);
2658
2659 m3_codec_reset(card, 0);
2660
2661 if(m3_codec_install(card)) {
2662 ret = -EIO;
2663 goto out;
2664 }
2665
2666 m3_assp_init(card);
2667 m3_amp_enable(card, 1);
2668
2669 for(i=0;i<NR_DSPS;i++) {
2670 struct m3_state *s=&card->channels[i];
2671
2672 s->index = i;
2673
2674 s->card = card;
2675 init_waitqueue_head(&s->dma_adc.wait);
2676 init_waitqueue_head(&s->dma_dac.wait);
2677 init_waitqueue_head(&s->open_wait);
2678 mutex_init(&(s->open_mutex));
2679 s->magic = M3_STATE_MAGIC;
2680
2681 m3_assp_client_init(s);
2682
2683 if(s->dma_adc.ready || s->dma_dac.ready || s->dma_adc.rawbuf)
2684 printk(KERN_WARNING PFX "initing a dsp device that is already in use?\n");
2685 /* register devices */
2686 if ((s->dev_audio = register_sound_dsp(&m3_audio_fops, -1)) < 0) {
2687 break;
2688 }
2689
2690 if( allocate_dmabuf(card->pcidev, &(s->dma_adc)) ||
2691 allocate_dmabuf(card->pcidev, &(s->dma_dac))) {
2692 ret = -ENOMEM;
2693 goto out;
2694 }
2695 }
2696
2697 if(request_irq(card->irq, m3_interrupt, IRQF_SHARED, card_names[card->card_type], card)) {
2698
2699 printk(KERN_ERR PFX "unable to allocate irq %d,\n", card->irq);
2700
2701 ret = -EIO;
2702 goto out;
2703 }
2704
2705 pci_set_drvdata(pci_dev, card);
2706
2707 m3_enable_ints(card);
2708 m3_assp_continue(card);
2709
2710 out:
2711 if(ret) {
2712 if(card->iobase)
2713 release_region(pci_resource_start(pci_dev, 0), pci_resource_len(pci_dev, 0));
2714 vfree(card->suspend_mem);
2715 if(card->ac97) {
2716 unregister_sound_mixer(card->ac97->dev_mixer);
2717 kfree(card->ac97);
2718 }
2719 for(i=0;i<NR_DSPS;i++)
2720 {
2721 struct m3_state *s = &card->channels[i];
2722 if(s->dev_audio != -1)
2723 unregister_sound_dsp(s->dev_audio);
2724 }
2725 kfree(card);
2726 }
2727
2728 return ret;
2729 }
2730
2731 static void m3_remove(struct pci_dev *pci_dev)
2732 {
2733 struct m3_card *card;
2734
2735 unregister_reboot_notifier(&m3_reboot_nb);
2736
2737 while ((card = devs)) {
2738 int i;
2739 devs = devs->next;
2740
2741 free_irq(card->irq, card);
2742 unregister_sound_mixer(card->ac97->dev_mixer);
2743 kfree(card->ac97);
2744
2745 for(i=0;i<NR_DSPS;i++)
2746 {
2747 struct m3_state *s = &card->channels[i];
2748 if(s->dev_audio < 0)
2749 continue;
2750
2751 unregister_sound_dsp(s->dev_audio);
2752 free_dmabuf(card->pcidev, &s->dma_adc);
2753 free_dmabuf(card->pcidev, &s->dma_dac);
2754 }
2755
2756 release_region(card->iobase, 256);
2757 vfree(card->suspend_mem);
2758 kfree(card);
2759 }
2760 devs = NULL;
2761 }
2762
2763 /*
2764 * some bioses like the sound chip to be powered down
2765 * at shutdown. We're just calling _suspend to
2766 * achieve that..
2767 */
2768 static int m3_notifier(struct notifier_block *nb, unsigned long event, void *buf)
2769 {
2770 struct m3_card *card;
2771
2772 DPRINTK(DPMOD, "notifier suspending all cards\n");
2773
2774 for(card = devs; card != NULL; card = card->next) {
2775 if(!card->in_suspend)
2776 m3_suspend(card->pcidev, PMSG_SUSPEND); /* XXX legal? */
2777 }
2778 return 0;
2779 }
2780
2781 static int m3_suspend(struct pci_dev *pci_dev, pm_message_t state)
2782 {
2783 unsigned long flags;
2784 int i;
2785 struct m3_card *card = pci_get_drvdata(pci_dev);
2786
2787 /* must be a better way.. */
2788 spin_lock_irqsave(&card->lock, flags);
2789
2790 DPRINTK(DPMOD, "pm in dev %p\n",card);
2791
2792 for(i=0;i<NR_DSPS;i++) {
2793 struct m3_state *s = &card->channels[i];
2794
2795 if(s->dev_audio == -1)
2796 continue;
2797
2798 DPRINTK(DPMOD, "stop_adc/dac() device %d\n",i);
2799 stop_dac(s);
2800 stop_adc(s);
2801 }
2802
2803 mdelay(10); /* give the assp a chance to idle.. */
2804
2805 m3_assp_halt(card);
2806
2807 if(card->suspend_mem) {
2808 int index = 0;
2809
2810 DPRINTK(DPMOD, "saving code\n");
2811 for(i = REV_B_CODE_MEMORY_BEGIN ; i <= REV_B_CODE_MEMORY_END; i++)
2812 card->suspend_mem[index++] =
2813 m3_assp_read(card, MEMTYPE_INTERNAL_CODE, i);
2814 DPRINTK(DPMOD, "saving data\n");
2815 for(i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2816 card->suspend_mem[index++] =
2817 m3_assp_read(card, MEMTYPE_INTERNAL_DATA, i);
2818 }
2819
2820 DPRINTK(DPMOD, "powering down apci regs\n");
2821 m3_outw(card, 0xffff, 0x54);
2822 m3_outw(card, 0xffff, 0x56);
2823
2824 card->in_suspend = 1;
2825
2826 spin_unlock_irqrestore(&card->lock, flags);
2827
2828 return 0;
2829 }
2830
2831 static int m3_resume(struct pci_dev *pci_dev)
2832 {
2833 unsigned long flags;
2834 int index;
2835 int i;
2836 struct m3_card *card = pci_get_drvdata(pci_dev);
2837
2838 spin_lock_irqsave(&card->lock, flags);
2839 card->in_suspend = 0;
2840
2841 DPRINTK(DPMOD, "resuming\n");
2842
2843 /* first lets just bring everything back. .*/
2844
2845 DPRINTK(DPMOD, "bringing power back on card 0x%p\n",card);
2846 m3_outw(card, 0, 0x54);
2847 m3_outw(card, 0, 0x56);
2848
2849 DPRINTK(DPMOD, "restoring pci configs and reseting codec\n");
2850 maestro_config(card);
2851 m3_assp_halt(card);
2852 m3_codec_reset(card, 1);
2853
2854 DPRINTK(DPMOD, "restoring dsp code card\n");
2855 index = 0;
2856 for(i = REV_B_CODE_MEMORY_BEGIN ; i <= REV_B_CODE_MEMORY_END; i++)
2857 m3_assp_write(card, MEMTYPE_INTERNAL_CODE, i,
2858 card->suspend_mem[index++]);
2859 for(i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2860 m3_assp_write(card, MEMTYPE_INTERNAL_DATA, i,
2861 card->suspend_mem[index++]);
2862
2863 /* tell the dma engine to restart itself */
2864 m3_assp_write(card, MEMTYPE_INTERNAL_DATA,
2865 KDATA_DMA_ACTIVE, 0);
2866
2867 DPRINTK(DPMOD, "resuming dsp\n");
2868 m3_assp_continue(card);
2869
2870 DPRINTK(DPMOD, "enabling ints\n");
2871 m3_enable_ints(card);
2872
2873 /* bring back the old school flavor */
2874 for(i = 0; i < SOUND_MIXER_NRDEVICES ; i++) {
2875 int state = card->ac97->mixer_state[i];
2876 if (!supported_mixer(card->ac97, i))
2877 continue;
2878
2879 card->ac97->write_mixer(card->ac97, i,
2880 state & 0xff, (state >> 8) & 0xff);
2881 }
2882
2883 m3_amp_enable(card, 1);
2884
2885 /*
2886 * now we flip on the music
2887 */
2888 for(i=0;i<NR_DSPS;i++) {
2889 struct m3_state *s = &card->channels[i];
2890 if(s->dev_audio == -1)
2891 continue;
2892 /*
2893 * db->ready makes it so these guys can be
2894 * called unconditionally..
2895 */
2896 DPRINTK(DPMOD, "turning on dacs ind %d\n",i);
2897 start_dac(s);
2898 start_adc(s);
2899 }
2900
2901 spin_unlock_irqrestore(&card->lock, flags);
2902
2903 /*
2904 * all right, we think things are ready,
2905 * wake up people who were using the device
2906 * when we suspended
2907 */
2908 wake_up(&card->suspend_queue);
2909
2910 return 0;
2911 }
2912
2913 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>");
2914 MODULE_DESCRIPTION("ESS Maestro3/Allegro Driver");
2915 MODULE_LICENSE("GPL");
2916
2917 #ifdef M_DEBUG
2918 module_param(debug, int, 0);
2919 #endif
2920 module_param(external_amp, int, 0);
2921 module_param(gpio_pin, int, 0);
2922
2923 static struct pci_driver m3_pci_driver = {
2924 .name = "ess_m3_audio",
2925 .id_table = m3_id_table,
2926 .probe = m3_probe,
2927 .remove = m3_remove,
2928 .suspend = m3_suspend,
2929 .resume = m3_resume,
2930 };
2931
2932 static int __init m3_init_module(void)
2933 {
2934 printk(KERN_INFO PFX "version " DRIVER_VERSION " built at " __TIME__ " " __DATE__ "\n");
2935
2936 if (register_reboot_notifier(&m3_reboot_nb)) {
2937 printk(KERN_WARNING PFX "reboot notifier registration failed\n");
2938 return -ENODEV; /* ? */
2939 }
2940
2941 if (pci_register_driver(&m3_pci_driver)) {
2942 unregister_reboot_notifier(&m3_reboot_nb);
2943 return -ENODEV;
2944 }
2945 return 0;
2946 }
2947
2948 static void __exit m3_cleanup_module(void)
2949 {
2950 pci_unregister_driver(&m3_pci_driver);
2951 }
2952
2953 module_init(m3_init_module);
2954 module_exit(m3_cleanup_module);
2955
2956 void check_suspend(struct m3_card *card)
2957 {
2958 DECLARE_WAITQUEUE(wait, current);
2959
2960 if(!card->in_suspend)
2961 return;
2962
2963 card->in_suspend++;
2964 add_wait_queue(&card->suspend_queue, &wait);
2965 set_current_state(TASK_UNINTERRUPTIBLE);
2966 schedule();
2967 remove_wait_queue(&card->suspend_queue, &wait);
2968 set_current_state(TASK_RUNNING);
2969 }
USB Experimental Work