3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
24 #include <linux/threads.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
38 #define DO_SOFT_DISABLE
41 * We layout physical memory as follows:
42 * 0x0000 - 0x00ff : Secondary processor spin code
43 * 0x0100 - 0x2fff : pSeries Interrupt prologs
44 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
45 * 0x6000 - 0x6fff : Initial (CPU0) segment table
46 * 0x7000 - 0x7fff : FWNMI data area
47 * 0x8000 - : Early init and support code
55 * SPRG0 reserved for hypervisor
56 * SPRG1 temp - used to save gpr
57 * SPRG2 temp - used to save gpr
58 * SPRG3 virt addr of paca
62 * Entering into this code we make the following assumptions:
64 * 1. The MMU is off & open firmware is running in real mode.
65 * 2. The kernel is entered at __start
68 * 1. The MMU is on (as it always is for iSeries)
69 * 2. The kernel is entered at system_reset_iSeries
75 #ifdef CONFIG_PPC_MULTIPLATFORM
77 /* NOP this out unconditionally */
79 b .__start_initialization_multiplatform
81 #endif /* CONFIG_PPC_MULTIPLATFORM */
83 /* Catch branch to 0 in real mode */
86 /* Secondary processors spin on this value until it goes to 1. */
87 .globl __secondary_hold_spinloop
88 __secondary_hold_spinloop:
91 /* Secondary processors write this value with their cpu # */
92 /* after they enter the spin loop immediately below. */
93 .globl __secondary_hold_acknowledge
94 __secondary_hold_acknowledge:
97 #ifdef CONFIG_PPC_ISERIES
99 * At offset 0x20, there is a pointer to iSeries LPAR data.
100 * This is required by the hypervisor
103 .llong hvReleaseData-KERNELBASE
104 #endif /* CONFIG_PPC_ISERIES */
108 * The following code is used on pSeries to hold secondary processors
109 * in a spin loop after they have been freed from OpenFirmware, but
110 * before the bulk of the kernel has been relocated. This code
111 * is relocated to physical address 0x60 before prom_init is run.
112 * All of it must fit below the first exception vector at 0x100.
114 _GLOBAL(__secondary_hold)
117 mtmsrd r24 /* RI on */
119 /* Grab our physical cpu number */
122 /* Tell the master cpu we're here */
123 /* Relocation is off & we are located at an address less */
124 /* than 0x100, so only need to grab low order offset. */
125 std r24,__secondary_hold_acknowledge@l(0)
128 /* All secondary cpus wait here until told to start. */
129 100: ld r4,__secondary_hold_spinloop@l(0)
133 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
134 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
142 /* This value is used to mark exception frames on the stack. */
145 .tc ID_72656773_68657265[TC],0x7265677368657265
149 * The following macros define the code that appears as
150 * the prologue to each of the exception handlers. They
151 * are split into two parts to allow a single kernel binary
152 * to be used for pSeries and iSeries.
153 * LOL. One day... - paulus
157 * We make as much of the exception code common between native
158 * exception handlers (including pSeries LPAR) and iSeries LPAR
159 * implementations as possible.
163 * This is the start of the interrupt handlers for pSeries
164 * This code runs with relocation off.
179 * We're short on space and time in the exception prolog, so we can't
180 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
181 * low halfword of the address, but for Kdump we need the whole low
184 #ifdef CONFIG_CRASH_DUMP
185 #define LOAD_HANDLER(reg, label) \
186 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
187 ori reg,reg,(label)@l; /* .. and the rest */
189 #define LOAD_HANDLER(reg, label) \
190 ori reg,reg,(label)@l; /* virt addr of handler ... */
194 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
195 * The firmware calls the registered system_reset_fwnmi and
196 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
197 * a 32bit application at the time of the event.
198 * This firmware bug is present on POWER4 and JS20.
200 #define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
201 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
202 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
203 std r10,area+EX_R10(r13); \
204 std r11,area+EX_R11(r13); \
205 std r12,area+EX_R12(r13); \
206 mfspr r9,SPRN_SPRG1; \
207 std r9,area+EX_R13(r13); \
209 clrrdi r12,r13,32; /* get high part of &label */ \
211 /* force 64bit mode */ \
212 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \
213 rldimi r10,r11,61,0; /* insert into top 3 bits */ \
214 /* done 64bit mode */ \
215 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
216 LOAD_HANDLER(r12,label) \
217 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
218 mtspr SPRN_SRR0,r12; \
219 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
220 mtspr SPRN_SRR1,r10; \
222 b . /* prevent speculative execution */
224 #define EXCEPTION_PROLOG_PSERIES(area, label) \
225 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
226 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
227 std r10,area+EX_R10(r13); \
228 std r11,area+EX_R11(r13); \
229 std r12,area+EX_R12(r13); \
230 mfspr r9,SPRN_SPRG1; \
231 std r9,area+EX_R13(r13); \
233 clrrdi r12,r13,32; /* get high part of &label */ \
235 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
236 LOAD_HANDLER(r12,label) \
237 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
238 mtspr SPRN_SRR0,r12; \
239 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
240 mtspr SPRN_SRR1,r10; \
242 b . /* prevent speculative execution */
245 * This is the start of the interrupt handlers for iSeries
246 * This code runs with relocation on.
248 #define EXCEPTION_PROLOG_ISERIES_1(area) \
249 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
250 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
251 std r10,area+EX_R10(r13); \
252 std r11,area+EX_R11(r13); \
253 std r12,area+EX_R12(r13); \
254 mfspr r9,SPRN_SPRG1; \
255 std r9,area+EX_R13(r13); \
258 #define EXCEPTION_PROLOG_ISERIES_2 \
260 ld r12,PACALPPACAPTR(r13); \
261 ld r11,LPPACASRR0(r12); \
262 ld r12,LPPACASRR1(r12); \
263 ori r10,r10,MSR_RI; \
267 * The common exception prolog is used for all except a few exceptions
268 * such as a segment miss on a kernel address. We have to be prepared
269 * to take another exception from the point where we first touch the
270 * kernel stack onwards.
272 * On entry r13 points to the paca, r9-r13 are saved in the paca,
273 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
274 * SRR1, and relocation is on.
276 #define EXCEPTION_PROLOG_COMMON(n, area) \
277 andi. r10,r12,MSR_PR; /* See if coming from user */ \
278 mr r10,r1; /* Save r1 */ \
279 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
281 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
282 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
283 bge- cr1,bad_stack; /* abort if it is */ \
284 std r9,_CCR(r1); /* save CR in stackframe */ \
285 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
286 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
287 std r10,0(r1); /* make stack chain pointer */ \
288 std r0,GPR0(r1); /* save r0 in stackframe */ \
289 std r10,GPR1(r1); /* save r1 in stackframe */ \
290 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
291 std r2,GPR2(r1); /* save r2 in stackframe */ \
292 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
293 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
294 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
295 ld r10,area+EX_R10(r13); \
298 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
299 ld r10,area+EX_R12(r13); \
300 ld r11,area+EX_R13(r13); \
304 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
305 mflr r9; /* save LR in stackframe */ \
307 mfctr r10; /* save CTR in stackframe */ \
309 lbz r10,PACASOFTIRQEN(r13); \
310 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
314 std r9,_TRAP(r1); /* set trap number */ \
316 ld r11,exception_marker@toc(r2); \
317 std r10,RESULT(r1); /* clear regs->result */ \
318 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
323 #define STD_EXCEPTION_PSERIES(n, label) \
325 .globl label##_pSeries; \
328 mtspr SPRN_SPRG1,r13; /* save r13 */ \
329 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
331 #define HSTD_EXCEPTION_PSERIES(n, label) \
333 .globl label##_pSeries; \
336 mtspr SPRN_SPRG1,r20; /* save r20 */ \
337 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
338 mtspr SPRN_SRR0,r20; \
339 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
340 mtspr SPRN_SRR1,r20; \
341 mfspr r20,SPRN_SPRG1; /* restore r20 */ \
342 mtspr SPRN_SPRG1,r13; /* save r13 */ \
343 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
346 #define MASKABLE_EXCEPTION_PSERIES(n, label) \
348 .globl label##_pSeries; \
351 mtspr SPRN_SPRG1,r13; /* save r13 */ \
352 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
353 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
354 std r10,PACA_EXGEN+EX_R10(r13); \
355 lbz r10,PACASOFTIRQEN(r13); \
358 beq masked_interrupt; \
359 mfspr r10,SPRN_SPRG1; \
360 std r10,PACA_EXGEN+EX_R13(r13); \
361 std r11,PACA_EXGEN+EX_R11(r13); \
362 std r12,PACA_EXGEN+EX_R12(r13); \
363 clrrdi r12,r13,32; /* get high part of &label */ \
365 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
366 LOAD_HANDLER(r12,label##_common) \
367 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
368 mtspr SPRN_SRR0,r12; \
369 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
370 mtspr SPRN_SRR1,r10; \
372 b . /* prevent speculative execution */
374 #define STD_EXCEPTION_ISERIES(n, label, area) \
375 .globl label##_iSeries; \
378 mtspr SPRN_SPRG1,r13; /* save r13 */ \
379 EXCEPTION_PROLOG_ISERIES_1(area); \
380 EXCEPTION_PROLOG_ISERIES_2; \
383 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
384 .globl label##_iSeries; \
387 mtspr SPRN_SPRG1,r13; /* save r13 */ \
388 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
389 lbz r10,PACASOFTIRQEN(r13); \
391 beq- label##_iSeries_masked; \
392 EXCEPTION_PROLOG_ISERIES_2; \
395 #ifdef CONFIG_PPC_ISERIES
396 #define DISABLE_INTS \
398 stb r11,PACASOFTIRQEN(r13); \
399 BEGIN_FW_FTR_SECTION; \
400 stb r11,PACAHARDIRQEN(r13); \
401 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
402 BEGIN_FW_FTR_SECTION; \
404 ori r10,r10,MSR_EE; \
406 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
409 #define DISABLE_INTS \
411 stb r11,PACASOFTIRQEN(r13); \
412 stb r11,PACAHARDIRQEN(r13)
414 #endif /* CONFIG_PPC_ISERIES */
416 #define ENABLE_INTS \
419 rlwimi r11,r12,0,MSR_EE; \
422 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
424 .globl label##_common; \
426 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
429 addi r3,r1,STACK_FRAME_OVERHEAD; \
434 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
435 * in the idle task and therefore need the special idle handling.
437 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
439 .globl label##_common; \
441 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
445 addi r3,r1,STACK_FRAME_OVERHEAD; \
449 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
451 .globl label##_common; \
453 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
456 bl .ppc64_runlatch_on; \
457 addi r3,r1,STACK_FRAME_OVERHEAD; \
459 b .ret_from_except_lite
462 * When the idle code in power4_idle puts the CPU into NAP mode,
463 * it has to do so in a loop, and relies on the external interrupt
464 * and decrementer interrupt entry code to get it out of the loop.
465 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
466 * to signal that it is in the loop and needs help to get out.
468 #ifdef CONFIG_PPC_970_NAP
471 clrrdi r11,r1,THREAD_SHIFT; \
472 ld r9,TI_LOCAL_FLAGS(r11); \
473 andi. r10,r9,_TLF_NAPPING; \
474 bnel power4_fixup_nap; \
475 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
481 * Start of pSeries system interrupt routines
484 .globl __start_interrupts
487 STD_EXCEPTION_PSERIES(0x100, system_reset)
490 _machine_check_pSeries:
492 mtspr SPRN_SPRG1,r13 /* save r13 */
493 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
496 .globl data_access_pSeries
505 rlwimi r13,r12,16,0x20
508 beq .do_stab_bolted_pSeries
511 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
512 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
515 .globl data_access_slb_pSeries
516 data_access_slb_pSeries:
519 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
520 std r3,PACA_EXSLB+EX_R3(r13)
522 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
525 /* Keep that around for when we re-implement dynamic VSIDs */
527 bge slb_miss_user_pseries
528 #endif /* __DISABLED__ */
529 std r10,PACA_EXSLB+EX_R10(r13)
530 std r11,PACA_EXSLB+EX_R11(r13)
531 std r12,PACA_EXSLB+EX_R12(r13)
533 std r10,PACA_EXSLB+EX_R13(r13)
534 mfspr r12,SPRN_SRR1 /* and SRR1 */
535 b .slb_miss_realmode /* Rel. branch works in real mode */
537 STD_EXCEPTION_PSERIES(0x400, instruction_access)
540 .globl instruction_access_slb_pSeries
541 instruction_access_slb_pSeries:
544 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
545 std r3,PACA_EXSLB+EX_R3(r13)
546 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
547 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
550 /* Keep that around for when we re-implement dynamic VSIDs */
552 bge slb_miss_user_pseries
553 #endif /* __DISABLED__ */
554 std r10,PACA_EXSLB+EX_R10(r13)
555 std r11,PACA_EXSLB+EX_R11(r13)
556 std r12,PACA_EXSLB+EX_R12(r13)
558 std r10,PACA_EXSLB+EX_R13(r13)
559 mfspr r12,SPRN_SRR1 /* and SRR1 */
560 b .slb_miss_realmode /* Rel. branch works in real mode */
562 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
563 STD_EXCEPTION_PSERIES(0x600, alignment)
564 STD_EXCEPTION_PSERIES(0x700, program_check)
565 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
566 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
567 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
568 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
571 .globl system_call_pSeries
579 oris r12,r12,system_call_common@h
580 ori r12,r12,system_call_common@l
582 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
586 b . /* prevent speculative execution */
588 STD_EXCEPTION_PSERIES(0xd00, single_step)
589 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
591 /* We need to deal with the Altivec unavailable exception
592 * here which is at 0xf20, thus in the middle of the
593 * prolog code of the PerformanceMonitor one. A little
594 * trickery is thus necessary
597 b performance_monitor_pSeries
599 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
601 #ifdef CONFIG_CBE_RAS
602 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
603 #endif /* CONFIG_CBE_RAS */
604 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
605 #ifdef CONFIG_CBE_RAS
606 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
607 #endif /* CONFIG_CBE_RAS */
608 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
609 #ifdef CONFIG_CBE_RAS
610 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
611 #endif /* CONFIG_CBE_RAS */
615 /*** pSeries interrupt support ***/
617 /* moved from 0xf00 */
618 MASKABLE_EXCEPTION_PSERIES(., performance_monitor)
621 * An interrupt came in while soft-disabled; clear EE in SRR1,
622 * clear paca->hard_enabled and return.
625 stb r10,PACAHARDIRQEN(r13)
627 ld r9,PACA_EXGEN+EX_R9(r13)
629 rldicl r10,r10,48,1 /* clear MSR_EE */
632 ld r10,PACA_EXGEN+EX_R10(r13)
638 _GLOBAL(do_stab_bolted_pSeries)
641 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
644 * We have some room here we use that to put
645 * the peries slb miss user trampoline code so it's reasonably
646 * away from slb_miss_user_common to avoid problems with rfid
648 * This is used for when the SLB miss handler has to go virtual,
649 * which doesn't happen for now anymore but will once we re-implement
650 * dynamic VSIDs for shared page tables
653 slb_miss_user_pseries:
654 std r10,PACA_EXGEN+EX_R10(r13)
655 std r11,PACA_EXGEN+EX_R11(r13)
656 std r12,PACA_EXGEN+EX_R12(r13)
658 ld r11,PACA_EXSLB+EX_R9(r13)
659 ld r12,PACA_EXSLB+EX_R3(r13)
660 std r10,PACA_EXGEN+EX_R13(r13)
661 std r11,PACA_EXGEN+EX_R9(r13)
662 std r12,PACA_EXGEN+EX_R3(r13)
665 mfspr r11,SRR0 /* save SRR0 */
666 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
667 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
669 mfspr r12,SRR1 /* and SRR1 */
672 b . /* prevent spec. execution */
673 #endif /* __DISABLED__ */
676 * Vectors for the FWNMI option. Share common code.
678 .globl system_reset_fwnmi
682 mtspr SPRN_SPRG1,r13 /* save r13 */
683 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
685 .globl machine_check_fwnmi
689 mtspr SPRN_SPRG1,r13 /* save r13 */
690 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
692 #ifdef CONFIG_PPC_ISERIES
693 /*** ISeries-LPAR interrupt handlers ***/
695 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
697 .globl data_access_iSeries
705 rlwimi r13,r12,16,0x20
708 beq .do_stab_bolted_iSeries
711 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
712 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
713 EXCEPTION_PROLOG_ISERIES_2
716 .do_stab_bolted_iSeries:
719 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
720 EXCEPTION_PROLOG_ISERIES_2
723 .globl data_access_slb_iSeries
724 data_access_slb_iSeries:
725 mtspr SPRN_SPRG1,r13 /* save r13 */
726 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
727 std r3,PACA_EXSLB+EX_R3(r13)
729 std r9,PACA_EXSLB+EX_R9(r13)
733 bge slb_miss_user_iseries
735 std r10,PACA_EXSLB+EX_R10(r13)
736 std r11,PACA_EXSLB+EX_R11(r13)
737 std r12,PACA_EXSLB+EX_R12(r13)
739 std r10,PACA_EXSLB+EX_R13(r13)
740 ld r12,PACALPPACAPTR(r13)
741 ld r12,LPPACASRR1(r12)
744 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
746 .globl instruction_access_slb_iSeries
747 instruction_access_slb_iSeries:
748 mtspr SPRN_SPRG1,r13 /* save r13 */
749 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
750 std r3,PACA_EXSLB+EX_R3(r13)
751 ld r3,PACALPPACAPTR(r13)
752 ld r3,LPPACASRR0(r3) /* get SRR0 value */
753 std r9,PACA_EXSLB+EX_R9(r13)
757 bge .slb_miss_user_iseries
759 std r10,PACA_EXSLB+EX_R10(r13)
760 std r11,PACA_EXSLB+EX_R11(r13)
761 std r12,PACA_EXSLB+EX_R12(r13)
763 std r10,PACA_EXSLB+EX_R13(r13)
764 ld r12,PACALPPACAPTR(r13)
765 ld r12,LPPACASRR1(r12)
769 slb_miss_user_iseries:
770 std r10,PACA_EXGEN+EX_R10(r13)
771 std r11,PACA_EXGEN+EX_R11(r13)
772 std r12,PACA_EXGEN+EX_R12(r13)
774 ld r11,PACA_EXSLB+EX_R9(r13)
775 ld r12,PACA_EXSLB+EX_R3(r13)
776 std r10,PACA_EXGEN+EX_R13(r13)
777 std r11,PACA_EXGEN+EX_R9(r13)
778 std r12,PACA_EXGEN+EX_R3(r13)
779 EXCEPTION_PROLOG_ISERIES_2
780 b slb_miss_user_common
783 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
784 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
785 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
786 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
787 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
788 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
789 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
791 .globl system_call_iSeries
795 EXCEPTION_PROLOG_ISERIES_2
798 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
799 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
800 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
802 .globl system_reset_iSeries
803 system_reset_iSeries:
804 mfspr r13,SPRN_SPRG3 /* Get paca address */
807 mtmsrd r24 /* RI on */
808 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
809 cmpwi 0,r24,0 /* Are we processor 0? */
810 beq .__start_initialization_iSeries /* Start up the first processor */
812 li r5,CTRL_RUNLATCH /* Turn off the run light */
819 lbz r23,PACAPROCSTART(r13) /* Test if this processor
822 LOAD_REG_IMMEDIATE(r3,current_set)
823 sldi r28,r24,3 /* get current_set[cpu#] */
825 addi r1,r3,THREAD_SIZE
826 subi r1,r1,STACK_FRAME_OVERHEAD
829 beq iSeries_secondary_smp_loop /* Loop until told to go */
830 bne .__secondary_start /* Loop until told to go */
831 iSeries_secondary_smp_loop:
832 /* Let the Hypervisor know we are alive */
833 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
835 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
836 #else /* CONFIG_SMP */
837 /* Yield the processor. This is required for non-SMP kernels
838 which are running on multi-threaded machines. */
840 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
841 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
842 li r4,0 /* "yield timed" */
843 li r5,-1 /* "yield forever" */
844 #endif /* CONFIG_SMP */
845 li r0,-1 /* r0=-1 indicates a Hypervisor call */
846 sc /* Invoke the hypervisor via a system call */
847 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
848 b 1b /* If SMP not configured, secondaries
851 .globl decrementer_iSeries_masked
852 decrementer_iSeries_masked:
853 /* We may not have a valid TOC pointer in here. */
855 ld r12,PACALPPACAPTR(r13)
856 stb r11,LPPACADECRINT(r12)
857 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
862 .globl hardware_interrupt_iSeries_masked
863 hardware_interrupt_iSeries_masked:
864 mtcrf 0x80,r9 /* Restore regs */
865 ld r12,PACALPPACAPTR(r13)
866 ld r11,LPPACASRR0(r12)
867 ld r12,LPPACASRR1(r12)
870 ld r9,PACA_EXGEN+EX_R9(r13)
871 ld r10,PACA_EXGEN+EX_R10(r13)
872 ld r11,PACA_EXGEN+EX_R11(r13)
873 ld r12,PACA_EXGEN+EX_R12(r13)
874 ld r13,PACA_EXGEN+EX_R13(r13)
876 b . /* prevent speculative execution */
877 #endif /* CONFIG_PPC_ISERIES */
879 /*** Common interrupt handlers ***/
881 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
884 * Machine check is different because we use a different
885 * save area: PACA_EXMC instead of PACA_EXGEN.
888 .globl machine_check_common
889 machine_check_common:
890 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
894 addi r3,r1,STACK_FRAME_OVERHEAD
895 bl .machine_check_exception
898 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
899 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
900 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
901 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
902 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
903 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
904 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
905 #ifdef CONFIG_ALTIVEC
906 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
908 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
910 #ifdef CONFIG_CBE_RAS
911 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
912 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
913 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
914 #endif /* CONFIG_CBE_RAS */
917 * Here we have detected that the kernel stack pointer is bad.
918 * R9 contains the saved CR, r13 points to the paca,
919 * r10 contains the (bad) kernel stack pointer,
920 * r11 and r12 contain the saved SRR0 and SRR1.
921 * We switch to using an emergency stack, save the registers there,
922 * and call kernel_bad_stack(), which panics.
925 ld r1,PACAEMERGSP(r13)
926 subi r1,r1,64+INT_FRAME_SIZE
947 addi r11,r1,INT_FRAME_SIZE
952 1: addi r3,r1,STACK_FRAME_OVERHEAD
957 * Return from an exception with minimal checks.
958 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
959 * If interrupts have been enabled, or anything has been
960 * done that might have changed the scheduling status of
961 * any task or sent any task a signal, you should use
962 * ret_from_except or ret_from_except_lite instead of this.
964 .globl fast_exception_return
965 fast_exception_return:
968 andi. r3,r12,MSR_RI /* check if RI is set */
971 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
974 ACCOUNT_CPU_USER_EXIT(r3, r4)
990 rldicl r10,r10,48,1 /* clear EE */
991 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
999 b . /* prevent speculative execution */
1003 1: addi r3,r1,STACK_FRAME_OVERHEAD
1004 bl .unrecoverable_exception
1008 * Here r13 points to the paca, r9 contains the saved CR,
1009 * SRR0 and SRR1 are saved in r11 and r12,
1010 * r9 - r13 are saved in paca->exgen.
1013 .globl data_access_common
1016 std r10,PACA_EXGEN+EX_DAR(r13)
1017 mfspr r10,SPRN_DSISR
1018 stw r10,PACA_EXGEN+EX_DSISR(r13)
1019 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
1020 ld r3,PACA_EXGEN+EX_DAR(r13)
1021 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1023 b .do_hash_page /* Try to handle as hpte fault */
1026 .globl instruction_access_common
1027 instruction_access_common:
1028 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
1030 andis. r4,r12,0x5820
1032 b .do_hash_page /* Try to handle as hpte fault */
1035 * Here is the common SLB miss user that is used when going to virtual
1036 * mode for SLB misses, that is currently not used
1040 .globl slb_miss_user_common
1041 slb_miss_user_common:
1043 std r3,PACA_EXGEN+EX_DAR(r13)
1044 stw r9,PACA_EXGEN+EX_CCR(r13)
1045 std r10,PACA_EXGEN+EX_LR(r13)
1046 std r11,PACA_EXGEN+EX_SRR0(r13)
1047 bl .slb_allocate_user
1049 ld r10,PACA_EXGEN+EX_LR(r13)
1050 ld r3,PACA_EXGEN+EX_R3(r13)
1051 lwz r9,PACA_EXGEN+EX_CCR(r13)
1052 ld r11,PACA_EXGEN+EX_SRR0(r13)
1056 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1057 beq- unrecov_user_slb
1065 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
1071 ld r9,PACA_EXGEN+EX_R9(r13)
1072 ld r10,PACA_EXGEN+EX_R10(r13)
1073 ld r11,PACA_EXGEN+EX_R11(r13)
1074 ld r12,PACA_EXGEN+EX_R12(r13)
1075 ld r13,PACA_EXGEN+EX_R13(r13)
1080 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
1081 ld r4,PACA_EXGEN+EX_DAR(r13)
1085 b .handle_page_fault
1088 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
1091 1: addi r3,r1,STACK_FRAME_OVERHEAD
1092 bl .unrecoverable_exception
1095 #endif /* __DISABLED__ */
1099 * r13 points to the PACA, r9 contains the saved CR,
1100 * r12 contain the saved SRR1, SRR0 is still ready for return
1101 * r3 has the faulting address
1102 * r9 - r13 are saved in paca->exslb.
1103 * r3 is saved in paca->slb_r3
1104 * We assume we aren't going to take any exceptions during this procedure.
1106 _GLOBAL(slb_miss_realmode)
1109 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1110 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1112 bl .slb_allocate_realmode
1114 /* All done -- return from exception. */
1116 ld r10,PACA_EXSLB+EX_LR(r13)
1117 ld r3,PACA_EXSLB+EX_R3(r13)
1118 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1119 #ifdef CONFIG_PPC_ISERIES
1120 BEGIN_FW_FTR_SECTION
1121 ld r11,PACALPPACAPTR(r13)
1122 ld r11,LPPACASRR0(r11) /* get SRR0 value */
1123 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1124 #endif /* CONFIG_PPC_ISERIES */
1128 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1134 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1137 #ifdef CONFIG_PPC_ISERIES
1138 BEGIN_FW_FTR_SECTION
1141 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1142 #endif /* CONFIG_PPC_ISERIES */
1143 ld r9,PACA_EXSLB+EX_R9(r13)
1144 ld r10,PACA_EXSLB+EX_R10(r13)
1145 ld r11,PACA_EXSLB+EX_R11(r13)
1146 ld r12,PACA_EXSLB+EX_R12(r13)
1147 ld r13,PACA_EXSLB+EX_R13(r13)
1149 b . /* prevent speculative execution */
1152 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1155 1: addi r3,r1,STACK_FRAME_OVERHEAD
1156 bl .unrecoverable_exception
1160 .globl hardware_interrupt_common
1161 .globl hardware_interrupt_entry
1162 hardware_interrupt_common:
1163 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1165 hardware_interrupt_entry:
1167 bl .ppc64_runlatch_on
1168 addi r3,r1,STACK_FRAME_OVERHEAD
1170 b .ret_from_except_lite
1172 #ifdef CONFIG_PPC_970_NAP
1175 std r9,TI_LOCAL_FLAGS(r11)
1176 ld r10,_LINK(r1) /* make idle task do the */
1177 std r10,_NIP(r1) /* equivalent of a blr */
1182 .globl alignment_common
1185 std r10,PACA_EXGEN+EX_DAR(r13)
1186 mfspr r10,SPRN_DSISR
1187 stw r10,PACA_EXGEN+EX_DSISR(r13)
1188 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1189 ld r3,PACA_EXGEN+EX_DAR(r13)
1190 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1194 addi r3,r1,STACK_FRAME_OVERHEAD
1196 bl .alignment_exception
1200 .globl program_check_common
1201 program_check_common:
1202 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1204 addi r3,r1,STACK_FRAME_OVERHEAD
1206 bl .program_check_exception
1210 .globl fp_unavailable_common
1211 fp_unavailable_common:
1212 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1213 bne .load_up_fpu /* if from user, just load it up */
1215 addi r3,r1,STACK_FRAME_OVERHEAD
1217 bl .kernel_fp_unavailable_exception
1221 .globl altivec_unavailable_common
1222 altivec_unavailable_common:
1223 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1224 #ifdef CONFIG_ALTIVEC
1226 bne .load_up_altivec /* if from user, just load it up */
1227 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1230 addi r3,r1,STACK_FRAME_OVERHEAD
1232 bl .altivec_unavailable_exception
1235 #ifdef CONFIG_ALTIVEC
1237 * load_up_altivec(unused, unused, tsk)
1238 * Disable VMX for the task which had it previously,
1239 * and save its vector registers in its thread_struct.
1240 * Enables the VMX for use in the kernel on return.
1241 * On SMP we know the VMX is free, since we give it up every
1242 * switch (ie, no lazy save of the vector registers).
1243 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1245 _STATIC(load_up_altivec)
1246 mfmsr r5 /* grab the current MSR */
1247 oris r5,r5,MSR_VEC@h
1248 mtmsrd r5 /* enable use of VMX now */
1252 * For SMP, we don't do lazy VMX switching because it just gets too
1253 * horrendously complex, especially when a task switches from one CPU
1254 * to another. Instead we call giveup_altvec in switch_to.
1255 * VRSAVE isn't dealt with here, that is done in the normal context
1256 * switch code. Note that we could rely on vrsave value to eventually
1257 * avoid saving all of the VREGs here...
1260 ld r3,last_task_used_altivec@got(r2)
1264 /* Save VMX state to last_task_used_altivec's THREAD struct */
1270 /* Disable VMX for last_task_used_altivec */
1272 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1275 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1277 #endif /* CONFIG_SMP */
1278 /* Hack: if we get an altivec unavailable trap with VRSAVE
1279 * set to all zeros, we assume this is a broken application
1280 * that fails to set it properly, and thus we switch it to
1283 mfspr r4,SPRN_VRSAVE
1287 mtspr SPRN_VRSAVE,r4
1289 /* enable use of VMX after return */
1290 ld r4,PACACURRENT(r13)
1291 addi r5,r4,THREAD /* Get THREAD */
1292 oris r12,r12,MSR_VEC@h
1296 stw r4,THREAD_USED_VR(r5)
1301 /* Update last_task_used_math to 'current' */
1302 subi r4,r5,THREAD /* Back to 'current' */
1304 #endif /* CONFIG_SMP */
1305 /* restore registers and return */
1306 b fast_exception_return
1307 #endif /* CONFIG_ALTIVEC */
1313 _GLOBAL(do_hash_page)
1317 andis. r0,r4,0xa450 /* weird error? */
1318 bne- .handle_page_fault /* if not, try to insert a HPTE */
1320 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1321 bne- .do_ste_alloc /* If so handle it */
1322 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1325 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1326 * accessing a userspace segment (even from the kernel). We assume
1327 * kernel addresses always have the high bit set.
1329 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1330 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1331 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1332 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1333 ori r4,r4,1 /* add _PAGE_PRESENT */
1334 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1337 * On iSeries, we soft-disable interrupts here, then
1338 * hard-enable interrupts so that the hash_page code can spin on
1339 * the hash_table_lock without problems on a shared processor.
1344 * r3 contains the faulting address
1345 * r4 contains the required access permissions
1346 * r5 contains the trap number
1348 * at return r3 = 0 for success
1350 bl .hash_page /* build HPTE if possible */
1351 cmpdi r3,0 /* see if hash_page succeeded */
1353 #ifdef DO_SOFT_DISABLE
1354 BEGIN_FW_FTR_SECTION
1356 * If we had interrupts soft-enabled at the point where the
1357 * DSI/ISI occurred, and an interrupt came in during hash_page,
1359 * We jump to ret_from_except_lite rather than fast_exception_return
1360 * because ret_from_except_lite will check for and handle pending
1361 * interrupts if necessary.
1363 beq .ret_from_except_lite
1364 /* For a hash failure, we don't bother re-enabling interrupts */
1368 * hash_page couldn't handle it, set soft interrupt enable back
1369 * to what it was before the trap. Note that .local_irq_restore
1370 * handles any interrupts pending at this point.
1373 bl .local_irq_restore
1375 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1377 BEGIN_FW_FTR_SECTION
1378 beq fast_exception_return /* Return from exception on success */
1379 ble- 12f /* Failure return from hash_page */
1382 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1384 /* Here we have a page fault that hash_page can't handle. */
1385 _GLOBAL(handle_page_fault)
1389 addi r3,r1,STACK_FRAME_OVERHEAD
1392 beq+ .ret_from_except_lite
1395 addi r3,r1,STACK_FRAME_OVERHEAD
1400 /* We have a page fault that hash_page could handle but HV refused
1404 addi r3,r1,STACK_FRAME_OVERHEAD
1409 /* here we have a segment miss */
1410 _GLOBAL(do_ste_alloc)
1411 bl .ste_allocate /* try to insert stab entry */
1413 beq+ fast_exception_return
1414 b .handle_page_fault
1417 * r13 points to the PACA, r9 contains the saved CR,
1418 * r11 and r12 contain the saved SRR0 and SRR1.
1419 * r9 - r13 are saved in paca->exslb.
1420 * We assume we aren't going to take any exceptions during this procedure.
1421 * We assume (DAR >> 60) == 0xc.
1424 _GLOBAL(do_stab_bolted)
1425 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1426 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1428 /* Hash to the primary group */
1429 ld r10,PACASTABVIRT(r13)
1432 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1434 /* Calculate VSID */
1435 /* This is a kernel address, so protovsid = ESID */
1436 ASM_VSID_SCRAMBLE(r11, r9)
1437 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1439 /* Search the primary group for a free entry */
1440 1: ld r11,0(r10) /* Test valid bit of the current ste */
1447 /* Stick for only searching the primary group for now. */
1448 /* At least for now, we use a very simple random castout scheme */
1449 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1451 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1454 /* r10 currently points to an ste one past the group of interest */
1455 /* make it point to the randomly selected entry */
1457 or r10,r10,r11 /* r10 is the entry to invalidate */
1459 isync /* mark the entry invalid */
1461 rldicl r11,r11,56,1 /* clear the valid bit */
1466 clrrdi r11,r11,28 /* Get the esid part of the ste */
1469 2: std r9,8(r10) /* Store the vsid part of the ste */
1472 mfspr r11,SPRN_DAR /* Get the new esid */
1473 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1474 ori r11,r11,0x90 /* Turn on valid and kp */
1475 std r11,0(r10) /* Put new entry back into the stab */
1479 /* All done -- return from exception. */
1480 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1481 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1483 andi. r10,r12,MSR_RI
1486 mtcrf 0x80,r9 /* restore CR */
1494 ld r9,PACA_EXSLB+EX_R9(r13)
1495 ld r10,PACA_EXSLB+EX_R10(r13)
1496 ld r11,PACA_EXSLB+EX_R11(r13)
1497 ld r12,PACA_EXSLB+EX_R12(r13)
1498 ld r13,PACA_EXSLB+EX_R13(r13)
1500 b . /* prevent speculative execution */
1503 * Space for CPU0's segment table.
1505 * On iSeries, the hypervisor must fill in at least one entry before
1506 * we get control (with relocate on). The address is give to the hv
1507 * as a page number (see xLparMap in lpardata.c), so this must be at a
1508 * fixed address (the linker can't compute (u64)&initial_stab >>
1511 . = STAB0_OFFSET /* 0x6000 */
1517 * Data area reserved for FWNMI option.
1518 * This address (0x7000) is fixed by the RPA.
1521 .globl fwnmi_data_area
1524 /* iSeries does not use the FWNMI stuff, so it is safe to put
1525 * this here, even if we later allow kernels that will boot on
1526 * both pSeries and iSeries */
1527 #ifdef CONFIG_PPC_ISERIES
1529 #include "lparmap.s"
1531 * This ".text" is here for old compilers that generate a trailing
1532 * .note section when compiling .c files to .s
1535 #endif /* CONFIG_PPC_ISERIES */
1540 * On pSeries and most other platforms, secondary processors spin
1541 * in the following code.
1542 * At entry, r3 = this processor's number (physical cpu id)
1544 _GLOBAL(generic_secondary_smp_init)
1547 /* turn on 64-bit mode */
1551 /* Set up a paca value for this processor. Since we have the
1552 * physical cpu id in r24, we need to search the pacas to find
1553 * which logical id maps to our physical one.
1555 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1556 li r5,0 /* logical cpu id */
1557 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1558 cmpw r6,r24 /* Compare to our id */
1560 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1565 mr r3,r24 /* not found, copy phys to r3 */
1566 b .kexec_wait /* next kernel might do better */
1568 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1569 /* From now on, r24 is expected to be logical cpuid */
1572 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1577 b 3b /* Never go on non-SMP */
1580 beq 3b /* Loop until told to go */
1582 /* See if we need to call a cpu state restore handler */
1583 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1585 ld r23,CPU_SPEC_RESTORE(r23)
1592 4: /* Create a temp kernel stack for use before relocation is on. */
1593 ld r1,PACAEMERGSP(r13)
1594 subi r1,r1,STACK_FRAME_OVERHEAD
1596 b .__secondary_start
1599 #ifdef CONFIG_PPC_ISERIES
1600 _STATIC(__start_initialization_iSeries)
1601 /* Clear out the BSS */
1602 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1603 LOAD_REG_IMMEDIATE(r8,__bss_start)
1604 sub r11,r11,r8 /* bss size */
1605 addi r11,r11,7 /* round up to an even double word */
1606 rldicl. r11,r11,61,3 /* shift right by 3 */
1610 mtctr r11 /* zero this many doublewords */
1614 LOAD_REG_IMMEDIATE(r1,init_thread_union)
1615 addi r1,r1,THREAD_SIZE
1617 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1619 LOAD_REG_IMMEDIATE(r3,cpu_specs)
1620 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1624 LOAD_REG_IMMEDIATE(r2,__toc_start)
1628 bl .iSeries_early_setup
1631 /* relocation is on at this point */
1633 b .start_here_common
1634 #endif /* CONFIG_PPC_ISERIES */
1636 #ifdef CONFIG_PPC_MULTIPLATFORM
1640 andi. r0,r3,MSR_IR|MSR_DR
1647 b . /* prevent speculative execution */
1651 * Here is our main kernel entry point. We support currently 2 kind of entries
1652 * depending on the value of r5.
1654 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1657 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1658 * DT block, r4 is a physical pointer to the kernel itself
1661 _GLOBAL(__start_initialization_multiplatform)
1662 #ifdef CONFIG_PPC_MULTIPLATFORM
1664 * Are we booted from a PROM Of-type client-interface ?
1667 bne .__boot_from_prom /* yes -> prom */
1670 /* Save parameters */
1674 /* Make sure we are running in 64 bits mode */
1677 /* Setup some critical 970 SPRs before switching MMU off */
1680 cmpwi r0,0x39 /* 970 */
1682 cmpwi r0,0x3c /* 970FX */
1684 cmpwi r0,0x44 /* 970MP */
1686 1: bl .__cpu_preinit_ppc970
1689 /* Switch off MMU if not already */
1690 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1693 b .__after_prom_start
1695 #ifdef CONFIG_PPC_MULTIPLATFORM
1696 _STATIC(__boot_from_prom)
1697 /* Save parameters */
1705 * Align the stack to 16-byte boundary
1706 * Depending on the size and layout of the ELF sections in the initial
1707 * boot binary, the stack pointer will be unalignet on PowerMac
1711 /* Make sure we are running in 64 bits mode */
1714 /* put a relocation offset into r3 */
1717 LOAD_REG_IMMEDIATE(r2,__toc_start)
1721 /* Relocate the TOC from a virt addr to a real addr */
1724 /* Restore parameters */
1731 /* Do all of the interaction with OF client interface */
1733 /* We never return */
1738 * At this point, r3 contains the physical address we are running at,
1739 * returned by prom_init()
1741 _STATIC(__after_prom_start)
1744 * We need to run with __start at physical address PHYSICAL_START.
1745 * This will leave some code in the first 256B of
1746 * real memory, which are reserved for software use.
1747 * The remainder of the first page is loaded with the fixed
1748 * interrupt vectors. The next two pages are filled with
1749 * unknown exception placeholders.
1751 * Note: This process overwrites the OF exception vectors.
1752 * r26 == relocation offset
1757 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1759 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1761 // XXX FIXME: Use phys returned by OF (r30)
1762 add r4,r27,r26 /* source addr */
1763 /* current address of _start */
1764 /* i.e. where we are running */
1765 /* the source addr */
1767 cmpdi r4,0 /* In some cases the loader may */
1768 beq .start_here_multiplatform /* have already put us at zero */
1769 /* so we can skip the copy. */
1770 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1773 li r6,0x100 /* Start offset, the first 0x100 */
1774 /* bytes were copied earlier. */
1776 bl .copy_and_flush /* copy the first n bytes */
1777 /* this includes the code being */
1778 /* executed here. */
1780 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1781 mtctr r0 /* that we just made/relocated */
1784 4: LOAD_REG_IMMEDIATE(r5,klimit)
1786 ld r5,0(r5) /* get the value of klimit */
1788 bl .copy_and_flush /* copy the rest */
1789 b .start_here_multiplatform
1791 #endif /* CONFIG_PPC_MULTIPLATFORM */
1794 * Copy routine used to copy the kernel to start at physical address 0
1795 * and flush and invalidate the caches as needed.
1796 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1797 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1799 * Note: this routine *only* clobbers r0, r6 and lr
1801 _GLOBAL(copy_and_flush)
1804 4: li r0,8 /* Use the smallest common */
1805 /* denominator cache line */
1806 /* size. This results in */
1807 /* extra cache line flushes */
1808 /* but operation is correct. */
1809 /* Can't get cache line size */
1810 /* from NACA as it is being */
1813 mtctr r0 /* put # words/line in ctr */
1814 3: addi r6,r6,8 /* copy a cache line */
1818 dcbst r6,r3 /* write it to memory */
1820 icbi r6,r3 /* flush the icache line */
1832 #ifdef CONFIG_PPC_PMAC
1834 * On PowerMac, secondary processors starts from the reset vector, which
1835 * is temporarily turned into a call to one of the functions below.
1840 .globl __secondary_start_pmac_0
1841 __secondary_start_pmac_0:
1842 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1852 _GLOBAL(pmac_secondary_start)
1853 /* turn on 64-bit mode */
1857 /* Copy some CPU settings from CPU 0 */
1858 bl .__restore_cpu_ppc970
1860 /* pSeries do that early though I don't think we really need it */
1863 mtmsrd r3 /* RI on */
1865 /* Set up a paca value for this processor. */
1866 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1867 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1868 add r13,r13,r4 /* for this processor. */
1869 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1871 /* Create a temp kernel stack for use before relocation is on. */
1872 ld r1,PACAEMERGSP(r13)
1873 subi r1,r1,STACK_FRAME_OVERHEAD
1875 b .__secondary_start
1877 #endif /* CONFIG_PPC_PMAC */
1880 * This function is called after the master CPU has released the
1881 * secondary processors. The execution environment is relocation off.
1882 * The paca for this processor has the following fields initialized at
1884 * 1. Processor number
1885 * 2. Segment table pointer (virtual address)
1886 * On entry the following are set:
1887 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1888 * r24 = cpu# (in Linux terms)
1889 * r13 = paca virtual address
1890 * SPRG3 = paca virtual address
1892 _GLOBAL(__secondary_start)
1893 /* Set thread priority to MEDIUM */
1899 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1900 bl .early_setup_secondary
1902 /* Initialize the kernel stack. Just a repeat for iSeries. */
1903 LOAD_REG_ADDR(r3, current_set)
1904 sldi r28,r24,3 /* get current_set[cpu#] */
1906 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1907 std r1,PACAKSAVE(r13)
1909 /* Clear backchain so we get nice backtraces */
1913 /* enable MMU and jump to start_secondary */
1914 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1915 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1916 #ifdef CONFIG_PPC_ISERIES
1917 BEGIN_FW_FTR_SECTION
1919 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1921 BEGIN_FW_FTR_SECTION
1922 stb r7,PACASOFTIRQEN(r13)
1923 stb r7,PACAHARDIRQEN(r13)
1924 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1929 b . /* prevent speculative execution */
1932 * Running with relocation on at this point. All we want to do is
1933 * zero the stack back-chain pointer before going into C code.
1935 _GLOBAL(start_secondary_prolog)
1937 std r3,0(r1) /* Zero the stack frame pointer */
1943 * This subroutine clobbers r11 and r12
1945 _GLOBAL(enable_64b_mode)
1946 mfmsr r11 /* grab the current MSR */
1948 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1951 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1957 #ifdef CONFIG_PPC_MULTIPLATFORM
1959 * This is where the main kernel code starts.
1961 _STATIC(start_here_multiplatform)
1962 /* get a new offset, now that the kernel has moved. */
1966 /* Clear out the BSS. It may have been done in prom_init,
1967 * already but that's irrelevant since prom_init will soon
1968 * be detached from the kernel completely. Besides, we need
1969 * to clear it now for kexec-style entry.
1971 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1972 LOAD_REG_IMMEDIATE(r8,__bss_start)
1973 sub r11,r11,r8 /* bss size */
1974 addi r11,r11,7 /* round up to an even double word */
1975 rldicl. r11,r11,61,3 /* shift right by 3 */
1979 mtctr r11 /* zero this many doublewords */
1986 mtmsrd r6 /* RI on */
1988 /* The following gets the stack and TOC set up with the regs */
1989 /* pointing to the real addr of the kernel stack. This is */
1990 /* all done to support the C function call below which sets */
1991 /* up the htab. This is done because we have relocated the */
1992 /* kernel but are still running in real mode. */
1994 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1997 /* set up a stack pointer (physical address) */
1998 addi r1,r3,THREAD_SIZE
2000 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2002 /* set up the TOC (physical address) */
2003 LOAD_REG_IMMEDIATE(r2,__toc_start)
2008 LOAD_REG_IMMEDIATE(r3, cpu_specs)
2010 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
2015 /* Do very early kernel initializations, including initial hash table,
2016 * stab and slb setup before we turn on relocation. */
2018 /* Restore parameters passed from prom_init/kexec */
2022 LOAD_REG_IMMEDIATE(r3, .start_here_common)
2023 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
2027 b . /* prevent speculative execution */
2028 #endif /* CONFIG_PPC_MULTIPLATFORM */
2030 /* This is where all platforms converge execution */
2031 _STATIC(start_here_common)
2032 /* relocation is on at this point */
2034 /* The following code sets up the SP and TOC now that we are */
2035 /* running with translation enabled. */
2037 LOAD_REG_IMMEDIATE(r3,init_thread_union)
2039 /* set up the stack */
2040 addi r1,r3,THREAD_SIZE
2042 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2044 /* Apply the CPUs-specific fixups (nop out sections not relevant
2048 bl .do_cpu_ftr_fixups
2049 bl .do_fw_ftr_fixups
2051 /* ptr to current */
2052 LOAD_REG_IMMEDIATE(r4, init_task)
2053 std r4,PACACURRENT(r13)
2057 std r1,PACAKSAVE(r13)
2061 /* Load up the kernel context */
2064 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
2065 #ifdef CONFIG_PPC_ISERIES
2066 BEGIN_FW_FTR_SECTION
2068 ori r5,r5,MSR_EE /* Hard Enabled */
2070 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
2072 BEGIN_FW_FTR_SECTION
2073 stb r5,PACAHARDIRQEN(r13)
2074 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
2082 * We put a few things here that have to be page-aligned.
2083 * This stuff goes at the beginning of the bss, which is page-aligned.
2089 .globl empty_zero_page
2093 .globl swapper_pg_dir
2098 * This space gets a copy of optional info passed to us by the bootstrap
2099 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2103 .space COMMAND_LINE_SIZE